Processors and methods of manufacturing the same
By using different parts of dynamic random access memory as multi-level caches for the processor and electrically connecting them to the core, the problem of speed mismatch between CPU caches and memory is solved, achieving processor miniaturization and efficient data access.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ICLEAGUE TECH CO LTD
- Filing Date
- 2022-07-12
- Publication Date
- 2026-07-10
Smart Images
Figure CN115172341B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a processor and a method of manufacturing the same. Background Technology
[0002] The Central Processing Unit (CPU) operates much faster than memory, causing the CPU to spend a considerable amount of time waiting for data to arrive or writing data to memory. Therefore, to resolve this mismatch between CPU processing speed and memory read / write speed, a CPU cache was developed. The CPU cache is a temporary data exchanger located between the CPU core and main memory. It has a smaller capacity than main memory but a faster data exchange speed. The size of the CPU cache and its distance from the CPU core affect CPU performance.
[0003] Improving CPU access speed and reducing CPU footprint are pressing issues that need to be addressed in this field. Summary of the Invention
[0004] To address the related technical problems, this disclosure proposes a processor and a method for manufacturing the same.
[0005] This disclosure provides a processor, including:
[0006] A first semiconductor structure, comprising a core, a first-level cache, and a second-level cache;
[0007] The second semiconductor structure includes a third to an Nth level cache; the caches at different levels among the third to Nth levels contain different portions of dynamic random access memory (DRAM); wherein, N is a positive integer greater than three.
[0008] A bonding layer is located between the first semiconductor structure and the second semiconductor structure, and is used to electrically connect the first semiconductor structure and the second semiconductor structure.
[0009] In the above scheme, N equals four;
[0010] The second semiconductor structure includes a third-level cache and a fourth-level cache; the dynamic random access memory includes a first part and a second part, the third-level cache includes the first part, and the fourth-level cache includes the second part.
[0011] In the above scheme, the distance between the first part and the kernel is W1, and the distance between the second part and the kernel is W2; wherein, W1 < W2.
[0012] In the above scheme, the second semiconductor structure includes:
[0013] First substrate;
[0014] Control section on the first substrate;
[0015] Hybrid bonding layer located on the control section;
[0016] A storage portion located on the hybrid bonding layer; the storage portion and the control portion include a third cache and a fourth cache;
[0017] The second substrate is located on the storage section;
[0018] The bonding layer is located between the first semiconductor structure and the first substrate.
[0019] In the above scheme, the processor includes a first bus and a second bus;
[0020] The first bus is dedicated to data transfer between the third-level cache and the kernel;
[0021] The second bus is used at least for data transfer between the fourth-level cache and the kernel.
[0022] In the above scheme, the communication protocols of the first bus and the second bus are different.
[0023] In the above scheme, the second bus is also used for data transmission between the fourth-level cache and the embedded neural network processor and / or Internet exchange processor.
[0024] In the above scheme, the processor includes a central processing unit.
[0025] In the above scheme, the bonding layer includes a first bump, a third substrate, and a second bump; the first bump is located on the first semiconductor structure, the third substrate is located on the first bump, and the second bump is located on the third substrate;
[0026] The second semiconductor structure further includes a through-silicon via (TSV); the TSV is used to electrically connect the second semiconductor structure and the second bump.
[0027] This disclosure also provides a method for manufacturing a processor, comprising:
[0028] A first semiconductor structure is formed, the first semiconductor structure including a core, a first-level cache, and a second-level cache;
[0029] A second semiconductor structure is formed, the second semiconductor structure including a third-level to an Nth-level cache; the caches at different levels among the third-level to Nth-level caches include different portions of dynamic random access memory; wherein, N is a positive integer greater than three;
[0030] A bonding layer is formed between the first semiconductor structure and the second semiconductor structure for electrically connecting the first semiconductor structure and the second semiconductor structure.
[0031] In the above scheme, N equals four;
[0032] The formed second semiconductor structure includes a third-level cache and a fourth-level cache; the dynamic random access memory includes a first part and a second part, the third-level cache includes the first part, and the fourth-level cache includes the second part.
[0033] In the above scheme, the distance between the first part and the kernel is W1, and the distance between the second part and the kernel is W2; wherein, W1 < W2.
[0034] In the above scheme, forming the second semiconductor structure includes:
[0035] Provide a first substrate;
[0036] A control portion is formed on the first substrate;
[0037] A hybrid bonding layer is formed on the control section;
[0038] A storage portion is formed on the hybrid bonding layer; the storage portion and the control portion include a third cache and a fourth cache;
[0039] A second substrate is formed on the storage section;
[0040] The formation of the bonding layer includes:
[0041] A bonding layer is formed between the first semiconductor structure and the first substrate.
[0042] The method in the above scheme further includes:
[0043] A first bus is formed; the first bus is dedicated to data transmission between the third-level cache and the kernel.
[0044] A second bus is formed; the second bus is used at least for data transfer between the fourth-level cache and the kernel.
[0045] In the above scheme, forming the bonding layer includes:
[0046] A first bump is formed on the first semiconductor structure;
[0047] A third substrate is formed on the first bump;
[0048] A second bump is formed on the third substrate;
[0049] The formation of the second semiconductor structure includes:
[0050] A through-silicon via (TSV) is formed; the TSV is used to electrically connect the second semiconductor structure and the second bump.
[0051] This disclosure provides a processor and its manufacturing method. The processor includes: a first semiconductor structure comprising a core, a first-level cache, and a second-level cache; a second semiconductor structure comprising third- to Nth-level caches; each of the third- to Nth-level caches comprising different portions of dynamic random access memory (DRAM); wherein N is a positive integer greater than three; and a bonding layer located between the first and second semiconductor structures for electrically connecting the first and second semiconductor structures. In this disclosure, different portions of DRAM are used as the processor's third- to Nth-level caches. Since the third-level cache is electrically connected to the processor's core via the bonding layer, and the DRAM has a high storage density, this results in a smaller footprint for the third-level cache, a larger storage capacity, and maintains a high access speed for the core. Furthermore, the fourth-level cache is electrically connected to the processor's core via the bonding layer, which improves the core's access speed to the fourth-level cache. Attached Figure Description
[0052] Figure 1a A schematic diagram of the structure of a computer storage system provided in an embodiment of this disclosure;
[0053] Figure 1b A schematic diagram of the structural layout of a processor provided in an embodiment of this disclosure;
[0054] Figure 2 A schematic diagram of the structure of a processor provided in an embodiment of this disclosure;
[0055] Figure 3 This is a schematic diagram of a specific structure of a processor provided in an embodiment of the present disclosure;
[0056] Figure 4 A schematic diagram of the framework structure of a processor provided in an embodiment of this disclosure;
[0057] Figure 5This is a schematic diagram illustrating the implementation process of a processor manufacturing method provided in an embodiment of the present disclosure. Detailed Implementation
[0058] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.
[0059] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0060] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0061] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.
[0062] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0063] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.
[0064] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0065] The processors involved in the embodiments of this disclosure include various processors with cores and multi-level caches, including but not limited to central processing units (CPUs). The following description uses a CPU as an example only.
[0066] Because different storage technologies vary greatly in storage speed and cost, to efficiently access data, computer storage systems place the most frequently used data on storage devices with fast read / write speeds, while storing less frequently used data on storage devices with slower read / write speeds. A memory system is a hierarchical structure of storage devices with different capacities, costs, and access times. For example... Figure 1a As shown, from left to right, the CPU's cache, main memory, and disk storage have progressively larger capacities, but their access speeds decrease. If the CPU takes about 3 cycles to find the required data in the first-level cache (L1), it takes about 10 cycles to find the data in the second-level cache (L2), and about 50 cycles to find the data in the third-level cache (L3). If it needs to retrieve data from main memory, it may take hundreds of cycles. The left-hand memory acts as a buffer for the right-hand memory, storing more frequently accessed data. The multi-level caches closer to the CPU core buffer a portion of the data and instructions in main memory. Main memory caches data on disk storage, which in turn often serves as a buffer for data stored on disks or tapes on other machines connected via a network.
[0067] In related technologies, such as Figure 1bAs shown, a central processing unit (CPU) typically has four levels of cache. The first to third levels of cache are composed of dense, high-speed static random access memory (SRAM), which resides on the first chip along with the CPU core. The fourth level cache is located on a second chip. In other words, the fourth level cache is on a different chip than the core. On one hand, because the CPU needs to access data off-chip, the access time and power consumption of the fourth level cache are relatively long, significantly limiting CPU performance. On the other hand, due to the low storage density of SRAM, in some cases, the SRAM cache occupies half or more of the silicon substrate area of the CPU chip, resulting in a large CPU area and hindering the miniaturization of memory systems. Furthermore, the large size of SRAM leads to greater distances between multiple levels of cache and larger interconnect RC delays.
[0068] In view of the above problems, this disclosure provides a processor, including:
[0069] A first semiconductor structure, comprising a core, a first-level cache, and a second-level cache;
[0070] The second semiconductor structure includes a third to an Nth level cache; the caches at different levels among the third to Nth levels contain different portions of dynamic random access memory; wherein, N is a positive integer greater than three.
[0071] A bonding layer is located between the first semiconductor structure and the second semiconductor structure, and is used to electrically connect the first semiconductor structure and the second semiconductor structure.
[0072] Figure 2 A schematic diagram of a processor structure is shown. Figure 2 As can be seen, the first semiconductor structure 108 and the second semiconductor structure 109 are stacked, and a bonding layer 120 is disposed between the first semiconductor structure 108 and the second semiconductor structure 109. It should be noted that... Figure 2 The structure of the processor is merely an exemplary demonstration and is not intended to limit the relative positions of the first semiconductor structure 108 and the second semiconductor structure 109 in the embodiments of this disclosure. The first semiconductor structure 108 may be located above the second semiconductor structure 109, or the first semiconductor structure 108 may be located below the second semiconductor structure 109.
[0073] Here, the first semiconductor structure 108 and the second semiconductor structure 109 are located on the same chip. The first semiconductor structure 108 and the second semiconductor structure 109 are stacked, which avoids the lateral expansion of the first semiconductor structure 108 and the second semiconductor structure 109 in the horizontal direction, which is conducive to the miniaturization of the processor.
[0074] Here, the capacity gradually increases in the order of Level 1 cache, Level 2 cache, Level 3 cache, and Level 4 cache.
[0075] In some specific examples, both the L1 and L2 caches are composed of SRAM. The distance between the L1 cache and the kernel is less than the distance between the L2 cache and the kernel. The rate at which the L1 cache exchanges data with the kernel is greater than the rate at which the L2 cache exchanges data with the kernel.
[0076] In some specific examples, a processor may include one core or multiple cores.
[0077] In some specific examples, the dynamic random access memory includes a storage section and a control section; wherein the storage section can be integrated with the control section on the same die, which allows for a wider bus and higher operating speed.
[0078] In some specific examples, the control section may include a complementary metal-oxide-semiconductor (CMOS) transistor and its control circuitry. The specific process of forming the transistor and related control circuitry of the control section of the dynamic random access memory may include: first forming a P-type well region (PWell) and an N-type well region (NWell) on a substrate (such as a silicon substrate); performing n-doping on the PWell and p-doping on the NWell to form the desired semiconductor doped region; then forming a metal gate above the substrate surface to obtain the control section containing the transistor and related control circuitry.
[0079] It is understood that in this embodiment of the present disclosure, the stacked dynamic random access memory is directly integrated on a single chip with the first semiconductor structure 108 containing the core, and a portion of the dynamic random access memory serves as the processor's fourth-level cache. This significantly reduces the access time compared to using off-chip dynamic random access memory as the fourth-level cache. Furthermore, the high storage density of the dynamic random access memory allows this processor to combine the advantages of large capacity and fast access speed.
[0080] Here, N is a positive integer greater than three, meaning that the dynamic random access memory can be divided into N-2 parts, each part serving as a different level of cache in the processor's third to Nth level caches. The following explanation uses N equal to four as an example.
[0081] In some embodiments, N equals four;
[0082] The second semiconductor structure 109 includes a third-level cache and a fourth-level cache; the dynamic random access memory includes a first part and a second part, the third-level cache includes the first part, and the fourth-level cache includes the second part.
[0083] Here, the dynamic random access memory is divided into two parts, one part serving as the processor's third-level cache and the other part serving as the processor's fourth-level cache.
[0084] Understandably, on the one hand, since the processor's L4 cache is located on the same chip as the core, the processor's access time to the L4 cache is shortened, and power consumption is reduced. On the other hand, since the processor's L3 cache is made up of high-density dynamic random access memory (DRAM), and the L3 cache is located on the same chip as the core, the high storage density of DRAM increases the cache capacity of the L3 cache, thereby greatly reducing the processor's miss probability and significantly reducing the area required for the L3 cache, while ensuring that the core can have a high access speed to the L3 cache.
[0085] In some embodiments, the distance between the first part and the kernel is W1, and the distance between the second part and the kernel is W2; wherein, W1 < W2.
[0086] Here, the first part corresponds to the third-level cache, and the second part corresponds to the fourth-level cache. This means that the distance between the third-level cache and the kernel is less than the distance between the fourth-level cache and the kernel. Furthermore, the capacity of the fourth-level cache is greater than the capacity of the third-level cache.
[0087] It is understandable that the distance between the L3 cache and the kernel is smaller than the distance between the L4 cache and the kernel, so as to meet the kernel's need for higher access speed to the L3 cache.
[0088] In some embodiments, the second semiconductor structure 109 includes:
[0089] First substrate;
[0090] Control section on the first substrate;
[0091] Hybrid bonding layer located on the control section;
[0092] A storage portion located on the hybrid bonding layer; the storage portion and the control portion include a third cache and a fourth cache;
[0093] The second substrate is located on the storage section;
[0094] The bonding layer 120 is located between the first semiconductor structure 108 and the first substrate.
[0095] In some specific examples, the second semiconductor structure 109 further includes a first metal layer and a second metal layer, the first metal layer being located between the control portion and the hybrid bonding layer, and the second metal layer being located between the hybrid bonding layer and the storage portion, the first metal layer and the second metal layer being used to interconnect the storage portion and the control portion.
[0096] In some specific examples, a hybrid bonding layer refers to a structure that achieves bonding on the same surface using multiple different bonding methods. A hybrid bonding layer can consist of multiple hybrid bond bodies, where a hybrid bond body is a single bump structure connecting the first metal layer and the second metal layer. Hybrid bonding layers can include various bonding methods such as insulator-insulator bonding, semiconductor-semiconductor bonding, and metal-metal bonding to achieve simultaneous bonding between metals and dielectrics, thereby solving the wafer-level underfill problem and exhibiting high physical connection reliability.
[0097] In some embodiments, the bonding layer 120 includes a first bump, a third substrate, and a second bump; the first bump is located on the first semiconductor structure 108, the third substrate is located on the first bump, and the second bump is located on the third substrate;
[0098] The second semiconductor structure 109 further includes a through-silicon via (TSV); the TSV is used to electrically connect the second semiconductor structure 109 and the second bump.
[0099] In some specific examples, the first bump includes a flip-chip bonding microbump, and the second bump includes a bonding bump.
[0100] In some specific examples, the first substrate, the second substrate, and the third substrate may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.
[0101] In some specific examples, the materials filling the through-silicon vias include, but are not limited to, conductive materials.
[0102] Figure 3 A schematic diagram of a specific processor structure is shown. Figure 3As can be seen, the processor, from bottom to top, includes: a first semiconductor structure 108, a first bump 113, a third substrate 112, a second bump 114, a first substrate 110, a control portion 115, a first metal layer 116, a hybrid bonding layer 119, a second metal layer 117, a storage portion 118, and a second substrate 111. Through-silicon vias (TSVs) 121 are also provided in the first substrate 110 and the control portion 115, through which the control portion 115 is electrically connected to the second bump 114.
[0103] In some embodiments, the processor includes a first bus and a second bus;
[0104] The first bus is dedicated to data transfer between the third-level cache and the kernel;
[0105] The second bus is used at least for data transfer between the fourth-level cache and the kernel.
[0106] In some embodiments, the communication protocols of the first bus and the second bus are different.
[0107] In some specific examples, the first bus may include, but is not limited to, a CCI (Camera Control Interface) bus and a NOC (Net On Chip) bus.
[0108] In some specific examples, the second bus may include, but is not limited to, an AXI (Advanced deXtensible Interface) bus.
[0109] Figure 4 A schematic diagram of a processor's framework structure is shown. From Figure 4 As can be seen from the diagram, the first semiconductor structure includes a core 101, a first-level cache 102, a second-level cache 103, a third-level cache 104 that transmits data with the core 101 via a first bus 106, and a fourth-level cache 105 that is mounted on a second bus 107 that transmits data with the core 101 via the second bus 107.
[0110] It is understood that in this embodiment of the present disclosure, a first bus 106 dedicated to data transmission between the third-level cache 104 and the kernel 101 is added, which allows the kernel 101 to retrieve data without going through the AXI bus. This improves the situation where the kernel 101 cannot access the third-level cache 104 through the AXI bus due to AXI bus congestion, thereby speeding up the access time of the kernel 101 to access the third-level cache 104.
[0111] In some embodiments, the second bus 107 is also used for data transfer between the fourth-level cache 105 and the embedded neural network processor and / or the Internet exchange processor.
[0112] It should be noted that the devices listed above that are mounted on the second bus 107 are merely illustrative examples and are not intended to limit the devices mounted on the second bus 107 in this embodiment of the present disclosure.
[0113] In some embodiments, the processor includes a central processing unit.
[0114] In some specific examples, the processor includes a central processing unit and may also be a graphics processing unit (GPU).
[0115] Understandably, in this embodiment, a portion of the on-chip dynamic random access memory is used as the processor's fourth-level cache 105, and the fourth-level cache 105 is directly connected to the AXI bus, which offers a significant advantage in access speed compared to traditional off-chip dynamic random access memory. Furthermore, other host devices connected to the AXI bus, such as embedded neural network processors or internet switching processors, can also utilize the fourth-level cache 105 when the central processing unit is idle, thereby maximizing memory utilization.
[0116] In this embodiment of the disclosure, a new cache allocation scheme is proposed based on System on Chip (SoC). With minor modifications to the soft core structure of the processor, the stacked dynamic random access memory is used as the processor's third-level cache 104 and fourth-level cache 105, so as to meet the processor's requirements for both capacity and access speed.
[0117] This disclosure provides a processor, including: a first semiconductor structure 108, the first semiconductor structure 108 including a core 101, a first-level cache 102, and a second-level cache 103; a second semiconductor structure 109, the second semiconductor structure 109 including third-level to Nth-level caches; the caches at different levels among the third-level to Nth-level caches include different portions of dynamic random access memory; wherein, N is a positive integer greater than three; and a bonding layer 120, the bonding layer 120 being located between the first semiconductor structure 108 and the second semiconductor structure 109, for electrically connecting the first semiconductor structure 108 and the second semiconductor structure 109. In this embodiment, different parts of the dynamic random access memory are used as the third to Nth level caches of the processor. Since the third level cache 104 is electrically connected to the processor core 101 through the bonding layer 120, and the dynamic random access memory has a high storage density, on the one hand, this makes the area occupied by the processor's third level cache 104 small, the storage capacity of the third level cache 104 large, and can maintain a high access speed of the core 101 to access the third level cache 104; on the other hand, since the fourth level cache 105 is electrically connected to the processor core 101 through the bonding layer 120, the access speed of the core 101 to the fourth level cache 105 can be improved.
[0118] This disclosure also provides a method for manufacturing a processor to obtain the aforementioned processor. Figure 5 This is a schematic diagram illustrating the implementation flow of the processor manufacturing method according to an embodiment of this disclosure. Figure 5 As shown, the method includes the following steps:
[0119] Step S1001: Form a first semiconductor structure, the first semiconductor structure including a core, a first-level cache, and a second-level cache;
[0120] Step S1002: Form a second semiconductor structure, the second semiconductor structure including a third-level to an Nth-level cache; the caches at different levels among the third-level to Nth-level caches include different portions of dynamic random access memory; wherein, N is a positive integer greater than three;
[0121] Step S1003: Form a bonding layer, which is located between the first semiconductor structure and the second semiconductor structure, for electrically connecting the first semiconductor structure and the second semiconductor structure.
[0122] In step S1001, the processor core, the first-level cache, and the second-level cache are mainly formed.
[0123] In step S1002, the third to Nth level buffers are mainly formed;
[0124] In some embodiments, N equals four;
[0125] The formed second semiconductor structure includes a third-level cache and a fourth-level cache; the dynamic random access memory includes a first part and a second part, the third-level cache includes the first part, and the fourth-level cache includes the second part.
[0126] In some embodiments, the distance between the first part and the kernel is W1, and the distance between the second part and the kernel is W2; wherein, W1 < W2.
[0127] In some embodiments, forming the second semiconductor structure includes:
[0128] Provide a first substrate;
[0129] A control portion is formed on the first substrate;
[0130] A hybrid bonding layer is formed on the control section;
[0131] A storage portion is formed on the hybrid bonding layer; the storage portion and the control portion include a third cache and a fourth cache;
[0132] A second substrate is formed on the storage section;
[0133] The formation of the bonding layer includes:
[0134] A bonding layer is formed between the first semiconductor structure and the first substrate.
[0135] In step S1003, the bonding layer is mainly formed.
[0136] In some embodiments, forming the bonding layer includes:
[0137] A first bump is formed on the first semiconductor structure;
[0138] A third substrate is formed on the first bump;
[0139] A second bump is formed on the third substrate;
[0140] The formation of the second semiconductor structure includes:
[0141] A through-silicon via (TSV) is formed; the TSV is used to electrically connect the second semiconductor structure and the second bump.
[0142] In some embodiments, the method further includes:
[0143] A first bus is formed; the first bus is dedicated to data transmission between the third-level cache and the kernel.
[0144] A second bus is formed; the second bus is used at least for data transfer between the fourth-level cache and the kernel.
[0145] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.
[0146] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.
[0147] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A processor, characterized in that, include: A first semiconductor structure, comprising a core, a first-level cache, and a second-level cache; A second semiconductor structure, the second semiconductor structure including a third-level to an Nth-level cache; The caches at different levels from the third to the Nth level comprise different portions of dynamic random access memory; wherein, N is a positive integer greater than three; the second semiconductor structure includes a third-level cache and a fourth-level cache; the dynamic random access memory comprises a first portion and a second portion, the third-level cache comprises the first portion, and the fourth-level cache comprises the second portion; A bonding layer is located between the first semiconductor structure and the second semiconductor structure, and is used to electrically connect the first semiconductor structure and the second semiconductor structure.
2. The processor according to claim 1, characterized in that, The distance between the first part and the kernel is W1, and the distance between the second part and the kernel is W2; wherein, W1 < W2.
3. The processor according to claim 1, characterized in that, The second semiconductor structure includes: First substrate; Control section on the first substrate; Hybrid bonding layer located on the control section; A storage portion located on the hybrid bonding layer; the storage portion and the control portion include a third cache and a fourth cache; The second substrate is located on the storage section; The bonding layer is located between the first semiconductor structure and the first substrate.
4. The processor according to claim 1, characterized in that, The processor includes a first bus and a second bus; The first bus is dedicated to data transfer between the third-level cache and the kernel; The second bus is used at least for data transfer between the fourth-level cache and the kernel.
5. The processor according to claim 4, characterized in that, The communication protocols of the first bus and the second bus are different.
6. The processor according to claim 4, characterized in that, The second bus is also used for data transfer between the fourth-level cache and the embedded neural network processor and / or the Internet switching processor.
7. The processor according to claim 1, characterized in that, The processor includes a central processing unit.
8. The processor according to claim 1, characterized in that, The bonding layer includes a first bump, a third substrate, and a second bump; the first bump is located on the first semiconductor structure, the third substrate is located on the first bump, and the second bump is located on the third substrate; The second semiconductor structure further includes a through-silicon via (TSV); the TSV is used to electrically connect the second semiconductor structure and the second bump.
9. A method for manufacturing a processor, characterized in that, include: A first semiconductor structure is formed, the first semiconductor structure including a core, a first-level cache, and a second-level cache; A second semiconductor structure is formed, the second semiconductor structure including a third-level to an Nth-level cache; the caches at different levels among the third-level to Nth-level caches include different portions of dynamic random access memory; wherein, N is a positive integer greater than three; the formed second semiconductor structure includes a third-level cache and a fourth-level cache; the dynamic random access memory includes a first portion and a second portion, the third-level cache includes the first portion, and the fourth-level cache includes the second portion; A bonding layer is formed between the first semiconductor structure and the second semiconductor structure for electrically connecting the first semiconductor structure and the second semiconductor structure.
10. The method according to claim 9, characterized in that, The distance between the first part and the kernel is W1, and the distance between the second part and the kernel is W2; wherein, W1 < W2.
11. The method according to claim 9, characterized in that, The formation of the second semiconductor structure includes: Provide a first substrate; A control portion is formed on the first substrate; A hybrid bonding layer is formed on the control section; A storage portion is formed on the hybrid bonding layer; the storage portion and the control portion include a third cache and a fourth cache; A second substrate is formed on the storage section; The formation of the bonding layer includes: A bonding layer is formed between the first semiconductor structure and the first substrate.
12. The method according to claim 9, characterized in that, The method further includes: A first bus is formed; the first bus is dedicated to data transmission between the third-level cache and the kernel. A second bus is formed; the second bus is used at least for data transfer between the fourth-level cache and the kernel.
13. The method according to claim 9, characterized in that, The formation of the bonding layer includes: A first bump is formed on the first semiconductor structure; A third substrate is formed on the first bump; A second bump is formed on the third substrate; The formation of the second semiconductor structure includes: A through-silicon via (TSV) is formed; the TSV is used to electrically connect the second semiconductor structure and the second bump.