A CMOS transistor based on double heterojunction and a preparation method thereof

Abstract

The application discloses a kind of CMOS transistor based on double heterojunction, including substrate, first AlN layer, second AlN layer, GaN buffer layer and SiN isolation layer being sequentially arranged from bottom to top, wherein, P-HEMT active area recess and N-HEMT active area recess are opened in SiN isolation layer;GaPN back barrier layer, first AlPN barrier layer, first GaPN channel layer and first GaN cap layer are sequentially arranged from bottom to top in P-HEMT active area recess;AlPN back barrier layer, second GaPN channel layer, second AlPN barrier layer and second GaN cap layer are sequentially arranged from bottom to top in N-HEMT active area recess;First source, first drain and first gate are arranged on the upper surface of first GaN cap layer;Second source, second drain and second gate are arranged on the upper surface of second GaN cap layer.The AlPN / GaPN heterojunction of the application can realize lattice matching, the in-plane stress of heterojunction can be effectively relieved, and the electrical performance of two-dimensional electron gas can be effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic integrated circuit technology, specifically relating to a CMOS transistor based on a double heterojunction and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), representing third-generation semiconductors, possesses superior physicochemical properties such as wide bandgap, high breakdown field strength, high thermal conductivity, low dielectric constant, high electron saturation drift velocity, strong radiation resistance, and good chemical stability. It has become a key material for fabricating next-generation microelectronic devices and circuits, following silicon (first-generation) and gallium arsenide (second-generation). It is particularly suitable for the development of high-frequency, high-power, high-temperature, and radiation-resistant electronic devices and circuits. Among these, GaN-based semiconductor materials, as the most important semiconductor material in the third generation, have a wide bandgap, effectively suppressing interband tunneling and gate-induced drain leakage, and have achieved widespread commercial applications.

[0003] Currently used ternary alloy heterojunction structures, such as AlGaN / GaN heterojunctions, suffer from stress between the barrier layer and the channel layer, and between the channel layer and the underlying buffer layer. This leads to poor film crystal quality, high alloy disorder scattering and inter-carrier scattering in the underlying channel, resulting in deterioration of the isoelectric properties of the two-dimensional electron gas, including mobility, areal density, and sheet resistance. Furthermore, the low activation energies of impurities such as C and O in commonly used Fe-doped GaN buffer layers lead to high background carrier concentrations, resulting in parasitic channels and degrading device performance. This limits the improvement of device specifications and restricts the commercial development of GaN-based semiconductor devices. Additionally, research on 2DHG in P-type HEMTs is currently lacking internationally, as the mobility of 2DHG in P-type HEMTs is very low. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a CMOS transistor based on a double heterojunction and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] One aspect of the present invention provides a CMOS transistor based on a double heterojunction, comprising, from bottom to top, a substrate, a first AlN layer, a second AlN layer, a GaN buffer layer, and a SiN isolation layer, wherein,

[0006] The SiN isolation layer has P-HEMT active region grooves and N-HEMT active region grooves, which extend from the upper surface of the SiN isolation layer to the upper surface of the GaN buffer layer.

[0007] The P-HEMT active region groove is provided with a GaPN back barrier layer, a first AlPN barrier layer, a first GaPN channel layer and a first GaN cap layer in sequence from bottom to top; the N-HEMT active region groove is provided with an AlPN back barrier layer, a second GaPN channel layer, a second AlPN barrier layer and a second GaN cap layer in sequence from bottom to top.

[0008] The upper surface of the first GaN cap layer is provided with a first source, a first drain, and a first gate that are spaced apart from each other; the upper surface of the second GaN cap layer is provided with a second source, a second drain, and a second gate that are spaced apart from each other.

[0009] The growth temperature of the first AlN layer is lower than that of the second AlN layer.

[0010] In one embodiment of the present invention, the P-HEMT active region groove and the N-HEMT active region groove are symmetrically formed inside the SiN isolation layer, and both extend from one side of the SiN isolation layer to the opposite side.

[0011] In one embodiment of the present invention, the first source, the first drain, and the first gate...

[0012] The electrodes are isolated from each other by SiN material, and the first gate is located between the first source and the first drain; the second source, the second drain and the second gate are isolated from each other by SiN material, and the second gate is located between the second source and the second drain.

[0013] In one embodiment of the present invention, a pre-laid aluminum layer is further included between the substrate and the first AlN layer.

[0014] In one embodiment of the present invention, the surface areas of the GaPN back barrier layer, the first AlPN barrier layer, and the first GaPN channel layer are equal, all equal to the inner surface area of ​​the P-HEMT active region groove; the surface areas of the AlPN back barrier layer, the second GaPN channel layer, and the second AlPN barrier layer are equal, all equal to the inner surface area of ​​the N-HEMT active region groove.

[0015] In one embodiment of the present invention, the thickness of the GaPN back barrier layer is 10-30 nm, the thickness of the first AlPN barrier layer is 20-40 nm, and the thickness of the first GaPN channel layer is 10-30 nm; the thickness of the AlPN back barrier layer is 20-40 nm, the thickness of the second GaPN channel layer is 10-30 nm, and the thickness of the second AlPN barrier layer is 20-40 nm.

[0016] In one embodiment of the present invention, the GaPN back barrier layer, the first AlPN barrier layer and the first GaPN channel layer form a double heterojunction structure GaPN / AlPN / GaPN; the AlPN back barrier layer, the second GaPN channel layer and the second AlPN barrier layer form a double heterojunction structure AlPN / GaPN / AlPN.

[0017] Another aspect of the present invention provides a method for fabricating a CMOS transistor based on a double heterojunction, used to fabricate the CMOS transistor described in any of the above embodiments, the fabrication method comprising:

[0018] Select a substrate and pre-bake the substrate;

[0019] A first AlN layer, a second AlN layer, and a GaN buffer layer are sequentially grown on the substrate.

[0020] A SiN isolation layer is deposited on the GaN buffer layer, and a P-HEMT active region groove is etched on the SiN isolation layer.

[0021] A GaPN back barrier layer, a first AlPN barrier layer, and a first GaPN channel layer are formed from bottom to top in the active region groove of the P-HEMT.

[0022] An N-HEMT active region groove is etched on the SiN isolation layer, and an AlPN back barrier layer, a second GaPN channel layer, and a second AlPN barrier layer are formed from bottom to top in the N-HEMT active region groove.

[0023] A first GaN cap layer is grown on the first GaPN channel layer, and a second GaN cap layer is grown on the second AlPN barrier layer;

[0024] A first source, a first drain, and a first gate are formed on the first GaN cap layer, and a second source, a second drain, and a second gate are formed on the second GaN cap layer.

[0025] In one embodiment of the present invention, a first AlN layer and a second AlN layer are sequentially grown on the substrate.

[0026] The AlN layer and GaN buffer layer include:

[0027] Trimethylaluminum is introduced into the reaction chamber of the MOCVD equipment at a temperature of 1050℃-1150℃ to grow a pre-laid aluminum layer with a thickness of 30-100nm on the substrate.

[0028] Trimethylaluminum and ammonia gas were introduced to grow a first AlN layer with a thickness of 20-40 nm on the pre-laid aluminum layer;

[0029] The reaction chamber temperature was adjusted to 1150-1250℃, and trimethylaluminum and ammonia were introduced to grow a second AlN layer with a thickness of 150-200nm on the first AlN layer.

[0030] The reaction chamber temperature was adjusted to 1100-1200℃, and trimethylgallium and ammonia were introduced to grow a GaN buffer layer with a thickness of 800-1000 nm on the second AlN layer.

[0031] In one embodiment of the present invention, a GaPN back barrier layer, a first AlPN barrier layer, and a first GaPN channel layer are formed from bottom to top within the active region groove of the P-HEMT, including:

[0032] At 1000-1150℃, trimethylgallium, tert-butylphosphine and ammonia are introduced to grow a GaPN back barrier layer with a thickness of 10-30nm in the active region groove of the P-HEMT, and the lower surface of the GaPN back barrier layer is in contact with the upper surface of the GaN buffer layer.

[0033] The temperature of the reaction chamber of the MOCVD equipment is adjusted to 1150-1160℃, and trimethylaluminum, tert-butylphosphine and ammonia are introduced to react and generate a first AlPN barrier layer with a thickness of 20-40nm.

[0034] The temperature of the MOCVD equipment reaction chamber is adjusted to 1070-1085℃, and trimethylgallium, tert-butylphosphine and ammonia are introduced to react and generate a first GaPN channel layer with a thickness of 10-30nm on the first AlPN barrier layer.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0036] 1. This invention proposes a CMOS high-mobility transistor based on AlPN / GaPN / AlPN and GaPN / AlPN / GaPN double heterojunctions, where the lattice matching between AlPN and GaPN materials is extremely small. In this embodiment, an AlPN layer is used as a barrier layer, effectively suppressing high lattice vibrational scattering caused by the deterioration of the thin film material quality. Furthermore, the AlPN layer is used as a back barrier; this bandgap modulation process improves the confinement of the two-dimensional electron gas, thereby enhancing its areal density and mobility, among other electrical properties. AlPN and GaPN can achieve better lattice matching, avoiding warping and heat dissipation problems caused by in-plane stress that could adversely affect the performance of subsequent devices.

[0037] 2. This invention utilizes the two-dimensional hole gas generated by polarization in the GaPN / AlPN heterojunction as the source of carriers in the P-type HEMT. Combined with the GaPN back barrier layer to improve confinement, it can be monolithically integrated with the aforementioned N-type HEMT materials, filling the gap in high-performance PMOS transistors and thus achieving the requirements of high-efficiency CMOS.

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0039] Figure 1 is a schematic diagram of a CMOS transistor based on a double heterojunction provided in an embodiment of the present invention;

[0040] Figure 2 is a top view of a CMOS transistor based on a double heterojunction provided in an embodiment of the present invention;

[0041] Figure 3 is a flowchart of a method for fabricating a CMOS transistor based on a double heterojunction according to an embodiment of the present invention;

[0042] Figures 4a to 4g are schematic diagrams illustrating the fabrication process of a CMOS transistor based on a double junction according to an embodiment of the present invention.

[0043] Explanation of reference numerals in the attached figures:

[0044] 1-Substrate; 2-First AlN layer; 3-Second AlN layer; 4-GaN buffer layer; 5-SiN isolation layer; 6-P-HEMT active region trench; 7-GaPN back barrier layer; 8-First AlPN barrier layer; 9-First GaPN channel layer; 10-N-HEMT active region trench; 11-AlPN back barrier layer; 12-Second GaPN channel layer; 13-Second AlPN barrier layer; 14-First GaN cap layer; 15-Second GaN cap layer; 16-First source; 17-First drain; 18-First gate; 19-Second source; 20-Second drain; 21-Second gate. Detailed Implementation

[0045] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a CMOS transistor based on a double heterojunction and its fabrication method according to the present invention.

[0046] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0047] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0048] Example 1

[0049] Please see Figure 1 , Figure 1 This is a schematic diagram of a CMOS transistor based on a double heterojunction according to an embodiment of the present invention. The CMOS transistor includes a substrate 1, a first AlN layer 2, a second AlN layer 3, a GaN buffer layer 4, and a SiN isolation layer 5 arranged sequentially from bottom to top. The SiN isolation layer 5 has a P-HEMT active region recess 6 and an N-HEMT active region recess 10. The P-HEMT active region recess 6 has a GaPN back barrier layer 7, a first AlPN barrier layer 8, a first GaPN channel layer 9, and a first GaN cap layer 14 arranged sequentially from bottom to top. The N-HEMT active region recess 10 has an AlPN back barrier layer 11, a second GaPN channel layer 12, a second AlPN barrier layer 13, and a second GaN cap layer 15 arranged sequentially from bottom to top. The upper surface of the first GaN cap layer 14 has a first source 16, a first drain 17, and a first gate 18 spaced apart from each other. The upper surface of the second GaN cap layer 15 has a second source 19, a second drain 20, and a second gate 21 spaced apart from each other.

[0050] In this embodiment, substrate 1 is selected as a sapphire substrate. The first AlN layer 2 is a low-temperature AlN layer, and the second AlN layer 3 is a high-temperature AlN layer. The growth temperature of the first AlN layer 2 is lower than that of the second AlN layer 3. Preferably, the thickness of the first AlN layer 2 is 20-40 nm, and the thickness of the second AlN layer 3 is 150-200 nm. The first AlN layer 2 is generated at a temperature of 1050℃-1150℃, and the second AlN layer 3 is generated at a temperature of 1150℃-1250℃. AlN grows in a three-dimensional mode at relatively low temperatures and in a two-dimensional mode at relatively high temperatures. The thickness of the GaN buffer layer 4 is 800-1000 nm.

[0051] In this embodiment, a pre-laid aluminum layer (not shown in the figure) with a thickness of 20-40 nm is also included between the substrate 1 and the first AlN layer 2. Since Al atoms have poor mobility on the substrate surface, the pre-laid aluminum layer can effectively improve the mobility of aluminum, improve the quality of subsequent epitaxial layers, and thus improve the electrical performance of the transistor.

[0052] Please see Figure 1 and Figure 2 , Figure 2 This is a top view of a CMOS transistor based on a double heterojunction provided in an embodiment of the present invention. The P-HEMT active region groove 6 and the N-HEMT active region groove 10 are symmetrically formed on the upper surface of the SiN isolation layer 5, and both extend from one side of the SiN isolation layer 5 to the opposite side. In other words, the P-HEMT active region groove 6 and the N-HEMT active region groove 10 are both grooves with openings at both ends, and their width is equal to the width of the SiN isolation layer 5.

[0053] Furthermore, the P-HEMT active region recess 6 and the N-HEMT active region recess 10 have the same depth. The lower surfaces of both the P-HEMT active region recess 6 and the N-HEMT active region recess 10 are in contact with the upper surface of the GaN buffer layer 4. The surface areas of the GaPN back barrier layer 7, the first AlPN barrier layer 8, and the first GaPN channel layer 9 are equal, all equal to the inner surface area of ​​the P-HEMT active region recess 6. The GaPN back barrier layer 7, the first AlPN barrier layer 8, and the first GaPN channel layer 9 form a double heterojunction structure GaPN / AlPN / GaPN. The surface areas of the AlPN back barrier layer 11, the second GaPN channel layer 12, and the second AlPN barrier layer 13 are equal, all equal to the inner surface area of ​​the N-HEMT active region recess 10. The AlPN back barrier layer 11, the second GaPN channel layer 12, and the second AlPN barrier layer 13 form a double heterojunction structure AlPN / GaPN / AlPN.

[0054] Furthermore, the thickness of the GaPN back barrier layer 7 is 10-30 nm, the thickness of the first AlPN barrier layer 8 is 20-40 nm, the thickness of the first GaPN channel layer 9 is 10-30 nm, the thickness of the AlPN back barrier layer 11 is 20-40 nm, the thickness of the second GaPN channel layer 12 is 10-30 nm, and the thickness of the second AlPN barrier layer 13 is 20-40 nm.

[0055] Continue as Figure 1 and Figure 2 As shown, the first source 16, the first drain 17, and the first gate 18 are isolated from each other by SiN material, and the first gate 18 is located between the first source 16 and the first drain 17. The lower surfaces of the first source 16, the first drain 17, and the first gate 18 are all in contact with the upper surface of the first GaN cap layer 14, and form ohmic contacts respectively.

[0056] The second source 19, the second drain 20, and the second gate 21 are isolated from each other by SiN material, and the second gate 21 is located between the second source 19 and the second drain 20. The lower surfaces of the second source 19, the second drain 20, and the second gate 21 are all in contact with the upper surface of the second GaN cap layer 15 and form ohmic contacts respectively.

[0057] Preferably, the first source 16, the first drain 17, the second source 19, and the second drain 20 each comprise four metal layers of Ti / Al / Ni / Au from bottom to top, and the first gate 18 and the second gate 21 each comprise two metal layers of Ni / Au from bottom to top.

[0058] This embodiment proposes a CMOS high-mobility transistor based on AlPN / GaPN / AlPN and GaPN / AlPN / GaPN double heterojunctions, where the lattice matching between AlPN and GaPN materials is extremely small. This embodiment uses an AlPN layer as a barrier layer, effectively suppressing high lattice vibrational scattering caused by the degradation of thin film material quality. Furthermore, utilizing the AlPN layer as a back barrier, this bandgap modulation process improves the confinement of the two-dimensional electron gas, thereby enhancing its areal density and mobility, among other electrical properties. AlPN and GaPN can achieve better lattice matching, avoiding warping and heat dissipation problems caused by in-plane stress that could adversely affect subsequent device performance.

[0059] Example 2

[0060] Based on Example 1, this example proposes a method for fabricating a CMOS transistor based on a double heterojunction. The fabrication process is generally carried out under metal-organic chemical vapor deposition (MOCVD) conditions. The MOCVD growth process is conducted under specific pressure and temperature. The metal-organic sources used in the fabrication process are ammonia, TMAl (trimethylaluminum), TMGa (trimethylgallium), and tBp (tert-butylphosphine), and the carrier gas is N2. Specifically, the fabrication method of the CMOS transistor in this example includes the following steps:

[0061] S1: Select substrate 1 and pre-bake substrate 1.

[0062] Specifically, sapphire was selected as substrate 1 and pre-baked in an MOCVD device.

[0063] S2: A first AlN layer 2, a second AlN layer 3, and a GaN buffer layer 4 are sequentially grown on substrate 1, as follows: Figure 4a As shown.

[0064] S2 in this embodiment includes:

[0065] S21: Trimethylaluminum is introduced into the reaction chamber of the MOCVD equipment for 3 minutes at a temperature of 1050℃-1150℃ to grow a pre-laid aluminum layer on substrate 1.

[0066] Specifically, under the temperature of 1100°C in the reaction chamber of the MOCVD equipment, trimethylaluminum was introduced for 3 minutes to grow a pre-laid aluminum layer on substrate 1, obtaining a pre-laid aluminum layer of about 30 nm (not shown in the attached figure). Since Al atoms have poor mobility on the substrate surface, the pre-laid aluminum layer can effectively improve the mobility of aluminum, improve the quality of subsequent epitaxial layers, and thus improve the electrical performance of transistors.

[0067] S22: Adjust the reaction chamber temperature to 1050-1150℃, and introduce trimethylaluminum and ammonia gas to grow the first AlN layer 2 on the pre-laid aluminum layer.

[0068] Specifically, under the temperature of 1100°C in the reaction chamber of the MOCVD equipment, trimethylaluminum and ammonia are introduced to grow a first AlN layer 2 with a thickness of 20-40 nm on the pre-laid aluminum layer. The AlN grows in a three-dimensional mode at a relatively low temperature.

[0069] S23: Adjust the reaction chamber temperature to 1150-1250℃, and introduce trimethylaluminum and ammonia gas to grow the second AlN layer 3 on the first AlN layer 2.

[0070] Specifically, under the MOCVD equipment reaction chamber temperature of 1210°C, trimethylaluminum and ammonia gas are introduced to grow a second AlN layer 3 with a thickness of 150-200 nm on the first AlN layer 2. The AlN grows in a two-dimensional mode at a relatively high temperature. In this embodiment, the application of a variable-temperature growth mode between the second AlN layer 3 and the first AlN layer 2 can result in lower roughness of the subsequent epitaxial layer and better crystal quality.

[0071] S24: Adjust the reaction chamber temperature to 1100-1200℃, and introduce trimethylgallium and ammonia gas to grow a GaN buffer layer 4 on the second AlN layer 3.

[0072] Specifically, under the temperature of 1150°C in the reaction chamber of the MOCVD equipment, trimethylgallium and ammonia gas were introduced for 40 minutes to grow an 800-1000 nm thick GaN buffer layer 4 on the basis of the second AlN layer 3.

[0073] S3: A SiN isolation layer 5 is deposited on the GaN buffer layer 4, and a P-HEMT active region groove 6 is etched on the SiN isolation layer 5, as shown in Figures 4b1 and 4b2, where Figure 4b2 is the top view corresponding to Figure 4b1.

[0074] Specifically, a SiN isolation layer 5 is deposited on the GaN buffer layer 4, and then a P-HEMT active region pattern is formed on the SiN isolation layer 5 by photolithography. The P-HEMT active region pattern is etched to form a P-HEMT active region groove 6. The depth of the P-HEMT active region groove 6 is equal to the thickness of the SiN isolation layer 5, so that the lower surface of the P-HEMT active region groove 6 extends to the upper surface of the GaN buffer layer 4. Furthermore, the P-HEMT active region groove 6 extends from one side of the SiN isolation layer 5 to the opposite side. In other words, the P-HEMT active region groove 6 is a groove with openings at both ends, and its width is equal to the width of the SiN isolation layer 5.

[0075] S4: A GaPN back barrier layer 7, a first AlPN barrier layer 8, and a first GaPN channel layer 9 are formed from bottom to top in the active region groove 6 of the P-HEMT.

[0076] Specifically, the reaction chamber temperature of the MOCVD equipment is adjusted to 1000-1150℃, and trimethylgallium, tert-butylphosphine, and ammonia are introduced. A GaPN back barrier layer 7 with a thickness of 10-30 nm is grown in the active region groove 6 of the P-HEMT. The lower surface of the GaPN back barrier layer 7 is in contact with the upper surface of the GaN buffer layer 4. By reducing the ammonia flow rate, a low V / III ratio (the molar fraction ratio of group V element N and group III element Ga or Al) is controlled, thereby allowing P element to replace Ga vacancies and reducing compressive stress.

[0077] Subsequently, the temperature of the MOCVD equipment reaction chamber was adjusted to 1150-1160℃, and trimethylaluminum, tert-butylphosphine and ammonia were introduced to grow a first AlPN barrier layer 8 with a thickness of 20-40nm on the GaPN back barrier layer 7. The lower surface of the first AlPN barrier layer 8 was in contact with the upper surface of the GaPN back barrier layer 7.

[0078] The first AlPN barrier layer 8 has a low V / III ratio to allow P elements to replace N vacancies and reduce tensile stress. In this embodiment, the V / III ratio of the first AlPN barrier layer 8 is greater than or equal to 1000. Subsequently, the reaction chamber temperature of the MOCVD equipment is adjusted to 1070-1085°C, and trimethylgallium, tert-butylphosphine, and ammonia are introduced to grow a 10-30 nm thick first GaPN channel layer 9 on the first AlPN barrier layer 8. The V / III ratio of the first GaPN channel layer 9 is lower than that of the first AlPN barrier layer 8 to allow P elements to replace Ga vacancies and reduce compressive stress. In this embodiment, the depth of the P-HEMT active region recess 6 is equal to the sum of the thicknesses of the GaPN back barrier layer 7, the first AlPN barrier layer 8, and the first GaPN channel layer 9.

[0079] S5: Etch N-HEMT active region groove 10 on SiN isolation layer 5, and form AlPN back barrier layer 11, second GaPN channel layer 12 and second AlPN barrier layer 13 sequentially from bottom to top in N-HEMT active region groove 10.

[0080] Specifically, firstly, SiN material is deposited on the upper surface of the sample obtained in step S4 as a hard mask. Then, an N-HEMT active region pattern is photolithographically formed, and the SiN isolation layer 5 in the N-HEMT active region pattern is etched away, forming an N-HEMT active region groove 10 spaced apart from the P-HEMT active region groove 6, as shown below. Figure 4d1 As shown in Figure 4d2, where Figure 4d2 is Figure 4d1 The corresponding top view. In this embodiment, the P-HEMT active region groove 6 and the N-HEMT active region groove 10 are symmetrically formed on both sides of the upper surface of the SiN isolation layer 5, and have the same shape and depth. In other words, the depth of the N-HEMT active region groove 10 is equal to the thickness of the SiN isolation layer 5, so that the lower surface of the N-HEMT active region groove 10 extends to the upper surface of the GaN buffer layer 4. Both the P-HEMT active region groove 6 and the N-HEMT active region groove 10 are grooves with openings at both ends, and their width is equal to the width of the SiN isolation layer 5.

[0081] Furthermore, the reaction chamber temperature of the MOCVD equipment is adjusted to 1150-1160℃, and trimethylaluminum, tert-butylphosphine, and ammonia are introduced to grow an AlPN back barrier layer 11 with a thickness of 20-40 nm in the N-HEMT active region groove 10. The lower surface of this AlPN back barrier layer 11 is adjacent to the upper surface of the GaN buffer layer 4.

[0082] Surface contact. By reducing the ammonia flow rate, the low V / III ratio (the mole fraction ratio of group V element N and group III element Ga or Al) is controlled, thereby allowing P element to replace Ga vacancies and reducing compressive stress.

[0083] The reaction chamber temperature of the MOCVD equipment is adjusted to 1070-1085℃, and trimethylgallium, tert-butylphosphine, and ammonia are introduced to grow a second GaPN channel layer 12 with a thickness of 10-30 nm on the AlPN back barrier layer 11. The V / III ratio of the second GaPN channel layer 12 is lower than that of the first AlPN barrier layer 8, so that P element replaces Ga vacancies and reduces compressive stress.

[0084] Subsequently, the temperature of the MOCVD reaction chamber was adjusted to 1150-1160℃, and trimethylaluminum, tert-butylphosphine, and ammonia were introduced to grow a 20-40 nm thick second AlPN barrier layer 13 on the second GaPN channel layer 12, as shown in Figure 4e. The V / III ratio of this second AlPN barrier layer 13 is the same as that of the first AlPN barrier layer 8, so that P elements replace N vacancies and reduce tensile stress. In this embodiment, the depth of the N-HEMT active region groove 10 is equal to the sum of the thicknesses of the AlPN back barrier layer 11, the second AlPN barrier layer 13, and the second GaPN channel layer 12.

[0085] S6: A first GaN cap layer 14 is grown on the first GaPN channel layer 9, and a second GaN cap layer 15 is grown on the second AlPN barrier layer 13.

[0086] Specifically, based on the previous step, the N-HEMT active region and the P-HEMT active region are etched simultaneously, that is, the upper surfaces of the first GaPN channel layer 9 and the second GaN cap layer 15 are exposed simultaneously, and the GaN cap layer is grown, forming the first GaN cap layer 14 and the second GaN cap layer 15 on the first GaPN channel layer 9 and the second AlPN barrier layer 13, respectively, as shown in Figure 4f.

[0087] S7: A first source 16, a first drain 17, and a first gate 18 are formed on the first GaN cap layer 14, and a second source 19, a second drain 20, and a second gate 21 are formed on the second GaN cap layer 15, as shown in Figure 4g.

[0088] Specifically, SiN is deposited on the first GaN cap layer 14 and the second GaN cap layer 15 as a hard layer.

[0089] A mask is used to etch a first source trench, a first drain trench, and a first gate trench on the first GaN cap layer 14, and simultaneously etch a second source trench, a second drain trench, and a second gate trench on the second GaN cap layer 15. Subsequently, Ti / Al / Ni / Au metal is deposited in the first source trench and the first drain trench to create ohmic contacts between the first source and the first drain. Similarly, Ti / Al / Ni / Au metal is deposited in the second source trench and the second drain trench to create ohmic contacts between the first and second sources and the second drain. After annealing, Ni / Au metal is deposited in the first gate trench to create an ohmic contact between the first and second gates, and Ni / Au metal is deposited in the second gate trench to create an ohmic contact between the first and second gates.

[0090] This embodiment utilizes the two-dimensional hole gas generated by polarization in the GaPN / AlPN heterojunction as the source of carriers for the P-type HEMT. Combined with the GaPN back barrier layer to improve confinement, it can be monolithically integrated with the aforementioned N-type HEMT material, filling the gap in high-performance PMOS transistors and thus achieving the requirements of high-efficiency CMOS.

[0091] Example 3

[0092] Based on the above embodiments, this embodiment specifically describes a method for fabricating a CMOS transistor based on an AlPN / GaPN heterojunction, the fabrication process including:

[0093] (1) A pretreated (0001) facet sapphire substrate was placed in an MOCVD equipment, and a pre-laid aluminum layer was grown on the substrate at a flow rate of 20 sccm for 3 minutes. Then, a first AlN layer with a thickness of 25 nm was grown at 1100 °C. Next, a second AlN layer with a thickness of 180 nm was grown at 1210 °C. A GaN buffer layer with a thickness of 1 μm was grown by introducing trimethylgallium at a flow rate of 50 sccm and ammonia at a flow rate of 3500 sccm at 1030 °C.

[0094] (2) Deposit a SiN isolation layer, photolithographically etch and etch out the P-HEMT active region groove, and introduce trimethylgallium with a flow rate of 500 sccm, tert-butylphosphine with a flow rate of 800 sccm, and ammonia with a flow rate of 4000 sccm at 1070℃ to grow a back barrier layer with a thickness of 30nm.

[0095] (3) Adjust the temperature of the reaction chamber of the MOCVD equipment to 1150℃, introduce trimethylaluminum at a flow rate of 100 sccm, tert-butylphosphine at a flow rate of 30 sccm, and ammonia at a flow rate of 4000 sccm to grow a first AlPN barrier layer with a thickness of 20nm.

[0096] (4) Adjust the temperature of the reaction chamber of the MOCVD equipment to 1070℃, and introduce trimethylgallium, tert-butylphosphine and ammonia to react and generate a first GaPN channel layer with a thickness of 10nm. The flow rate of trimethylgallium is 500sccm, the flow rate of tert-butylphosphine is 800sccm, and the flow rate of ammonia is 50000sccm.

[0097] (5) Photolithography and etching of the N-HEMT active region groove, and introduction of trimethylaluminum at a flow rate of 100 sccm, tert-butylphosphine at a flow rate of 30 sccm, and ammonia at a flow rate of 4000 sccm at 1150℃ to grow a 20nm thick AlPN back barrier layer.

[0098] (6) Adjust the temperature of the reaction chamber of the MOCVD equipment to 1070℃, and introduce trimethylgallium, tert-butylphosphine and ammonia to react and generate a second GaPN channel layer with a thickness of 10nm. The flow rate of trimethylgallium is 500sccm, the flow rate of tert-butylphosphine is 800sccm, and the flow rate of ammonia is 50000sccm.

[0099] (7) Adjust the temperature of the reaction chamber to 1150℃, introduce trimethylaluminum at a flow rate of 100 sccm, tert-butylphosphine at a flow rate of 30 sccm, and ammonia at a flow rate of 4000 sccm to grow a second AlPN barrier layer with a thickness of 20 nm.

[0100] (6) Deposit a SiN mask, photolithographically etch and etch the N-HEMT active region and P-HEMT active region, grow a first GaN cap layer on the first GaPN channel layer, and grow a second GaN cap layer on the second AlPN barrier layer. Subsequently, etch a first source trench, a first drain trench, and a first gate trench on the first GaN cap layer, and simultaneously etch a second source trench, a second drain trench, and a second gate trench on the second GaN cap layer. Then, deposit Ti / Al / Ni / Au metal in the first source trench and the first drain trench to form ohmic contacts between the first source and the first drain, and deposit Ti / Al / Ni / Au metal in the second source trench and the second drain trench to form ohmic contacts between the first and second sources and the second drain. After annealing, deposit Ni / Au metal in the first gate trench to form ohmic contacts between the first and second gates, and deposit Ni / Au metal in the second gate trench to form ohmic contacts between the first and second gates.

[0101] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A CMOS transistor based on a double heterojunction, characterized in that, It includes, from bottom to top, a substrate (1), a first AlN layer (2), a second AlN layer (3), a GaN buffer layer (4), and a SiN isolation layer (5), wherein, The SiN isolation layer (5) has a P-HEMT active region groove (6) and an N-HEMT active region groove (10), which extend from the upper surface of the SiN isolation layer (5) to the upper surface of the GaN buffer layer (4). The P-HEMT active region groove (6) is provided with a GaPN back barrier layer (7), a first AlPN barrier layer (8), a first GaPN channel layer (9) and a first GaN cap layer (14) in sequence from bottom to top; the N-HEMT active region groove (10) is provided with an AlPN back barrier layer (11), a second GaPN channel layer (12), a second AlPN barrier layer (13) and a second GaN cap layer (15) in sequence from bottom to top; The upper surface of the first GaN cap layer (14) is provided with a first source (16), a first drain (17) and a first gate (18) spaced apart from each other; the upper surface of the second GaN cap layer (15) is provided with a second source (19), a second drain (20) and a second gate (21) spaced apart from each other; The first AlN layer (2) is generated by reaction at a temperature of 1050℃-1150℃, and the second AlN layer (3) is generated by reaction at a temperature of 1150℃-1250℃.

2. The CMOS transistor based on a double heterojunction according to claim 1, characterized in that, The P-HEMT active region groove (6) and the N-HEMT active region groove (10) are symmetrically formed inside the SiN isolation layer (5), and both extend from one side of the SiN isolation layer (5) to the opposite side.

3. The CMOS transistor based on a double heterojunction according to claim 1, characterized in that, The first source (16), the first drain (17), and the first gate (18) are mutually isolated by SiN material, and the first gate (18) is located between the first source (16) and the first drain (17); the second source (19), the second drain (20), and the second gate (21) are isolated by SiN material. They are isolated from each other, and the second gate (21) is located between the second source (19) and the second drain (20).

4. The CMOS transistor based on a double heterojunction according to claim 1, characterized in that, The substrate (1) and the first AlN layer (2) also include a pre-laid aluminum layer.

5. The CMOS transistor based on a double heterojunction according to claim 1, characterized in that, The surface areas of the GaPN back barrier layer (7), the first AlPN barrier layer (8), and the first GaPN channel layer (9) are equal, and are all equal to the inner surface area of ​​the P-HEMT active region groove (6); the surface areas of the AlPN back barrier layer (11), the second GaPN channel layer (12), and the second AlPN barrier layer (13) are equal, and are all equal to the inner surface area of ​​the N-HEMT active region groove (10).

6. The CMOS transistor based on a double heterojunction according to claim 1, characterized in that, The thickness of the GaPN back barrier layer (7) is 10-30 nm, the thickness of the first AlPN barrier layer (8) is 20-40 nm, the thickness of the first GaPN channel layer (9) is 10-30 nm, the thickness of the AlPN back barrier layer (11) is 20-40 nm, the thickness of the second GaPN channel layer (12) is 10-30 nm, and the thickness of the second AlPN barrier layer (13) is 20-40 nm.

7. The CMOS transistor based on a double heterojunction according to claim 1, characterized in that, The GaPN back barrier layer (7), the first AlPN barrier layer (8), and the first GaPN channel layer (9) form a double heterojunction structure GaPN / AlPN / GaPN; the AlPN back barrier layer (11), the second GaPN channel layer (12), and the second AlPN barrier layer (13) form a double heterojunction structure AlPN / GaPN / AlPN.

8. A method for fabricating a CMOS transistor based on a double heterojunction, characterized in that, The method for fabricating a CMOS transistor according to any one of claims 1 to 7 comprises: Select a substrate and pre-bake the substrate; A first AlN layer, a second AlN layer, and a GaN buffer layer are sequentially grown on the substrate. A SiN isolation layer is deposited on the GaN buffer layer, and a P-HEMT active region groove is etched on the SiN isolation layer. A GaPN back barrier layer and a first layer are formed from bottom to top in the active region groove of the P-HEMT. AlPN barrier layer and first GaPN channel layer; An N-HEMT active region groove is etched on the SiN isolation layer, and an AlPN back barrier layer, a second GaPN channel layer, and a second AlPN barrier layer are formed from bottom to top in the N-HEMT active region groove. A first GaN cap layer is grown on the first GaPN channel layer, and a second GaN cap layer is grown on the second AlPN barrier layer; A first source, a first drain, and a first gate are formed on the first GaN cap layer, and a second source, a second drain, and a second gate are formed on the second GaN cap layer.

9. The method for fabricating a CMOS transistor based on a double heterojunction according to claim 8, characterized in that, A first AlN layer, a second AlN layer, and a GaN buffer layer are sequentially grown on the substrate, including: Trimethylaluminum is introduced into the reaction chamber of the MOCVD equipment at a temperature of 1050℃-1150℃ to grow a pre-laid aluminum layer with a thickness of 30-100nm on the substrate. Trimethylaluminum and ammonia gas are introduced to grow a first layer with a thickness of 20-40 nm on the pre-laid aluminum layer. AlN layer; The reaction chamber temperature was adjusted to 1150-1250℃, and trimethylaluminum and ammonia gas were introduced to react in the first... A second AlN layer with a thickness of 150-200 nm is grown on top of the AlN layer; The reaction chamber temperature was adjusted to 1100-1200℃, and trimethylgallium and ammonia gas were introduced to react in the second... A GaN buffer layer with a thickness of 800-1000 nm is grown on the AlN layer.

10. The method for fabricating a CMOS transistor based on a double heterojunction according to claim 8 or 9, characterized in that, A GaPN back barrier layer, a first AlPN barrier layer, and a first GaPN channel layer are formed from bottom to top within the active region recess of the P-HEMT, including: At 1000-1150℃, trimethylgallium, tert-butylphosphine and ammonia are introduced to grow a GaPN back barrier layer with a thickness of 10-30nm in the active region groove of the P-HEMT, and the lower surface of the GaPN back barrier layer is in contact with the upper surface of the GaN buffer layer. The temperature of the reaction chamber of the MOCVD equipment is adjusted to 1150-1160℃, and trimethylaluminum, tert-butylphosphine and ammonia are introduced to react and generate a first AlPN barrier layer with a thickness of 20-40nm. The temperature of the MOCVD equipment reaction chamber is adjusted to 1070-1085℃, and trimethylgallium, tert-butylphosphine and ammonia are introduced to react and generate a first GaPN channel layer with a thickness of 10-30nm on the first AlPN barrier layer.

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