Display device

Abstract

Provided are a high-definition LED display device and a substrate for the LED display device. The LED display device comprises: a substrate; an insulating layer on the substrate; a plurality of first mounting electrodes and a second mounting electrode, provided on a first surface of the insulating layer; and a light-emitting element; in a display region, the second mounting electrode comprises a plurality of first portions extending in a first direction and arranged at intervals in a second direction intersecting the first direction, a plurality of second portions extending in a second direction and arranged at intervals in the first direction, and a plurality of openings; each opening is surrounded by a pair of adjacent first portions among the plurality of first portions and a pair of adjacent second portions among the plurality of second portions; each opening surrounds at least one first mounting electrode among the plurality of first mounting electrodes; and the light-emitting element comprises a first electrode connected to one first mounting electrode and a second electrode connected to the second mounting electrode, and is mounted astride the first mounting electrode and the second mounting electrode.

Description

[0001] This application is a divisional application of the Chinese patent application with application number "201980058445.6", application date "2019 / 08 / 28", and invention name "Display Device". Technical Field

[0002] The present invention relates to a display device. Background Art

[0003] As a display device, LED display devices using light emitting diodes (LEDs) as self-luminous elements are known. In recent years, as a more sophisticated display device, display devices in which tiny light emitting diodes called micro LEDs are mounted on an array substrate (hereinafter referred to as micro LED display devices) have been developed.

[0004] Micro LED displays are different from conventional liquid crystal displays or organic EL displays. They are formed by installing many chip-shaped micro LEDs in the display area, so it is easier to achieve both high precision and large size, and are attracting attention as the next generation of display devices.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2018-26540 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] The present invention provides a display device capable of achieving higher definition.

[0010] Means used to solve problems

[0011] An LED display device according to a technical solution comprises: a substrate; an insulating layer on the substrate; a plurality of first mounting electrodes and a second mounting electrode, which are arranged on the first surface of the insulating layer; and a light-emitting element; in a display area, the second mounting electrode has a plurality of first portions extending in a first direction and arranged at intervals in a second direction intersecting the first direction, a plurality of second portions extending in the second direction and arranged at intervals in the first direction, and a plurality of openings; each of the openings is surrounded by a pair of adjacent first portions among the plurality of first portions and a pair of adjacent second portions among the plurality of second portions; each of the openings surrounds at least one of the plurality of first mounting electrodes; the light-emitting element has a first electrode connected to the one first mounting electrode and a second electrode connected to the second mounting electrode, and is mounted across the first mounting electrode and the second mounting electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a perspective view showing the structure of the display device according to the first embodiment.

[0013] Figure 2 is a circuit diagram showing the above-mentioned display device.

[0014] Figure 3 Yes Figure 2 The equivalent circuit diagram of the pixel shown.

[0015] Figure 4 Yes Figure 1 The partial cross-sectional view of the display region of the display panel shown shows a driving transistor, a first mounting electrode, a second mounting electrode, a light-emitting element, and the like.

[0016] Figure 5 This is a schematic diagram showing the arrangement structure of a plurality of pixels of the above-mentioned display device.

[0017] Figure 6 Yes Figure 5 A plan view of the primary pixel is shown.

[0018] Figure 7 1 is a plan view showing the display panel, and is a diagram showing the overall structure of the power supply line and the second mounting electrode.

[0019] Figure 8 It is along Figure 7 Line VIII-VIII is a partial cross-sectional view of the display area and the non-display area of ​​the display panel, showing a power supply line, a second mounting electrode, and the like.

[0020] Figure 9 It is an enlarged plan view showing a portion of the display area of ​​the display panel, and is a diagram showing a portion of the second implementation electrode and a plurality of first implementation electrodes.

[0021] Figure 10 1 is a cross-sectional view showing a portion of the display region of the display panel, and shows a first implementation electrode, a second implementation electrode, a light-emitting element, and the like.

[0022] Figure 11 is a cross-sectional view showing the light emitting element.

[0023] Figure 12 This is an enlarged plan view showing a plurality of first implementation electrodes and second implementation electrodes of the display device according to the second embodiment.

[0024] Figure 13 This is an enlarged plan view showing a plurality of first implementation electrodes and second implementation electrodes of a display device according to a first modification of the second embodiment.

[0025] Figure 14 This is an enlarged plan view showing a plurality of first implementation electrodes and second implementation electrodes of a display device according to a second modification of the second embodiment.

[0026] Figure 15 This is an enlarged plan view showing a plurality of first implementation electrodes and second implementation electrodes of a display device according to a third modification of the second embodiment.

[0027] Figure 16 This is a cross-sectional view showing a portion of the display region of the display panel according to the third modification, showing a first implementation electrode, a second implementation electrode, a light-emitting element, and the like.

[0028] Figure 17 This is an enlarged plan view showing a plurality of first implementation electrodes and second implementation electrodes of a display device according to a fourth modification of the second embodiment. DETAILED DESCRIPTION

[0029] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the disclosure is merely an example, and solutions that can be easily conceived by those skilled in the art for appropriate changes that maintain the main purpose of the invention are included in the scope of the present invention. In addition, in order to make the description clearer, the drawings schematically show the width, thickness, shape, etc. of each part compared to the actual form, but this is merely an example and does not limit the interpretation of the present invention. In addition, in this specification and the drawings, the same reference numerals are given to the same elements as those described with respect to the drawings already given, and repeated detailed descriptions may be appropriately omitted.

[0030] (First embodiment)

[0031] First, the display device according to the first embodiment will be described. Figure 1 It is a perspective view showing the structure of the display device 1 according to this embodiment. Figure 1 The diagram shows a three-dimensional space defined by a first direction X, a second direction Y perpendicular to the first direction X, and a third direction Z perpendicular to both the first and second directions X and Y. The first and second directions X and Y are perpendicular to each other, but may intersect at angles other than 90 degrees. Furthermore, in this embodiment, the third direction Z is defined as upward, and the direction opposite to the third direction Z is defined as downward. In the cases of "a second component above the first component" and "a second component below the first component," the second component can be in contact with or spaced apart from the first component.

[0032] Hereinafter, in this embodiment, a case where the display device 1 is a micro LED display device using micro light emitting diodes (hereinafter referred to as micro LEDs (Light Emitting Diodes)) as self-luminous elements will be mainly described.

[0033] like Figure 1 As shown, the display device 1 includes a display panel 2 , a first circuit board 3 , a second circuit board 4 , and the like.

[0034] The display panel 2 has a rectangular shape in one example. In the example shown in the figure, the short side EX of the display panel 2 is parallel to the first direction X, and the long side EY of the display panel 2 is parallel to the second direction Y. The third direction Z corresponds to the thickness direction of the display panel 2. The main surface of the display panel 2 is parallel to the X-Y plane defined by the first direction X and the second direction Y. The display panel 2 has a display area DA and a non-display area NDA outside the display area DA. The non-display area NDA has a terminal area MT. In the example shown in the figure, the non-display area NDA surrounds the display area DA.

[0035] The display area DA is an area for displaying an image, and includes a plurality of pixels PX arranged in a matrix, for example.

[0036] The terminal region MT is provided along the short side EX of the display panel 2 and includes terminals for electrically connecting the display panel 2 to external devices or the like.

[0037] The first circuit substrate 3 is mounted on the terminal area MT and is electrically connected to the display panel 2. The first circuit substrate 3 is, for example, a flexible printed circuit substrate. The first circuit substrate 3 includes a driver IC chip (hereinafter referred to as a panel driver) 5 for driving the display panel 2. In addition, in the example shown in the figure, the panel driver 5 is arranged on the first circuit substrate 3, but it can also be arranged below the first circuit substrate 3. Alternatively, the panel driver 5 can also be mounted outside the first circuit substrate 3, for example, it can also be mounted on the second circuit substrate 4. The second circuit substrate 4 is, for example, a flexible printed circuit substrate. The second circuit substrate 4 is connected to the first circuit substrate 3, for example, below the first circuit substrate 3.

[0038] The panel driver 5 is connected to a control board (not shown) via, for example, the second circuit board 4. The panel driver 5 drives the plurality of pixels PX based on, for example, a video signal output from the control board, thereby controlling image display on the display panel 2.

[0039] The display panel 2 may also include a bending area BA, indicated by diagonal lines. The bending area BA is a region that is bent when the display device 1 is housed in a housing of an electronic device, etc. The bending area BA is located on the terminal area MT side of the non-display area NDA. When the bending area BA is bent, the first circuit board 3 and the second circuit board 4 are arranged below the display panel 2, facing the display panel 2.

[0040] Figure 2 2 is a circuit diagram showing the display device 1 . Figure 3 Yes Figure 2 The equivalent circuit diagram of the pixel PX shown.

[0041] like Figure 2 and Figure 3 As shown, the display panel 2 includes a light-transmitting insulating substrate SUB such as a resin substrate or a glass substrate, m×n pixels PX arranged in a matrix on the substrate SUB in a display area DA, a plurality of (m / 2) first scanning lines Sga (1 to m / 2), a plurality of (m) second scanning lines Sgb (1 to m), a plurality of (m / 2) third scanning lines Sgc (1 to m / 2), a plurality of (m / 2) reset wirings Sgr (1 to m / 2) and a plurality of (n) image signal lines VL (1 to n).

[0042] There are m pixels PX arranged in the second direction Y and n pixels PX arranged in the first direction X. A first scanning line Sga, a second scanning line Sgb, and a reset line Sgr extend in the first direction X. The reset line Sgr is formed by a plurality of electrodes electrically connected to each other. A video signal line VL extends in the second direction Y.

[0043] The display panel 2 includes a high-potential power supply line SLa fixed to a high potential Pvdd and a low-potential power supply electrode (second mounting electrode) SLb fixed to a low potential Pvss. The high-potential power supply line SLa is connected to a high-potential power supply, while the low-potential power supply electrode SLb is connected to a low-potential power supply (reference potential power supply).

[0044] The display panel 2 includes scan line driver circuits YDR1 and YDR2 that sequentially drive the first scan line Sga, the second scan line Sgb, and the third scan line Sgc for each row of pixels PX, and a signal line driver circuit XDR that drives the video signal line VL. The scan line driver circuits YDR1 and YDR2 and the signal line driver circuit XDR are formed on the substrate SUB in the non-display area NDA and, together with the panel driver 5, constitute a driver unit 7.

[0045] Each pixel PX includes a display element and a pixel circuit that supplies a driving current to the display element. The light-emitting element 10 is, for example, a self-luminous element, and in this embodiment, a micro light-emitting diode (hereinafter referred to as a micro LED). The display device 1 of this embodiment is a micro LED display device.

[0046] The pixel circuit of each pixel PX is a voltage-signal-based pixel circuit that controls the light emission of the light-emitting element 10 based on a video signal Vsig composed of a voltage signal. It includes a pixel switch SST, a drive transistor DRT, a holding capacitor Cs, and an auxiliary capacitor Cad. The holding capacitor Cs and auxiliary capacitor Cad are capacitors. The auxiliary capacitor Cad is provided to adjust the light emission current, but may not be required depending on the situation. The capacitor portion Cled is the capacitance of the light-emitting element 10 itself. The light-emitting element 10 also functions as a capacitor.

[0047] Each pixel PX includes an output switch BCT. Multiple pixels PX adjacent in the second direction Y share the output switch BCT. In this embodiment, four pixels PX adjacent in the first direction X and the second direction Y share one output switch BCT. Furthermore, the scan line driver circuit YDR2 (or scan line driver circuit YDR1) is provided with multiple reset switches RST. The reset switches RST are connected to the reset wiring Sgr on a one-to-one basis.

[0048] The pixel switch SST, drive transistor DRT, output switch BCT, and reset switch RST are formed here using TFTs (thin-film transistors) of the same conductivity type, for example, N-channel types. Of course, the various switches and drive transistor DRT may also be formed using P-channel TFTs, and a single pixel PX may also be formed using both N-channel and P-channel TFTs.

[0049] In the display device of this embodiment, the TFTs that constitute each driver transistor and each switch are all formed using the same process and layer structure. These thin-film transistors have a top-gate structure using polycrystalline silicon as the semiconductor layer. Alternatively, the semiconductor layer may utilize semiconductors other than polycrystalline silicon, such as amorphous silicon and oxide semiconductors.

[0050] The pixel switch SST, the drive transistor DRT, the output switch BCT, and the reset switch RST each have a first terminal, a second terminal, and a control terminal. In this embodiment, the first terminal is a source electrode, the second terminal is a drain electrode, and the control terminal is a gate electrode.

[0051] In the pixel circuit of the pixel PX, the drive transistor DRT and the output switch BCT are connected in series with the light-emitting element 10 between the high-potential power supply line SLa and the low-potential power supply electrode SLb. The high-potential power supply line SLa (high potential Pvdd) is set to, for example, 10V, and the low-potential power supply electrode SLb (low potential Pvss) is set to, for example, 0V.

[0052] The output switch BCT has a drain electrode connected to the high-potential power supply line SLa, a source electrode connected to the drain electrode of the drive transistor DRT, and a gate electrode connected to the first scanning line Sga. Thus, the output switch BCT is controlled to be on (conductive state) or off (non-conductive state) by a control signal BG applied to the first scanning line Sga. The output switch BCT controls the light-emission duration of the light-emitting element 10 in response to the control signal BG.

[0053] The drive transistor DRT has a drain electrode connected to the source electrode of the output switch BCT and the reset line Sgr, and a source electrode connected to one electrode (here, the anode) of the light-emitting element 10. The other electrode (here, the cathode) of the light-emitting element 10 is connected to the low-potential power supply electrode SLb. The drive transistor DRT outputs a drive current corresponding to the video signal Vsig to the light-emitting element 10.

[0054] In the pixel switch SST, the source electrode is connected to the video signal line VL(1-n), the drain electrode is connected to the gate electrode of the drive transistor DRT, and the gate electrode is connected to the second scanning line Sgb(1-m), which functions as a gate wiring for signal writing control. The pixel switch SST is turned on / off by a control signal SG(1-m) supplied from the second scanning line Sgb. Furthermore, in response to the control signal SG(1-m), the pixel switch SST controls the connection / disconnection between the pixel circuit and the video signal line VL(1-n), and receives the video signal Vsig and the initialization signal Vini from the video signal line VL into the pixel circuit.

[0055] Reset switches RST are provided in the scan line driver circuit YDR2 for every two rows arranged in the second direction Y. The reset switches RST are connected between the drain electrodes of the drive transistors DRT and the reset power supply. The reset switches RST have a source electrode connected to a reset power supply line SLc connected to the reset power supply, a drain electrode connected to a reset wiring Sgr, and a gate electrode connected to a third scan line Sgc, which functions as a reset control gate wiring. As described above, the reset power supply line SLc is connected to the reset power supply and is fixed to a fixed potential, Vrst.

[0056] The reset switch RST switches the reset power line SLc and the reset wiring Sgr between a conductive state (on) and a non-conductive state (off) according to a control signal RG supplied via the third scanning line Sgc. By switching the reset switch RST to the on state, the potential of the source electrode of the driving transistor DRT is initialized.

[0057] on the other hand, Figure 2 The panel driver 5 shown controls the scan line driver circuits YDR1 and YDR2 and the signal line driver circuit XDR. The panel driver 5 receives externally supplied digital video signals and synchronization signals and, based on the synchronization signals, generates vertical scanning control signals for controlling vertical scanning timing and horizontal scanning control signals for controlling horizontal scanning timing.

[0058] The panel driver 5 supplies the vertical scanning control signals and the horizontal scanning control signals to the scanning line driving circuits YDR1 and YDR2 and the signal line driving circuit XDR, respectively, and supplies the digital video signal and the initialization signal to the signal line driving circuit XDR in synchronization with the horizontal and vertical scanning timings.

[0059] The signal line driver circuit XDR converts the digital video signals sequentially obtained during each horizontal scanning period under the control of the horizontal scanning control signal into analog format and supplies the video signals Vsig corresponding to the grayscale levels in parallel to the plurality of video signal lines VL (1-n). Furthermore, the signal line driver circuit XDR supplies the initialization signal Vini to the video signal lines VL. Alternatively, the digital video signals may be converted into analog format within the panel driver 5 and supplied to the signal line driver circuit XDR in analog format.

[0060] Scan line driver circuits YDR1 and YDR2 include shift registers and output buffers (not shown). They output pulses based on an externally supplied horizontal scan start pulse and sequentially transmit these pulses to downstream stages. These pulses are then supplied to pixels PX in each row via the output buffers, supplying three control signals: control signals BG, SG, and RG. While control signal RG is not directly supplied to pixels PX, a predetermined voltage is supplied from a reset power supply line SLc, which is fixed at a reset potential Vrst, at predetermined timing corresponding to control signal RG.

[0061] Thus, the first scanning line Sga, the second scanning line Sgb, and the third scanning line Sgc are driven by the control signals BG, SG, and RG, respectively.

[0062] Next, refer to Figure 4 , the structures of the driving transistor DRT, the first mounting electrode PE, the second mounting electrode CE, the light emitting element 10, etc. will be described in detail. Figure 4 Yes Figure 1The partial cross-sectional view of the display area DA of the display panel 2 is a diagram showing the driving transistor DRT, the first mounting electrode PE, the second mounting electrode CE, the light emitting element 10, etc. Figure 4 In FIG, the display device 1 is depicted with its display surface, ie, the light emitting surface, facing upward and its back surface facing downward.

[0063] like Figure 4 As shown, the n-channel TFT forming the drive transistor DRT includes a semiconductor layer SC. The semiconductor layer SC is disposed on an insulating layer UC provided on a substrate SUB. The semiconductor layer SC is, for example, a polycrystalline silicon layer including p-type and n-type regions. The semiconductor layer SC is covered by an insulating layer GI. A gate electrode G of the drive transistor DRT is disposed on the insulating layer GI. The gate electrode G faces the semiconductor layer SC. An insulating layer II is provided on the insulating layer GI and the gate electrode G.

[0064] A source electrode SE and a drain electrode DE are arranged on the insulating layer II. The source electrode SE and the drain electrode DE are connected to the source region and the drain region of the semiconductor layer SC, respectively, through contact holes formed in the insulating layer II and the insulating layer GI. The source electrode SE is provided on the substrate SUB and functions as a first wiring layer located in the display area DA. An insulating layer PS is provided on the insulating layer II, the source electrode SE, and the drain electrode DE. The insulating layer PS covers the source electrode SE and the drain electrode DE. The insulating layer PS has a first opening (contact hole) OP1 that exposes a portion of the source electrode SE. The insulating layer PS also has a plurality of first openings OP1, each of which exposes a portion of the corresponding source electrode SE. The insulating layer PS functions as a first insulating layer.

[0065] The first mounting electrode PE and the second mounting electrode CE are provided on the insulating layer PS. The first mounting electrode PE passes through the first opening OP1 and is electrically connected to the source electrode SE. In this embodiment, the first mounting electrode PE and the second mounting electrode CE are formed of metal as a conductive material. However, the first mounting electrode PE and the second mounting electrode CE may be formed of a conductive material other than metal, for example, ITO (indium tin oxide), which is a transparent conductive material.

[0066] An insulating layer CL is provided over the insulating layer PS, the first mounting electrode PE, and the second mounting electrode CE, covering the first mounting electrode PE and the second mounting electrode CE. The insulating layer CL functions as a second insulating layer and has a plurality of openings that expose portions of the upper surfaces of the first mounting electrode PE and the second mounting electrode CE.

[0067] In the display area DA, the multiple openings (contact holes) of the insulating layer CL are divided into a third opening OP3 and a fourth opening OP4. A portion of the upper surface of the first mounting electrode PE is exposed outside the insulating layer CL through the third opening OP3. A portion of the upper surface of the second mounting electrode CE is exposed outside the insulating layer CL through the fourth opening OP4. The first mounting electrode PE and the second mounting electrode CE are located between the insulating layers PS and CL. Therefore, the first mounting electrode PE and the second mounting electrode CE are provided on the same layer.

[0068] The insulating layers UC, GI, II, PS, and CL are each formed of an inorganic insulating material such as silicon nitride (SiN) or silicon oxide (SiO), or an organic insulating material such as acrylic resin. In this embodiment, the insulating layers UC, GI, II, and CL are each formed of an inorganic insulating material, and the insulating layer PS is formed of an organic insulating material.

[0069] The light-emitting element 10 is mounted astride a first mounting electrode PE and a second mounting electrode CE. The light-emitting element 10 includes a first electrode E1 electrically connected to the first mounting electrode PE through a third opening OP3, and a second electrode E2 electrically connected to the second mounting electrode CE through a fourth opening OP4. In this embodiment, the first electrode E1 is electrically connected to the first mounting electrode PE via a conductor CM1, and the second electrode E2 is electrically connected to the second mounting electrode CE via a conductor CM2.

[0070] Next, the arrangement structure of the plurality of pixels PX will be described. Figure 5 1 is a schematic diagram showing the arrangement structure of a plurality of pixels PX of the display device 1 .

[0071] like Figure 5 As shown, the plurality of pixels PX include a blue (B) pixel PX, a red (R) pixel PX adjacent to the blue pixel PX in the second direction Y, a white (W) pixel PX adjacent to the blue pixel PX in the first direction X, and a green (G) pixel PX adjacent to the red pixel PX in the first direction X and adjacent to the white pixel PX in the second direction Y. The white (W) pixel PX is also called a colorless pixel.

[0072] The red pixel PX, the green pixel PX, the blue pixel PX, and the white pixel PX constitute the main pixel MP. The plurality of main pixels MP are arranged in a matrix in the first direction X and the second direction Y. When the plurality of main pixels MP are arranged as described above, the arrangement of the pixels PX is not limited to Figure 5 In the example shown, two of the red, green, blue, and white pixels PX may be arranged in even-numbered rows, and the remaining two may be arranged in odd-numbered rows.

[0073] The output switch BCT is shared by the four pixels PX of the main pixel MP. Based on the above, the number of the first scanning line Sga and the third scanning line Sgc is m / 2.

[0074] Furthermore, the four pixels PX of the main pixel MP may be arranged in stripes in the first direction X. Furthermore, the main pixel MP may have three (three-color) pixels PX of red, green, and blue instead of the white pixel PX.

[0075] Figure 6 1 is a plan view showing the main pixel MP according to this embodiment.

[0076] like Figure 6 As shown, to efficiently arrange the components within the pixel circuit, the four pixels PX that share the output switch BCT are arranged so that the drive transistor DRT, pixel switch SST, video signal line VL, holding capacitor Cs, auxiliary capacitor Cad, and second scan line Sgb are substantially line-symmetrical in the column and row directions around the output switch BCT. While this embodiment uses the terms pixel PX and primary pixel MP, these pixels can be referred to as sub-pixels instead. In this case, the primary pixel is a pixel.

[0077] Next, the overall structure of the second mount electrode CE and the power supply line will be described. Figure 7 2 is a plan view showing the display panel 2 , and is a diagram showing the overall structure of the power supply line PSL and the second mount electrode CE.

[0078] like Figure 7 As shown, the display panel 2 includes power lines PSL provided on the substrate SUB. In this embodiment, the display panel 2 includes two power lines PSL, but may also include one or more power lines PSL. Each power line PSL is located in the non-display area NDA and not in the display area DA. In this embodiment, the power lines PSL are connected to a low-potential power supply and are fixed at a low potential Pvss. The power lines PSL function as a second wiring layer.

[0079] The second implementation electrode CE is located throughout the display area DA and part of the non-display area NDA. In the non-display area NDA, the second implementation electrode CE overlaps with each power supply line PSL. The second implementation electrode CE has multiple openings, through which the first implementation electrode PE is exposed. Details will be described later.

[0080] Figure 8 It is along Figure 7 A line VIII-VIII is a partial cross-sectional view of the display area DA and the non-display area NDA of the display panel 2 , and is a diagram showing the power supply line PSL, the second mount electrode CE, and the like.

[0081] like Figure 8 As shown, the power lines PSL are provided on the insulating layer II. The insulating layer PS is located not only in the display area DA but also in the non-display area NDA. In the non-display area NDA, the insulating layer PS covers the power lines PSL and has second openings (contact holes) OP2 that partially expose each power line PSL. The second mounting electrode CE is provided on the insulating layer PS and electrically connected to the power lines PSL in the non-display area NDA through the second openings OP2. The insulating layer PS does not have an opening in the display area DA for connecting the second mounting electrode CE to the power lines PSL.

[0082] Next, the structures of the first mounting electrode PE, the second mounting electrode CE, and the light emitting element 10 will be described. Figure 9 It is an enlarged plan view showing a portion of the display area DA of the display panel 2 , and is a diagram showing a portion of the second implementation electrode CE and a plurality of first implementation electrodes PE.

[0083] like Figure 9 As shown, the second mounting electrode CE includes multiple first portions CE1 and multiple second portions CE2. The multiple first portions CE1 extend in the first direction X and are spaced apart in the second direction Y. The multiple second portions CE2 extend in the second direction Y and are spaced apart in the first direction X, intersecting the multiple first portions CE1. The multiple first portions CE1 and the multiple second portions CE2 of the second mounting electrode CE are integrally formed. The second mounting electrode CE has multiple openings A, each of which corresponds to an area enclosed by a pair of adjacent first portions CE1 and a pair of adjacent second portions CE2. The second mounting electrode CE functions not only as an electrode but also as wiring.

[0084] In this embodiment, the blue pixel PX functions as the first pixel PX1 , the red pixel PX functions as the second pixel PX2 , the white pixel PX functions as the third pixel PX3 , and the green pixel PX functions as the fourth pixel PX4 .

[0085] The first pixel PX1 has a first mounting electrode PE1 and a light-emitting element (first light-emitting element) 10a that emits blue light. The second pixel PX2 has a first mounting electrode PE2 and a light-emitting element (second light-emitting element) 10b that emits red light. The third pixel PX3 has a first mounting electrode PE3 and a light-emitting element (third light-emitting element) 10c that emits white light. The fourth pixel PX4 has a first mounting electrode PE4 and a light-emitting element (first light-emitting element) 10d that emits green light. The first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 share the second mounting electrode CE. In a plan view, the length of one side of the light-emitting element 10, which is a micro LED, is, for example, less than 100 μm.

[0086] One or more first mounting electrodes from the plurality of first mounting electrodes PE are arranged in each area (opening A) surrounded by a pair of adjacent first portions CE1 and a pair of adjacent second portions CE2. In this embodiment, four first mounting electrodes are arranged in each opening A. In other words, the second mounting electrodes CE are arranged so as to individually surround one or more first mounting electrodes PE. In this embodiment, the second mounting electrodes CE are arranged so as to individually surround four first mounting electrodes PE: the first mounting electrodes PE2 and PE4 of one primary pixel MP and the first mounting electrodes PE1 and PE3 of another primary pixel MP. In each opening A, the four first mounting electrodes PE are arranged at intervals from one another.

[0087] A first portion CE1 is located between the electrode group of the first mounting electrode PE1 and the first mounting electrode PE3 and the electrode group of the first mounting electrode PE2 and the first mounting electrode PE4 of a primary pixel MP. The light-emitting elements 10a to 10d overlap with the same first portion CE1 among the multiple first portions CE1. In a primary pixel MP, for example, the light-emitting elements 10a and 10b are arranged line-symmetrically in the second direction Y, and the light-emitting elements 10c and 10d are arranged line-symmetrically in the second direction Y.

[0088] Figure 10 1 is a cross-sectional view showing a portion of the display area DA of the display panel 2, and is a diagram showing the first mounting electrode PE, the second mounting electrode CE, and the light emitting elements 10a and 10b. Figure 10 In FIG. 1 , attention is paid to a first pixel PX1 and a second pixel PX2 of one main pixel MP.

[0089] like Figure 10 As shown, multiple first mounting electrodes PE are located in the display area DA and are provided on the insulating layer PS. Each first mounting electrode PE is electrically connected to one of the multiple source electrodes SE through one of the multiple first openings OP1. The insulating layer CL covers the multiple first mounting electrodes PE and the second mounting electrodes CE. The insulating layer CL has multiple openings that expose portions of the upper surface of each first mounting electrode PE and multiple locations of the upper surface of the second mounting electrode CE. These multiple openings are the multiple third openings OP3 and the multiple fourth openings OP4 located in the display area DA.

[0090] A portion of the top surface of each first implementation electrode PE is exposed outside the insulating layer CL through a corresponding one of the plurality of third openings OP3. As multiple portions of the top surface of the second implementation electrode CE, multiple portions of the top surface of the first portion CE1 are exposed outside the insulating layer CL through a plurality of fourth openings OP4.

[0091] The light-emitting element 10a is mounted across one first mounting electrode PE1 and the second mounting electrode CE (first portion CE1). The light-emitting element 10b is mounted across another first mounting electrode PE2 and the second mounting electrode CE (first portion CE1). The second electrode E2 of the light-emitting element 10a and the second electrode E2 of the second light-emitting element 10b each face the same first portion CE1.

[0092] In the light-emitting element 10a, the first electrode E1 is electrically connected to a first mounting electrode PE1 through a corresponding third opening OP3, and the second electrode E2 is electrically connected to the second mounting electrode CE (first portion CE1) through a fourth opening OP4. In the light-emitting element 10b, the first electrode E1 is electrically connected to another first mounting electrode PE2 through a corresponding third opening OP3, and the second electrode E2 is electrically connected to the second mounting electrode CE (first portion CE1) through another fourth opening OP4.

[0093] Next, an example of the structure of the light emitting element 10 will be described. Figure 11 2 is a cross-sectional view showing the light emitting element 10 .

[0094] like Figure 11 As shown, the light-emitting element 10 is a flip-chip light-emitting diode element. The light-emitting element 10 has a transparent substrate 11 with insulating properties. The substrate 11 is, for example, a sapphire substrate. On the main surface of the substrate 11, a crystal layer (semiconductor layer) is formed in which an n-type semiconductor layer 12, an active layer (light-emitting layer) 13 and a p-type semiconductor layer 14 are stacked in this order. In the above-mentioned crystal layer (semiconductor layer), the region containing P-type impurities is the p-type semiconductor layer 14, and the region containing N-type impurities is the n-type semiconductor layer 12. The material of the above-mentioned crystal layer (semiconductor layer) is not particularly limited, and the above-mentioned crystal layer (semiconductor layer) may contain gallium nitride (GaN) or gallium arsenide (GaAs).

[0095] Light-reflecting film 15 is formed of a conductive material and is electrically connected to p-type semiconductor layer 14. P-electrode 16 is electrically connected to light-reflecting film 15. N-electrode 18 is electrically connected to n-type semiconductor layer 12. Second electrode E2 covers n-electrode 18 and is electrically connected to n-electrode 18. Protective layer 17 covers n-type semiconductor layer 12, active layer 13, p-type semiconductor layer 14, and light-reflecting film 15, and also covers a portion of p-electrode 16. First electrode E1 covers p-electrode 16 and is electrically connected to p-electrode 16.

[0096] In the display device 1 of the first embodiment configured as described above, the second mounting electrode CE is arranged to surround the first mounting electrode PE. Therefore, wiring fixed to the low potential Pvss need not be arranged in the layer closer to the substrate SUB than the first mounting electrode PE. This increases the area of ​​the second mounting electrode CE. For example, this allows for greater margin when mounting the light-emitting element 10.

[0097] Furthermore, since the second mounting electrode CE is routed within the display area DA, the resistance of the second mounting electrode CE can be reduced. Furthermore, since the voltage drop across the second mounting electrode CE can be minimized, the potential uniformity of the second mounting electrode CE across the entire display area DA can be improved. Furthermore, higher-definition pixels can be achieved.

[0098] Furthermore, by laying out the first mounting electrode PE and the second mounting electrode CE in this manner, both can be formed from the same conductive layer. As a result, the surfaces of the first mounting electrode PE and the second mounting electrode CE are highly aligned with each other, enabling good mounting of the light emitting element 10.

[0099] The main pixels MP share the output switch BCT. Compared to providing one output switch BCT for each pixel PX, this reduces the number of output switches BCT to one-quarter, reduces the number of first scan lines Sga, third scan lines Sgc, and reset lines Sgr to one-half, and reduces the number of reset switches RST to one-half. This contributes to narrower bezels and higher-definition pixels in the display device.

[0100] Based on the above, a display device capable of achieving high definition can be obtained.

[0101] (Second embodiment)

[0102] Next, a display device 1 according to a second embodiment will be described. Figure 12 It is an enlarged plan view showing a plurality of first implementation electrodes PE and second implementation electrodes CE of the display device 1 according to the second embodiment.

[0103] like Figure 12As shown, the main pixel MP includes three color pixels PX arranged in the first direction X. In each main pixel MP, the red pixel PX functions as the first pixel PX1, the green pixel PX functions as the second pixel PX2, and the blue pixel PX functions as the third pixel PX3. The first pixel PX1 includes a first mounting electrode PE1 and a light-emitting element (first light-emitting element) 10a that emits red light. The second pixel PX2 includes a first mounting electrode PE2 and a light-emitting element (second light-emitting element) 10b that emits green light. The third pixel PX3 includes a first mounting electrode PE3 and a light-emitting element (third light-emitting element) 10c that emits blue light.

[0104] exist Figure 12 In the illustrated example, unlike the first embodiment described above, a single first implementation electrode PE is disposed in each region (each opening A) enclosed by a pair of adjacent first portions CE1 and a pair of adjacent second portions CE2. The first implementation electrodes PE1 and the second portions CE2 are alternately disposed in the first direction X. Consequently, the width of the second portions CE2 in the first direction X can be reduced compared to the first embodiment described above.

[0105] The first mounting electrodes PE1 and the first portions CE1 are alternately arranged in the second direction Y. Of the two primary pixels MP arranged in the second direction Y, the first portion CE1 used in one primary pixel MP is different from the first portion CE1 used in the other primary pixel MP. Therefore, the width of the first portion CE1 in the second direction Y can be reduced compared to the first embodiment described above.

[0106] The display device 1 of the second embodiment, constructed as described above, also achieves the same effects as the first embodiment. In this embodiment, the first implementation electrodes PE1 and the second portions CE2 are alternately arranged in the first direction X. This further reduces the resistance of the second implementation electrodes CE. Furthermore, the center of light emission can be easily determined.

[0107] (Variation 1 of the Second Embodiment)

[0108] Next, a first modification of the above-mentioned second embodiment will be described. Figure 13 It is an enlarged plan view showing a plurality of first implementation electrodes PE and second implementation electrodes CE of the display device 1 according to the first modification of the second embodiment.

[0109] like Figure 13 As shown, all the first mounting electrodes PE of one main pixel MP are arranged in each region (each opening A) surrounded by a pair of adjacent first portions CE1 and a pair of adjacent second portions CE2 , which is different from the second embodiment.

[0110] The display device 1 of Modification 1, constructed as described above, also achieves the same effects as those of the second embodiment. Unlike the second embodiment, Modification 1 does not alternately arrange the first mounting electrodes PE and the second portions CE2 in the first direction X. Therefore, compared to the second embodiment, this is advantageous in achieving higher definition.

[0111] (Variation 2 of the Second Embodiment)

[0112] Next, a second modification of the above-mentioned second embodiment will be described. Figure 14 It is an enlarged plan view showing a plurality of first implementation electrodes PE and second implementation electrodes CE of a display device 1 according to a second modification of the second embodiment.

[0113] like Figure 14 As shown, in each region (each opening A) surrounded by a pair of adjacent first portions CE1 and a pair of adjacent second portions CE2, all of the first mounting electrodes PE of two primary pixels MP adjacent in the second direction Y are arranged, which is different from the above-described first modification. Furthermore, all of the light-emitting elements 10 of two primary pixels MP adjacent in the second direction Y overlap with the same first portion CE1 among the plurality of first portions CE1. The two light-emitting elements 10 adjacent in the second direction Y are arranged line-symmetrically in the second direction Y.

[0114] The display device 1 of Modification 2 configured as described above also achieves the same effects as those of the second embodiment. In Modification 2, two primary pixels MP adjacent to each other in the second direction Y utilize the same first portion CE1. Therefore, the layout efficiency of the second mounting electrode CE can be improved compared to the second embodiment.

[0115] (Variation 3 of the Second Embodiment)

[0116] Next, a third modification of the above-mentioned second embodiment will be described. Figure 15 It is an enlarged plan view showing a plurality of first implementation electrodes PE and second implementation electrodes CE of a display device 1 according to a third modification of the second embodiment.

[0117] like Figure 15 As shown, in Modification 3, each light-emitting element 10 is mounted astride a first portion CE1 located between a pair of first mounting electrodes PE and second mounting electrodes CE, which differs from the second embodiment described above. Each light-emitting element 10 is shared by a pair of pixels PX of the same color in two primary pixels MP adjacent in the second direction Y.

[0118] Figure 161 is a cross-sectional view showing a portion of the display area DA of the display panel 2 according to the third modification, and is a diagram showing the first mounting electrode PE, the second mounting electrode CE, the light emitting element 10, and the like. Figure 16 , a pair of first pixels PX1 of the same color are shown in two primary pixels MP adjacent to each other in the second direction Y. Figure 16 The relationship between the pair of first pixels PX1 shown is the same as the relationship between the pair of second pixels PX2 and the relationship between the pair of third pixels PX.

[0119] like Figure 16 As shown, the light-emitting element 10 further includes a first electrode E1a, another first electrode E1b, and a second electrode E2. The light-emitting element 10 comprises a single continuous semiconductor layer. The semiconductor layer of the light-emitting element 10 includes two light-emitting layers 13a and 13b spaced apart from each other. In the light-emitting element 10, the first electrodes E1a and E1b are connected one-to-one to a pair of first mounting electrodes PE. The second electrode E2 is connected to a first portion CE1 of the second mounting electrode CE located between the pair of first mounting electrodes PE.

[0120] The light-emitting layer 13a emits light when current flows between the first electrode E1a and the second electrode E2. The light-emitting layer 13b emits light when current flows between the first electrode E1b and the second electrode E2. The light-emitting layers 13a and 13b emit light of the same color.

[0121] The display device 1 of Modification 3 configured as described above can also achieve the same effects as those of Embodiment 2. In Modification 3, since light emitting elements 10 that emit light at two locations are used, the light emitting elements 10 can be arranged more efficiently.

[0122] (Variation 4 of the Second Embodiment)

[0123] Next, a fourth modification of the above-mentioned second embodiment will be described. Figure 17 It is an enlarged plan view showing a plurality of first implementation electrodes PE and second implementation electrodes CE of a display device 1 according to a fourth modification of the second embodiment.

[0124] like Figure 17 As shown, the multiple light-emitting elements 10 in each primary pixel MP are not arranged in vertical stripes (not aligned in the first direction X). This modification example 4 differs from the second embodiment described above in this respect. In each primary pixel MP, the multiple light-emitting elements 10 can be arranged close to each other as a group. In this modification example 4, in a primary pixel MP, the light-emitting element 10a and the light-emitting element 10c are adjacent to each other in the first direction X, and the light-emitting element 10b is adjacent to the light-emitting element 10a and the light-emitting element 10c in the second direction Y.

[0125] The light-emitting element 10a overlaps with the first mounting electrode PE1 and the portion of the second mounting electrode CE adjacent to the first mounting electrode PE1 in the second direction Y. The light-emitting element 10c overlaps with the first mounting electrode PE3 and the portion of the second mounting electrode CE adjacent to the first mounting electrode PE3 in the second direction Y. The light-emitting element 10b overlaps with the first mounting electrode PE2 and the portion of the second mounting electrode CE adjacent to the first mounting electrode PE2 in the first direction X.

[0126] The second mounting electrodes CE are laid out so as to match the arrangement pattern of the light emitting elements 10. Therefore, as in the fourth modification, the opening A may have a shape other than a quadrilateral.

[0127] Even in the display device 1 according to the fourth modification configured as described above, the same effects as those of the second embodiment can be obtained.

[0128] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0129] The arrangement pattern of the plurality of light emitting elements 10 in each primary pixel MP is not limited to the above example and can be variously modified. For example, the plurality of light emitting elements 10 in the primary pixel MP can be arranged in a horizontal stripe pattern, or in other words, can be arranged in the second direction Y.

Claims

1. An LED display device, characterized in that: have: substrate; an insulating layer on the substrate; a plurality of first mounting electrodes and a second mounting electrode provided on the first surface of the insulating layer; and Light-emitting element; In the display area, the second mounting electrode includes a plurality of first portions extending in a first direction and arranged at intervals in a second direction intersecting the first direction, a plurality of second portions extending in the second direction and arranged at intervals in the first direction, and a plurality of openings. Each of the openings is surrounded by a pair of adjacent first portions among the plurality of first portions and a pair of adjacent second portions among the plurality of second portions; Each of the openings surrounds at least one of the plurality of first implementation electrodes; The light emitting element includes a first electrode connected to the one first mounting electrode and a second electrode connected to the second mounting electrode, and is mounted astride the first mounting electrode and the second mounting electrode. A power supply line is further provided in a non-display area surrounding the display area; The power line is provided between the substrate and a second surface of the insulating layer opposite to the first surface and facing the substrate; The second mounting electrode extends from the display area to the non-display area; In the non-display region, the second mounting electrode is connected to the power line via a contact hole formed in the insulating layer.

2. An LED display device, characterized in that: have: substrate; an insulating layer on the substrate; a plurality of first mounting electrodes and a second mounting electrode provided on the first surface of the insulating layer; and Light-emitting element; In the display area, the second mounting electrode includes a plurality of first portions extending in a first direction and arranged at intervals in a second direction intersecting the first direction, and a plurality of second portions extending in the second direction and arranged at intervals in the first direction, formed in a grid pattern. At least one of the plurality of first implementation electrodes is located in an opening of the second implementation electrode surrounded by a pair of adjacent first portions of the plurality of first portions and a pair of adjacent second portions of the plurality of second portions. The light emitting element includes a first electrode connected to the one first mounting electrode and a second electrode connected to the second mounting electrode, and is mounted astride the first mounting electrode and the second mounting electrode. A power supply line is further provided in a non-display area surrounding the display area; The power line is provided between the substrate and a second surface of the insulating layer opposite to the first surface and facing the substrate; The second mounting electrode extends from the display area to the non-display area; In the non-display region, the second mounting electrode is connected to the power line via a contact hole formed in the insulating layer.

3. The LED display device according to claim 1 or 2, wherein: The plurality of first implementation electrodes and the second implementation electrode are in contact with the first surface.

4. The LED display device according to claim 3, wherein: The insulating layer is formed of an organic insulating material.

5. The LED display device according to claim 1 or 2, wherein: Each of the openings surrounds only the one first implementation electrode among the plurality of first implementation electrodes.

6. The LED display device according to claim 1 or 2, wherein: Each of the openings surrounds two or more of the plurality of first implementation electrodes.

7. The LED display device according to claim 1 or 2, wherein: The plurality of openings are arranged in a matrix in the display area.

8. The LED display device according to claim 1 or 2, wherein: The width of the first portion in the second direction is greater than the width of the second portion in the first direction.

9. A substrate for an LED display device, comprising: a substrate; an insulating layer on the substrate; and a plurality of first mounting electrodes and second mounting electrodes provided on a first surface of the insulating layer. The above-mentioned substrate for LED display device is characterized in that: In the LED mounting region, the second mounting electrode includes a plurality of first portions extending in a first direction and arranged at intervals in a second direction intersecting the first direction, a plurality of second portions extending in the second direction and arranged at intervals in the first direction, and a plurality of openings. Each of the openings is surrounded by a pair of adjacent first portions among the plurality of first portions and a pair of adjacent second portions among the plurality of second portions; Each of the openings surrounds at least one of the plurality of first implementation electrodes; The one first mounting electrode is an electrode connected to the first electrode of the light-emitting element having a first electrode and a second electrode on the substrate side; The second mounting electrode is an electrode for mounting the second electrode; A power line is further provided in a non-LED installation area surrounding the LED installation area; The power line is provided between the substrate and a second surface of the insulating layer opposite to the first surface and facing the substrate; The second mounting electrode extends from the LED mounting area to the non-LED mounting area; In the non-LED mounting region, the second mounting electrode is connected to the power line via a contact hole formed in the insulating layer.

10. The substrate for an LED display device according to claim 9, wherein The plurality of first implementation electrodes and the second implementation electrode are in contact with the first surface.

11. The substrate for an LED display device according to claim 10, wherein: The insulating layer is formed of an organic insulating material.

12. The substrate for an LED display device according to claim 9, wherein: Each of the openings surrounds only the one first implementation electrode among the plurality of first implementation electrodes.

13. The substrate for an LED display device according to claim 9, wherein Each of the openings surrounds two or more of the plurality of first implementation electrodes.

14. The substrate for an LED display device according to claim 9, wherein The plurality of openings are provided in a matrix in the LED mounting area.

15. The substrate for an LED display device according to claim 9, wherein The width of the first portion in the second direction is greater than the width of the second portion in the first direction.

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