Display panel and mobile terminal

Abstract

The application discloses a display panel and a mobile terminal; the display panel comprises display parts, each display part comprises a substrate, an auxiliary electrode, a planarization layer covering the edge of the auxiliary electrode, a common layer and a cathode layer, the planarization layer has an auxiliary contact hole corresponding to the auxiliary electrode, and a bridging layer is arranged on the auxiliary electrode in the auxiliary contact hole, wherein the common layer is provided with a first via hole in the part corresponding to the auxiliary contact hole, and the cathode layer is electrically connected with the bridging layer through the first via hole; the application electrically connects the cathode layer with the bridging layer through the first via hole on the common layer, reduces the resistance of the cathode layer, improves the voltage drop phenomenon, improves the display uniformity of the display panel, and, compared with the prior art, reduces the wiring space occupied by the metal electrode between the cathode and the auxiliary electrode, thereby reducing the bridging area between different film layers, and further facilitating the preparation of a high-resolution display panel and improving the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a mobile terminal. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have garnered widespread attention due to their superior display characteristics and quality compared to LCDs, such as thinner and lighter designs, shorter response times, lower driving voltages, better color reproduction, and improved viewing angles. Their development has been rapid in recent years, enabling the creation of curved displays and a gradual shift towards larger sizes. However, the voltage drop issue in large-size OLED displays, caused by their larger size and thinner cathodes, is particularly challenging to address, especially for top-emitting panels, which are highly susceptible to visible mura (display unevenness).

[0003] Currently, auxiliary electrodes are often connected in parallel with the cathode layer to improve voltage drop. This typically involves depositing a separate metal electrode layer between the cathode and auxiliary electrodes to achieve overlap. However, depositing a separate metal electrode layer adds multiple overlap areas between adjacent film layers, causing the metal electrode to occupy a large wiring space. This is detrimental to the design of high-resolution display backplanes and makes it difficult to improve the display effect of the display panel. Summary of the Invention

[0004] This application provides a display panel and a mobile terminal, which can improve the technical problem that the metal electrode between the cathode and auxiliary electrode in the existing display panel occupies a large wiring space.

[0005] This application first provides a display panel, including a display unit. Each display unit includes a substrate, an auxiliary electrode disposed on the substrate, a planarization layer covering the edge of the auxiliary electrode, a common layer disposed on the side of the planarization layer away from the substrate, and a cathode layer disposed on the side of the common layer away from the planarization layer. The planarization layer has an auxiliary contact hole corresponding to the auxiliary electrode. An overlap layer is disposed on the auxiliary electrode in the auxiliary contact hole. The common layer extends into the auxiliary contact hole and covers part of the overlap layer.

[0006] The common layer has a first via corresponding to the auxiliary contact hole, and the cathode layer is electrically connected to the overlapping layer through the first via.

[0007] In the display panel provided in the embodiments of this application, the display panel further includes a pixel definition layer disposed on the planarization layer, the pixel definition layer including a plurality of first openings and a plurality of second openings, the second openings being located between two adjacent first openings;

[0008] The first opening contains a sub-pixel, and the auxiliary contact hole is located in the second opening.

[0009] In the display panel provided in this embodiment, the display portion includes a central region and an edge region located on one side of the central region;

[0010] The distribution density of the auxiliary contact holes gradually decreases in the direction from the center region to the edge region.

[0011] In the display panel provided in this application embodiment, a plurality of sub-pixels displaying different colors constitute a pixel unit;

[0012] Each pixel unit has a corresponding auxiliary contact hole.

[0013] In the display panel provided in this application embodiment, each sub-pixel includes an anode layer and a light-emitting layer disposed on the anode layer;

[0014] The overlapping layer is in the same layer as the anode layer and is insulated from it, and the overlapping layer is made of the same material as the anode layer.

[0015] In the display panel provided in the embodiments of this application, the thickness of the overlapping layer is less than the thickness of the anode layer, and the thickness of the central portion of the overlapping layer is less than the thickness of the edge portion of the overlapping layer.

[0016] In the display panel provided in the embodiments of this application, the display panel further includes a light-shielding layer disposed on the substrate, a buffer layer disposed on the light-shielding layer, an interlayer dielectric layer disposed on the buffer layer, and a source electrode and a drain electrode disposed on the interlayer dielectric layer and spaced apart, wherein one of the drain electrodes is electrically connected to one of the anode layers.

[0017] The auxiliary electrode is disposed on the same layer as the drain electrode and is insulated from it. The auxiliary electrode is electrically connected to the light-shielding layer through a second via disposed on the interlayer dielectric layer.

[0018] In the display panel provided in this application embodiment, the light-emitting layer includes a hole injection layer disposed on the anode layer, a hole transport layer disposed on the hole injection layer, a light-emitting material layer disposed on the hole transport layer, an electron transport layer disposed on the light-emitting material layer, and an electron injection layer disposed on the electron transport layer;

[0019] The common layer includes the hole injection layer, the hole transport layer disposed on the hole injection layer, the electron transport layer disposed on the hole transport layer, and the electron injection layer disposed on the electron transport layer.

[0020] In the display panel provided in this application embodiment, the slope angle of the planarization layer corresponding to the auxiliary contact hole is greater than the slope angle at both ends of the edge of the planarization layer.

[0021] Accordingly, this application also provides a mobile terminal, including a terminal body and a display panel as described in any of the above claims, wherein the terminal body and the display panel are integrated into one unit.

[0022] Beneficial effects of this application: This application provides a display panel including a display unit. Each display unit includes a substrate, an auxiliary electrode disposed on the substrate, a planarization layer covering the edge of the auxiliary electrode, a common layer disposed on the side of the planarization layer away from the substrate, and a cathode layer disposed on the side of the common layer away from the planarization layer. The planarization layer has an auxiliary contact hole corresponding to the auxiliary electrode. An overlap layer is disposed on the auxiliary electrode in the auxiliary contact hole. The common layer extends into the auxiliary contact hole and covers a portion of the overlap layer. The common layer corresponds to the auxiliary contact hole. The hole portion is provided with a first via, through which the cathode layer is electrically connected to the overlap layer; in this application, the cathode layer is electrically connected to the overlap layer disposed on the auxiliary electrode located in the auxiliary contact hole through the first via on the common layer, which reduces the resistance of the cathode layer, improves the voltage drop phenomenon, and enhances the display uniformity of the display panel; and compared with the prior art, this application reduces the wiring space occupied by the metal electrode between the cathode and the auxiliary electrode, thereby reducing the overlap area between different film layers, which is beneficial to the fabrication of high-resolution display panels and improves the display effect of the display panel. Attached Figure Description

[0023] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of this application;

[0025] Figure 2 for Figure 1 Sectional view at A1A2;

[0026] Figure 3 This is a schematic diagram of the structure for fabricating the overlapping layer in the display panel provided in an embodiment of this application;

[0027] Figure 4 A schematic diagram illustrating a method for forming differential slope angles in different areas of a planarization layer in a display panel, as provided in an embodiment of this application.

[0028] Figure 5 A flowchart illustrating the manufacturing method of the display panel provided in this application embodiment. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0030] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0031] Please see Figures 1 to 5 This application discloses a display panel 100; the display panel 100 includes a display portion 101, each of the display portions 101 including a substrate 10, an auxiliary electrode 21 disposed on the substrate 10, a planarization layer 54 covering the edge of the auxiliary electrode 21, a common layer 71 disposed on the side of the planarization layer 54 away from the substrate 10, and a cathode layer 40 disposed on the side of the common layer 71 away from the planarization layer 54. The planarization layer 54 has an auxiliary contact hole 541 corresponding to the auxiliary electrode 21, and an overlap layer 31 is disposed on the auxiliary electrode 21 in the auxiliary contact hole 541. The common layer 71 extends into the auxiliary contact hole 541 and covers part of the overlap layer 31. The common layer 71 has a first through hole 711 in the portion corresponding to the auxiliary contact hole 541, and the cathode layer 40 is electrically connected to the overlap layer 31 through the first through hole 711.

[0032] This application electrically connects the cathode layer 40 to the overlap layer 31 disposed on the auxiliary electrode 21 located in the auxiliary contact hole 541 through the first via 711 on the common layer 71, thereby reducing the resistance of the cathode layer 40, improving the voltage drop phenomenon, and enhancing the display uniformity of the display panel 100. Moreover, compared with the prior art, this application reduces the wiring space occupied by the metal electrode between the cathode layer 40 and the auxiliary electrode 21, thereby reducing the overlap area between different film layers, which is beneficial to the fabrication of the high-resolution display panel 100 and improves the display effect of the display panel 100.

[0033] The technical solution of this application will now be described in conjunction with specific embodiments.

[0034] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the planar structure of the display panel 100 provided in the embodiment of this application; wherein, the display panel 100 provided in the embodiment of this application includes a display portion 101 and a non-display portion 102 adjacent to the display portion 101.

[0035] Each display unit 101 includes a plurality of pixel units 1010, each pixel unit 1011 includes a plurality of sub-pixels 1011 displaying different light-emitting colors, and an auxiliary contact hole 541 is provided between at least two adjacent sub-pixels 1011.

[0036] In one embodiment of this application, each pixel unit 1010 is provided with an auxiliary electrode 21; the advantage of this design is that it can evenly improve the voltage drop phenomenon of each pixel unit 1010.

[0037] Further, please refer to Figure 2 , Figure 2 for Figure 1 A cross-sectional view at A1A2; wherein, the display unit 101 further includes a substrate 10 and a plurality of thin film transistors disposed on the substrate 10, a planarization layer 54 disposed on the thin film transistors, a pixel definition layer 55 disposed on the planarization layer 54, a common layer 71 disposed on the pixel definition layer 54, and a cathode layer 40 disposed on the common layer 71.

[0038] In the embodiments of this application, the thin-film transistor includes any one of the following: top-gate thin-film transistor, bottom-gate thin-film transistor, low-temperature polycrystalline silicon thin-film transistor, semiconductor metal oxide thin-film transistor, and hydrogenated polycrystalline thin-film transistor produced by low-temperature solid-state crystallization process.

[0039] Furthermore, the thin-film transistor includes a light-shielding layer 61 disposed on the substrate 10, a buffer layer 51 disposed on the substrate 10 and covering the light-shielding layer 61, an active layer 62 disposed on the buffer layer 51 and located above the light-shielding layer 61, a gate insulating layer 53 disposed on the buffer layer 51 and covering a portion of the upper surface of the active layer 62, a gate 63 disposed on the gate insulating layer 53, an interlayer dielectric layer 52 disposed on the buffer layer 51 and covering the active layer 62, the gate insulating layer 53 and the gate 63, a first metal layer 20 disposed on the interlayer dielectric layer 52, a passivation layer 30 disposed on the interlayer dielectric layer 52 and covering a portion of the first metal layer 20, and a planarization layer 54 disposed on the passivation layer 30.

[0040] In this embodiment, the first metal layer 20 includes a plurality of auxiliary electrodes 21, a plurality of source electrodes 22, a plurality of drain electrodes 23 disposed in the display section 101, and a plurality of signal terminals 24 disposed in the non-display section 102. One source electrode 22 and one drain electrode 23 are respectively disposed on the upper two sides of an active layer 62, and one source electrode 22 and one drain electrode 23 pass through the interlayer dielectric layer 52 and overlap with the two sides of the corresponding active layer 62.

[0041] Specifically, the light-shielding layer 61 includes a first light-shielding layer 611 and a second light-shielding layer 612 that are on the same layer and spaced apart. A second via 521 is provided on the interlayer dielectric layer 52. The auxiliary electrode 21 is electrically connected to the first light-shielding layer 611 through the second via 521, thereby transferring excess charge on the auxiliary electrode 21 to the first light-shielding layer 611 to reduce voltage drop.

[0042] Furthermore, each drain 23 also overlaps with the second light-shielding layer 612 through the interlayer dielectric layer 52 and the buffer layer 51, thereby applying a stable voltage to the second light-shielding layer 612 through the drain 23 to reduce signal crosstalk.

[0043] The passivation layer 30 also includes a plurality of openings disposed in the non-display portion 102, and each opening corresponds to a signal terminal 24 to expose a portion of the upper surface of the corresponding signal terminal 24 for subsequent bonding of the signal terminal 24.

[0044] In this embodiment, the planarization layer 54 is disposed on the passivation layer 30, and the planarization layer 54 includes auxiliary contact holes 541 disposed in the display part 101 and corresponding to the auxiliary electrode 21. Each auxiliary contact hole 541 is disposed corresponding to an auxiliary electrode 21, and each auxiliary contact hole 541 exposes a portion of the upper surface of the corresponding auxiliary electrode 21.

[0045] In this embodiment of the application, the pixel definition layer 55 is disposed on the planarization layer 54. The pixel definition layer 55 includes a plurality of first openings 551 and a plurality of second openings 552, and the second openings 552 are located between two adjacent first openings 551.

[0046] The first opening 551 contains a corresponding sub-pixel 1011; the auxiliary contact hole 541 is correspondingly disposed in the second opening 552, that is, the orthographic projection of each auxiliary contact hole 541 on the substrate 10 is located within the coverage area of ​​the orthographic projection of the corresponding second opening 552 on the substrate 10.

[0047] In this embodiment, the display unit 101 further includes a second metal layer 30 disposed on the first metal layer 20. The second metal layer 30 includes a plurality of overlapping layers 31 and an anode layer 32 disposed within the display unit 101. Each overlapping layer 31 is disposed on an auxiliary electrode 21 in the auxiliary contact hole 541, corresponding to a second opening 552; each anode layer 32 corresponds to a first opening 551.

[0048] Specifically, each overlapping layer 31 is disposed on the auxiliary electrode 21 and partially extends to the sidewall of the second opening 552, and each overlapping layer 31 does not extend above the corresponding auxiliary contact hole 541, thereby ensuring that the orthographic projection of the auxiliary contact hole 541 on the auxiliary electrode 21 completely covers the orthographic projection of the overlapping layer 31 on the auxiliary electrode 21. Each anode layer 32 is electrically connected to a drain electrode 23 through a corresponding first opening 551.

[0049] It should be noted that the overlapping layer 31 includes a first sub-layer, a second sub-layer, and a third sub-layer stacked together; each anode layer 32 includes a fourth sub-layer, a fifth sub-layer, and a sixth sub-layer stacked together. The first sub-layer is made of the same material as the fourth sub-layer, the second sub-layer is made of the same material as the fifth sub-layer, and the third sub-layer is made of the same material as the sixth sub-layer. That is, the overlapping layer 31 and the anode layer 32 are a stacked structure formed by three metal sub-layers.

[0050] In one embodiment of this application, the materials of the first sublayer and the fourth sublayer can both be Mo, Ti and Ni, the materials of the second sublayer and the fifth sublayer can both include ANCL, and ANCL is a mixture of Al, Ni, Cu and La, and the materials of the third sublayer and the sixth sublayer can both include ITO (Indium Tin Oxides).

[0051] In another embodiment of this application, the materials of the first sublayer, the third sublayer, the fourth sublayer and the sixth sublayer are all transparent conductive oxide (TCO) materials, and the materials of the second and fifth sublayers are all metallic silver.

[0052] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of the overlapping layer 31 in the display panel 100 provided in this application embodiment; wherein, after the second metal layer 30 is deposited on the planarization layer 54 by chemical vapor deposition, in order to prepare the patterned anode layer 32, the second metal layer 30 is first coated with photoresist, then the photoresist layer 80 on the second metal layer 30 that needs to be etched is exposed and developed to remove this part of the photoresist layer 80; finally, the part of the second metal layer 30 that does not cover the photoresist layer 80 is etched away, thereby obtaining the patterned anode layer 32.

[0053] Specifically, for the sake of the flatness of the sub-pixel 1011, especially in the organic light-emitting diode display panel 100 prepared by inkjet printing, the thickness of the planarization layer 54 is generally greater than or equal to 4 μm. This results in a relatively large slope angle (65–80°) near the auxiliary contact hole 541, leading to a thicker accumulation of photoresist layer 80 on the auxiliary electrode 21 at the bottom of the auxiliary contact hole 541. This causes insufficient exposure, resulting in a stable residue of the second metal layer 30 on the auxiliary electrode 21 at the bottom of the auxiliary contact hole 541, forming an overlap layer 31. Therefore, the thickness of the overlap layer 31 is less than the thickness of the anode layer 32. In this case, the residual photoresist layer 80 requires overexposure to remove.

[0054] Because the residual amount of photoresist layer 80 in the edge region of the bottom of the auxiliary contact hole 541 is greater than that in the center region of the bottom of the auxiliary contact hole 541, the thickness of the center portion of the overlap layer 31 is less than the thickness of the edge portion of the overlap layer 31.

[0055] Meanwhile, since the slope angle (30-50°) of the planarization layer 54 at the edge of the non-display portion 102 is relatively small, the photoresist layer 80 at the edge of the planarization layer 54 at the edge of the non-display portion 102 will not accumulate, thereby preventing the second metal layer 30 from remaining at the edge of the planarization layer 54 at the edge of the non-display portion 102, and thus preventing the formation of an overlap layer 31 at the edge of the planarization layer 54 at the edge of the non-display portion 102.

[0056] Please see Figure 4 , Figure 4This is a schematic diagram of a method for forming differential slope angles in different areas of a planarization layer 54 in a display panel 100 provided in this application embodiment; wherein, differential slope angles are formed in different areas of the planarization layer 54 using the same gray-toned mask 90.

[0057] Specifically, because the grayscale mask 90 uses a large-diameter first mask opening 91 to expose and develop the photoresist layer 80 in the area of ​​the planarization layer 54 corresponding to the auxiliary contact hole 541 in the display section 101, the slope angle formed by the planarization layer 54 corresponding to the auxiliary contact hole 541 is relatively large; at the same time, the grayscale mask 90 uses a small-diameter second mask opening 92 to expose and develop the photoresist layer 80 at both ends of the planarization layer 54 in the non-display section 102, the slope angle formed by the planarization layer 54 in the edge area of ​​the non-display section 102 is relatively small.

[0058] Therefore, the slope angle of the planarization layer 54 corresponding to the auxiliary contact hole 541 is greater than the slope angle at both ends of the edge of the planarization layer 54. Subsequently, when the patterned anode layer 32 is prepared in the photolithography process, the photoresist layer 80 accumulates less in the edge region of the planarization layer 54 located in the non-display area 102, and can be removed by subsequent exposure, thereby preventing the formation of the overlap layer 31.

[0059] In this embodiment of the application, each sub-pixel 1011 includes an anode layer 32 and a light-emitting layer 70 disposed on the anode layer 32, the light-emitting layer 70 being disposed corresponding to the first opening 551; wherein, the light-emitting layer 70 includes a hole injection layer disposed on the anode layer 32, a hole transport layer disposed on the hole injection layer, a light-emitting material layer disposed on the hole transport layer, an electron transport layer disposed on the light-emitting material layer, and an electron injection layer disposed on the electron transport layer.

[0060] In this embodiment, a common layer 71 is provided in the display section 101 corresponding to the area outside the first opening 551. The common layer 71 is provided on the side of the planarization layer 54 away from the substrate 10. The common layer 71 extends into the auxiliary contact hole 541 and covers part of the overlapping layer 31. The common layer 71 is also electrically connected to the light-emitting layer 70 on the sidewall of the first opening 551.

[0061] The common layer 71 includes a hole injection layer, a hole transport layer disposed on the hole injection layer, an electron transport layer disposed on the hole transport layer, and an electron injection layer disposed on the electron transport layer.

[0062] In this embodiment, the cathode layer 40 is disposed on the light-emitting layer 70, and the cathode layer 40 covers the common layer 71 and extends into the auxiliary contact hole 541 and overlaps with the auxiliary electrode 21 through the first through hole 711.

[0063] Specifically, because the slope angle of the area near the auxiliary contact hole 541 is large, the shape of the overlapping layer 31 is not a smooth structure. Since the common layer 71 is composed of the non-light-emitting material layer in the light-emitting layer 70, its thickness is relatively thin. When the display panel 100 starts to work, the overlapping layer 31 is electrically connected to the auxiliary electrode 21, which makes it easy for the overlapping layer 31 to penetrate the common layer 71 and form the first via 711, thereby achieving the overlap with the cathode layer 40, thus forming the overlap path of the auxiliary electrode 21.

[0064] It should be noted that, in the embodiments of this application, by controlling the vapor deposition process parameters, the cathode layer 40 is not interrupted at the auxiliary contact hole 541 and the first opening 551, and continuously covers the sidewalls of the light-emitting layer 70 and the common layer 71, and extends into the auxiliary contact hole 541 to overlap with the auxiliary electrode 21.

[0065] Please see Figure 2 In this embodiment of the application, the display unit 101 includes a central region and an edge region located on one side of the central region;

[0066] In the direction from the center area to the edge area (X direction), the distribution density of the auxiliary contact holes 541 gradually decreases. This is because each auxiliary contact hole 541 is provided with an auxiliary electrode 21, and the distribution density of the auxiliary electrodes 21 is determined according to the size of the display product and the voltage drop. The more severe the voltage drop, the greater the density of the auxiliary electrodes 21. Theoretically, due to the impedance of the resistor in the cathode layer 40, the closer to the center of the display section 101, the more severe the voltage drop.

[0067] In the above embodiments of this application, this application mainly introduces a new overlapping structure of the auxiliary electrode 21 with edge contact, which can also reduce the wiring space occupied by the edge contact between the auxiliary electrode 21 and the cathode layer 40, which is beneficial to the design of high-resolution backplane. That is, in the auxiliary contact hole 541, the medium for forming the edge contact, namely the metal electrode pattern in the same layer as the anode layer 32, is no longer designed and manufactured separately. Instead, the residue of the second metal layer 30 at the bottom of the planarization layer 54 opening is used as the edge contact medium. In addition to forming the edge contact with the cathode layer 40, compared with the prior art, the overlapping area between different film layers is reduced, thereby reducing the space occupied by the auxiliary electrode 21.

[0068] In the existing display panel 100, since a separate metal electrode needs to be deposited between the cathode layer 40 and the auxiliary electrode 21 to make the cathode layer 40 and the auxiliary electrode 21 overlap, there is an overlap area between the auxiliary medium—metal electrode and the opening position of the planarization layer 54, and there is also an overlap area with the pixel definition layer 55. The overlap area between adjacent layers depends on the accuracy of the photoluminescence device, and is generally between 1.2 and 2.5 μm depending on the device. At this time, part of the metal electrode is located outside the auxiliary contact hole 541, and the edge contact path of the cathode layer 40 and the auxiliary electrode 21 is the outer perimeter of the metal electrode.

[0069] In this embodiment, the second metal layer 30 remaining at the bottom of the area corresponding to the auxiliary contact hole 541 of the planarization layer 54 is used as an edge contact medium to make the cathode layer 40 and the auxiliary electrode 21 overlap. At the same time, the overlap area between the metal electrode and the planarization layer 54 in the original design is eliminated, which reduces the space occupied by the overlap layer 31. Since the overlap layer 31 is completely located on the auxiliary electrode 21 in the auxiliary contact hole 541, the edge contact path between the cathode layer 40 and the auxiliary electrode 21 is the bottom perimeter of the auxiliary contact hole 541.

[0070] Please see Figure 5 This is a flowchart illustrating a method for manufacturing a display panel 100 according to an embodiment of this application. In this embodiment, the method for manufacturing the display panel 100 includes the following steps:

[0071] S10, A plurality of auxiliary electrodes 21 are formed on a substrate 10;

[0072] S20. A planarization layer 54 is formed on the substrate 10. The planarization layer 54 covers the edge of the auxiliary electrode 21 and has an auxiliary contact hole 541 corresponding to the auxiliary electrode 21.

[0073] S30. A first metal layer is formed on the planarization layer 54. The first metal layer includes an overlap layer 31 and an anode layer 32 that are spaced apart and insulated from each other. The overlap layer 31 is disposed on the auxiliary electrode 21 in the auxiliary contact hole 541.

[0074] S40. A pixel definition layer is formed on the planarization layer 54. The pixel definition layer includes a plurality of first openings 551 and a plurality of second openings 552. The second openings 552 are located between two adjacent first openings 551. The first openings 551 expose the anode layer 32. The auxiliary contact hole 541 is correspondingly disposed in the second opening 552.

[0075] S50, A light-emitting layer 70 is formed on the anode layer 32, and a common layer 71 is formed in the area outside the first opening 551. The common layer 71 is provided with a first through hole 711 in the portion corresponding to the auxiliary contact hole 541.

[0076] S60. A cathode layer 40 is formed on the pixel definition layer 55. The cathode layer 40 covers the light-emitting layer 70 and the common layer 71. The cathode layer 40 is electrically connected to the overlapping layer 31 through the first via 711.

[0077] To address the technical problem that the metal electrode between the cathode layer 40 and the auxiliary electrode 21 in existing display panels 100 occupies a large wiring space, this application provides a display panel 100 including a display unit 101. Each display unit 101 includes a substrate 10, an auxiliary electrode 21 disposed on the substrate 10, a planarization layer 54 covering the edge of the auxiliary electrode 21, a common layer 71 disposed on the side of the planarization layer 54 away from the substrate 10, and a common layer 71 disposed on the side of the common layer 71 away from the planarization layer 54. The cathode layer 40, the planarization layer 54 having an auxiliary contact hole 541 corresponding to the auxiliary electrode 21, the overlapping layer 31 disposed on the auxiliary electrode 21 in the auxiliary contact hole 541, the common layer 71 extending into the auxiliary contact hole 541 and covering part of the overlapping layer 31, wherein the common layer 71 has a first through hole 711 corresponding to the portion of the auxiliary contact hole 541, and the cathode layer 40 is electrically connected to the overlapping layer 31 through the first through hole 711; this application describes the cathode layer 40 The first via 711 on the common layer 71 is electrically connected to the overlap layer 31 disposed on the auxiliary electrode 21 located in the auxiliary contact hole 541, thereby reducing the resistance of the cathode layer 40, improving the voltage drop phenomenon, and enhancing the display uniformity of the display panel 100. Moreover, compared with the prior art, this application reduces the wiring space occupied by the metal electrode between the cathode layer 40 and the auxiliary electrode 21, thereby reducing the overlap area between different film layers, which is beneficial to the fabrication of the high-resolution display panel 100 and improves the display effect of the display panel 100.

[0078] Accordingly, this application also proposes a mobile terminal, which includes a terminal body and the aforementioned display panel 100, wherein the terminal body and the display panel 100 are integrated into one unit. The terminal body may be a circuit board or other device bonded to the display panel 100. The mobile terminal may include electronic devices such as mobile phones, televisions, and laptops.

[0079] Continuing from the above, this application provides a display panel 100, including a display unit 101. Each display unit 101 includes a substrate 10, an auxiliary electrode 21 disposed on the substrate 10, a planarization layer 54 covering the edge of the auxiliary electrode 21, a common layer 71 disposed on the side of the planarization layer 54 away from the substrate 10, and a cathode layer 40 disposed on the side of the common layer 71 away from the planarization layer 54. The planarization layer 54 has an auxiliary contact hole 541 corresponding to the auxiliary electrode 21. An overlap layer 31 is disposed on the auxiliary electrode 21 in the auxiliary contact hole 541. The common layer 71 extends into the auxiliary contact hole 541 and covers a portion of the overlap layer 31. A first via 711 is provided on the portion of the common layer 71 corresponding to the auxiliary contact hole 541. The cathode layer 40 is electrically connected to the overlap layer 31 through the first via 711. In this application, the cathode layer 40 is connected to the common layer 71 through the common layer 71. The first via 711 on the cathode layer 40 is electrically connected to the overlap layer 31 disposed on the auxiliary electrode 21 located in the auxiliary contact hole 541, which reduces the resistance of the cathode layer 40, improves the voltage drop phenomenon, and enhances the display uniformity of the display panel 100. Moreover, compared with the prior art, this application reduces the wiring space occupied by the metal electrode between the cathode layer 40 and the auxiliary electrode 21, thereby reducing the overlap area between different film layers, which is beneficial to the fabrication of the high-resolution display panel 100 and improves the display effect of the display panel 100.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0081] The above provides a detailed description of a display panel 100 and a mobile terminal provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, comprising a display section, characterized in that, Each of the aforementioned display units includes: substrate; An auxiliary electrode is disposed on the substrate; A planarization layer, the planarization layer covering the edge of the auxiliary electrode and having auxiliary contact holes corresponding to the auxiliary electrode; An overlap layer is disposed on the auxiliary electrode in the auxiliary contact hole; A common layer is disposed on the side of the planarization layer away from the substrate, the common layer extending into the auxiliary contact hole and covering a portion of the overlap layer; and A cathode layer is disposed on the side of the common layer away from the planarization layer; The common layer is provided with a first via corresponding to the auxiliary contact hole, and the cathode layer is electrically connected to the overlapping layer through the first via. The slope angle of the planarization layer corresponding to the auxiliary contact hole ranges from 65° to 80°; the thickness of the central portion of the overlap layer is less than the thickness of the edge portion of the overlap layer.

2. The display panel according to claim 1, characterized in that, The display panel further includes a pixel definition layer disposed on the planarization layer, the pixel definition layer including a plurality of first openings and a plurality of second openings, the second openings being located between two adjacent first openings; The first opening contains a sub-pixel, and the auxiliary contact hole is located in the second opening.

3. The display panel according to claim 2, characterized in that, The display unit includes a central region and an edge region located on one side of the central region; The distribution density of the auxiliary contact holes gradually decreases in the direction from the center region to the edge region.

4. The display panel according to claim 2, characterized in that, Multiple sub-pixels displaying different colors constitute a pixel unit; Each pixel unit has a corresponding auxiliary contact hole.

5. The display panel according to claim 2, characterized in that, Each of the sub-pixels includes an anode layer and a light-emitting layer disposed on the anode layer; The overlapping layer is in the same layer as the anode layer and is insulated from it, and the overlapping layer is made of the same material as the anode layer.

6. The display panel according to claim 5, characterized in that, The thickness of the overlap layer is less than the thickness of the anode layer.

7. The display panel according to claim 5, characterized in that, The display panel further includes a light-shielding layer disposed on the substrate, a buffer layer disposed on the light-shielding layer, an interlayer dielectric layer disposed on the buffer layer, and a source electrode and a drain electrode disposed on the interlayer dielectric layer and spaced apart, wherein one of the drain electrodes is electrically connected to one of the anode layers. The auxiliary electrode is disposed on the same layer as the drain electrode and is insulated from it. The auxiliary electrode is electrically connected to the light-shielding layer through a second via disposed on the interlayer dielectric layer.

8. The display panel according to claim 5, characterized in that, The light-emitting layer includes a hole injection layer disposed on the anode layer, a hole transport layer disposed on the hole injection layer, a light-emitting material layer disposed on the hole transport layer, an electron transport layer disposed on the light-emitting material layer, and an electron injection layer disposed on the electron transport layer; The common layer includes the hole injection layer, the hole transport layer disposed on the hole injection layer, the electron transport layer disposed on the hole transport layer, and the electron injection layer disposed on the electron transport layer.

9. The display panel according to claim 1, characterized in that, The slope angle of the planarization layer corresponding to the auxiliary contact hole is greater than the slope angle at both ends of the edge of the planarization layer.

10. A mobile terminal, characterized in that, It includes a terminal body and a display panel as described in any one of claims 1 to 9, wherein the terminal body and the display panel are integrated into one unit.

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