Thin film transistor, array substrate and display panel

Abstract

The application provides a thin film transistor, an array substrate and a display panel. The thin film transistor comprises an active pattern, a source heavily doped portion and a drain heavily doped portion, the channel is located between the source heavily doped portion and the drain heavily doped portion, and the thickness of at least part of the channel is smaller than the thickness of at least part of the drain heavily doped portion; a gate electrode corresponding to the channel; a source electrode in contact with the source heavily doped portion; and a drain electrode in contact with the drain heavily doped portion.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a thin-film transistor, an array substrate, and a display panel. Background Technology

[0002] To achieve the ultimate display effect, the display panel needs to have characteristics such as high resolution, high aperture ratio and narrow bezel, while meeting the display requirements of high frequency and low power consumption.

[0003] To achieve the aforementioned characteristics and display requirements, the size of thin-film transistors (TFTs) in the display panel needs to be reduced to decrease the space occupied by TFTs and lower their power consumption and RC delay. However, scaling down the size of TFT devices to a certain extent will cause an increase in leakage current.

[0004] Therefore, it is necessary to propose a technical solution to reduce the leakage current of thin-film transistors. Summary of the Invention

[0005] The purpose of this application is to provide a thin-film transistor, an array substrate, and a display panel to reduce the leakage current of the thin-film transistor.

[0006] To achieve the above objectives, the technical solution is as follows:

[0007] A thin-film transistor, the thin-film transistor comprising:

[0008] An active pattern includes a channel, a heavily doped source region, and a heavily doped drain region, wherein the channel is located between the heavily doped source region and the heavily doped drain region, and the thickness of at least a portion of the channel is less than the thickness of at least a portion of the heavily doped drain region.

[0009] A gate is disposed corresponding to the channel;

[0010] The source electrode is in contact with the heavily doped portion of the source electrode; and

[0011] The drain electrode is in contact with the heavily doped portion of the drain electrode.

[0012] In some embodiments of the thin-film transistor, the thickness of the channel is less than the thickness of the heavily doped source portion and the thickness of the heavily doped drain portion.

[0013] In some embodiments of the thin-film transistor, the active pattern includes an opening that is disposed at least corresponding to the channel in the thickness direction of the active pattern. The opening is located between the heavily doped source portion and the heavily doped drain portion in a direction perpendicular to the thickness of the active pattern. The opening includes a first sidewall on the heavily doped source portion and a second sidewall on the heavily doped drain portion. The angle between the first sidewall and the second sidewall and the channel is greater than or equal to 90 degrees and less than or equal to 120 degrees.

[0014] In some embodiments of the thin-film transistor, the active pattern further includes:

[0015] A lightly doped source portion is connected between the heavily doped source portion and the channel, wherein the thickness of the lightly doped source portion is less than the thickness of the heavily doped source portion; and

[0016] A lightly doped drain portion is connected between the heavily doped drain portion and the channel, and the thickness of the lightly doped drain portion is less than the thickness of the heavily doped drain portion.

[0017] In some embodiments of the thin-film transistor, the thickness of the lightly doped source portion and the thickness of the lightly doped drain portion are equal to the thickness of the channel.

[0018] In some embodiments of the thin-film transistor, the thickness of the heavily doped drain portion is the same as the thickness of the heavily doped source portion, and the ratio of the thickness of the channel to the thickness of the heavily doped drain portion is greater than or equal to 1 / 2 and less than or equal to 4 / 5.

[0019] In some embodiments of the thin-film transistor, the thickness of the channel is greater than or equal to 300 angstroms and less than or equal to 500 angstroms, and the thickness of the heavily doped source portion and the heavily doped drain portion is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms.

[0020] An array substrate, the array substrate comprising:

[0021] Substrate; and

[0022] The aforementioned thin-film transistor is disposed on the substrate.

[0023] In some embodiments, the array substrate further includes:

[0024] A light-shielding layer is disposed between the substrate and the thin-film transistor, and is disposed corresponding to the channel.

[0025] A display panel comprising the array substrate described above.

[0026] Beneficial Effects: This application provides a thin-film transistor, an array substrate, and a display panel. Since the thickness of at least a portion of the channel in the active pattern is less than the thickness of at least a portion of the heavily doped drain portion of the active pattern, it is beneficial to thin the channel. When the drain electric field generated by the voltage difference between the heavily doped source and drain portions is too large, the excessive drain electric field has a smaller impact on the thinned channel, thereby reducing the leakage current of the thin-film transistor. Furthermore, the thinning of the channel reduces the cross-sectional area for transporting charge carriers, decreasing the contact area between the channel and the heavily doped drain portion when they are in direct contact, thus reducing the influence of the drain electric field on the channel and reducing the drain-induced barrier reduction effect. In addition, the thinning of the channel improves the gate's control over the channel; the fact that the thickness of at least a portion of the channel is less than the thickness of at least a portion of the heavily doped drain portion of the active pattern avoids an increase in the overall resistance of the thin-film transistor. Attached Figure Description

[0027] Figure 1 This is a planar schematic diagram of an array substrate according to an embodiment of this application;

[0028] Figure 2 For along Figure 1 A schematic diagram of the first cross-section of the array substrate shown by the AA tangent.

[0029] Figure 3 For along Figure 1 A schematic diagram of the cross-section of the BB tangent of the array substrate shown;

[0030] Figure 4 For along Figure 1 A schematic diagram of a second cross-section of the array substrate shown by the AA tangent.

[0031] Figure 5 This is a cross-sectional schematic diagram of an array substrate according to another embodiment of this application;

[0032] Figures 6A-6G For manufacturing Figure 2 The diagram shows the process of the array substrate. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0034] Please see Figure 1 , Figure 2 as well as Figure 3 , Figure 1This is a planar schematic diagram of an array substrate according to an embodiment of this application. Figure 2 For along Figure 1 A schematic diagram of the first cross-section of the array substrate shown, with the AA tangent. Figure 3 For along Figure 1 A schematic cross-sectional view of the BB tangent of the array substrate shown.

[0035] The array substrate 100 includes a substrate 10, a light-shielding layer 20, a buffer layer 30, an active pattern 40, a gate insulating layer 50, a gate 60, an interlayer insulating layer 70, a source 801, and a drain 802. The active pattern 40, the gate insulating layer 50, the gate 60, the interlayer insulating layer 70, the source 801, and the drain 802 constitute a thin film transistor T.

[0036] Substrate 10 is a glass substrate. It can be understood that substrate 10 can also be a flexible substrate.

[0037] A light-shielding layer 20 is located on the substrate 10. The material used to fabricate the light-shielding layer 20 includes at least one of molybdenum or aluminum. The thickness of the light-shielding layer 20 is greater than or equal to 400 angstroms and less than or equal to 600 angstroms.

[0038] The buffer layer 30 covers the light-shielding layer 20 and the substrate 10. The material used to fabricate the buffer layer 30 includes at least one of silicon nitride or silicon oxide. The thickness of the buffer layer 30 is greater than or equal to 2000 angstroms and less than or equal to 4000 angstroms.

[0039] An active pattern 40 is disposed on the surface of the buffer layer 30 away from the light-shielding layer 20. The active pattern 40 includes a channel 401, a heavily doped source region 402, and a heavily doped drain region 403. The channel 401 is located between the heavily doped source region 402 and the heavily doped drain region 403, and the channel 401 is disposed corresponding to the light-shielding layer 20. The active pattern 40 is fabricated from at least one of polycrystalline silicon, metal oxide, or amorphous silicon.

[0040] The thickness of at least a portion of the channel 401 is less than the thickness of at least a portion of the heavily doped drain portion 403, which facilitates thinning of the channel 401. When the drain electric field generated by the voltage difference between the heavily doped source portion 402 and the heavily doped drain portion 403 is too large, the excessive drain electric field has a smaller impact on the thinned channel, thereby helping to reduce the leakage current caused by the shrinkage of the thin-film transistor. Moreover, when the spacing between the channel 401 and the gate 60 is constant, the thinner the channel 401, the greater the proportion of the channel portion controlled by the gate 60 in the thickness direction of the channel 401 in the entire channel 401. Correspondingly, this helps to improve the control capability of the gate 60 over the channel 401 when the size of the thin-film transistor is reduced. Furthermore, reducing the thickness of the channel 401 decreases the cross-sectional area for carrier transport, reducing the contact area between the channel 401 and the heavily doped drain portion 403 when they are in direct contact. This reduces the influence of the drain electric field on the channel, thereby mitigating the drain-induced barrier reduction effect that occurs when the thin-film transistor size is reduced. In addition, at least a portion of the thickness of the channel 401 is less than at least a portion of the thickness of the heavily doped drain portion 403 in the active pattern 40, which helps to maintain the thickness of the heavily doped drain portion 403 and avoids an increase in the overall resistance of the thin-film transistor T.

[0041] Furthermore, the thickness of the channel 401 is less than the thickness of the heavily doped source portion 402 and the heavily doped drain portion 403. This is beneficial for thinning the channel 401 while keeping the thicknesses of the heavily doped source portion 402 and the heavily doped drain portion 403 unchanged, so as to further avoid increasing the overall resistance of the thin-film transistor T.

[0042] The thickness of the heavily doped source region 402 is equal to the thickness of the heavily doped drain region 403. It is understandable that the thickness of the heavily doped source region 402 may also be different from the thickness of the heavily doped drain region 403.

[0043] The ratio of the thickness of the channel 401 to the thickness of the heavily doped drain portion 403 is greater than or equal to 1 / 2 and less than or equal to 4 / 5. This improves the control capability of the gate 60 over the channel 401, reduces the leakage current of the thin-film transistor T, and also improves the drain-induced barrier reduction effect, ensuring the overall impedance of the thin-film transistor T. For example, the ratio of the thickness of the channel 401 to the thickness of the heavily doped drain portion 403 is 1 / 2, 3 / 5, or 7 / 10.

[0044] Specifically, the thickness of channel 401 is greater than or equal to 300 angstroms and less than or equal to 500 angstroms, and the thickness of the heavily doped source portion 402 and the heavily doped drain portion 403 is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms. For example, the thickness of channel 401 is 300 angstroms, 350 angstroms, 400 angstroms, or 450 angstroms, and the thickness of the heavily doped source portion 402 and the heavily doped drain portion 403 is 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, or 1000 angstroms.

[0045] The source heavily doped portion 402 and the drain heavily doped portion 403 are symmetrically disposed on opposite sides of the channel 401. That is, the source heavily doped portion 402 and the drain heavily doped portion 403 have the same shape, size and thickness. This is beneficial because when the array substrate is applied to the liquid crystal display panel, the performance of the thin film transistor T is not affected when the voltage applied to the source heavily doped portion 402 and the drain heavily doped portion 403 alternates.

[0046] It is understandable that the source heavy doped portion 402 and the drain heavy doped portion 403 can also be asymmetrically disposed on opposite sides of the channel 401.

[0047] Please see Figure 2 When the active pattern 40 is made of polycrystalline silicon, the active pattern 40 also includes a lightly doped source portion 404 and a lightly doped drain portion 405. The lightly doped source portion 404 is connected between the heavily doped source portion 402 and the channel 401, and the lightly doped drain portion 405 is connected between the heavily doped drain portion 403 and the channel 401. The thickness of the lightly doped source portion 404 is less than the thickness of the heavily doped source portion 402, and the thickness of the lightly doped drain portion 405 is less than the thickness of the heavily doped drain portion 403, so as to further reduce the leakage current when the size of the thin film transistor T is reduced and improve the drain-induced barrier reduction effect that exists when the size of the thin film transistor is reduced.

[0048] Specifically, the thickness of the lightly doped source portion 404 and the thickness of the lightly doped drain portion 405 are equal to the thickness of the channel 401, so as to further reduce the leakage current when the size of the thin film transistor T is reduced and improve the drain-induced barrier reduction effect that exists when the size of the thin film transistor is reduced.

[0049] It is understandable that when the active pattern 40 is made of polycrystalline silicon, the active pattern 40 may not include the lightly doped source portion 404 and the lightly doped drain portion 405. In this case, the heavily doped source portion 402 and the heavily doped drain portion 403 are directly connected to the opposite sides of the channel 401.

[0050] When the active pattern 40 is made of metal oxide, the active pattern 40 does not include the lightly doped source electrode 404 and the lightly doped drain electrode 405.

[0051] It should be noted that the heavily doped source region 402, the heavily doped drain region 403, the lightly doped source region 404, and the lightly doped drain region 405 are all obtained by ion doping of the semiconductor layer. Phosphorus ions can be used for ion doping. The ion doping concentration of the heavily doped source region 402 and the heavily doped drain region 403 is greater than that of the lightly doped source region 404 and the lightly doped drain region 405.

[0052] The active pattern 40 also includes an opening 40a. The opening 40a is disposed in the thickness direction of the active pattern 40, corresponding to the channel 401, the lightly doped source portion 404, and the lightly doped drain portion 405. The opening 40a is located between the heavily doped source portion 402 and the heavily doped drain portion 403 in the direction perpendicular to the thickness of the active pattern 40. The opening 40a includes a first sidewall 40a1 on the heavily doped source portion 402 and a second sidewall 40a2 on the heavily doped drain portion 403. The angle between the first sidewall 40a1 and the second sidewall 40a2 and the channel 401 is greater than or equal to 90 degrees and less than or equal to 120 degrees, to weaken the drain electric field strength and thus reduce the leakage current that occurs when the drain electric field is too large. For example, the angle between the first sidewall 40a1 and the second sidewall 40a2 and the channel 401 is 90 degrees, 100 degrees, 110 degrees, and 120 degrees.

[0053] Specifically, the angle between the first sidewall 40a1 and the second sidewall 40a2 and the channel 401 is 90 degrees, that is, the first sidewall 40a1 and the second sidewall 40a2 are both perpendicular to the channel 401.

[0054] When the active pattern 40 is made of metal oxide, or when the active pattern 40 is made of polysilicon and the active pattern 40 does not include the lightly doped source portion 404 and the lightly doped drain portion 405, the opening 40a is provided only in the direction perpendicular to the thickness of the active pattern 40, corresponding to the channel 401, and the opening 40a is located between the heavily doped source portion 402 and the heavily doped drain portion 403 in the direction perpendicular to the thickness of the active pattern 40.

[0055] The gate insulating layer 50 covers the buffer layer 30 and the active pattern 40. The material used to fabricate the gate insulating layer 50 is selected from at least one of silicon nitride or silicon oxide. The thickness of the gate insulating layer 50 is greater than or equal to 1000 angstroms and less than or equal to 1500 angstroms.

[0056] A gate 60 is disposed on the surface of the gate insulating layer 50 away from the active pattern 40. The gate 60 is disposed corresponding to the channel 401. The material used to fabricate the gate 60 is selected from at least one of molybdenum, aluminum, titanium, copper, and silver. The thickness of the gate 60 is greater than or equal to 2500 angstroms and less than or equal to 5000 angstroms.

[0057] Interlayer insulating layer 70 covers gate 60 and gate insulating layer 50. The material used to prepare interlayer insulating layer 70 is selected from at least one of silicon nitride or silicon oxide. The thickness of interlayer insulating layer 70 is greater than or equal to 5000 angstroms and less than or equal to 7000 angstroms.

[0058] Source 801 and drain 802 are disposed on the surface of interlayer insulating layer 70 away from gate 60. Source 801 contacts heavily doped source portion 402 through a first contact hole 100a penetrating interlayer insulating layer 70 and gate insulating layer 50, and drain 802 contacts heavily doped drain portion 403 through a second contact hole 100b penetrating interlayer insulating layer 70 and gate insulating layer 50. The materials used to fabricate source 801 and drain 802 are selected from at least one of molybdenum, aluminum, titanium, copper, and silver. The thickness of source 801 and drain 802 is greater than or equal to 4000 angstroms and less than or equal to 8000 angstroms.

[0059] Please see Figure 4 , it is along Figure 1 A schematic diagram of a second cross-section of the array substrate shown, with the AA tangent line. Figure 4 The array substrate shown and Figure 2 The array substrates shown are basically similar, except that the thickness of the lightly doped source portion 404 is the same as the thickness of the lightly doped drain portion 405, and the thickness of the lightly doped source portion 404 is greater than the thickness of the channel 401 and less than the thickness of the heavily doped source portion 402.

[0060] Compared to Figure 4 The array substrate shown, due to Figure 2 The thinner thickness of the source lightly doped portion 404 and the drain lightly doped portion 405 in the array substrate shown is more conducive to reducing the influence of the drain electric field on the source lightly doped portion 404 and the drain lightly doped portion 405, thus enabling the thin film transistor size to be reduced. Figure 2 The thin-film transistors in the array substrate shown generate less leakage current. Figure 2 The array substrate shown is more conducive to improving the drain-induced barrier reduction effect that exists when the size of thin-film transistors is reduced.

[0061] Please see Figure 5 This is a cross-sectional schematic diagram of an array substrate according to another embodiment of this application. Figure 5 The array substrate shown and Figure 2 The array substrates shown are basically similar, except that... Figure 5 The array substrate 100 shown also includes a planarization layer 90, a common electrode layer 110, a passivation layer 120, and a pixel electrode layer 130.

[0062] The planarization layer 90 is made of polyimide or polyacrylate. The thickness of the planarization layer 90 is greater than or equal to 1.5 micrometers and less than or equal to 3 micrometers.

[0063] The common electrode layer 110 is located on the surface of the planarization layer 90 away from the source electrode 801 and the drain electrode 802. The common electrode 110 is made of a transparent conductive material, such as indium tin oxide or indium zinc oxide. The thickness of the common electrode 110 is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms.

[0064] Passivation layer 120 covers common electrode layer 110 and planarization layer 90. The material used to prepare passivation layer 120 is selected from at least one of silicon nitride or silicon oxide. The thickness of passivation layer 120 is greater than or equal to 800 angstroms and less than or equal to 1600 angstroms.

[0065] The pixel electrode layer 130 is disposed on the surface of the passivation layer 120 away from the common electrode layer 110. The pixel electrode layer 130 is made of a transparent conductive material, such as indium tin oxide or indium zinc oxide. The thickness of the pixel electrode layer 130 is greater than or equal to 400 angstroms and less than or equal to 800 angstroms.

[0066] It is understandable that the positions of the pixel electrode layer 130 and the common electrode layer 110 can be interchanged.

[0067] This application also provides Figure 2 The method for manufacturing the array substrate shown includes the following steps:

[0068] S101: A light-shielding layer is formed on the substrate.

[0069] The material used to prepare the light-shielding layer 20 includes at least one of molybdenum or aluminum, and the thickness of the light-shielding layer 20 is greater than or equal to 400 angstroms and less than or equal to 600 angstroms.

[0070] Specifically, firstly, a first conductive layer is formed on the substrate 10 using a physical vapor deposition process. A first photoresist layer is then formed on the first conductive layer. The first photoresist layer is exposed using a first photomask. The exposed first photoresist layer is developed using a first developing solution. The first conductive layer not covered by the first photoresist layer after the first developing solution treatment is etched to remove the remaining first photoresist layer, resulting in a light-shielding layer 20. Figure 6A As shown.

[0071] Finally, a buffer layer 30 covering the light-shielding layer 20 and the substrate 10 is formed by chemical vapor deposition, such as... Figure 6A As shown. The material used to prepare the buffer layer 30 is selected from at least one of silicon nitride or silicon oxide. The thickness of the buffer layer is greater than or equal to 2000 angstroms and less than or equal to 4000 angstroms.

[0072] S102: An active pattern is formed on the side of the light-shielding layer away from the substrate, and a gate is formed on the side of the active pattern away from the substrate.

[0073] The active pattern is fabricated using polycrystalline silicon. The gate material is selected from at least one of molybdenum, aluminum, titanium, copper, and silver. The gate thickness is greater than or equal to 2500 angstroms and less than or equal to 5000 angstroms.

[0074] Specifically, firstly, an amorphous silicon semiconductor layer is formed on the buffer layer 30 using chemical vapor deposition. Then, the amorphous silicon semiconductor layer is transformed into a polycrystalline silicon semiconductor layer using excimer laser annealing. A second photoresist layer is formed on the polycrystalline silicon semiconductor layer. The second photoresist layer is exposed using a second photomask, and then developed using a second etchant. The polycrystalline silicon semiconductor layer not covered by the second photoresist layer after the second etchant treatment is etched to obtain a patterned polycrystalline silicon semiconductor layer 406. (Figure) The polycrystalline silicon semiconductor layer 406 has a heavily doped source region 406a, a heavily doped drain region 406b, a channel region 406c, a lightly doped source region 406d, and a lightly doped drain region 406e. The channel region 406c is located between the heavily doped source region 406a and the heavily doped drain region 406b, the lightly doped source region 406d is located between the heavily doped source region 406a and the channel region 406c, and the lightly doped drain region 406e is located between the lightly doped drain region 406e and the channel region 406c. Figure 6B As shown.

[0075] Next, a third photoresist layer is formed on the patterned polysilicon semiconductor layer 406. The third photoresist layer is exposed using a third photomask, and then the exposed portions of the third photoresist layer corresponding to the heavily doped source region 406a and the heavily doped drain region 406b are removed using a third developing solution. Phosphorus ions are implanted into the heavily doped source region 406a and the heavily doped drain region 406b of the patterned polysilicon semiconductor layer 406 using a heavy doping process. The remaining third photoresist layer is then removed, resulting in the heavily doped source region 402 and the heavily doped drain region 403. Figure 6C As shown.

[0076] Subsequently, a fourth photoresist layer is formed on the patterned polysilicon semiconductor layer 406, which includes the heavily doped source region 402, the heavily doped drain region 403, the channel region 406c, the lightly doped source region 406d, and the lightly doped drain region 406e. The fourth photoresist layer is exposed using the aforementioned third photomask, and then the portions of the exposed fourth photoresist layer corresponding to the lightly doped source region 406d, the lightly doped drain region 406e, and the channel region 406c are removed using a fourth developing solution. Finally, an etching process is used to remove the lightly doped source region 406d. The patterned polysilicon semiconductor layer 406 of the lightly doped drain region 406e and the channel region 406c is etched to form an opening 40a. The opening 40a is located between the heavily doped source region 402 and the heavily doped drain region 403 in the thickness direction perpendicular to the substrate 10. The depth of the opening 40a is less than the thickness of the heavily doped source region 402 and the heavily doped drain region 403. The opening 40a includes a first sidewall 40a1 of the heavily doped source region 402 and a second sidewall 40a2 of the heavily doped drain region 403. Figure 6D As shown.

[0077] Finally, a gate insulating layer 50 covering the heavily doped source region 402, the heavily doped drain region 403, and the opening 40a is formed by chemical vapor deposition. A second conductive layer is formed on the gate insulating layer 50, and a fifth photoresist layer is formed on the second conductive layer. The exposed fifth photoresist layer is exposed using a fourth photomask. The second conductive layer not covered by the fifth photoresist layer after treatment with the fifth developer is etched to remove the remaining fifth photoresist layer, resulting in a gate 60. The gate 60 corresponds to the channel region 406c. Then, using the gate 60 as a mask, phosphorus ions are implanted into the lightly doped source region 406d and the lightly doped drain region 406e of the patterned polysilicon semiconductor layer 406 using a light doping process, resulting in a lightly doped source region 404, a lightly doped drain region 405, and a channel 401. The lightly doped source region 404, the lightly doped drain region 405, the channel 401, the heavily doped source region 402, the heavily doped drain region 403, and the opening 40a constitute an active pattern 40, as shown below. Figure 6E As shown.

[0078] It should be noted that when the third photoresist layer is positive, the fourth photoresist layer is negative. Both the third and fourth photoresist layers are exposed using the third photomask, which helps reduce the number of photomasks required to manufacture the array substrate. It is understandable that the third photoresist layer could also be negative, while the fourth photoresist layer could be positive.

[0079] S104: The source and drain are formed on the side of the gate away from the substrate.

[0080] The source and drain electrodes are made of at least one material selected from molybdenum, aluminum, titanium, copper, and silver. The thickness of the source and drain electrodes is greater than or equal to 4000 angstroms and less than or equal to 8000 angstroms.

[0081] Specifically, firstly, an interlayer insulating layer 70 covering the gate 60 and the gate insulating layer 50 is formed. A sixth photoresist layer is then formed on the interlayer insulating layer 70. The sixth photoresist layer is exposed using a fifth photomask, and then developed using a sixth developer to remove the sixth photoresist layer corresponding to the heavily doped source portion 402 and the heavily doped drain portion 403. Next, the gate insulating layer 50 and the interlayer insulating layer 70 corresponding to the heavily doped source portion 402 and the heavily doped drain portion 403 are etched, forming a first contact hole 100a and a second contact hole 100b penetrating the gate insulating layer 50 and the interlayer insulating layer 70. The first contact hole 100a corresponds to the heavily doped source portion 402, and the second contact hole 100b corresponds to the heavily doped drain portion 403. Figure 6F As shown.

[0082] Finally, a third conductive layer is formed by physical vapor deposition on the surface of the interlayer insulating layer 70 away from the gate 60 in the first contact hole 100a and the second contact hole 100b. A seventh photoresist layer is formed on the third conductive layer. The seventh photoresist layer is exposed using a sixth photomask, and the exposed seventh photoresist layer is developed using a seventh developer. The third conductive layer not covered by the seventh photoresist layer after the seventh developer treatment is etched to obtain the source 801 and the drain 802. The source 801 contacts the heavily doped source portion 402 through the first contact hole 100a, and the drain 802 contacts the heavily doped drain portion 403 through the second contact hole 100b. Figure 6G As shown.

[0083] The method for manufacturing the array substrate in this embodiment reduces the number of photomasks required to manufacture the array substrate while thinning the channel of the thin-film transistor. Thinning the channel of the thin-film transistor is beneficial for reducing the size of the thin-film transistor to increase the aperture ratio of the array substrate, improving the gate control capability of the thin-film transistor over the channel, reducing leakage current, improving the leakage-induced barrier reduction effect, and avoiding an increase in the overall resistance of the thin-film transistor.

[0084] This application also provides a display panel, the display panel package Figure 5 The array substrate, the color filter substrate disposed opposite to the array substrate, and the liquid crystal layer disposed between the array substrate and the color filter substrate are shown.

[0085] In this embodiment, the thinning of the channel of the thin-film transistor in the display panel reduces the size of the thin-film transistor to achieve narrow bezels, high aperture ratio, or high resolution. This is beneficial for improving the gate control capability of the thin-film transistor over the channel, reducing leakage current, improving the leakage-induced barrier reduction effect, and avoiding an increase in the overall resistance of the thin-film transistor.

[0086] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A thin-film transistor, characterized in that, The thin-film transistor includes: An active pattern includes a channel, a heavily doped source region, a heavily doped drain region, a lightly doped source region, and a lightly doped drain region. The channel is located between the heavily doped source region and the heavily doped drain region. The lightly doped source region is connected between the heavily doped source region and the channel. The lightly doped drain region is connected between the heavily doped drain region and the channel. The thickness of the channel is less than the thickness of both the heavily doped source region and the heavily doped drain region. The thickness of the lightly doped drain region is greater than the thickness of the channel and less than the thickness of the heavily doped drain region. A gate is disposed corresponding to the channel; The source electrode is in contact with the heavily doped portion of the source electrode; and The drain electrode is in contact with the heavily doped portion of the drain electrode. The thickness of the heavily doped source portion is different from the thickness of the heavily doped drain portion, and the ratio of the thickness of the channel to the thickness of the heavily doped drain portion is greater than or equal to 1 / 2 and less than or equal to 4 / 5.

2. The thin-film transistor according to claim 1, characterized in that, The active pattern includes an opening, which is disposed at least corresponding to the channel in the thickness direction of the active pattern. The opening is located between the heavily doped source portion and the heavily doped drain portion in a direction perpendicular to the thickness of the active pattern. The opening includes a first sidewall on the heavily doped source portion and a second sidewall on the heavily doped drain portion. The angle between the first sidewall and the second sidewall and the channel is greater than or equal to 90 degrees and less than or equal to 120 degrees.

3. The thin-film transistor according to claim 1, characterized in that, The thickness of the lightly doped source portion is the same as the thickness of the lightly doped drain portion.

4. The thin-film transistor according to claim 1, characterized in that, The thickness of the channel is greater than or equal to 300 angstroms and less than or equal to 500 angstroms, and the thickness of the heavily doped source and the heavily doped drain are greater than or equal to 500 angstroms and less than or equal to 1000 angstroms.

5. An array substrate, characterized in that, The array substrate includes: Substrate; and The thin-film transistor as described in any one of claims 1-4 is disposed on the substrate.

6. The array substrate according to claim 5, characterized in that, The array substrate further includes: A light-shielding layer is disposed between the substrate and the thin-film transistor, and is disposed corresponding to the channel.

7. A display panel, characterized in that, The display panel includes the array substrate as described in claim 5 or 6.

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