A rail-to-rail current-steering DAC structure with self-calibration function

Abstract

The present invention belongs to the technical field of integrated circuits, particularly the DAC circuit in analog integrated circuits. Specifically, it is a rail-to-rail current-steering DAC structure with a self-calibration function, including a digital input register, a decoder, a PMOS current source differential driver, an NMOS current source differential driver, a PMOS current source, an NMOS current source, a digital pre-calibration module, and a strobe switch. The digital input register receives an external digital input and transmits it to the decoder. After decoding the input digital signal, the decoder transmits the digital signal to the PMOS current source differential driver and the NMOS current source differential driver. The PMOS current source differential driver and the NMOS current source differential driver are respectively connected to the PMOS current source and the NMOS current source. The digital pre-calibration module is connected to the PMOS current source and the NMOS current source. The strobe switch is connected to the PMOS current source and the NMOS current source.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, especially the DAC circuit in analog integrated circuits. Specifically, it is a rail-to-rail current-steering DAC structure with a self-calibration function. Background Art

[0002] As an indispensable part of daily life, the development needs of intelligentization and electrification of automobiles are the future development trend of the automotive electronics industry. These development requirements have broken the original concept of automotive electronics that mainly relies on mechanical structures and supplemented by electronic technologies, and promoted the transformation of the automotive field from the original mechanical-dominated to intelligent products controlled by electronic information systems. Its intelligentization is mainly reflected in the automotive electronic technology, including electronic control unit technology, motor control technology, autonomous driving technology, intelligent cockpit technology, etc. The digital-to-analog converter is the core of the engine electronic control system. The traditional current-steering digital-to-analog converter has a small output swing and cannot meet the design requirements of rail-to-rail output for automotive engine sensor interfaces.

[0003] The output voltage range of the traditional current-steering DAC is generally from ground to half of the power supply voltage. And as the output voltage swing increases, it becomes more difficult for the internal MOS current source in the circuit to maintain operation in the saturation region, the output resistance value of the current source will decrease accordingly, and the performance of the current-steering DAC will deteriorate further. Therefore, for the problem of how to achieve a current-steering DAC with a high swing and high-precision output, a circuit structure implemented through an output amplifier has emerged. However, since its rail-to-rail output is achieved through a push-pull amplifier, its circuit quiescent operating point is greatly affected by the outside world, and problems such as lower circuit accuracy and slower speed are likely to occur.

[0004] In addition, if the traditional current-steering DAC is to achieve a wide output swing, large nonlinear problems will occur when the current source enters the edge of the linear region near a certain voltage limit of the output. If a buffer amplifier is added at the output, it will affect the conversion rate and accuracy of the current-steering DAC.

[0005] Therefore, for a high-swing current-steering DAC, it can be achieved by adding a buffer amplifier, and at the same time, it can isolate the interference of the external load on the internal network and provide a sufficiently stable output voltage. However, due to the large output swing, it is difficult to achieve high precision and high speed. Summary of the Invention

[0006] To solve the above technical problems, the present invention discloses a rail-to-rail current-steering DAC structure with a self-calibration function. This structure is a rail-to-rail DAC structure with dual differential outputs, and a pre-calibration method is adopted to solve the problems of poor output linearity caused by different errors of current sources composed of different types of MOS devices affected by the external environment, and the large glitch problem caused by the switching of output units at half of the power supply voltage when the output increases step by step.

[0007] The specific technical solution adopted by the present invention is as follows:

[0008] A rail-to-rail current-steering DAC structure with a self-calibration function, including a digital input register, a decoder, a PMOS current source differential driver, an NMOS current source differential driver, a PMOS current source, an NMOS current source, a digital pre-calibration module, and a strobe switch. The digital input register receives an external digital input and transmits it to the decoder. After the decoder decodes the input digital signal, it transmits the digital signal to the PMOS current source differential driver and the NMOS current source differential driver. The PMOS current source differential driver and the NMOS current source differential driver are respectively connected to the PMOS current source and the NMOS current source. The digital pre-calibration module is connected to the PMOS current source and the NMOS current source. The strobe switch is connected to the PMOS current source and the NMOS current source.

[0009] Compared with the traditional digital-to-analog conversion circuit, the present invention adds a quaternary drive circuit, complementary current sources, a complementary output strobe switch, and a digital pre-calibration module for calibrating the output.

[0010] The present invention will work in two modes:

[0011] (1) Pre-calibration mode;

[0012] (2) Normal digital-to-analog conversion mode.

[0013] Set this current-steering DAC as a 10-bit DAC:

[0014] Pre-calibration mode:

[0015] Before the circuit officially starts digital-to-analog conversion, the circuit will first enter the pre-calibration mode. At this time, the pre-calibration mode will temporarily disconnect the external digital input of the DAC and the circuit gating switch module, so that there is no output signal at OUTP and OUTN. And the output of the input digital register will be clamped to a fixed digital value "10b’1000000000". The digital input register will transmit the clamped digital signal to the decoder unit after clock synchronization. The decoder decodes the input digital signal and then transmits the digital signal to the current source differential drive unit, so that the synchronized multiple digital output signals after decoding are used as the drive signals for each current source MOS switch, thereby controlling the on and off of each current source switch, controlling the magnitude of the total output current, and converting it into the analog voltage signal required by the circuit through the load resistor. The desired rail-to-rail digital-to-analog conversion should be that when the digital code is "10b’1111111111", the output analog signal is the power supply voltage value. Therefore, when the input digital value is "10b’1000000000", according to the normal digital-to-analog conversion mode, it can be known that in the ideal case, the corresponding output P_ONTP of the PMOS current source and the corresponding output N_OUTP of the NMOS current source of this digital input should exactly correspond to half of the output analog signal voltage when the input digital code is "10b’1111111111". At this time, the gate voltage bias signals of the NMOS and PMOS current sources will be calibrated in sequence. When the DAC is started, it will enter the reset state. At this time, the digital clock signal used for calibration and the gate voltage biases of the PMOS current source and the NMOS current source generated by the reference module at this time will be used as the inputs of the calibration module. Because the gate voltage bias signals of the PMOS current source array and the NMOS current source array are copied from the current source gate voltage bias signal in the reference module, and the gate voltages of the same type of current source arrays are the same signal. After resetting each position of the digital signal, calibration starts. The digital clock signal is used as the clock signal of the pre-calibration module to control the counter in the pre-calibration module to count, thereby controlling the internal resistor array. At the same time, the two outputs of P_OUTP and N_OUTP are respectively compared with the standard 1 / 2 supply voltage generated by resistor voltage division to control the counting of the counter, and then change the magnitudes of the gate voltages of the PMOS current source array and the NMOS current source array. After calibration is completed, the calibrated gate voltage biases of the current source arrays will be locked in the corresponding positions. The digital pre-calibration module outputs the calibrated gate voltage biases of the PMOS current source and the NMOS current source array, and fixes the bias voltage unchanged before the next pre-calibration mode comes. Through the above process, the voltage biases of the NMOS current source and the PMOS current source are calibrated in sequence. The digital pre-calibration mode is used to solve the deviations of the PMOS current source and the NMOS current source caused by process errors and other environmental factors. And solve the problem of output voltage jump caused by the output switching of the NMOS current source and the PMOS current source at the intermediate potential.

[0016] Normal digital-to-analog conversion mode:

[0017] After the pre-calibration is completed, the digital pre-calibration module enables the strobe switch. The digital input register reads the digital signal input to the current-steering DAC, synchronizes it through the register, and then inputs a 10-bit synchronous digital code to the decoder unit. The decoder unit decodes the input digital code into multiple digital signals through a symmetric decoder. The decoded digital signals are respectively input to the PMOS current source switch driving unit and the NMOS current source switch driving unit, and the inputs of the two switch driving units are the same. The digital signals after passing through the driving unit are used as the switch driving outputs INP#P, INN#P, INP#N, and INN#N. And INP#N and INN#P, INP#P and INN#N are signals with the same logic, and INP#N and INN#P have the same logic as the digital signal output by the decoder. INP#P and INN#N have the opposite logic to the digital signal output by the decoder. The digital signals output by the driving module are used as the gate voltages of the MOS switches to control whether each path of the current source array conducts or not, so as to control the magnitude of the output current, and thus control the magnitude of the current applied to the load resistor.

[0018] The current-steering DAC of the present invention adopts a quaternary drive, that is, after the current source differential drive, each of the PMOS current source and the NMOS current source switch arrays has a group of differential digital signals to control the differential output of its current source, so as to output a double-differential voltage, namely NOUT_P, NOUT_N, POUT_P, and POUT_N. As the input digital code increases, the output POUT_P voltage is 0 to 1 / 2*VDD to 0, the POUT_N voltage is 1 / 2*VDD to 0 to 1 / 2*VDD; the NOUT_N voltage is 1 / 2*VDD to VDD to 1 / 2*VDD, and the NOUT_P voltage is VDD to 1 / 2*VDD to VDD. That is, the decoder adopts a symmetric decoder so that the four outputs of the decoder reach the maximum value of the decoder output (the digital signal output by the decoder is all 1) when the input digital code of the decoder is the intermediate value of "10b'1000000000", and the output is symmetric left and right, that is, the output is the same when the differential digital signals are input to the decoder. When the strobe switch module strobes at the output end, it needs to detect the highest-bit digital code of the DAC input digital signal. When the highest-bit digital code is 0, the positive output is strobed to POUT_P, and the negative output is strobed to NOUT_P; when the highest-bit digital code is 1, the positive output is strobed to NOUT_P, and the negative output is strobed to POUT_P, thereby realizing the output of a differential rail-to-rail voltage signal.

[0019] For the traditional current-steering DAC that realizes rail-to-rail output by increasing the output-stage amplifier, its linearity is generally poor, and because the operating state of the MOS devices in its output stage is uncertain, the static operating point of the circuit is easily affected by external factors such as temperature.

[0020] Through the quaternary drive and dual differential output mode, the output voltage range of the output unit with NMOS as the current source is from ground to half of the power supply voltage, and the output voltage range of the output unit with PMOS as the current source is from half of the power supply voltage to the power supply voltage. Thus, the rail-to-rail output of the current-steering DAC of the present invention is realized by switching the dual-channel differential output. And because the output current magnitude when the two current source modules are fully connected is only half of that when using a single current source module, the circuit power consumption is not increased. Moreover, the present invention adds a pre-calibration module, which can avoid the problem of performance degradation of the DAC caused by the mismatch between the two types of current sources due to different current source errors generated by current sources composed of different device types under the influence of the same external environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of the circuit structure of the present invention.

[0022] Figure 2 is a schematic diagram of the digital pre-calibration module structure in the present invention.

[0023] Figure 3 is a diagram of the symmetric decoder in the present invention.

[0024] Figure 4 is a digital calibration flow chart in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] For the convenience of those of ordinary skill in the art to understand and implement the present invention, the present invention will be further described in detail below in conjunction with embodiments. It should be understood that the embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0026] Embodiment: As Figure 1 shown, a rail-to-rail current-steering DAC structure with a self-calibration function includes a digital input register, a decoder, a PMOS current source differential drive, an NMOS current source differential drive, a PMOS current source, an NMOS current source, a digital pre-calibration module, and a strobe switch. The digital input register receives external digital inputs and transmits them to the decoder. After decoding the input digital signals, the decoder transmits the digital signals to the PMOS current source differential drive and the NMOS current source differential drive. The PMOS current source differential drive and the NMOS current source differential drive are respectively connected to the PMOS current source and the NMOS current source. The digital pre-calibration module is connected to the PMOS current source and the NMOS current source. The strobe switch is connected to the PMOS current source and the NMOS current source.

[0027] When the DAC is powered on, it will first enter the digital pre-calibration mode. The digital pre-calibration module mainly uses the core digital logic module to control the operation of the entire circuit and control the corresponding switch to select the circuit, ensuring that the circuit is disconnected from the outside world during calibration. Here, it is assumed that the current-steering DAC of this invention is a 10-bit DAC.

[0028] As Figure 2 and 4 shown, when the circuit is powered on and enters the pre-calibration mode, all digital modules (403), (405), (406), and (501) are reset. Special attention should be paid to the reset of the positive feedback modules (405) and (406). After the reset is completed, the circuit officially enters the pre-calibration process, and the gate voltages of the NMOS and PMOS current sources are calibrated in sequence. Figure 2 In the output module shown in (101) of [reference], the NMOS (102) current source and the PMOS current source (105) in [reference] are examples of one of the current source arrays. In the actual circuit, VN and VP are connected in parallel to the gates of all corresponding current sources to calibrate each current source. At this time, the input of the decoder circuit is disconnected from the DAC digital input and clamped to "10b'1000000000" by the digital pre-calibration module, so that the ideal expected voltage values of nodes (103) and (104) at this time are 1 / 2*VDD.

[0029] When calibrating the gate voltage of the NMOS current source, close the S4 switch of the (301) switch array and disconnect the S3 switch. At this time, the P half-output (103) of the differential output in the output module of (101) is coupled to the negative input terminal of the comparator (404) of the (401) module, and the 1 / 2*VDD voltage generated by the resistor voltage division network is sent to the positive input terminal of the comparator (404).

[0030] Resistor voltage division network: As shown in the 205 resistor network in the figure, since the gate voltage bias value of the current source is not fluctuated too much due to external environment and other factors, we can make R 1 and R n be resistors with a resistance ratio much larger than R 2 -R n-1 . Where Verror is the maximum fluctuation of the bias voltage of the current source caused by process and other non-ideal factors. To ensure that the voltage range generated at the top and bottom of the resistor array is greater than the maximum value of the error to be calibrated.

[0031]

[0032] When the NMOS current source calibration starts, the digital logic module turns on the switch in the switch array (203) that is connected to the lowest voltage in the resistor network (202). S5 is switched from the lower port to the upper port, enabling the MUX (405) to be coupled to the flip-flop and coupling the lowest output voltage in the resistor network to the gates of all NMOS current sources in the NMOS current source array in module (101). At this time, the voltage of the corresponding gate changes the current magnitude of each MOS current source, and is converted into the voltage at node (103) through the load resistor. This voltage is output to the negative input terminal of the comparator (404). The comparator outputs the comparison result to the CK terminal of the D flip-flop (403) and serves as the clock signal for the flip-flop. This flip-flop is triggered on the falling edge. During design, it is ensured that the voltage at node (103) corresponding to the VN gate voltage at this time is lower than 1 / 2*VDD, that is, the output of the comparator is high when the comparison starts, and the output of the D flip-flop is 0 at this time. At the same time, the CK signal is input to the digital logic module (501), and the shift register in the digital logic module controls the switch array (203) to turn on one by one in sequence. The VN voltage gradually rises until the voltage (103) converted from the VN voltage is within the voltage difference generated by one resistor step higher than 1 / 2*VDD voltage. The output of the comparator (404) flips from high level to low level, and the flip-flop (403) transfers the data "1" at the D terminal to the output terminal Q. At this time, switch S5 is closed at the upper port, and S6 is closed at the lower port "0". After Q becomes "1", the positive feedback circuit (405) composed of the MUX continuously maintains the output as "1". At this time, FLAG1 after passing through the inverter is 0, that is, the output of the AND gate composed of FLAG1 and CK at this time is 0, disabling CK from the digital logic module. The shift register stops working and no longer changes the state of the switch array (203), and the gate bias voltage applied to VN is fixed, and the NMOS current source calibration ends.

[0033] After the digital logic module circuit detects that FLAG1 = 0, it continues to enter the PMOS current source output calibration state. Switch S4 is disconnected, and switch S3 is closed to reset the D flip-flop (403), digital logic circuit (501), and positive feedback circuit (405). Voltage (104) is transmitted to the negative input terminal of the comparator (404). Meanwhile, the shift register within the digital logic module will strobe and control the resistor array (206). At this time, switch S6 will be toggled to the upper port and connected to the Q output terminal of the flip-flop. For the same reason, at this time, the voltage of the endpoint (104) controlled by the PMOS current source is lower than 1 / 2*VDD, and the output of the comparator (404) is high. With the input of the clock signal, the switches of the shift register controlling the switch array (206) are sequentially turned on one by one. The VP voltage increases step by step until the voltage of (104) converted from the VP voltage is just higher than 1 / 2*VDD by a voltage difference generated by one resistor step. The output of the comparator (404) is inverted from high level to low level, causing the output of the Q terminal to change from low level to high level. The output is latched to the high level via the positive feedback latch module (406). At this time, "FALG2" will be changed to the low level, and the CK signal is no longer enabled for the digital logic module. At this time, the shift register within the digital logic module stops shifting, the switch array (206) it controls also remains constant, and the VP voltage remains constant.

[0034] After the calibration mode ends, the circuit will maintain the calibrated VN and VP voltages and enter the normal digital-to-analog conversion mode. The input of the decoder in the circuit is the digital register at the input terminal of the current-steering DAC. The input digital code is decoded to the drive circuit through the symmetric decoder. The symmetric decoder realizes equal output signals when the input digital signal is differential. As Figure 3 shown, when the most significant bit of the input digital code is 0, the MUX selects and passes the input digital signals D(1), D(2) …… D(N - 1). The decoder normally decodes the input digital code except for the most significant bit. At this time, the most significant bit is 0, and whether to decode the most significant bit does not affect its decoded output. When the most significant bit is 1, the MUX selects and passes the inverse of the input digital signal. The decoder normally decodes the inverse of the input digital code except for the most significant bit. In this way, symmetric decoding is achieved, making the decoded outputs equal when the input differential digital codes are input, thereby realizing the function of symmetric decoding.

[0035] The four-element drive circuit controls the switches of the PMOS current source module and the NMOS current source module array respectively, and converts the output current into the double-differential output voltages POUT_P, POUT_N, NOUT_P, and NOUT_N through the load resistors.

[0036] The strobe switch detects the most significant bit of the input digital code of the current-steering DAC to determine the ratio of the output analog quantity to 1 / 2*VDD. If the most significant bit of the digital code is 0, it means that the analog voltage signal output from the positive terminal of the current-steering DAC is less than 1 / 2*VDD, and the positive output terminal is strobed to POUT_P. Similarly, the negative terminal is strobed to NOUT_P. If the most significant bit of the digital code is 1, it means that the analog voltage signal output from the positive terminal is greater than 1 / 2*VDD, and the positive output terminal is strobed to NOUT_P. Similarly, the negative terminal is strobed to POUT_P, thereby realizing the output of a differential rail-to-rail voltage signal.

[0037] The above are only the embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various changes and modifications can be made to the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A rail-to-rail current-steering DAC structure with a self-calibration function, Characterized in that, It includes a digital input register, a decoder, a PMOS current source differential drive, an NMOS current source differential drive, a PMOS current source, an NMOS current source, a digital pre-calibration module, and a strobe switch. The digital input register receives an external digital input and transmits it to the decoder. After the decoder decodes the input digital signal, it transmits the digital signal to the PMOS current source differential drive and the NMOS current source differential drive. The PMOS current source differential drive and the NMOS current source differential drive are respectively connected to the PMOS current source and the NMOS current source. The digital pre-calibration module is connected to the PMOS current source and the NMOS current source. The strobe switch is connected to the PMOS current source and the NMOS current source; When this DAC structure works, it is divided into: a pre-calibration mode and a normal digital-to-analog conversion mode; The pre-calibration mode is as follows: Set the current-steering DAC as a 10-bit DAC. Before the circuit officially starts digital-to-analog conversion, the circuit will first enter the pre-calibration mode. At this time, the pre-calibration mode will temporarily disconnect the external digital input of the DAC and the circuit strobe switch module, so that there is no output signal at OUTP and OUTN, and clamp the output of the input digital register to a fixed digital value "10b'1000000000". The digital input register synchronizes the clamped digital signal through the clock and then transmits it to the decoder unit. The decoder decodes the input digital signal and then transmits the digital signal to the current source differential drive unit, so that the synchronized multiple digital output signals after decoding are used as the drive signals for each current source MOS switch, thereby controlling the on and off of each current source switch to control the magnitude of the total output current, and converting it into the analog voltage signal required by the circuit through the load resistor. The gate voltage biases of the NMOS and PMOS current sources will be calibrated in sequence. When the DAC starts, it enters the reset state. At this time, the digital clock signal used for calibration and the gate voltage biases of the PMOS current source and the NMOS current source generated by the reference module at this time are used as the inputs of the calibration module. After resetting each position of the digital signal, calibration starts. The digital clock signal is used as the clock signal of the pre-calibration module to control the counter in the pre-calibration module to count, thereby controlling the internal resistor array. At the same time, the two outputs of P_OUTP and N_OUTP are respectively compared with the standard 1 / 2 supply voltage generated by resistor voltage division to control the counting of the counter, thereby changing the magnitudes of the gate voltages of the PMOS current source array and the NMOS current source array. After calibration, the gate voltage biases of the calibrated current source arrays are locked in the corresponding positions. The digital pre-calibration module outputs the calibrated gate voltage biases of the PMOS current source and the NMOS current source arrays, and fixes the bias voltage unchanged before the next pre-calibration mode comes. Through the above process, the NMOS current source voltage bias and the PMOS current source voltage bias are calibrated in sequence.

2. The rail-to-rail current-steering DAC structure with self-calibration function according to claim 1, characterized in that, the normal digital-to-analog conversion mode is as follows: After pre-calibration is completed, the digital pre-calibration module enables the gating switch. The digital input register reads the digital signal input to the current-steering DAC, synchronizes it through the register, and then inputs a 10-bit synchronous digital code to the decoder unit. The decoder unit decodes the input digital code into multiple digital signals through a symmetric decoder, and inputs the decoded digital signals to the PMOS current source switch driving unit and the NMOS current source switch driving unit respectively. The inputs of the two switch driving units are the same. The digital signals after passing through the driving unit are used as the switch driving outputs INP#P, INN#P, INP#N, INN#N. And INP#N and INN#P, INP#P and INN#N are signals with the same logic. And INP#N and INN#P have the same logic as the decoded digital signal output by the decoder. INP#P and INN#N have the opposite logic to the decoded digital signal output by the decoder. The digital signals output by the driving module are used as the gate voltages of the MOS switches to control whether each path of the output current source array is turned on or off, thereby controlling the magnitude of the output current, and thus controlling the magnitude of the current applied to the load resistor.

3. The rail-to-rail current-steering DAC structure with self-calibration function according to claim 2, characterized in that, this DAC adopts a quaternary drive: after current source differential drive, each of the PMOS current source and NMOS current source switch arrays has a set of differential digital signals to control the differential output of its current source, so as to output double-differential voltages, namely NOUT_P, NOUT_N, POUT_P, POUT_N respectively. As the input digital code increases, the output POUT_P voltage ranges from 0 to 1 / 2*VDD to 0, the POUT_N voltage ranges from 1 / 2*VDD to 0 to 1 / 2*VDD; the NOUT_N voltage ranges from 1 / 2*VDD to VDD to 1 / 2*VDD, and the NOUT_P voltage ranges from VDD to 1 / 2*VDD to VDD.

4. The rail-to-rail current-steering DAC structure with self-calibration function according to claim 3, characterized in that, the decoder adopts a symmetric decoder such that the four outputs of the decoder reach the maximum value of the decoder output when the input digital code of the decoder is the middle value of "10b’1000000000", and the outputs are symmetric left and right, that is, the outputs are the same when the differential digital signals are input to the decoder.

5. The rail-to-rail current-steering DAC structure with self-calibration function according to claim 4, characterized in that, when the gating switch module is gated at the output end, it needs to detect the highest-bit digital code of the DAC input digital signal. When the highest-bit digital code is 0, the positive terminal is gated to POUT_P and the negative terminal is gated to NOUT_P; when the highest-bit digital code is 1, the positive terminal is gated to NOUT_P and the negative terminal is gated to POUT_P, thereby realizing the output of differential rail-to-rail voltage signals.

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