A knee point detection circuit based on slope detection

Abstract

The present application belongs to the technical field of power management, and particularly relates to a knee point detection circuit based on slope detection. The circuit of the present application performs differential operation on a feedback reference voltage to generate a differential current, and then inputs the differential operation result into a comparator. When the knee point is reached, the feedback reference voltage will rapidly drop, the differential voltage after the differential operation rapidly increases, and then the comparator is triggered to flip over, so that the knee point is detected. The present application can accurately detect the knee point position of the feedback reference voltage, and provide a control signal for sampling the knee point voltage of the feedback reference voltage.

Description

Technical Field

[0001] This invention belongs to the field of power management technology, specifically relating to a knee detection circuit based on slope detection. Background Technology

[0002] In power management topologies, flyback converters have become a research hotspot due to their ease of achieving electrical isolation between input and output, relatively simple peripheral circuitry, and low cost. Flyback converters can be categorized into primary-side feedback and secondary-side feedback types based on their output feedback method. Primary-side feedback flyback converters, by eliminating the need for optocouplers and the TL431, offer better miniaturization compared to secondary-side feedback flyback converters and exhibit better temperature characteristics, thus gaining market attention.

[0003] In a primary-side feedback flyback converter, the output voltage information of the flyback circuit is divided and fed back to the primary-side control chip via an auxiliary winding or primary winding. The control chip samples the feedback reference voltage, and the converter loop adjusts the output voltage based on the sampled voltage containing the output voltage information. Therefore, accurate sampling is crucial for achieving a precise and constant output voltage. The sampling of the feedback reference voltage in a primary-side feedback flyback converter is typically accomplished by two modules: knee detection and sample-and-hold. The knee detection module detects the "knee" of the feedback reference voltage and generates a sampling signal to sample the feedback reference voltage. Therefore, the accuracy of the knee detection determines the accuracy of the sampled voltage. Summary of the Invention

[0004] This invention mainly proposes a knee point detection circuit based on slope detection. This circuit performs a differential operation on the feedback reference voltage to generate a differential current, and then inputs the result of the differential operation into a comparator. When the knee point is reached, the feedback reference voltage drops rapidly, and the differential voltage after the differential operation increases rapidly, triggering the comparator to flip and thus detecting the knee point.

[0005] The technical solution of this invention is as follows:

[0006] A knee detection circuit based on slope detection is used for knee detection in a primary-side feedback flyback converter. The feedback reference voltage of the primary-side feedback flyback converter is defined as V. RREF The detection circuit is characterized in that it includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first capacitor, a second capacitor, a first resistor, a voltage source, a first comparator, a second comparator, and logic circuitry.

[0007] The drain of the first NMOS transistor is connected to V. RREF Its gate is connected to the inverse signal of the leading edge blanking signal, and its source is connected to the drain of the second NMOS transistor and one end of the first capacitor.

[0008] The gate of the second NMOS transistor is connected to the leading-edge blanking signal, and its source is connected to the other end of the first capacitor, the inverting input of the first comparator, one end of the first resistor, and the negative terminal of the voltage source.

[0009] The drain of the third NMOS transistor is connected to V. RREF Its gate is connected to the inverted signal of the leading edge blanking signal, and its source is connected to one end of the second capacitor and the non-inverting input of the first comparator; the other end of the second capacitor is grounded.

[0010] The output of the first comparator is connected to the other end of the first resistor and the non-inverting input of the second comparator. The inverting input of the second comparator is connected to the positive terminal of the voltage source.

[0011] The output of the second comparator is connected to the input of the logic circuit and the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the leading-edge blanking signal, and its source is grounded.

[0012] The logic circuit is a single-wave extraction logic circuit, and the logic circuit outputs the detected knee voltage signal.

[0013] Furthermore, the second comparator is a fast comparator, including a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a current source, a second resistor, a third resistor, a first inverter, and a second inverter;

[0014] The source of the first PMOS transistor is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the input terminal of the current source; the output terminal of the current source is grounded.

[0015] The source of the second PMOS transistor is connected to the power supply, and its gate is connected to the drain of the first PMOS transistor. The drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor and the source of the fifth PMOS transistor.

[0016] The source of the third PMOS transistor is connected to the power supply, and its gate is connected to the drain of the first PMOS transistor. The drain of the third PMOS transistor is connected to the source of the seventh PMOS transistor and the source of the eighth PMOS transistor.

[0017] The gate of the fourth PMOS transistor is the non-inverting input of the second comparator, and its drain is grounded through the second resistor; the gate of the fifth PMOS transistor is the inverting input of the second comparator, and its drain is grounded through the third resistor.

[0018] The source of the sixth PMOS transistor is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the drain of the fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the source of the fifth NMOS transistor is grounded.

[0019] The gate of the seventh PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the seventh PMOS transistor is connected to the gate and drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded.

[0020] The gate of the eighth PMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the eighth PMOS transistor is connected to the gate and drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor; the source of the seventh NMOS transistor is grounded.

[0021] The source of the ninth PMOS transistor is connected to the power supply, and its gate is connected to the drain of the sixth PMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the eighth NMOS transistor and the input terminal of the first inverter; the source of the eighth NMOS transistor is grounded.

[0022] The input of the second inverter is connected to the output of the first inverter, and the output of the second inverter is the output of the second comparator.

[0023] The beneficial effects of the present invention are as follows: the present invention can accurately detect the knee position of the feedback reference voltage, and provide a control signal for subsequent knee voltage sampling of the feedback reference voltage. Attached Figure Description

[0024] Figure 1 Schematic diagram of a primary-side feedback flyback converter with auxiliary winding.

[0025] Figure 2 Schematic diagram of a primary-side feedback flyback converter without auxiliary windings.

[0026] Figure 3 Waveforms of the feedback reference voltage and inductor current.

[0027] Figure 4 The circuit framework diagram of the knee point detection based on slope detection proposed in this invention.

[0028] Figure 5 The waveform diagram of the slope detection knee point detection circuit proposed in this invention.

[0029] Figure 6 The schematic diagram of the fast comparator A2 circuit proposed in this invention.

[0030] Figure 7 The schematic diagram of the logic module circuit proposed in this invention.

[0031] Figure 8 The working principle diagram of the logic module circuit proposed in this invention. Detailed Implementation

[0032] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0033] The schematic diagrams of the primary-side feedback flyback converters with and without auxiliary windings proposed in this invention are shown below. Figure 1 As shown in Figure 2, the waveforms of the feedback reference voltage and inductor current are as follows: Figure 3 As shown. When the t0-t1 converter is in primary-side conduction mode for t... on During this stage, the feedback reference voltage V RREF The value is 0; when the t1-t3 converter is in the secondary side demagnetization t off During this stage, V is affected by the leakage inductance of the primary-side inductor and the parasitic capacitance of the primary-side main power transistor. RREF Ringing occurs during the t1-t2 phase. To prevent false triggering of the knee detection circuit, this ringing time is masked; this masking time is called the leading-edge blanking time. After the leading-edge blanking, the knee detection circuit begins to operate. Because converters with and without auxiliary windings feed the output voltage back to the primary side differently, converters with auxiliary windings directly generate the feedback reference voltage V by dividing the voltage from the flyback to the auxiliary winding. RREF The converter without auxiliary windings is clamped to the feedback resistor R via the VIN clamping module. FB The voltage signal fed back to the primary winding is converted into a current signal and then passed through the feedback reference resistor R. REF Forming a feedback reference voltage V RREF Therefore, the feedback reference voltage can be expressed as:

[0034] V RREF (t)=K[V OUT +V F (t)+I S (t)R par ]

[0035]

[0036] Where K is the feedback coefficient, and the feedback coefficient with the auxiliary winding converter is K. AUX The feedback coefficient without an auxiliary winding converter is K. WIO V OUT V is the output voltage. F I is the forward voltage drop of the secondary freewheeling diode D. S R is the secondary inductor current. par N is the parasitic resistance of the second side. AS To adjust the turns ratio of the auxiliary winding and the secondary transformer, N PS R is the turns ratio of the primary and secondary transformers. f1 With Rf2 For feedback voltage divider resistors, R FB For the feedback resistor, R REF This is the feedback reference resistor.

[0037] During this stage, the secondary inductor current decreases linearly with time, and the forward voltage drop of the freewheeling diode D also changes with the inductor current. Therefore, it is necessary to sample the feedback reference voltage when the secondary inductor current is zero to eliminate the effects of parasitic capacitance and forward voltage drop. After the secondary current drops to zero, V... RREF It will drop rapidly, so the point corresponding to the moment when the secondary current is 0 is called the "knee point".

[0038] During the time period t3-t4, the parasitic capacitance C of the power transistor... par and the primary excitation inductance L m The impact, V RREF Resonance will occur again, and its resonant frequency can be expressed as:

[0039]

[0040] Then V RREF The voltage at the first falling edge during the resonance phase can be expressed as:

[0041]

[0042] The circuit framework diagram of the knee point detection based on slope detection proposed in this invention is as follows: Figure 4 As shown, it mainly consists of two parts: a slope differentiating circuit and a fast comparator. The waveform of the knee point detection circuit based on slope detection is shown below. Figure 5 As shown.

[0043] Firstly, for the slope differentiating circuit section, MN1 and MN2 are used to realize the slope differentiating V. RREF The shielding during the step and resonance phases is respectively determined by V nLEB The opposite signal V LEB Control, V LEB This is the leading-edge blanking signal, which is high during the leading-edge blanking time. During the leading-edge blanking time, transistor MN1 is turned off, "cutting off" V. RREF In connection with the differentiating circuit, MN2 transistor is turned on, which in turn affects the differentiating capacitor C. diff A short circuit ensures that the capacitor stores zero charge, thus guaranteeing V. RREF When connected, it can accurately measure V RREF Perform differentiation operations.

[0044] MN3 and C ref Used for V RREF Coarse sampling is performed to ensure the accuracy of sampling during circuit startup. After the leading-edge blanking time, MN3 disconnects V.RREF With C ref The connection, C ref Roughly sampled V in the nth period RREF The platform voltage value, i.e., V ref =V RREF (n), due to V ref Still includes R par Information such as this cannot accurately reflect the output voltage value, and therefore cannot be used as the sampling voltage. However, due to the V after leading-edge blanking... RREF The change is small before the knee point, i.e., V ref The difference between the voltage at the knee and the voltage at the knee is small, therefore the V obtained by coarse sampling is relatively small. ref As an adaptive reference voltage pair V smo Clamping is performed to reduce the time required for clamping and ensure the accuracy of differential calculations.

[0045] V RREF After differentiation, the output voltage V of the differentiating circuit is... diff They can be represented as follows:

[0046] V diff (t)=V ref +πf r ·R diff C diff KV OUT sin2πf r t

[0047] Among them, R diff With C diff These are the differential resistor and differential capacitor, respectively. Then V RREF V during the resonance phase diff With V smo The difference is expressed as

[0048] △V=V diff -V smo =πf r ·R diff C diff KV OUT sin2πf r t

[0049] V diff With V smo The voltage is input to the fast comparator when ΔV > V. OS The time comparator flips, where V OS This is the comparator offset voltage. Because V diff and V smo The difference eliminates the DC component and contains only the resonance information, thus allowing for accurate calculation of the delay between the knee point and the comparator flip point.

[0050]

[0051] Due to the vanishing time before the knee point V RREF Due to non-ideal factors such as secondary parasitic resistance, an inherent slope will be generated, therefore V diff With V ref There exists a non-zero difference; the comparator's offset voltage Vos needs to be higher than this difference to avoid false triggering. To further reduce the possibility of false triggering, the offset voltage is set with a 50% margin; therefore, the offset voltage is set to...

[0052]

[0053] During the leading edge blanking time, MN4 pulls the output down to ground potential, providing double protection to prevent the knee detection circuit from being falsely triggered during the ringing phase.

[0054] To reduce comparison delay and achieve accurate knee detection, comparator A2 employs a two-stage amplification method, and its circuit schematic is shown below. Figure 6 As shown. There are four sets of current mirrors with the following ratios: MP1:MP2:MP3=1:K1:K2, MP6:MP7=1:K3, MN1:MN2=1:1, MN3:MN4=1:K3.

[0055] The first stage of the fast amplifier is a pre-amplification module with two functions: amplifying the input voltage difference and setting the comparator offset. This stage features low gain and high bandwidth, rapidly amplifying the input voltage difference by a certain factor to convert the small-signal voltage difference into a large-signal voltage difference input to the secondary amplification module, reducing the delay caused by the small signal. Within the common-mode input range, MP4 and MP5 always operate in the saturation region, and the current flowing through R1 and R2 is:

[0056]

[0057] Where (W / L)1 is the aspect ratio of MP4, and (W / L)2 is the aspect ratio of MP5. This can be obtained using KCL's law.

[0058] i1+i2=K1·I bias

[0059] When the voltage at point A equals the voltage at point B, comparator A2 flips. Therefore, the voltage difference at which the comparator flips can be expressed as...

[0060]

[0061] To achieve better matching, MP4 and MP5 use the same components and have the same dimensions, and are connected without a bias resistor. The offset voltage can then be adjusted using R1 and R2.

[0062]

[0063] The second part is the secondary amplification module, consisting of a symmetrical OTA operational amplifier with high gain and high SR, and two shaping inverters. Since comparator A2 uses a two-stage amplification, its small-signal delay is negligible compared to its large-signal delay; therefore, the delay generated by the comparator can be expressed as…

[0064]

[0065] Among them, V DD To power the high rail, the inverter's switching requires the comparator's output voltage to be V. DD / 2, C OUT,comp This is the output node capacitor for the OTA op-amp.

[0066] Considering the delay caused by the comparator, the knee point to the output V of comparator A2 comp The delay correction caused by the flip point is

[0067]

[0068] V RREF At resonance, it approximates a cosine waveform. When the voltage drops, specifically at times t4 and t6, the comparator output V will be affected. comp The flipping can lead to misidentification of the knee point. The digital logic circuit of the logic module can effectively avoid this problem, and its circuit schematic is shown below. Figure 7 As shown. When the comparator detects the first V RREF When the slope is negative, V comp The signal jumps to a higher level, triggering the logic module to obtain the first square wave information. Then, the logic module locks down, V comp Subsequent square waves will no longer trigger V. knee Flip it to avoid knee point detection errors.

[0069] The working waveform of the Logic module is as follows Figure 8 As shown, the Driver signal is the primary-side power switch control signal, V PLEB The signal is the primary-side leading-edge blanking signal. When the Driver signal is high, the primary-side power transistor is turned on; when it is low, the primary-side power transistor is turned off. V PLEB It turns high within a narrow pulse time after the Driver signal turns high. When the Driver signal turns high, V... PLEBThe falling edge triggers the D flip-flop, and Q2 is sampled as high. At this time, no knee point is detected, V comp Keep it low, V knee The output is low. When the knee point is detected, the comparator toggles the output of the first square wave's rising edge, while Q2 remains high, corresponding to the high V. comp The combination of V knee Flip up, when the detected V comp On the falling edge, the D flip-flop is triggered to sample and obtain Q2 as low, causing V to... knee The signal drops. Afterward, although a continuous decrease in the feedback reference signal is detected, the Driver signal remains low because the primary-side power transistor is off. Therefore, the triggered Q2 remains low, and V... knee The level does not change during this cycle.

Claims

1. A knee detection circuit based on slope detection for knee detection in a primary-side feedback flyback converter, wherein the feedback reference voltage of the primary-side feedback flyback converter is defined as V. RREF Its characteristics are, The detection circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first capacitor, a second capacitor, a first resistor, a voltage source, a first comparator, a second comparator, and logic circuitry. The drain of the first NMOS transistor is connected to V. RREF Its gate is connected to the inverse signal of the leading edge blanking signal, and its source is connected to the drain of the second NMOS transistor and one end of the first capacitor. The gate of the second NMOS transistor is connected to the leading-edge blanking signal, and its source is connected to the other end of the first capacitor, the inverting input of the first comparator, one end of the first resistor, and the negative terminal of the voltage source. The drain of the third NMOS transistor is connected to V. RREF Its gate is connected to the inverted signal of the leading edge blanking signal, and its source is connected to one end of the second capacitor and the non-inverting input of the first comparator; the other end of the second capacitor is grounded. The output of the first comparator is connected to the other end of the first resistor and the non-inverting input of the second comparator. The inverting input of the second comparator is connected to the positive terminal of the voltage source. The output of the second comparator is connected to the input of the logic circuit and the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the leading-edge blanking signal, and its source is grounded. The logic circuit is a single-wave extraction logic circuit, and the logic circuit outputs the detected knee voltage signal. The second comparator is a fast comparator, comprising a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a current source, a second resistor, a third resistor, a first inverter, and a second inverter; The source of the first PMOS transistor is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the input terminal of the current source; the output terminal of the current source is grounded. The source of the second PMOS transistor is connected to the power supply, and its gate is connected to the drain of the first PMOS transistor. The drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor and the source of the fifth PMOS transistor. The source of the third PMOS transistor is connected to the power supply, and its gate is connected to the drain of the first PMOS transistor. The drain of the third PMOS transistor is connected to the source of the seventh PMOS transistor and the source of the eighth PMOS transistor. The gate of the fourth PMOS transistor is the non-inverting input of the second comparator, and its drain is grounded through the second resistor. The gate of the fifth PMOS transistor is the inverting input of the second comparator, and its drain is grounded through the third resistor. The source of the sixth PMOS transistor is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the source of the fifth NMOS transistor is grounded. The gate of the seventh PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the seventh PMOS transistor is connected to the gate and drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded. The gate of the eighth PMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the eighth PMOS transistor is connected to the gate and drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor; the source of the seventh NMOS transistor is grounded. The source of the ninth PMOS transistor is connected to the power supply, and its gate is connected to the drain of the sixth PMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the eighth NMOS transistor and the input terminal of the first inverter; the source of the eighth NMOS transistor is grounded. The input of the second inverter is connected to the output of the first inverter, and the output of the second inverter is the output of the second comparator. The voltage source is set to be higher than V. diff and V ref The difference, where V diff It is V RREF Voltage after differentiation: ， Among them, V ref It is C ref V sampled in the nth period RREF The platform voltage value, R diff With C diff These are the differential resistor and differential capacitor, respectively, where K is the feedback coefficient and V is the differential capacitor. OUT For output voltage, It is V RREF The resonant frequency.

Images