Power conversion device and control method for power conversion device

Abstract

In a case where the frequency of the carrier cannot be set sufficiently high with respect to the voltage command value, as the phase of the carrier is shifted from the voltage command value, the symmetry of the output voltage is broken, and an increase in high-order harmonics contained in the voltage / current generated by the power conversion section becomes a problem. A power conversion device including: a power conversion section that controls the on / off of a plurality of switching elements to convert electric power; and a gate pulse generation section that generates a gate pulse signal for controlling the on / off of the switching elements based on a plurality of phase first voltage command values indicating a desired output voltage, in the power conversion device, the gate pulse generation section generates a carrier whose phase is synchronized with the first voltage command values based on the plurality of phase first voltage command values, and generates a second voltage command value by adding the carrier to the first voltage command values.

Description

Technical Field

[0001] This invention relates to a power conversion device and a control method for the power conversion device. Background Technology

[0002] For example, various circuit configurations are known in power converters that convert DC power to AC power. For high-voltage applications, multi-stage power converters consisting of multiple single-phase bridge circuits connected in series are frequently used.

[0003] The switching elements within the power conversion unit are operated by gate pulse signals that are input to indicate whether they are turned on or off. A common method for generating these gate pulse signals is PWM (Pulse Width Modulation) control. In this control, the gate pulse signal is generated based on a voltage command value indicating the desired output voltage and a separately generated carrier wave, such as a triangular wave. Heat generation occurs in the power conversion unit due to switching losses of the switching elements. Therefore, in practical applications, there is an upper limit to the carrier frequency, and control is implemented to suppress the number of switching operations (pulse count) as much as possible.

[0004] Patent document 1 describes the following control method: PWM pulses are generated by comparing the carrier wave with the output voltage command, and the carrier wave amplitude or carrier wave frequency is gradually reduced.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent document 1: Japanese Patent Application Publication No. 2003-319662. Summary of the Invention

[0008] The problem the invention aims to solve

[0009] When the carrier frequency cannot be set high enough relative to the voltage command value, the increase in high-order harmonics contained in the voltage / current output from the power conversion unit becomes a problem.

[0010] Solution for solving the problem

[0011] The power conversion apparatus of the present invention includes: a power conversion unit that controls the switching on and off of a plurality of switching elements to convert power; and a gate pulse generation unit that generates a gate pulse signal for controlling the switching on and off of the switching elements based on first voltage command values ​​of a plurality of phases indicating a desired output voltage. In the power conversion apparatus, the gate pulse generation unit generates a carrier wave whose phase is synchronized with the first voltage command value based on each of the plurality of phases, and adds the carrier wave to the first voltage command value to generate a second voltage command value.

[0012] The control method of the power conversion device of the present invention comprises: a power conversion unit that controls the switching on and off of a plurality of switching elements to convert power; and a gate pulse generation unit that generates a gate pulse signal for controlling the switching on and off of the switching elements based on first voltage command values ​​of a plurality of phases indicating a desired output voltage. In the control method of the power conversion device, the gate pulse generation unit generates a carrier wave whose phase is synchronized with the first voltage command value based on each of the first voltage command values ​​of the plurality of phases, and adds the carrier wave to the first voltage command value to generate a second voltage command value.

[0013] The effects of the invention

[0014] According to the present invention, even when the carrier frequency cannot be set high enough relative to the voltage command value, higher harmonics can be suppressed. Attached Figure Description

[0015] Figure 1 This is a block diagram of a power conversion device.

[0016] Figure 2 This is a circuit diagram of a converter cell.

[0017] Figure 3 This is a block diagram of the primary side gate pulse generation section.

[0018] Figure 4 This is a block diagram of the carrier generation unit.

[0019] Figure 5 (a) to (e) are diagrams showing the waveforms of signals, etc., when set to "k=3".

[0020] Figure 6 This is a block diagram of the primary side gate pulse generation section in the comparative example.

[0021] Figure 7 (a) to (e) are diagrams showing the waveforms of the signals, etc., in the comparative examples.

[0022] Figure 8 (a) to (e) are diagrams showing the waveforms of signals, etc., when set to "k=5".

[0023] Figure 9 (a) to (e) are diagrams showing the waveforms of signals, etc., in the second embodiment when “k=3” is set.

[0024] Figure 10 This is a block diagram of the power conversion device in the third embodiment.

[0025] Figure 11This is a circuit diagram of the power conversion unit in the third embodiment.

[0026] Figure 12 This is a block diagram of the carrier generation unit in the fourth embodiment.

[0027] Figure 13 (a) to (e) are diagrams showing the waveforms of signals, etc., in the fourth embodiment when “k=4” is set. Detailed Implementation

[0028] [First Implementation Method]

[0029] Figure 1 This is a block diagram of the power conversion device 100 according to the first embodiment.

[0030] The power conversion device 100 includes a power conversion unit 101, a primary-side gate pulse generation unit 102, and a secondary-side gate pulse generation unit 103. The power conversion device 100 performs bidirectional or unidirectional power conversion between a primary-side system 30 and a secondary-side system 40, both of which are three-phase AC systems. Here, the primary-side system 30 has a neutral line 30N, an R-phase line 30R that generates the R-phase voltage, an S-phase line 30S that generates the S-phase voltage, and a T-phase line 30T that generates the T-phase voltage. The secondary-side system 40 has a neutral line 40N, a U-phase line 40U that generates the U-phase voltage, a V-phase line 40V that generates the V-phase voltage, and a W-phase line 40W that generates the W-phase voltage. Although not shown in the figures, a series of [something] are provided between the neutral line 30N and the T-phase line 30T, and between the neutral line 40N and the W-phase line 40W. Figure 1 The same power conversion device 100. Additionally, although the illustration is omitted, a connection is provided between the neutral line 30N and the S-phase line 30S, and between the neutral line 40N and the V-phase line 40V. Figure 1 The same power conversion device 100.

[0031] The voltage amplitude, frequency, and phase of the primary system 30 and the secondary system 40 are independent of each other. Furthermore, the R-phase, S-phase, and T-phase voltages have a phase difference of 2π / 3 from each other at the primary-side frequency, and the U-phase, V-phase, and W-phase voltages have a phase difference of 2π / 3 from each other at the secondary-side frequency. The primary system 30 and the secondary system 40 can be, for example, various power generation or receiving equipment such as commercial power systems, solar power systems, and motors.

[0032] The power conversion unit 101 has P converter units 20-1 to 20-P (P being a natural number of 2 or more). Hereinafter, converter units 20-1 to 20-P are sometimes collectively referred to as "converter unit 20". Converter units 20-1 to 20-P are connected in series between the R-phase line 30R and the neutral line 30N on the primary side. Similarly, on the secondary side, converter units 20-1 to 20-P are connected in series between the U-phase line 40U and the neutral line 40N.

[0033] The primary side control unit 104 detects the voltage and current of the primary side system 30 and outputs primary side voltage command values ​​VREFR, VREFS, and VREFT. Similarly, the secondary side control unit 105 detects the voltage and current of the secondary side system 40 and outputs secondary side voltage command values ​​VREFU, VREFV, and VREFW.

[0034] The primary-side gate pulse generation unit 102 generates gate pulse signals GT11~GT1P and GT11'~GT1P' for controlling the switching elements included on the primary side of the converter units 20-1~20-P. Similarly, the secondary-side gate pulse generation unit 103 generates gate pulse signals GT21~GT2P and GT21'~GT2P' for controlling the switching elements included on the secondary side of the converter units 20-1~20-P.

[0035] Figure 2 This is the circuit diagram of converter unit 20-1. Converter units 20-2 to 20-P are the same as converter unit 20-1, so their detailed descriptions are omitted.

[0036] The converter unit 20-1 has a pair of primary side terminals 21a, 21b, a pair of secondary side terminals 22a, 22b, AC-DC power converters 23-26, capacitors 27, 28, and a high-frequency transformer 29.

[0037] The AC-DC power converter 23 has four switching elements Q1-Q4 connected in an H-bridge configuration, and an FWD (Free Wheeling Diode, not shown in the figure) connected in reverse parallel with these switching elements Q1-Q4. The switching elements Q1-Q4 are controlled by gate pulse signals GT11-GT1P and GT11'-GT1P'.

[0038] Furthermore, AC-DC power converter 26 has four switching elements Q5-Q8 connected in an H-bridge configuration, and a gate-controlled power supply (FWD) connected in reverse parallel with these switching elements Q5-Q8. Similarly, AC-DC power converters 24 and 25 have four switching elements connected in an H-bridge configuration, and a gate-controlled power supply (FWD) connected in reverse parallel with these switching elements (none are labeled in the figures). The switching elements Q5-Q8 are controlled using gate pulse signals GT11-GT1P and GT11'-GT1P'.

[0039] Furthermore, in this embodiment, these switching elements are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0040] The voltage appearing between primary side terminals 21a and 21b is called the primary side AC terminal voltage V1-1, and the voltage appearing between the two ends of capacitor 27 is called the primary side DC link voltage Vdc1. Furthermore, the AC-DC power converter 23 performs bidirectional or unidirectional conversion of the primary side AC terminal voltage V1-1 and the primary side DC link voltage Vdc1 to transmit power.

[0041] The high-frequency transformer 29 has a primary winding 29a and a secondary winding 29b, and transmits power between the primary winding 29a and the secondary winding 29b at a predetermined frequency. The AC-DC power converters 24 and 25 input and output high-frequency currents between themselves and the high-frequency transformer 29. Here, high frequency is, for example, a frequency of 100Hz or higher, but preferably a frequency of 1kHz or higher, and more preferably a frequency of 10kHz or higher. The AC-DC power converter 24 transmits power by bidirectionally or unidirectionally converting the primary-side DC link voltage Vdc1 and the AC voltage appearing in the primary winding 29a.

[0042] The voltage appearing between secondary terminals 22a and 22b is called the secondary AC terminal voltage V2-1, and the voltage appearing between the two ends of capacitor 28 is called the secondary DC link voltage Vdc2. AC-DC power converter 25 performs bidirectional or unidirectional conversion between the secondary DC link voltage Vdc2 and the AC voltage appearing in the secondary winding 29b to transmit power. Furthermore, AC-DC power converter 26 performs bidirectional or unidirectional conversion between the secondary AC terminal voltage V2-1 and the secondary DC link voltage Vdc2 to transmit power.

[0043] Here, the primary side gate pulse generation unit 102 (see reference) Figure 1Based on the primary side voltage command values ​​VREFR, VREFS, and VREFT, gate pulse signals GT11~GT1P and GT11'~GT1P' are generated to indicate either a "LOW" or "HIGH" state. Taking converter unit 20-1 as an example, gate signal GT11 is supplied to the switching elements Q1 and Q4 of AC-DC power converter 23 to control their on / off state. If gate signal GT11 is "high", switching elements Q1 and Q4 are in the on state; if gate signal GT11 is "low", switching elements Q1 and Q4 are in the off state. Similarly, gate signal GT11' is supplied to the switching elements Q2 and Q3 of AC-DC power converter 23 to control their on / off state.

[0044] In the AC-DC power converter 23, when switching elements Q1 and Q4 are in the ON state, the voltage between primary side terminals 21a and 21b is Vdc1; when switching elements Q2 and Q3 are in the ON state, the voltage between primary side terminals 21a and 21b is -Vdc1. Furthermore, when all switching elements Q1 to Q4 are in the OFF state, the voltage between primary side terminals 21a and 21b is zero. That is, the AC-DC power converter 23 can output three voltage levels (-Vdc1, 0, Vdc1).

[0045] Similar to the primary side gate pulse generation unit 102, the secondary side gate pulse generation unit 103 (see reference) Figure 1 Based on the secondary-side voltage command values ​​VREFU, VREFV, and VREFW, gate pulse signals GT21~GT2P and GT21'~GT2P' are generated to indicate "low" or "high" states. Taking converter unit 20-1 as an example, gate signal GT21 is supplied to the switching elements Q5 and Q8 of AC-DC power converter 26 to control their on / off states. That is, if gate signal GT21 is "high", switching elements Q5 and Q8 are in the on state; if gate signal GT21 is "low", switching elements Q5 and Q8 are in the off state. Similarly, gate signal GT21' is supplied to the switching elements Q6 and Q7 of AC-DC power converter 26 to control their on / off states.

[0046] In the AC-DC power converter 26, when switching elements Q5 and Q8 are in the ON state, the voltage between secondary side terminals 22a and 22b is Vdc2; when switching elements Q6 and Q7 are in the ON state, the voltage between secondary side terminals 22a and 22b is -Vdc2. Furthermore, when all switching elements Q5 to Q8 are in the OFF state, the voltage between secondary side terminals 22a and 22b is zero. That is, similar to the AC-DC power converter 23, the AC-DC power converter 26 of the power conversion unit 101 can output voltages at three levels (-Vdc2, 0, Vdc2).

[0047] Figure 3 This is a block diagram of the primary gate pulse generation unit 102. The primary gate pulse generation unit 102 includes a carrier generation unit 300, an adder 301, and comparators CMP11~CMP1P and CMP11'~CMP1P'.

[0048] The carrier generation unit 300 generates a carrier Sm whose phase is synchronized with the voltage command value VREFR based on the voltage command values ​​VREFR, VREFS, and VREFT of the R-phase, S-phase, and T-phase, which indicate the desired output voltage. Then, the voltage command value VREFR (first voltage command value) is added to the carrier Sm by the adder 301 to generate a voltage command value VREFR' (second voltage command value).

[0049] exist Figure 3 The diagram shows a carrier generation unit 300 corresponding to R, but the carrier generation unit 300 corresponding to S is omitted. Based on the voltage command values ​​VREFR, VREFS, and VREFT of the R-phase, S-phase, and T-phase indicating the desired output voltage, a carrier Sm whose phase is synchronized with the voltage command value VREFS is generated. Then, the voltage command value VREFS (first voltage command value) is added to the carrier Sm by adder 301 to generate a voltage command value VREFS' (second voltage command value).

[0050] Additionally, the carrier generation unit 300 corresponding to T in the illustration is omitted. Based on the voltage command values ​​VREFR, VREFS, and VREFT of the R-phase, S-phase, and T-phase indicating the desired output voltage, it generates a carrier Sm whose phase is synchronized with the voltage command value VREFT. Then, the voltage command value VREFT (first voltage command value) is added to the carrier Sm by the adder 301 to generate a voltage command value VREFT' (second voltage command value).

[0051] like Figure 3As shown, in comparators CMP11~CMP1P and CMP11'~CMP1P', the second voltage command value VREFR' is compared with thresholds 1~threshold P and thresholds 1'~threshold P', respectively, which are preset for the voltage magnitude. Gate pulse signals GT11~GT1P and GT11'~GT1P' are generated by comparators CMP11~CMP1P and CMP11'~CMP1P'. For example, comparator CMP11 sets the gate pulse signal GT11 low when the second voltage command value VREFR' is less than threshold 1, and sets the gate pulse signal GT11 high when the second voltage command value VREFR' is greater than threshold 1. Similarly, comparator CMP11' sets the gate pulse signal GT11' low when the second voltage command value VREFR' is greater than threshold 1', and sets the gate pulse signal GT11' high when the second voltage command value VREFR' is less than threshold 1'. The gate pulse signals GT11 and GT11' are output to converter unit 20-1.

[0052] The other comparators CMP12~CMP1P and CMP12'~CMP1P' operate the same, except for the different threshold values.

[0053] Although the diagram is omitted, the second voltage command value VREFS' and the second voltage command value VREFT' are also compared with the threshold 1 to threshold P and the threshold 1' to threshold P' respectively in the comparators CMP11~CMP1P and CMP11'~CMP1P' to generate gate pulse signals.

[0054] Figure 4 This is a block diagram of the carrier generation unit 300 corresponding to phase R. The carrier generation unit 300 includes a voltage command comparison unit 400, a voltage amplitude calculation unit 401, a triangular wave generation unit 402, a subtractor 403, a limiter 404, and a multiplier 405. The carrier generation unit 300 corresponding to phases S and T has the same structure, and its description is omitted.

[0055] The voltage command comparison unit 400 compares the first voltage command values ​​VREFR, VREFS, and VREFT with each other and outputs the maximum value Vmax and the minimum value Vmin among them.

[0056] The voltage amplitude calculation unit 401 calculates the voltage amplitude value Va according to the first voltage command values ​​VREFR, VREFS, and VREFT, and follows the formulas (1) to (3).

[0057] VREFA=√(2 / 3)·(VREFR-1 / 2·VREFS-1 / 2·VREFT)···(1)

[0058] VREFB=√(2 / 3)·(√(3) / 2·VREFS-√(3) / 2·VREFT)···(2)

[0059] Va=√(2 / 3) √(VREFA^2+VREFB^2)···(3).

[0060] In addition, the triangular wave generating unit 402 generates a triangular wave Stri with an amplitude of 1 according to the following formula (4) or (5).

[0061] In the case of [k=1, 5, 9, 13, ...], a triangular wave Stri with an amplitude of 1 is generated according to equation (4).

[0062] Stri=(2 / π)·arcsin(sin((k·π / Va)·(Vmax+Vmin)))…(4)

[0063] In the case of [k=3, 7, 11, 15, ...], a triangular wave Stri with an amplitude of 1 is generated according to equation (5).

[0064] Stri=-(2 / π)·arcsin(sin((k·π / Va)·(Vmax+Vmin)))…(5).

[0065] In equations (4) and (5), the coefficient k is an odd number greater than or equal to 1. The results of equations (4) and (5) are not strictly linearly increasing or decreasing triangular waves, but in this embodiment, Stri is referred to as a triangular wave for explanation. The triangular wave Stri is a signal with an amplitude of 1 that varies at a frequency 3k times the frequency of the first voltage command value VREFR (or VREFS, VREFT). Furthermore, "arcsin" represents the inverse function of sin.

[0066] Subtractor 403 subtracts voltage amplitude Va from the maximum voltage Vlim that the power conversion unit 101 can output, performing the operation "Vlim-Va". The maximum voltage Vlim is the maximum voltage that the power conversion unit 101 can output. For example, if the number of series connections P of the converter units is 3, and the primary side DC link voltage of each converter unit is Vdc1, then "Vlim=3・Vdc1".

[0067] Limiter 404 directly outputs the result of subtractor 403, "Vlim-Va", when "Va≤Vlim", and limits the result of subtractor 403 to zero when "Vlim<Va". That is, limiter 404 limits the result of subtractor 403, "Vlim-Va", in a way that makes the result of subtractor 403, "Vlim-Va", not negative (in a way that makes the minimum value greater than 0).

[0068] Multiplier 405 multiplies the triangular wave Stri generated by triangular wave generator 402 with the result of subtractor 403 after limiter 404 to generate carrier wave Sm. Specifically, the result of subtractor 403, "Vlim-Va", is multiplied by a triangular wave with an amplitude of 1 in multiplier 405 after limiter 404. That is, the value multiplied by triangular wave Stri in multiplier 405 is equivalent to the amplitude value of carrier wave Sm (hereinafter, the signal after limiter 404 will also be referred to as carrier amplitude Ma). The carrier wave Sm output by carrier generator 300 becomes zero when the voltage amplitude Va is greater than the maximum voltage Vlim (Vlim < Va) due to the action of limiter 404.

[0069] Furthermore, the primary gate pulse generation units for the S-phase and T-phase on the primary side, and the secondary gate pulse generation units for the U-phase, V-phase, and W-phase on the secondary side, are not shown in the diagrams, but their main structures are as described above. Figure 3 The primary side R phase is the same as shown. For example, for the primary side S phase, the first voltage command value VREFS is added to the carrier Sm to generate the second voltage command value VREFS'. Then, the second voltage command value VREFS' is compared with a threshold in multiple comparators to generate a gate pulse signal. For the primary side T phase, the first voltage command value VREFT is added to the carrier Sm to generate the second voltage command value VREFT'. Then, the second voltage command value VREFT' is compared with a threshold in multiple comparators to generate a gate pulse signal. The secondary side U phase, V phase, and W phase are configured in the same way. The carrier generation unit 300 is used in common in all phases. That is, the carrier Sm added to the first voltage command value is common in all phases.

[0070] Figure 5 (a)~ Figure 5 (e) is a graph showing the waveform of the signal, etc., when k is set to "k=3" in equation (5). However, the number of series connections P of the converter unit is "1". In addition, the output voltage range of the power conversion unit 101 is set to -1 to 1 (Vlim=Vdc1=1), and the threshold 1 and threshold 1' are set to 0.5 and -0.5, respectively.

[0071] Figure 5 (a) shows the first voltage command value VREFR and the carrier Sm, with the horizontal axis representing the phase and the vertical axis representing the voltage. Figure 5 (b) uses solid lines to represent gate pulse signal GT11 and dashed lines to represent gate pulse signal GT11'. The horizontal axis represents phase and the vertical axis represents voltage. Figure 5 (c) shows the second voltage command value VREFR' and the phase voltage between phase line 30R and neutral line 30N, with the horizontal axis representing phase and the vertical axis representing voltage. Figure 5(d) shows the second voltage command value VREFR'-second voltage command value VREFS', and the line voltage between phase R line 30R and phase S line 30S. The horizontal axis represents phase and the vertical axis represents voltage. Figure 5 (e) shows the higher harmonic components of the line voltage, with the horizontal axis representing the harmonic order and the vertical axis representing the voltage.

[0072] like Figure 5 As shown in (a), the carrier Sm is generated by the carrier generation unit 300 based on the first voltage command values ​​VREFR, VREFS, and VREFT. Therefore, the phase relationship between the carrier Sm and the first voltage command value VREFR is synchronized. Thus, as Figure 5 As shown in (b), the gate pulse signals GT11 and GT11' obtained by comparing the second voltage command value VREFR', which is the sum of the carrier Sm and the first voltage command value VREFR, with the threshold value, become the same signals with a phase difference of 180°.

[0073] Moreover, such as Figure 5 As shown in (c), the phase voltage of the power conversion unit 101 appearing between the R-phase line 30R and the neutral line 30N becomes a symmetrical waveform with a boundary of 180°. Furthermore, the second voltage command value VREFR' is controlled to not exceed -1 to 1, which is the output voltage range, enabling high-precision output of a voltage equivalent to the first voltage command value VREFR. This is because the amplitude of the carrier wave is controlled by the primary-side gate pulse generation unit 102, causing the second voltage command value VREFR' to cross a threshold set for the voltage magnitude multiple times within one cycle of the first voltage command value VREFR.

[0074] The line-to-line voltage of the power conversion unit 101 appearing between phase R 30R and phase S 30S is equivalent to “VREFR’-VREFS’”, such as Figure 5 As shown in (d), the waveform becomes sinusoidal. Therefore, the influence of the carrier wave Sm is absent. This is because the carrier wave Sm is a signal that varies in multiples of 3, and these variations cancel each other out in the line voltages. According to... Figure 5 The results of the higher harmonic components of the line voltage shown in (e) also confirm the higher harmonic components of the order that do not appear as multiples of 3 in the line voltage.

[0075] Figure 6 This is a block diagram of the primary-side gate pulse generation unit 600 in the comparative example. This comparative example is an example where this embodiment is not applied, and is described for comparison with this embodiment. The difference between this example and the primary-side gate pulse generation unit 300 in this embodiment is that a carrier generation unit 601 for generating the carrier Sm is provided independently. Therefore, the phase relationship between the carrier Sm and the voltage command value VREFR may not be synchronized.

[0076] The operation after the first voltage command value VREFR is added to the carrier Sm by the adder 602 to generate the second voltage command value VREFR' is the same as that of the primary side gate pulse generation unit 300 in this embodiment.

[0077] Figure 7 (a)~ Figure 7 (e) is shown Figure 6 The diagram shows the waveforms of the signals, etc., in the comparative example. However, the number of series connections P of the converter unit is "1". In addition, the output voltage range of the power conversion unit 101 is set to -1 to 1 (Vlim=Vdc1=1), and the threshold 1 and threshold 1' are set to 0.5 and -0.5, respectively.

[0078] Figure 7 (a) shows the first voltage command value VREFR and the carrier Sm, with the horizontal axis representing the phase and the vertical axis representing the voltage. Figure 7 (b) uses solid lines to represent gate pulse signal GT11 and dashed lines to represent gate pulse signal GT11'. The horizontal axis represents phase and the vertical axis represents voltage. Figure 7 (c) shows the second voltage command value VREFR' and the phase voltage between phase line 30R and neutral line 30N, with the horizontal axis representing phase and the vertical axis representing voltage. Figure 7 (d) shows the second voltage command value VREFR'-second voltage command value VREFS', and the line voltage between phase R line 30R and phase S line 30S. The horizontal axis represents phase and the vertical axis represents voltage. Figure 7 (e) shows the higher harmonic components of the line voltage, with the horizontal axis representing the harmonic order and the vertical axis representing the voltage.

[0079] In the comparative example, the carrier Sm is set to a triangular wave that varies at a frequency 12 times that of the first voltage command value VREFR, and is adjusted so that the second voltage command value VREFR', which is the sum of the carrier Sm and the first voltage command value VREFR, does not exceed the output voltage range of -1 to 1.

[0080] like Figure 7 As shown in (a), the phase relationship between the carrier Sm and the first voltage command value VREFR is asynchronous. Furthermore, as... Figure 7 As shown in (c), the phase voltage appearing between phase line 30R and neutral line 30N is not a symmetrical waveform with a 180° boundary, resulting in voltage imbalance. This is because the carrier wave Sm and the first voltage command value VREFR are out of phase. This voltage imbalance may be a cause of increased higher harmonic components in the output voltage. Figure 7 As shown in (e), it can be confirmed that, apart from the multiples of 3, there are high-order harmonic components of the line voltage distributed throughout.

[0081] As described above, the power conversion device 100 of this embodiment generates a carrier wave Sm based on the first voltage command values ​​VREFR, VREFS, and VREFT, and generates gate pulse signals GT11~GT1P and GT11'~GT1P' for controlling the switching elements Q1~Q4.

[0082] Therefore, the phase relationship between the carrier Sm and the first voltage command values ​​VREFR, VREFS, and VREFT can be synchronized. Even under conditions where there is an upper limit to the frequency of the carrier Sm and the number of switching operations (pulses) is reduced, the power conversion device 100 of this embodiment can effectively suppress high-order harmonics contained in the voltage / current.

[0083] Furthermore, in this embodiment, the power conversion device 100 controls the carrier amplitude Ma so that the peak values ​​of the second voltage command values ​​VREFR', VREFS', and VREFT' are consistent with the maximum output voltage Vlim of the power conversion unit 101. This suppresses errors between the first voltage command values ​​VREFR, VREFS, and VREFT and the output voltage.

[0084] The power conversion device 100 of this embodiment can increase the number of switching operations (pulse count) by increasing the number of series connections (P) of the converter unit, or the coefficient k in equations (4) and (5).

[0085] Figure 8 (a)~ Figure 8 (e) is a diagram showing the waveform of the signal, etc., when "k=5" is set in this embodiment. However, the number of series connections P of the converter unit is "2". In addition, the output voltage range of the power conversion unit 101 is set to -1 to 1 (Vlim=(Vdc1) / 2=1), the threshold 1 and threshold 1' are set to 0.25 and -0.25 respectively, and the threshold 2 and threshold 2' are set to 0.75 and -0.75 respectively.

[0086] and Figure 5 (a)~ Figure 5 Compared to the waveform shown in (e), as Figure 8 As shown in (a), the frequency of the carrier Sm increases. Furthermore, correspondingly, the number of series connections of the converter unit increases, as... Figure 8 As shown in (c), the threshold value within the output voltage range is set more precisely. Consequently, the number of times the second voltage command VREFR' crosses the threshold, i.e., the number of switching operations (pulses), increases. As a result, as... Figure 8 As shown in (e), the power conversion device 100 is able to output a voltage with fewer high-order harmonic components.

[0087] [Second Implementation]

[0088] In the first embodiment, the case where each converter unit 20 outputs three voltage levels in a multi-stage power conversion device 100 formed by connecting multiple converter units 20 in series is described. In the second embodiment, referring to... Figure 9 The scenarios where each converter unit 20 outputs two voltage levels will be explained. Furthermore, in the second embodiment, it is also similar to... Figure 1 The block diagram of the power conversion device 100 shown is as follows: Figure 2 The circuit structure diagram of the converter unit 20 shown is as follows: Figure 3 The block diagram of the primary side gate pulse generation unit 102 shown below. Figure 4 The block diagram of the carrier generation unit 300 shown has the same structure.

[0089] In the second embodiment, in Figure 2 In the structure of the converter unit 20-1 shown, in order to enable the AC-DC power converter 23 located on the primary side to output two voltage levels, control is performed to eliminate the period when all switching elements Q1 to Q4 are in the off state, and to ensure that one pair of switching elements Q1 and Q4 or switching elements Q2 and Q3 is always in the on state. As a result, the AC-DC power converter 23 of the power conversion unit 101 outputs two voltage levels (-Vdc1, Vdc1).

[0090] Figure 9 (a)~ Figure 9 (e) is a diagram showing the waveform of the signal, etc., in the second embodiment when "k=3" is set. However, the number of series connections P of the converter unit 20 is "1". In addition, the output voltage range of the power conversion unit 101 is set to -1 to 1 (Vlim=Vdc1=1), and both threshold 1 and threshold 1' are set to 0.

[0091] Figure 9 (a) shows the first voltage command value VREFR and the carrier Sm, with the horizontal axis representing the phase and the vertical axis representing the voltage. Figure 9 (b) uses solid lines to represent gate pulse signal GT11 and dashed lines to represent gate pulse signal GT11'. The horizontal axis represents phase and the vertical axis represents voltage. Figure 9 (c) shows the second voltage command value VREFR' and the phase voltage between phase line 30R and neutral line 30N, with the horizontal axis representing phase and the vertical axis representing voltage. Figure 9 (d) shows the second voltage command value VREFR'-second voltage command value VREFS', and the line voltage between phase R line 30R and phase S line 30S. The horizontal axis represents phase and the vertical axis represents voltage. Figure 9 (e) shows the higher harmonic components of the line voltage, with the horizontal axis representing the harmonic order and the vertical axis representing the voltage.

[0092] Similarly to the first embodiment, such as Figure 9 As shown in (a), the carrier Sm and the first voltage command value VREFR are in phase synchronization. Figure 9 As shown in (c), the phase voltage of the power conversion unit 101 appearing between phase line 30R and neutral line 30N becomes a symmetrical waveform with a boundary of 180°. Furthermore, the second voltage command value VREFR' is controlled to not exceed -1 to 1, which is the output voltage range. Figure 9 The results of the higher harmonic components of the line voltage shown in (e) can also identify higher harmonic components that do not appear as multiples of 3 in the line voltage.

[0093] As described above, in the multi-stage power conversion device 100 formed by connecting multiple converter units 20 in series, the same effect as in the first embodiment can be obtained even when each converter unit 20 outputs two levels of voltage.

[0094] [Third Implementation Method]

[0095] In the first and second embodiments, with Figure 1 The multi-stage power conversion device 100 shown is an example, but it can also be applied to other types of power conversion devices. Figure 10 This is a block diagram of the power conversion device 1000 in the third embodiment.

[0096] like Figure 10 As shown, the power conversion device 1000 includes a power conversion section 1001 and a gate pulse generation section 1002. The power conversion device 1000 performs bidirectional or unidirectional power conversion between a DC system 50 and a three-phase AC system 60. Here, the DC system 50 has terminals 50P and 50N. The AC system 60 has a U-phase terminal 60U, a V-phase terminal 60V, and a W-phase terminal 60W. For example, the DC system 50 can be powered by a battery, and the AC system 60 can be powered by a motor, etc.

[0097] The control unit 1003 detects the voltage and current of the DC system 50 and the AC system 60, and outputs the first voltage command values ​​VREFU, VREFV, and VREFW to the gate pulse generation unit 1002.

[0098] The gate pulse generation unit 1002 generates gate pulse signals GTup, GTun, GTvp, GTvn, GTwp, and GTwn for controlling the switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn included in the power conversion unit 1001.

[0099] Figure 11 The circuit structure diagram of the power conversion unit 1001 is shown.

[0100] The power conversion unit 1001 has a pair of DC system terminals 70a and 70b, a pair of AC system terminals 71a, 71b and 71c, and capacitors 72a and 72b. Furthermore, in the power conversion unit 1001, switching elements Qup and Qun, Qvp and Qvn, and Qwp and Qwn are connected in series, and these circuits consisting of pairs of two switching elements are connected in parallel. That is, each switching element constitutes a three-phase bridge circuit, and the power conversion unit 1001 performs power conversion between DC power and three-phase AC power. Additionally, each switching element Qup, Qun, Qvp, Qvn, Qwp, and Qwn has a reverse-parallel connected FWD. In this embodiment, these switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn are, for example, MOSFETs. Furthermore, in the power conversion unit 1001, the voltage appearing across the capacitors 72a and 72b is called the DC link voltage Vdc.

[0101] Details of the gate pulse generation unit 1002 and Figure 3 The primary-side gate pulse generation unit 1002 shown is identical, and its description is omitted. The gate pulse generation unit 1002 generates "low" or "high" gate pulse signals GTup, GTun, GTvp, GTvn, GTwp, and GTwn based on the first voltage command values ​​VREFU, VREFV, and VREFW. These gate pulse signals GTup, GTun, GTvp, GTvn, GTwp, and GTwn are supplied to the switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn, respectively, to control their on / off states.

[0102] In the power conversion unit 1001, the circuit composed of pairs of switching elements Qup and Qun, Qvp and Qvn, and Qwp and Qwn is controlled such that when one of them is in the ON state, the other must be in the OFF state.

[0103] The voltage appearing between any two terminals of AC system terminals 71a, 71b, and 71c in the power conversion unit 1001 is Vdc or -Vdc. That is, the power conversion unit 1001 is a power conversion unit that outputs two voltage levels.

[0104] Therefore, in the third embodiment, a reference can be applied. Figure 9The second embodiment described herein illustrates two levels of power conversion devices. However, the gate pulse signals GTup and GTun in the third embodiment correspond to the gate pulse signals GT11 and GT11' in the second embodiment. The gate pulse signals GTvp, GTvn, GTwp, and GTwn are also the same. In the third embodiment, the same effects as in the first or second embodiment can be obtained.

[0105] [Fourth Implementation Method]

[0106] In the fourth embodiment, the control is explained when the coefficient k is set to an even number of 2 or more.

[0107] Figure 12 This is a block diagram of the carrier generation unit 1200 in the fourth embodiment. The difference from the carrier generation unit 300 in the first embodiment is that it includes an amplitude adjustment unit 1201 for adjusting the carrier amplitude Ma. Furthermore, in the fourth embodiment, it is also similar to... Figure 1 The block diagram of the power conversion device 100 shown is as follows: Figure 2 The circuit structure diagram of the converter unit 20 shown is as follows: Figure 3 The block diagram of the primary side gate pulse generation unit 102 shown has the same structure.

[0108] like Figure 12 As shown, the output of limiter 404 is multiplied with triangular wave Stri in multiplier 405 after passing through amplitude adjustment unit 1201.

[0109] The amplitude adjustment unit 1201 controls the carrier amplitude Ma so that the peak values ​​of the second voltage command values ​​VREFR', VREFS', and VREFT' are consistent with the maximum output voltage Vlim of the power conversion device 100. That is, the amplitude adjustment unit 1201 adjusts the calculation result of the limiter 404 so that the sum of the amplitude values ​​of the second voltage command values ​​VREFR', VREFS', and VREFT' and the amplitude value of the carrier Sm is consistent with the maximum voltage Vlim.

[0110] When the coefficient k is set to an even number of 2 or more, the triangular wave generating unit 402 generates a triangular wave Stri according to the following formula (6).

[0111] In the case of [k=2, 4, 6, 8, ...]

[0112] Stri=(2 / π)·arcsin(sin((k·π / Va)·(Vmax+Vmin)))···(6)

[0113] Figure 13 (a)~ Figure 13(e) is a diagram showing the waveform of the signal, etc., in the fourth embodiment when "k=4" is set. However, the number of series connections P of the converter unit 20 is "1". In addition, the output voltage range of the power conversion unit 101 is set to -1 to 1 (Vlim=Vdc1=1), and the threshold 1 and threshold 1' are set to 0.5 and -0.5, respectively.

[0114] like Figure 13 As shown in (a), the carrier wave Sm is not a complete triangular wave, but the phase relationship between the carrier wave Sm and the first voltage command value VREFR is synchronized. However, the timing of the first voltage command value VREFR and the carrier wave Sm reaching their peak values ​​is misaligned. Furthermore, when k is set to an odd number greater than or equal to 1 (k = 1, 3, 5, ...), the timing of the first voltage command value VREFR and the carrier wave Sm reaching their peak values ​​is consistent. Therefore, in the fourth embodiment, in order to obtain the same effect as in other embodiments, an amplitude adjustment unit 1201 is added to adjust the carrier amplitude Ma according to the set value of the coefficient k.

[0115] In addition, such as Figure 13 As shown in (b), the gate pulse signals GT11 and GT11' obtained by comparing the sum of the carrier Sm and the voltage command value VREFR' with the threshold are identical signals with a phase difference of 180°. Furthermore, as... Figure 13 As shown in (c), the phase voltage of the power conversion unit 101 appearing between the R-phase line 30R and the neutral line 30N becomes a symmetrical waveform with a boundary of 180°. Furthermore, the second voltage command value VREFR' is controlled to not exceed -1 to 1, which is the output voltage range, enabling high-precision output of a voltage equivalent to the first voltage command value VREFR. The line-to-line voltage of the power conversion unit 101 appearing between the R-phase line 30R and the S-phase line 30S corresponds to "VREFR'-VREFS'", as shown in (c). Figure 13 As shown in (d), it is a sinusoidal waveform. According to... Figure 13 The results of the higher harmonic components of the line voltage shown in (e) also confirm the higher harmonic components of the order that do not appear as multiples of 3 in the line voltage.

[0116] <Variation Example 1>

[0117] Furthermore, the present invention is not limited to the embodiments described above, and includes various modifications. For example, the embodiments described above are detailed to aid in understanding the present invention and are not limited to having all the described structures. Additionally, a portion of the structure of one embodiment can be replaced with the structure of another embodiment, and it is also possible to add structures of other embodiments to the structure of one embodiment. Furthermore, for a portion of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0118] The variations that can be made to the above embodiments are as follows.

[0119] Figure 2 The AC-DC power converters 23-26 shown employ an H-bridge using switching elements to enable bidirectional power conversion. However, if unidirectional power conversion is sufficient, an H-bridge using rectifier elements can also be used in a portion of the AC-DC power converters 23-26. As an example, AC-DC power converter 25 can be replaced with an AC-DC power converter using four rectifier elements (not shown). In this modified example, the transformer potential difference of the high-frequency transformer 29 is the same as in the above embodiments, thus enabling the power conversion device 100 to be constructed in a compact and inexpensive manner. The four rectifier elements used in this modified example can be semiconductor diodes or vacuum tube-type mercury rectifiers, etc. When using semiconductors, the material can be any material such as Si, SiC, GaN, etc.

[0120] <Variation Example 2>

[0121] This assumes that both the primary and secondary sides of the converter unit 20 in the above embodiments are AC systems. However, either the primary or secondary side can also be a DC system. As an example, it is possible to replace it with... Figure 2 The structure of the AC-DC power converter 26 shown is illustrated. In this case, the voltage V1-1 appearing between terminals 22a and 22b becomes the secondary-side DC link voltage Vdc2 appearing across capacitor 28. Furthermore, in this modified example, an example is shown where the primary side is an AC system and the secondary side is a DC system, but it is also possible to have the primary side as a DC system and the secondary side as an AC system.

[0122] According to the implementation method described above, the following effects can be obtained.

[0123] (1) The power conversion devices 100 and 1000 include: a power conversion unit 101 and 1001 that controls the switching on and off of a plurality of switching elements Q1~Q4 and Q5~Q8 to convert power; and a gate pulse generation unit 102, 103, and 1002 that generates gate pulse signals GT11~GT1P, GT11'~GT1P', GT21~GT2P, and GT21'~GT1P' for controlling the switching on and off of the switching elements Q1~Q4 and Q5~Q8 based on first voltage command values ​​VREFR, VREFS, and VREFT of a plurality of phases indicating a desired output voltage. In power conversion devices 100 and 1000, the gate pulse generation units 102, 103, and 1002 generate a carrier Sm whose phase is synchronized with the first voltage command values ​​VREFR, VREFS, and VREFT based on the first voltage command values ​​VREFR, VREFS, and VREFT of the multiple phases. The carrier Sm is then added to the first voltage command values ​​VREFR, VREFS, and VREFT to generate second voltage command values ​​VREFR', VREFS', and VREFT'. Therefore, even when the carrier frequency cannot be set high enough relative to the voltage command values, higher harmonics can be suppressed.

[0124] (2) The control method of the power conversion devices 100 and 1000 is as follows: the power conversion devices 100 and 1000 include: a power conversion unit 101 and 1001, which controls the switching on and off of multiple switching elements Q1~Q4 and Q5~Q8 to convert power; and a gate pulse generation unit 102, 103, and 1002, which generates gate pulse signals GT11~GT1P, GT11'~GT1P', GT21~GT2P, and G based on first voltage command values ​​VREFR, VREFS, and VREFT of multiple phases indicating the desired output voltage, for controlling the switching on and off of the switching elements Q1~Q4 and Q5~Q8. In the control method of power conversion devices 100 and 1000, T21'~GT2P', GTup, GTvp, GTwp, GTun, GTvn, and GTwn, gate pulse generation units 102, 103, and 1002 generate a carrier Sm whose phase is synchronized with the first voltage command values ​​VREFR, VREFS, and VREFT based on the first voltage command values ​​VREFR, VREFS, and VREFT of multiple phases. The carrier Sm is then added to the first voltage command values ​​VREFR, VREFS, and VREFT to generate second voltage command values ​​VREFR', VREFS', and VREFT'. Therefore, even when the carrier frequency cannot be set high enough relative to the voltage command values, higher harmonics can be suppressed.

[0125] This invention is not limited to the embodiments described above. Other embodiments considered within the scope of the technical concept of this invention are also included within the scope of this invention, as long as they do not destroy the characteristics of this invention. Alternatively, the structure may be obtained by combining the above embodiments with multiple variations.

[0126] Explanation of reference numerals in the attached figures

[0127] 100, 1000: Power conversion device; 101, 1001: Power conversion unit; 102: Primary side gate pulse generation unit; 103: Secondary side gate pulse generation unit; 104: Primary side control unit; 105: Secondary side control unit; 20-1~20-P: Converter unit; 300, 600, 1200: Carrier generation unit; CMP11~CMP1P: Comparator; CMP11'~CMP1P': Comparator; 400: Voltage command comparison unit; 401: Voltage amplitude calculation unit; 402: Triangular wave generation unit; 404: Limiter; 1002: Gate pulse generation unit; 1003: Control unit; 1201: Amplitude adjustment unit; Q1~Q4, Q5~Q8, Qup, Qun, Qvp, Qvn, Qwp, Qwn: Switching element; GT11~GT1P, GT 11'~GT1P': Gate pulse signal (primary side); GT21~GT2P, GT21'~GT2P': Gate pulse signal (secondary side); GTup, GTvp, GTwp: Gate pulse signal (upper arm side); GTun, GTvn, GTwn: Gate pulse signal (lower arm side); VREFR, VREFS, VREFT: First voltage command value (primary side); VREFU, VREFV, VREFW: First voltage command value (secondary side); VREFR', VREFS', VREFT': Second voltage command value (primary side); VREFU', VREFV', VREFW': Second voltage command value (secondary side); Sm: Carrier wave; Stri: Triangular wave; Ma: Carrier amplitude; Va: Voltage amplitude; Vlim: Maximum voltage.

Claims

1. A power conversion device comprising: a power conversion unit that controls the switching on and off of a plurality of switching elements to convert power; and a gate pulse generation unit that generates gate pulse signals for controlling the switching on and off of the switching elements based on first voltage command values ​​of a plurality of phases indicating a desired output voltage, wherein in the power conversion device, The gate pulse generation unit generates a carrier wave whose phase is synchronized with the first voltage command value based on each of the plurality of phases, and adds the carrier wave to the first voltage command value to generate a second voltage command value. The gate pulse generation unit controls the amplitude of the carrier wave so that the second voltage command value crosses a threshold preset for the magnitude of the voltage multiple times within one cycle of the first voltage command value, and generates the gate pulse signal based on the comparison result between the second voltage command value and the threshold.

2. The power conversion device according to claim 1, characterized in that, The gate pulse generation unit includes a carrier generation unit. The carrier generation unit includes a voltage command comparison unit, a voltage amplitude calculation unit, a triangular wave generation unit, a subtractor, a limiter, and a multiplier. The voltage command comparison unit compares the first voltage command values ​​of each phase with each other and outputs the maximum value Vmax and the minimum value Vmin among these first voltage command values. The voltage amplitude calculation unit calculates the voltage amplitude Va based on the first voltage command value of each phase. The triangular wave generating unit generates a triangular wave Stri with an amplitude of 1 based on the following formula. The subtractor outputs the result obtained by subtracting the voltage amplitude Va from the maximum voltage Vlim that the power conversion device can output. The limiter restricts the subtractor's operation in a way that prevents the result from being negative. The multiplier generates the carrier wave by multiplying the triangular wave Stri with the result of the subtractor after passing through the limiter. In the case of [k=1, 5, 9, 13, ...], Stri=(2 / π)·arcsin(sin((k·π / Va)·(Vmax+Vmin))), In the case of [k=3, 7, 11, 15, ...], Stri=-(2 / π)·arcsin(sin((k·π / Va)·(Vmax+Vmin))), Where k represents an odd number greater than 1 (k = 1, 3, 5, ...).

3. The power conversion device according to claim 1, wherein, The gate pulse generation unit includes a carrier generation unit. The carrier generation unit includes a voltage command comparison unit, a voltage amplitude calculation unit, a triangular wave generation unit, a subtractor, a limiter, an amplitude adjustment unit, and a multiplier. The voltage command comparison unit compares the first voltage command values ​​of each phase with each other and outputs the maximum value Vmax and the minimum value Vmin among these first voltage command values. The voltage amplitude calculation unit calculates the voltage amplitude Va based on the first voltage command value of each phase. The triangular wave generating unit generates a triangular wave Stri with an amplitude of 1 based on the following formula. The subtractor outputs the result obtained by subtracting the voltage amplitude Va from the maximum voltage Vlim that the power conversion device can output. The limiter restricts the subtractor in a way that prevents the result of the subtractor from being negative. The amplitude adjustment unit adjusts the calculation result of the limiter so that the sum of the amplitude value of the second voltage command value and the amplitude value of the carrier wave is consistent with the maximum voltage Vlim. The multiplier generates the carrier wave by multiplying the triangular wave Stri with the result of the subtractor after passing through the limiter. In the case of [k=2, 4, 6, 8, ...], Stri=(2 / π)·arcsin(sin((k·π / Va)·(Vmax+Vmin))), Where k represents an even number greater than 2 (k = 2, 4, 6, ...).

4. The power conversion device according to any one of claims 1 to 3, wherein, The power conversion unit outputs voltages at three levels: positive, negative, and zero.

5. The power conversion device according to any one of claims 1 to 3, wherein, The power conversion unit outputs both positive and negative voltage levels.

6. The power conversion device according to any one of claims 1 to 3, wherein, The power conversion unit performs power conversion between DC power and three-phase AC power.

7. A control method for a power conversion device, the power conversion device comprising: a power conversion unit that controls the switching on and off of a plurality of switching elements to convert power; and a gate pulse generation unit that generates gate pulse signals for controlling the switching on and off of the switching elements based on first voltage command values ​​of a plurality of phases indicating a desired output voltage, wherein in the control method of the power conversion device, The gate pulse generation unit generates a carrier wave whose phase is synchronized with the first voltage command value based on each of the plurality of phases. The carrier wave is then added to the first voltage command value to generate a second voltage command value. The gate pulse generation unit controls the amplitude of the carrier wave so that the second voltage command value crosses a threshold preset for the magnitude of the voltage multiple times within one cycle of the first voltage command value, and generates the gate pulse signal based on the comparison result between the second voltage command value and the threshold.

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