Single wire debug and download circuit for swd serial debug port

Abstract

The application relates to chip control, in particular to a single-wire debugging and downloading circuit for a SWD serial debugging port, which comprises a reset interface NRST, a first data transmission interface SWDIO, a second data transmission interface SWCLK, a debugging port monitoring circuit, a first reset control circuit and a second reset control circuit; the debugging port monitoring circuit monitors input signals of the first data transmission interface SWDIO and the second data transmission interface SWCLK; the first reset control circuit generates a reset control intermediate signal based on output signals of the debugging port monitoring circuit; the second reset control circuit generates a chip reset control signal in combination with an input signal of the reset interface NRST and the reset control intermediate signal and sends the chip reset control signal to the chip; the technical scheme provided by the application can effectively overcome the defects of the prior art, that is, the existing 2-wire debugging / download mode occupies one more GPIO, leading to waste of chip resources.

Description

Technical Field

[0001] This invention relates to chip control, and more specifically to a single-wire debugging and downloading circuit for an SWD serial debugging port. Background Technology

[0002] SWD: The Serial Wire Debug Port (SW-DP), is a protocol introduced by ARM and one of the two debug ports currently supported by ARM. Based on the ARM CoreSight debug architecture, SWD can read and write to the chip's registers by transmitting data packets to debug / download the ARM core chip. The chip's debug / download interface circuit typically uses a circuit with two pins, SWDIO and SWCLK (referred to as a 2-wire debug / download method).

[0003] In traditional technical solutions, a two-wire debugging / downloading method is generally used to improve the flexibility of chip debugging. Within the internal circuitry of traditional technical solutions, such as... Figure 3 As shown, the two signals (swdio, swclk) inside the chip are connected to the two pads (SWDIO, SWCLK) at the bare die level, and the two pads are bonded to the two pins (SWDIO, SWCLK) at the package level.

[0004] In the external circuit of traditional technical solutions, such as Figure 4 As shown, the chip needs to encapsulate the SWDIO signal onto a separate GPIO, and a dedicated external circuit is also required to connect this GPIO to the programmer to ensure normal data transmission via SWDIO. After chip debugging / downloading is complete, the programmer will send a reset signal to the chip through the GPIO corresponding to NRST, thus resetting the chip.

[0005] The above technical solution has limitations. Using a 2-wire debug / download method will occupy an additional GPIO (SWDIO), resulting in a waste of chip resources. As is well known, increasing the number of chip pins increases the manufacturing and packaging costs of the chip. Especially for chips with fewer than 8 pins, each additional pin will increase the chip production cost by more than 15%. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a single-wire debugging and downloading circuit for the SWD serial debugging port, which can effectively overcome the defect that the existing 2-wire debugging / downloading method occupies an extra GPIO, resulting in a waste of chip resources.

[0008] (II) Technical Solution

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A single-wire debugging and downloading circuit for an SWD serial debugging port includes a reset interface NRST, a first data transmission interface SWDIO, a second data transmission interface SWCLK, a debugging port monitoring circuit, a first reset control circuit, and a second reset control circuit.

[0011] The debugging port monitoring circuit monitors the input signals of the first data transmission interface SWDIO and the second data transmission interface SWCLK.

[0012] The first reset control circuit generates an intermediate reset control signal based on the output signal of the debugging port monitoring circuit.

[0013] The second reset control circuit combines the input signal of the reset interface NRST with the intermediate reset control signal to generate a chip reset control signal and sends it to the chip.

[0014] The first data transmission interface SWDIO and the second data transmission interface SWCLK are connected to the chip, and the reset interface NRST and the first data transmission interface SWDIO are packaged together into one pin.

[0015] Preferably, the input terminal of the debugging port monitoring circuit is connected to the first data transmission interface SWDIO and the second data transmission interface SWCLK, and the output terminal of the debugging port monitoring circuit is connected to the first reset control circuit.

[0016] Preferably, the debugging port monitoring circuit is used to monitor the low level of the first data transmission interface SWDIO for 50 consecutive clock cycles.

[0017] Preferably, the input terminal of the first reset control circuit is connected to the output terminal of the debug port monitoring circuit and the NRST mode register, and the output terminal of the first reset control circuit is connected to the second reset control circuit.

[0018] Preferably, the input terminal of the second reset control circuit is connected to the reset interface NRST and the output terminal of the first reset control circuit, and the output terminal of the second reset control circuit is connected to the chip.

[0019] Preferably, the first reset control circuit uses an AND gate circuit, and the second reset control circuit uses an OR gate circuit.

[0020] Preferably, an analog filter circuit is connected between the reset interface NRST and the input terminal of the second reset control circuit. The analog filter circuit includes an NRST filter circuit, a POR trigger circuit, and a level conversion circuit.

[0021] NRST filter circuit, used to filter out burrs with a width of less than 2μs;

[0022] The POR trigger circuit, composed of a Schmitt trigger, is used to implement the reset function;

[0023] The level conversion circuit is used to convert the external input 3.3V voltage to 1.2V voltage and send it to the internal circuit.

[0024] (III) Beneficial Effects

[0025] Compared with the prior art, the single-wire debugging and downloading circuit for the SWD serial debugging port provided by the present invention has the following advantages:

[0026] 1) The design adopts a single-wire debug / download method, which encapsulates the SWDIO pad into the original NRST pin. Compared with the 2-wire debug / download method, it can ensure that users can use the SWD debug / download function normally without affecting the NRST reset function, which greatly improves the GPIO utilization.

[0027] 2) The circuit size of this application is extremely small, and its impact on chip cost is almost negligible, thereby enabling a significant reduction in chip production cost by reducing the number of pins. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a circuit diagram of the present invention;

[0030] Figure 2 This is a schematic diagram of the analog filter circuit in this invention;

[0031] Figure 3 This is the internal circuit diagram for the existing 2-wire debugging / downloading method;

[0032] Figure 4 This is the external circuit diagram for the existing 2-wire debugging / downloading method. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0034] A single-wire debugging and downloading circuit for the SWD serial debug port, such as Figure 1 As shown, it includes a reset interface NRST, a first data transmission interface SWDIO, a second data transmission interface SWCLK, a debug port monitoring circuit, a first reset control circuit, and a second reset control circuit.

[0035] The debugging port monitoring circuit monitors the input signals of the first data transmission interface SWDIO and the second data transmission interface SWCLK.

[0036] The first reset control circuit generates an intermediate reset control signal based on the output signal of the debugging port monitoring circuit.

[0037] The second reset control circuit combines the input signal of the reset interface NRST with the intermediate reset control signal to generate a chip reset control signal and sends it to the chip.

[0038] The first data transmission interface SWDIO and the second data transmission interface SWCLK are connected to the chip. The reset interface NRST is packaged with the first data transmission interface SWDIO into one pin.

[0039] ① The input terminal of the debugging port monitoring circuit is connected to the first data transmission interface SWDIO and the second data transmission interface SWCLK, and the output terminal of the debugging port monitoring circuit is connected to the first reset control circuit.

[0040] The debug port monitoring circuit is used to monitor the low level of the first data transmission interface SWDIO for 50 consecutive clock cycles.

[0041] ② The input terminal of the first reset control circuit is connected to the output terminal of the debugging port monitoring circuit and the NRST mode register, and the output terminal of the first reset control circuit is connected to the second reset control circuit.

[0042] ③ The input terminal of the second reset control circuit is connected to the reset interface NRST and the output terminal of the first reset control circuit, and the output terminal of the second reset control circuit is connected to the chip.

[0043] In the technical solution of this application, the first reset control circuit adopts an AND gate circuit, and the second reset control circuit adopts an OR gate circuit.

[0044] In the above technical solution, since the reset interface NRST and the first data transmission interface SWDIO are combined into one pin, it is crucial to accurately distinguish the state between the reset signal on the NRST / SWDIO GPIO and the data transmission signal on the first data transmission interface SWDIO.

[0045] When there is no "continuous low level for 50 clock cycles" on the first data transmission interface SWDIO, the chip transmits SWD data normally. During this period, even if the level of the reset interface NRST changes with a falling edge, the chip will not reset.

[0046] When the debug port monitoring circuit detects that the output of the first data transmission interface SWDIO is high after "continuously inputting a low level for 50 clock cycles", and the NRST mode register (regs_NRSTmode) is set to 1, the reset control intermediate signal (NRST enable signal NRST_Disable) output by the first reset control circuit is 1, and the chip is reset.

[0047] like Figure 2 As shown, an analog filter circuit is connected between the reset interface NRST and the input terminal of the second reset control circuit. The analog filter circuit includes an NRST filter circuit, a POR trigger circuit, and a level conversion circuit.

[0048] NRST filter circuit, used to filter out burrs with a width of less than 2μs;

[0049] The POR trigger circuit, composed of a Schmitt trigger, is used to implement the reset function;

[0050] The level conversion circuit is used to convert the external input 3.3V voltage to 1.2V voltage and send it to the internal circuit.

[0051] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single-wire debugging and downloading circuit for an SWD serial debugging port, characterized in that: It includes a reset interface NRST, a first data transmission interface SWDIO, a second data transmission interface SWCLK, a debug port monitoring circuit, a first reset control circuit, and a second reset control circuit; The debugging port monitoring circuit monitors the input signals of the first data transmission interface SWDIO and the second data transmission interface SWCLK. The first reset control circuit generates an intermediate reset control signal based on the output signal of the debugging port monitoring circuit. The second reset control circuit combines the input signal of the reset interface NRST with the intermediate reset control signal to generate a chip reset control signal and sends it to the chip. The first data transmission interface SWDIO and the second data transmission interface SWCLK are connected to the chip. The reset interface NRST is encapsulated with the first data transmission interface SWDIO into one pin. When there is no "continuous input of a low level for 50 clock cycles" on the first data transmission interface SWDIO, the chip transmits SWD data normally. When the debug port monitoring circuit detects "continuous input of a low level for 50 clock cycles" on the first data transmission interface SWDIO, it outputs a high level and the NRST mode register is set to 1. At this time, the reset control intermediate signal output by the first reset control circuit is 1, and the chip is reset.

2. The single-wire debugging and downloading circuit for the SWD serial debugging port according to claim 1, characterized in that: The input terminal of the debugging port monitoring circuit is connected to the first data transmission interface SWDIO and the second data transmission interface SWCLK, and the output terminal of the debugging port monitoring circuit is connected to the first reset control circuit.

3. The single-wire debugging and downloading circuit for the SWD serial debugging port according to claim 2, characterized in that: The input terminal of the first reset control circuit is connected to the output terminal of the debug port monitoring circuit and the NRST mode register, and the output terminal of the first reset control circuit is connected to the second reset control circuit.

4. The single-wire debugging and downloading circuit for the SWD serial debugging port according to claim 3, characterized in that: The input terminal of the second reset control circuit is connected to the reset interface NRST and the output terminal of the first reset control circuit, and the output terminal of the second reset control circuit is connected to the chip.

5. The single-wire debugging and downloading circuit for the SWD serial debugging port according to claim 4, characterized in that: The first reset control circuit uses an AND gate circuit, and the second reset control circuit uses an OR gate circuit.

6. The single-wire debugging and downloading circuit for the SWD serial debugging port according to claim 4, characterized in that: An analog filter circuit is connected between the reset interface NRST and the input terminal of the second reset control circuit. The analog filter circuit includes an NRST filter circuit, a POR trigger circuit, and a level conversion circuit. NRST filter circuit, used to filter out burrs with a width of less than 2μs; The POR trigger circuit, composed of a Schmitt trigger, is used to implement the reset function; The level conversion circuit is used to convert the external input 3.3V voltage to 1.2V voltage and send it to the internal circuit.

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