Chip-based data transmission method, device and storage medium

Abstract

The present invention relates to a chip-based data transmission method, device, and storage medium. The method comprises: a first DMA controller reads data to be decompressed from outside the chip; a compression / decompression unit decompresses the data to obtain decompressed data and stores the decompressed data in on-chip memory; a second DMA controller within the chip reads the decompressed data from the on-chip memory; and the second DMA controller transmits the decompressed data to a relevant storage path within the chip. The present invention can reduce the demand for external chip storage bandwidth, reduce the number of data transfers, and reduce chip dynamic power consumption while also reducing data transmission latency. The time it takes for data to arrive from outside the chip to inside the chip is correspondingly shortened, thereby improving overall chip performance.

Description

Technical Field

[0001] The present invention relates to the field of data transmission technology, and in particular to a chip-based data transmission method, device and storage medium. Background Art

[0002] At present, artificial intelligence (AI) technology using deep neural networks (DNN) has been widely used in various industries. Since the amount of data required for DNN calculations (including weights, feature maps, intermediate calculation results, etc.) is very large, it puts tremendous pressure on the entire system, especially the transmission bandwidth between the chip and external storage (for example, DRAM, Flash, hard disk, etc.).

[0003] In order to alleviate the pressure on the bandwidth demand for chip external storage, the existing technology usually adds compression and decompression functional modules to the chip to reduce the actual amount of data transmitted when the large amount of data inside the chip overflows to the external storage, or reads compressed data from the external storage and decompresses it into a large amount of data for use on the chip. Although this solution can reduce the bandwidth demand for external storage, it also adds an additional data transfer step inside the chip. The power consumption caused by data transfer is very high, which has exceeded the power consumption required for the same amount of floating-point operations. Every additional data transfer will increase the power consumption of the chip by a large proportion.

[0004] Therefore, how to reduce the demand for chip external storage bandwidth and the number of data transfers when transmitting data between the chip and the outside of the chip has become a technical problem that technicians in this field urgently need to solve. Summary of the Invention

[0005] In view of the above, the present invention provides a chip-based data transmission method, device and storage medium, which aims to solve the above technical problems.

[0006] In a first aspect, the present invention provides a chip-based data transmission method, wherein the chip includes an integrated module integrating an on-chip memory, a first DMA controller without a FIFO memory, and a compression and decompression unit without the FIFO memory, the method comprising:

[0007] After the first DMA controller reads the data to be decompressed outside the chip, the compression and decompression unit decompresses the data to be decompressed to obtain decompressed data and stores the decompressed data in the on-chip memory;

[0008] A second DMA controller inside the chip reads the decompressed data from the on-chip memory;

[0009] The second DMA controller sends the decompressed data to a related storage path inside the chip.

[0010] In a second aspect, the present invention provides a chip-based data transmission method, wherein the chip integrates an on-chip memory, an internal DMA controller without a FIFO module, and a compression and decompression module without the FIFO module, the method comprising:

[0011] Reading the data to be compressed generated by the chip;

[0012] Writing the data to be compressed into the on-chip memory, and performing a compression operation on the data to be compressed by the compression and decompression unit to obtain compressed data;

[0013] The first DMA controller reads the compressed data and pushes the compressed data to a storage space outside the chip.

[0014] In a third aspect, the present invention provides an electronic device, comprising a chip, the chip comprising an integrated module integrating an on-chip memory, a first DMA controller excluding a FIFO memory, and a compression / decompression unit excluding the FIFO memory, the electronic device further comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0015] Memory for storing computer programs;

[0016] The processor is used to implement the steps of the chip-based data transmission method described in any embodiment of the first aspect when executing the program stored in the memory.

[0017] In a fourth aspect, the present invention provides an electronic device, comprising a chip, the chip comprising an integrated module integrating an on-chip memory, a first DMA controller excluding a FIFO memory, and a compression / decompression unit excluding the FIFO memory, the electronic device further comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0018] Memory for storing computer programs;

[0019] The processor is used to implement the steps of the chip-based data transmission method described in any embodiment of the second aspect when executing the program stored in the memory.

[0020] In a fifth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip-based data transmission method as described in any embodiment of the first aspect are implemented.

[0021] In a sixth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip-based data transmission method as described in any embodiment of the second aspect are implemented.

[0022] The above technical solution provided by the embodiment of the present invention has the following advantages compared with the prior art:

[0023] The chip has an integrated module that integrates on-chip memory, a DMA controller without FIFO memory, and a compression and decompression unit without FIFO memory. When transmitting data between the outside and inside of the chip, only three steps are needed to complete the data transmission between the outside and inside of the chip, which reduces the demand for external chip storage bandwidth, reduces the number of data transfers, reduces the dynamic power consumption of the chip, and also reduces data transmission delay. The data transmission time between the outside and inside of the chip is also shortened accordingly, improving the overall performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 Schematic diagram of a flow chart of a preferred embodiment of the chip-based data transmission method of the present invention;

[0027] Figure 2 It is a schematic diagram of a DMA controller without removing the FIFO memory;

[0028] Figure 3 Schematic diagram of a compression and decompression unit without removing the FIFO memory;

[0029] Figure 4 is a schematic diagram of an on-chip memory before the present invention is integrated;

[0030] Figure 5 A schematic diagram of an integrated module of the chip of the present invention integrating on-chip memory, DMA controller and compression and decompression unit;

[0031] Figure 6 A schematic diagram of data flow when transmitting data between the outside and inside of a chip in the prior art;

[0032] Figure 7 This is a schematic diagram of data flow when transmitting data between the outside and inside of the chip of the present invention;

[0033] Figure 8 Schematic diagram of a flow chart of another preferred embodiment of the chip-based data transmission method of the present invention;

[0034] Figure 9 A schematic structural diagram of an electronic device for executing a chip-based data transmission method according to the present invention;

[0035] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0037] It should be noted that the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0038] FIFO: FIFO memory is the buffer link of the system. It is a first-in-first-out dual-port buffer. That is, the first data that enters the FIFO memory will be the first to be removed.

[0039] DMA: DMA (Direct Memory Access) control is the read and write control within the hard disk. It can reduce the CPU burden and speed up the reading speed. It is a high-speed data transfer operation that allows data to be read and written directly between external devices and memory without going through the CPU or requiring CPU intervention. Data transfer operations are performed under the control of the DMA controller.

[0040] SRAM: Static Random-Access Memory (SRAM), which can save the data stored in it without refreshing the circuit.

[0041] DRAM: Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0042] The present invention provides a chip-based data transmission method. Figure 1 FIG2 is a flow chart of an embodiment of a chip-based data transmission method according to the present invention. The method can be performed by an electronic device, which can be implemented by software and / or hardware. The electronic device includes a chip, which includes an integrated module integrating on-chip memory, a first DMA controller without FIFO memory, and a compression and decompression unit without FIFO memory. The chip-based data transmission method includes:

[0043] Step S110: After the first DMA controller reads the data to be decompressed outside the chip, the compression and decompression unit decompresses the data to be decompressed to obtain decompressed data and stores the decompressed data in the on-chip memory;

[0044] Step S120: the second DMA controller inside the chip reads the decompressed data from the on-chip memory;

[0045] Step S130: the second DMA controller sends the decompressed data to a related storage path inside the chip.

[0046] The present invention integrates the functions of a DMA controller, a compression and decompression unit, and an on-chip memory (Scratchpad). The three are integrated together. The DMA controller and the compression and decompression unit directly use the SRAM storage in the on-chip memory Scratchpad instead of being equipped with FIFOs respectively. That is, the DMA controller removes the FIFO memory, and the compression and decompression unit removes the FIFO memory. It can be understood that the compression and decompression unit can decompress the data to be decompressed, and can also compress the compressed data.

[0047] like Figure 2 FIG. 1 is a schematic diagram of a DMA controller without removing the FIFO memory. The DMA controller needs to control data transmission through the FIFO memory. The FIFO memory is a first-in-first-out dual-port buffer, that is, the first data to enter the memory is the first to be removed.

[0048] like Figure 3 , which is a schematic diagram of a compression and decompression unit without removing the FIFO memory. Before data compression or decompression, and after data decompression or compression, the FIFO memory is required to control data transmission.

[0049] like Figure 4 FIG. 1 is a schematic diagram of an on-chip memory before the present invention is integrated.

[0050] like Figure 5 As shown in FIG, a schematic diagram of an integrated module of the chip of the present invention integrating on-chip memory, a first DMA controller and a compression and decompression unit. The first DMA controller and the compression and decompression unit directly use the SRAM storage in the Scratchpad instead of being equipped with FIFOs respectively. That is, after the integration, the first DMA controller in the chip removes the FIFO memory, and the compression and decompression unit removes the FIFO memory.

[0051] At present, due to the large amount of data required for the calculation of neural network models, the chip usually reads compressed data with a small amount of data from the outside of the chip first, decompresses it inside the chip to obtain large data volume, and then uses it to reduce the pressure on the transmission bandwidth. However, when the compression and decompression unit inside the chip performs compression or decompression operations, the existence of the FIFO memory in the compression and decompression unit will increase the number of data transfers inside the chip. Each additional data transfer will increase the power consumption of the chip by a large proportion, such as Figure 6 As shown, the order of ①②③④⑤ is the data transmission process from the storage space outside the chip (for example, DRAM) to the Consumer inside the chip. ①, DMA0 inside the chip reads the compressed data from the DRAM outside the chip. ②, DMA0 sends the compressed data to the De-compressor. ③, the De-compressor decompresses the data and sends it to the Scratchpad. ④, DMA1 inside the chip reads the decompressed data from the Scratchpad. ⑤, DMA1 sends the decompressed data to the Consumer. Similarly, the order of ⑤④③②① is the large amount of data generated by the Producer inside the chip, which is compressed by the Compressor and then transmitted to the outside of the chip. It can be seen that when there is no integrated module inside the chip, five steps are required to transmit data between the outside and inside of the chip.

[0052] The present invention has an integrated module inside the chip that integrates on-chip memory, a first DMA controller without FIFO memory, and a compression and decompression unit without FIFO memory. When transmitting data between the outside and inside of the chip, only three steps of transmission are required, such as Figure 7As shown, ①, after the first DMA controller in the integrated module reads the data to be decompressed from the DRAM outside the chip, the compression and decompression unit of the integrated module decompresses the data to be decompressed to obtain the decompressed data. ④, the second DMA controller (DMA1) inside the chip then reads the decompressed data from the on-chip memory of the integrated module. ⑤, DMA1 sends the decompressed data to the consumer. The present invention only requires three steps (①, ④, and ⑤) to complete the data transmission from the outside of the chip to the inside of the chip, reducing the demand for external chip storage bandwidth, reducing the number of data transfers, reducing the chip's dynamic power consumption, and reducing data transmission delay. The time it takes for data to reach the consumer inside the chip from the outside of the chip is correspondingly shortened, thereby improving the overall performance of the chip.

[0053] Specifically, after the first DMA controller reads the data to be decompressed outside the chip, the compression and decompression unit decompresses the data to be decompressed to obtain decompressed data and stores the decompressed data in the on-chip memory, including:

[0054] The first DMA controller reads the data to be decompressed from outside the chip and writes it to the SRAM memory of the on-chip memory. The compression and decompression unit reads the data to be decompressed from the SRAM memory of the on-chip memory and decompresses it to obtain the decompressed data. The compression and decompression unit then writes the decompressed data to the SRAM memory of the on-chip memory. The second DMA controller (DMA1) reads the decompressed data from the SRAM memory of the on-chip memory and transfers it to the storage space corresponding to the decompressed data for chip processing.

[0055] The DMA controller reads the data to be decompressed from the external bus through the AXI master Read port and writes it directly to the SRAM memory through the SRAM Arbiter. The decompression unit reads the data to be decompressed through the SRAM Arbiter, decompresses the data to be decompressed to obtain the decompressed data, and writes the decompressed data back to the SRAM memory through the SRAM Arbiter. The second DMA controller (DMA1) reads the decompressed data in the SRAM memory through the AXI slave Read port and the SRAM Arbiter, and transmits it to the storage space corresponding to the chip processing the decompressed data.

[0056] Reference Figure 8FIG2 is a flow chart of another embodiment of a chip-based data transmission method according to the present invention. The method can be performed by an electronic device, which can be implemented by software and / or hardware. The electronic device includes a chip, which includes an integrated module integrating on-chip memory, a first DMA controller without FIFO memory, and a compression and decompression unit without FIFO memory. The chip-based data transmission method includes:

[0057] Step S210: reading the data to be compressed generated by the chip;

[0058] Step S220: writing the data to be compressed into the on-chip memory, and the compression and decompression unit performing a compression operation on the data to be compressed to obtain compressed data;

[0059] Step S230: the first DMA controller reads the compressed data and pushes the compressed data to a storage space outside the chip.

[0060] This embodiment has an integrated module inside the chip that integrates on-chip memory, a first DMA controller without FIFO memory, and a compression and decompression unit without FIFO memory. When transmitting data between the outside and inside of the chip, only three steps of transmission are required, such as Figure 7 As shown, ⑤, the data to be compressed generated by the chip is transmitted to the second DMA controller (DMA1) inside the chip, that is, the second DMA controller of the chip reads the data to be compressed generated by the chip, ④, the second DMA controller (DMA1) inside the chip writes the data to be compressed into the integrated module, and the integrated module compresses the data to be compressed to obtain compressed data, and ①, the first DMA controller of the integrated module transmits the compressed data to the storage space outside the chip. Only three steps ⑤, ④, and ① are required to complete the data transmission from the outside of the chip to the inside of the chip, which reduces the demand for chip external storage bandwidth, reduces the number of data transfers, reduces the dynamic power consumption of the chip, and also reduces data transmission delay. The time it takes for data to travel from the Producer inside the chip to the outside of the chip is correspondingly shortened, improving the overall performance of the chip.

[0061] Specifically, writing the data to be compressed into the on-chip memory, and the compression and decompression unit performing a compression operation on the data to be compressed to obtain compressed data, includes:

[0062] The data to be compressed is written into the SRAM memory of the on-chip memory, the compression and decompression unit reads the data to be compressed from the SRAM memory, and a compression operation is performed on the data to be compressed to obtain compressed data. Furthermore, the compressed data is written into the SRAM memory through the SRAM Arbiter, so that the first DMA controller can read the compressed data from the SRAM memory.

[0063] The second DMA controller (DMA1) writes the data to be compressed into the SRAM memory via the SRAM Arbiter through the AXI slave Write port. The Compression unit reads the data to be compressed through the SRAM Arbiter, compresses the data to be compressed to obtain compressed data, and writes the compressed data back to the SRAM memory through the SRAM Arbiter, so that the DMA controller can read the compressed data of the SRAM memory via the SRAM Arbiter and push it to the external storage of the chip through the AXI master Write port.

[0064] In one embodiment, performing a compression operation on the data to be compressed to obtain compressed data includes:

[0065] Dividing the to-be-compressed data into a plurality of sub-compression codes based on a preset number of bytes as a boundary, and performing a first padding operation on the sub-compression codes to obtain a first padded compression code;

[0066] A second padding operation is performed on the first padding compression code to obtain compressed data.

[0067] The data to be decompressed is divided into several sub-compression codes with a preset number of bytes as the boundary, and a first filling operation is performed on the sub-compression code to obtain a first filling compression code. The preset number of bytes can be 4Byte. For example, if the compression code is 4KB, the compression code can be divided into 1000 sub-compression codes. Since the compression value in each sub-compression code is not necessarily a complete compression value, each sub-compression code can be filled with a numerical value to obtain a first filling compression code, so that the starting bit of each sub-compression code in the first filling compression code is a complete compression value, and then a second filling operation is performed on the first filling compression code to obtain the compressed data. The starting bit and end bit of each sub-compression code of the compressed data are complete values. The second filling operation (for example, filling in idx) can be an indication of the number of bytes that can be decompressed from each sub-compression code, so that the start bit and end bit addresses of each sub-compression code after decompression are clearly known, so that there is no dependency between the sub-compression codes, and they can be decompressed in parallel later, thereby improving the decompression efficiency. When faced with the calculation of large amounts of neural network data, it can also respond promptly and is widely applicable to lossless decompression scenarios of AI acceleration devices.

[0068] Reference Figure 9 As shown, the present invention also provides an electronic device 1 for executing the above chip-based data transmission method.

[0069] The electronic device 1 includes, but is not limited to, a memory 11, a processor 12, and a communication interface 13. The electronic device 1 may further include a chip, wherein the chip includes an integrated module that integrates on-chip memory, a first DMA controller excluding a FIFO memory, and a compression and decompression unit excluding a FIFO memory. The electronic device 1 is connected to a network via the communication interface 13. The network may be a wireless or wired network such as the Internet, Global System of Mobile Communications (GSM), a 4G network, a 5G network, Bluetooth, Wi-Fi, or a telephone network.

[0070] The memory 11 includes at least one type of readable storage medium, including flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory), random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, a magnetic disk, an optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as a hard disk or memory of the electronic device 1. The memory 11 is typically used to store an operating system and various application software installed on the electronic device 1, such as the program code of the chip-based data transmission program 10.

[0071] In some embodiments, the processor 12 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor 12 is generally used to control the overall operation of the electronic device 1, such as performing control and processing related to data interaction or communication. The processor 12 is used to execute program code stored in the memory 11 or process data, such as executing the program code of the chip-based data transmission program 10.

[0072] The communication interface 13 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface). The communication interface 13 is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0073] Figure 9Only the electronic device 1 having components 11 - 13 and the chip-based data transmission program 10 is shown, but it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0074] When the processor 12 executes the chip-based data transmission program 10 stored in the memory 11, the following steps may be implemented:

[0075] After the first DMA controller reads the data to be decompressed outside the chip, the compression and decompression unit decompresses the data to be decompressed to obtain decompressed data and stores the decompressed data in the on-chip memory;

[0076] A second DMA controller inside the chip reads the decompressed data from the on-chip memory;

[0077] The second DMA controller sends the decompressed data to a related storage path inside the chip.

[0078] When the processor 12 executes the chip-based data transmission program 10 stored in the memory 11, the processor 12 may further implement the following steps:

[0079] Reading the data to be compressed generated by the chip;

[0080] Writing the data to be compressed into the on-chip memory, and performing a compression operation on the data to be compressed by the compression and decompression unit to obtain compressed data;

[0081] The first DMA controller reads the compressed data and pushes the compressed data to a storage space outside the chip.

[0082] For a detailed description of the above steps, please refer to the Figure 1 and Figure 8 Description of a flowchart of an embodiment of a chip-based data transmission method.

[0083] In addition, an embodiment of the present invention further provides a computer-readable storage medium, which can be non-volatile or volatile. The computer-readable storage medium can be any one of a hard disk, a multimedia card, an SD card, a flash memory card, an SMC, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a USB memory, etc., or any combination thereof. The computer-readable storage medium includes a data storage area and a program storage area. The program storage area stores a chip-based data transmission program 10. When the chip-based data transmission program 10 is executed by a processor, the following operations are implemented:

[0084] After the first DMA controller reads the data to be decompressed outside the chip, the compression and decompression unit decompresses the data to be decompressed to obtain decompressed data and stores the decompressed data in the on-chip memory;

[0085] A second DMA controller inside the chip reads the decompressed data from the on-chip memory;

[0086] The second DMA controller sends the decompressed data to a related storage path inside the chip.

[0087] When the chip-based data transmission program 10 is executed by the processor, the following operations are also implemented:

[0088] Reading the data to be compressed generated by the chip;

[0089] Writing the data to be compressed into the on-chip memory, and performing a compression operation on the data to be compressed by the compression and decompression unit to obtain compressed data;

[0090] The first DMA controller reads the compressed data and pushes the compressed data to a storage space outside the chip.

[0091] The specific implementation of the computer-readable storage medium of the present invention is substantially the same as the specific implementation of the chip-based data transmission method described above, and will not be described in detail here.

[0092] It should be noted that the serial numbers of the above-mentioned embodiments of the present invention are for descriptive purposes only and do not represent the advantages or disadvantages of the embodiments. In addition, the terms "including", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "including a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0093] Through the description of the above embodiments, those skilled in the art can clearly understand that the above embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, electronic device, or network equipment, etc.) to execute the methods described in each embodiment of the present invention.

[0094] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip-based data transmission method, characterized in that: The chip includes an integrated module integrating an on-chip memory, a first DMA controller excluding a FIFO memory, and a compression and decompression unit excluding the FIFO memory, and the method includes: After the first DMA controller reads the data to be decompressed outside the chip, the compression and decompression unit decompresses the data to be decompressed to obtain decompressed data and stores the decompressed data in the on-chip memory; A second DMA controller inside the chip reads the decompressed data from the on-chip memory; The second DMA controller sends the decompressed data to a related storage path inside the chip.

2. The chip-based data transmission method according to claim 1, wherein: After the first DMA controller reads the data to be decompressed outside the chip, the compression and decompression unit decompresses the data to be decompressed to obtain decompressed data and stores the decompressed data in the on-chip memory, including: The first DMA controller reads the data to be decompressed outside the chip and writes it to the SRAM memory of the on-chip memory; The compression and decompression unit reads the data to be decompressed from the SRAM memory, and performs a decompression operation on the data to be decompressed to obtain decompressed data; The compression and decompression unit writes the decompressed data into the SRAM memory.

3. A chip-based data transmission method, characterized in that: The chip includes an integrated module integrating an on-chip memory, a first DMA controller excluding a FIFO memory, and a compression and decompression unit excluding the FIFO memory, and the method includes: Reading the data to be compressed generated by the chip; Writing the data to be compressed into the on-chip memory, and the compression and decompression unit performing a compression operation on the data to be compressed to obtain compressed data; The first DMA controller reads the compressed data and pushes the compressed data to a storage space outside the chip.

4. The chip-based data transmission method according to claim 3, wherein: The reading of the data to be compressed generated by the chip includes: A second DMA controller based on the chip reads the data to be compressed generated by the chip.

5. The chip-based data transmission method according to claim 3, wherein: The step of writing the data to be compressed into the on-chip memory and performing a compression operation on the data to be compressed by the compression and decompression unit to obtain compressed data includes: The data to be compressed is written into the SRAM memory of the on-chip memory, the compression and decompression unit reads the data to be compressed from the SRAM memory, and performs a compression operation on the data to be compressed to obtain compressed data.

6. The chip-based data transmission method according to claim 5, characterized in that: The performing a compression operation on the data to be compressed to obtain compressed data includes: Dividing the to-be-compressed data into a plurality of sub-compression codes based on a preset number of bytes as a boundary, and performing a first padding operation on the sub-compression codes to obtain a first padded compression code; A second padding operation is performed on the first padding compression code to obtain compressed data.

7. An electronic device, characterized in that: The electronic device includes a chip, the chip includes an integrated module integrating an on-chip memory, a first DMA controller excluding a FIFO memory, and a compression and decompression unit excluding the FIFO memory, the electronic device also includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; Memory for storing computer programs; The processor is configured to implement the chip-based data transmission method according to claim 1 or 2 when executing a program stored in the memory.

8. An electronic device, characterized in that: The electronic device includes a chip, the chip includes an integrated module integrating an on-chip memory, a first DMA controller excluding a FIFO memory, and a compression and decompression unit excluding the FIFO memory, the electronic device also includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; Memory for storing computer programs; The processor is configured to implement the chip-based data transmission method according to any one of claims 3 to 6 when executing a program stored in the memory.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip-based data transmission method according to claim 1 or 2 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip-based data transmission method according to any one of claims 3 to 6 are implemented.

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