Method of processing access requests

Abstract

A method for processing an access request, a processing device, an electronic device and a non-transitory readable storage medium are disclosed. The first access request is used to acquire data in a processing device comprising a multi-level buffer memory. The method for processing an access request comprises: in response to the current level of the buffer memory receiving an access request, determining a priority level corresponding to the first access request; and based on the priority level corresponding to the first access request, determining the order in which the buffer memory processes the first access request or a second access request.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a method for processing access requests, a processing apparatus, an electronic device, and a non-transitory readable storage medium. Background Technology

[0002] Each level of cache may receive access requests from various request units. These access requests include, but are not limited to, requests to read data or instructions from the cache, or requests to prefetch data or / or instructions from the cache. After receiving various access requests, the cache typically processes them using a polling method. For example, polling can be used to pipe access requests into a pipeline. While polling is relatively simple and fair, it is often not intelligent enough, leading to a performance penalty for the CPU. Therefore, further improvements are needed to the cache's access request processing scheme to enhance overall CPU performance. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a method for processing access requests, a processing apparatus, an electronic device, and a non-transitory readable storage medium.

[0004] At least one embodiment of this disclosure provides a method for processing an access request, the first access request being used to retrieve data in a processing apparatus including a multi-level cache memory, the method comprising: in response to a current-level cache memory receiving an access request, determining a priority level corresponding to the first access request; and based on the priority level corresponding to the first access request, determining an order in which the cache memory processes the first access request or a second access request.

[0005] For example, in at least one embodiment of this disclosure, determining the priority corresponding to the first access request in response to the current level buffer receiving an access request includes: determining the priority corresponding to the first access request in response to the current level buffer receiving a priority update command for the first access request.

[0006] For example, in at least one embodiment of this disclosure, the first access request includes a priority field, and the step of determining the priority corresponding to the first access request in response to the current level buffer receiving the access request includes: determining the priority corresponding to the first access request based on the priority indicated by the priority field in the first access request.

[0007] For example, in at least one embodiment of this disclosure, determining the order in which the buffer memory processes the first access request or the second access request based on the priority level corresponding to the first access request includes: in response to the response queue of the buffer memory including access responses and the access responses including the data requested by the first access request, adjusting the priority level of the access responses based on the priority level corresponding to the first access request.

[0008] For example, in at least one embodiment of this disclosure, determining the order in which the buffer memory processes the first access request or the second access request based on the priority level corresponding to the first access request includes: in response to the request queue of the buffer memory including the second access request and the second access request and the received first access request both requesting access to the same address, adjusting the priority level corresponding to the second access request based on the priority level corresponding to the first access request, and determining the order in which the second access request is processed in the buffer memory in a pipelined manner based on the adjusted priority level corresponding to the second access request.

[0009] For example, in at least one embodiment of this disclosure, determining the order in which the buffer memory processes the first access request or the second access request based on the priority level corresponding to the first access request includes: in response to the first access request having a high priority level, the buffer memory will preferentially process the first access request in a pipelined manner.

[0010] For example, in at least one embodiment of this disclosure, determining the order in which the buffer memory processes the first access request or the second access request based on the priority level corresponding to the first access request includes: in response to the first access request being missed in the buffer memory at the current level, the buffer memory at the current level records the first access request and the priority level corresponding to the first access request in its miss history register; and in response to the first access request and the priority level corresponding to the first access request, sending the first access request to the lower-level buffer memory.

[0011] For example, in at least one embodiment of this disclosure, the processing apparatus further includes a processor core, the processor core including a reordering buffer, the priority update command of the first access request being at least partially associated with the state of the reordering buffer.

[0012] For example, in at least one embodiment of this disclosure, the processing apparatus further includes a processor core, the processor core including an instruction fetch unit, wherein the priority update command of the first access request is at least partially associated with the branch prediction result corresponding to the instruction fetch unit.

[0013] For example, in at least one embodiment of this disclosure, the processing apparatus further includes a processor core, the processor core including an instruction fetch unit and a reordering buffer, wherein the priority update command of the first access request is at least partially associated with the state of the reordering buffer and the branch prediction result corresponding to the instruction fetch unit.

[0014] At least one embodiment of this disclosure provides a processing apparatus, including: a processor core; a multi-level cache memory; wherein the processor core or the multi-level cache memory is configured to perform the above-described method.

[0015] At least one embodiment of this disclosure provides an electronic device including the processing apparatus described above.

[0016] At least one embodiment of this disclosure provides a non-transitory readable storage medium having computer instructions stored thereon, wherein the computer instructions, when executed by a processing device, perform the method described above.

[0017] The embodiments of this disclosure can optimize the response speed of the processing device to access requests of different urgency levels by setting different priorities for access requests, thereby improving the performance of the processing device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0019] Figure 1 This is a schematic diagram of a microprocessor core architecture provided for at least one embodiment of the present disclosure.

[0020] Figure 2 This is a schematic diagram illustrating the use of a pipelined approach to process request queues in a cache memory provided for at least one embodiment of this disclosure.

[0021] Figure 3 A flowchart of a method for processing access requests provided in at least one embodiment of this disclosure.

[0022] Figure 4 A schematic diagram of a processing apparatus for processing access requests provided in at least one embodiment of this disclosure.

[0023] Figure 5 This is an example of adjusting the priority level of an access request, which is an embodiment of at least one of the present disclosures.

[0024] Figure 6 This is yet another example of adjusting the priority level of an access request, which is an embodiment of at least one of the present disclosures.

[0025] Figure 7 This is yet another example of adjusting the priority level of an access request, which is an embodiment of at least one of the present disclosures.

[0026] Figure 8 A schematic block diagram of a processing apparatus provided for at least one embodiment of the present disclosure.

[0027] Figure 9 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0028] Figure 10 This is a schematic diagram of a non-transiently readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0030] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0031] The following is a brief introduction to the terminology associated with this disclosure in order to illustrate this disclosure.

[0032] Cache: Cache memory is a small-capacity memory located between the core and main memory (e.g., secondary storage). Its read / write speed is faster than main memory, enabling high-speed delivery of instructions and data to the central processing unit core, thus improving program execution speed. With the continuous improvement of semiconductor device integration, multi-level cache systems have emerged, where all control logic for each cache level is implemented by its internal controller.

[0033] Level 1 cache: The L1 cache is a high-speed cache located next to the CPU core. It is the cache most closely integrated with the CPU. The L1 cache is further divided into instruction cache and data cache, and has the smallest capacity, which is dedicated to each core / cluster.

[0034] Level 2 cache: L2 cache is a second-level high-speed cache memory of the CPU. Its capacity directly affects the performance of the CPU and is exclusively used by each core / cluster.

[0035] Level 3 cache (L3 cache): L3 cache is a third-level high-speed cache memory for the CPU. Its function is to further reduce memory latency. It is shared by multiple cores / clusters and has the largest capacity. Typically, L3 is also the last-level cache (LLC) of multi-core processors, and L3 is coupled to secondary storage.

[0036] External storage: This is a concept relative to the processor core's memory. It is usually Dynamic Random Access Memory (DRAM), which is typically connected to the Level 3 cache via a bus. External storage has a large capacity but slow access speed.

[0037] Cache line: A cache line is the smallest unit of data exchange between the cache and memory, typically 32 or 64 bytes.

[0038] Write Back: The operation of returning data from the previous level buffer and writing it to the next level buffer or external storage.

[0039] Directory: A record table of the current level of buffer memory that records the access status of the data in the previous level of buffer memory.

[0040] Prefetch: By predicting data reads, data is loaded into the buffer in advance, reducing the latency for each core to retrieve data.

[0041] Miss History Register: Typical examples of miss history registers are the Missing Address Buffer (MAB) or the Missing Status Handling Register (MSHR). When a read / write or prefetch request is not in the current level of the buffer and needs to be read from the next level buffer, the request and its corresponding attributes are stored in the miss history register until the next level buffer returns the requested data.

[0042] Re-order buffer (ROB): A re-order buffer allows instructions to be executed out of order and then committed in their original order. In some dynamic scheduling out-of-order execution mechanisms, there are four phases: issue, execute, write result, and commit. During the write result phase, the result of the instruction is temporarily stored in the re-order buffer. Subsequently, the result of the instruction execution is stored in a register or main memory. If other instructions urgently need this result, the re-order buffer can directly transfer the required data to them.

[0043] Figure 1 This is a schematic diagram of a microprocessor core architecture provided for at least one embodiment of the present disclosure.

[0044] like Figure 1 As shown, in at least one embodiment of this disclosure, an exemplary microprocessor architecture includes a five-stage pipeline, wherein each instruction can be issued in each clock cycle and executed over a fixed period of time, such as five clock cycles. The execution of each instruction is divided into five steps: an instruction fetch (IF) stage 1001, a register read (RD) stage 1002, an arithmetic / logic unit (ALU) stage 1003, a memory (MEM) stage 1004, and a write-back (WB) stage 1005. In the IF stage 1001, a specified instruction is fetched from the instruction cache. A portion of the fetched instruction is used to specify a source register that can be used to execute the instruction. In the RD stage 1002, the system fetches the contents of the specified source register. The obtained value can be used to perform arithmetic or logical operations in the ALU stage 1003. In the MEM stage 1004, the instruction can be read / written to memory in the data cache. Finally, in the WB stage 1005, the value obtained by executing the instruction can be written back to a register.

[0045] Typically, processor cores process data very quickly, but reading data from main memory takes a long time. Therefore, current high-performance processor cores generally employ multi-level caches to buffer data. Caches can also use a pipelined approach to process cache lines corresponding to access requests. For example, each cache line in the cache can be read, written, and updated sequentially.

[0046] However, when performing the aforementioned sequential operations, related structures may be operated on simultaneously, leading to conflicts. For example, when two instructions need to operate on the same or different cache lines with the same index (e.g., in a multi-way set-associative structure, the same index may correspond to 4 or 8 cache lines), an arbitrator is needed to determine which access request is processed first due to the conflict. For example, the arbitrator will determine which cache line corresponding to which access request will be read, written, or updated first.

[0047] Furthermore, because the buffer memory receives a large number of access requests continuously, it is likely to generate numerous conflicts. Frequent conflicts increase the buffer memory's latency. If the buffer memory processes non-critical access requests first, critical access requests may be blocked, leading to delays in the response to critical requests.

[0048] Figure 2 This is a schematic diagram illustrating the use of a pipelined approach to process request queues in a cache memory provided for at least one embodiment of this disclosure.

[0049] For example, in at least one embodiment of this disclosure, such as Figure 2 As shown, the cache memory uses arbitrator 220 to select access requests from request queue 210 to enter the read-write-update pipeline described above. For example, access requests from upper-level cache memory or processors are stored in request queue 210. Requests in request queue 210 can enter arbitrator 220 if they meet preset conditions (e.g., sufficient resources). Arbitrator 220 has arbitration selection logic, that is, it selects access requests according to certain rules. After arbitrator 220 selects an access request, the access request can be processed in a pipelined manner.

[0050] It should be noted that, in the embodiments of this disclosure, there are no restrictions on the preset conditions required for the above-mentioned requests to travel from the request queue 210 to the arbitrator 220, and these conditions can be set according to actual needs. It should also be noted that, in the embodiments of this disclosure, there are no restrictions on the arbitration selection logic of the arbitrator 220. For example, in one example, the arbitration selection logic can be set to allow the request that enters the arbitrator first to be retrieved first; of course, other selection logic (e.g., a polling method) can also be used, and these can be set according to actual needs.

[0051] Because buffers can process access requests put into the pipeline by the arbitrator in a continuous, pipelined manner, there may be situations where consecutive access requests access the same structure. For example, structures with the same index. If the structure cannot process requests consecutively, then a conflict will occur in the buffer's pipeline processing flow.

[0052] For example, in one example, such as Figure 2 As shown, assume there are two access requests – access request A and access request B – both attempting to access the cache line corresponding to index 5 in the L1 buffer, and there are 8 cache lines corresponding to index 5. Assume access request A expects to access the first cache line corresponding to index 5 in the L1 buffer, but the first cache line corresponding to index 5 does not store the data DATA-A that access request A expects to access (i.e., a miss). Further assume that access request B also attempts to access the second cache line among the 8 cache lines corresponding to index 5 in the L1 buffer, and this cache line happens to store the data DATA-B that access request B expects to access (i.e., a hit).

[0053] If the arbitrator 220 uses a round-robin approach to select access request A for pipelined processing first, then during pipelined processing, it may decide, based on a random strategy, to replace the data DATA-B in the second cache line corresponding to index 5, so that access request A can subsequently obtain the desired data DATA-A. For example, during pipelined processing, it is possible to look up the data DATA-A corresponding to access request A in the lower-level buffer, then replace the data DATA-B stored in the second cache line corresponding to index 5 with DATA-A, and correspondingly place the access response A' of access request A, which includes DATA-A, into the response queue 230.

[0054] However, because data DATA-B in the second cache line is replaced with data DATA-A, access request B, which enters the pipeline later, will also be unable to obtain data DATA-B. In other words, in this situation, a pipeline conflict occurs between access request B and access request A, causing access request B, which should have been hit, to miss. This results in reduced efficiency for access request B in obtaining data DATA-B, requiring a longer wait time before an access response B' can be generated for access request B.

[0055] To reduce the aforementioned conflicts, at least one embodiment of this disclosure provides a method for processing access requests. Accordingly, at least one embodiment of this disclosure also provides a processing apparatus, electronic device, and non-transitory readable storage medium corresponding to the above method. Thus, by determining the priority of access requests, at least one embodiment of this disclosure can optimize the response to access requests of different urgency levels, thereby improving the efficiency of data access.

[0056] The following describes, in a non-limiting manner, a method for processing access requests according to at least one embodiment of the present disclosure through several examples or embodiments. As described below, different features in these specific examples or embodiments can be combined with each other without conflict to obtain new examples or embodiments, all of which are also within the scope of protection of the present disclosure.

[0057] Figure 3 A flowchart of a method 30 for processing access requests provided in at least one embodiment of this disclosure. Figure 4 A schematic diagram of a processing apparatus 400 for processing access requests provided in at least one embodiment of this disclosure.

[0058] For example, at least one embodiment of this disclosure provides a method 30 for processing access requests, as shown in FIG3. For example, this method 30 can be applied to various types of processing devices. For example, in at least one embodiment of this disclosure, method 30 can be applied to... Figure 4 The processing device 400 shown.

[0059] For example, in at least one embodiment of this disclosure, such as Figure 3 As shown, the method 30 for processing access requests may include the following operations S301 to S302.

[0060] In operation S301, in response to the current level of the buffer receiving an access request, the priority level corresponding to the first access request is determined.

[0061] In operation S302, the order in which the buffer memory processes the first access request or the second access request is determined based on the priority level corresponding to the first access request.

[0062] For example, the buffer memory can process the first access request in a pipelined manner, or the buffer memory can process the second access request in a pipelined manner. The second access request may be associated with the first access request in various ways; for example, the second access request may access the same data or the second access request may have already obtained the data that the first access request expected to access. This disclosure is not limited thereto.

[0063] The method 30 for processing access requests provided in at least one embodiment of this disclosure can optimize the response speed to access requests of different urgency levels and improve the efficiency of accessing data by determining the priority level corresponding to the first access request.

[0064] It should be noted that in at least one embodiment of this disclosure, operations S301-S302 can be executed sequentially, in parallel, or in other adjusted orders. The embodiments of this disclosure do not restrict the execution order of each step and can be adjusted according to the actual situation.

[0065] It should also be noted that, in at least one embodiment of this disclosure, the method 30 for processing access requests may selectively perform some steps of operations S301 to S302, or may perform some additional steps other than operations S301 to S302. The embodiments of this disclosure do not limit this.

[0066] Optionally, in one example of this disclosure, the access request may include a priority field to indicate the priority of the access request. Taking the L2 buffer as an example, suppose the L2 buffer receives an access request C, indicating that it needs to access data at address 0x06. Optionally, access request C may also indicate that its corresponding priority level is any one of low, medium, or high priority. Alternatively, access request C may also indicate its corresponding priority numerically.

[0067] Those skilled in the art will understand that including a priority field in the access request is merely one example of an implementation of this disclosure. The access request may also omit the priority field. In such cases, the L2 buffer may default to any one of low, medium, or high priority for the access request C. Alternatively, the L2 buffer may analyze the access address corresponding to access request C and, in conjunction with the access requests of each current cache line, assign a priority to access request C. This disclosure does not impose any limitations on this.

[0068] For example, in one embodiment of this disclosure, operation S301 may optionally include determining the priority corresponding to the first access request in response to the current level buffer receiving a priority update command for the first access request. Figure 4 As shown, assuming that in operation S301, the current level of the buffer memory is the L2 buffer memory, and the L2 buffer memory has already stored the access request C in its corresponding request queue. Next, the miss history register in the L1 buffer memory sends a priority update command to the L2 buffer memory, which updates the priority level of the access request C.

[0069] For example, there might be situations where the processor core determines that an access request requires priority processing only after the request has already been sent. Therefore, in such cases, a simple priority update command can be used to indicate whether the access request's priority is being upgraded or downgraded. In some examples, this priority update command is used only to adjust the priority. In other examples, the priority update command may include other fields to assist in implementing other functions, and this disclosure is not limited thereto.

[0070] For example, suppose access request C in the request queue has a low priority. However, the processor core determines that the priority of access request C should be increased. Then, a priority update request for access request C can indicate that its priority level needs to be updated to high priority. In this case, the L2 cache will accordingly set the priority level of access request C to high priority.

[0071] In one example, upon receiving the priority update command, the L2 buffer further queries its built-in request and response queues and updates them accordingly. The following details an example of the L2 buffer updating the request and response queues, but this disclosure is not limited thereto.

[0072] For example, operation S302 may further include adjusting the priority level of the access response based on the priority level corresponding to the first access request, in response to the response queue of the buffer memory including an access response and the access response including the data requested by the first access request. Suppose that the L2 buffer memory finds in its response queue that data at address 0x06 has been prefetched from the L3 buffer memory based on access request K, and stores the access response K' corresponding to access request K in the response queue. Correspondingly, the L2 buffer memory will adjust the priority level of the access response K' in the response queue based on this priority update command, so that the data at address 0x06 can be sent to the L1 buffer memory as quickly as possible. In this case, as an embodiment, an access response C' corresponding to access request C can also be directly generated, and the access response C' correspondingly includes the data at address 0x06. Then, the access response C' can be directly stored in the response queue, and the priority level of the access response C' can be set to high priority. The response queue can also determine the order in which access responses are sent to the L1 buffer memory based on the priority level of each access response. This disclosure does not limit this.

[0073] For example, operation S302 may also include, in response to the request queue of the buffer memory including a second access request, and the second access request and the received first access request both requesting access to the same address, adjusting the priority level of the second access request based on the priority level of the first access request. Suppose the L2 buffer memory finds an existing access request F for data at address 0x06 in its request queue. Correspondingly, the L2 buffer memory will adjust the priority level of access request F in the request queue based on the priority update command (e.g., setting the priority level of access request F to high priority), so that the L2 buffer memory's arbitrator preferentially selects access request F to enter the pipeline. For example, based on access request F, the data at address 0x06 can be retrieved in advance, and a corresponding access response F' can be generated, with the priority level of access response F' also set to high priority. Then, the response queue can also determine the order in which access responses are sent to the L1 buffer memory based on the priority levels of each access response. This disclosure does not limit this.

[0074] For example, operation S302 may also include, in response to the first access request having a high priority level, the buffer memory will preferentially process the first access request in a pipelined manner. Assume that the L2 buffer memory does not find any request attempting to access data at address 0x06 in either its request queue or response queue. Correspondingly, the L2 buffer memory will place access request C into the request queue based on the priority update command and set a higher priority for access request C, so that the L2 buffer memory's arbitrator will preferentially select access request C to enter the pipeline.

[0075] For example, operation S302 may also include, in response to the first access request being missed in the current level of the buffer memory, the current level of the buffer memory recording the first access request and the priority level corresponding to the first access request in its miss history register; and in response to the first access request and the priority level corresponding to the first access request, sending the first access request to the lower level buffer memory.

[0076] Continuing with any of the above examples, after the arbiter of the L2 buffer selects access request C or access request F to enter the pipeline processing flow, after pipeline processing, the L2 buffer may determine that it does not store the data at address 0x06 and needs to further query the L3 buffer for the data at address 0x06. The L2 buffer will correspondingly record access request C or access request F in its miss history register, set access request C or access request F to high accordingly, and then send access request C or access request F with high priority to the L3 buffer. The L3 buffer will also perform a similar process to adjust the priority level of access request C or access request F, which will not be described in detail here.

[0077] It should be noted that, Figure 4 This is merely an example. In the embodiments of this disclosure, the processing apparatus including multi-level caching may also include more or fewer components. The embodiments of this disclosure do not impose specific limitations in this regard and can be configured according to actual needs.

[0078] Therefore, by setting different priorities for access requests, the embodiments of this disclosure can optimize the response speed of the processing device to access requests of different urgency levels, thereby improving the performance of the processing device.

[0079] For example, in at least one embodiment of this disclosure, references can also be made. Figures 5 to 7 The described scenario further adjusts the priority level of access requests.

[0080] First, refer to Figure 5This describes an example scenario of adjusting the priority level of an access request. In this example scenario, the processing device also includes a processor core (e.g., a CPU), and the CPU includes a reordering buffer. The priority update command for the first access request...

[0081] It is at least partially related to the state of the reordering buffer of the processing device.

[0082] exist Figure 5 In this example, it is assumed that the processing unit also includes a CPU. The CPU can execute in out-of-order (OOO) mode. Figure 1 The CPU executes multiple instructions in a pipeline. For example, suppose a program contains five instructions written in sequence: instruction 1, instruction 2, instruction 3, instruction 4, and instruction 5. The actual execution order of these instructions in the CPU could be instruction 3, instruction 4, instruction 5, instruction 1, and instruction 2. However, although the execution order of these instructions can be changed, the CPU's state must be changed strictly according to the order of instruction 1, instruction 2, instruction 3, instruction 4, and instruction 5. For example, changing the CPU's state includes modifying the data corresponding to a specific address in the CPU, modifying various registers in the CPU (e.g., the CPU's architecture registers, and...). Figure 5 The state of the reordering cache in the cache.

[0083] continue Figure 5 In the example above, under out-of-order execution, instruction 2 might be the last to be executed. Therefore, even if instructions 3, 4, and 5 have all finished executing, the reorder buffer must wait for instruction 2 to complete before it can further change its state. In this example, the reorder buffer will place instruction 2 at the bottom and wait for its result.

[0084] In such a situation, if instruction 2 needs to access data stored at a certain address (e.g., address 0*08), but that data is not yet available in memory, the CPU will spend a long time waiting to retrieve the data from the L2 cache or even secondary storage. To further save time, the reorder buffer sends an instruction to the miss history register in the L1 cache, instructing the unnamed history register to return the data stored at address 0*08 as soon as possible. At this point, the unnamed history register in the L1 cache sends a priority update command to the L2 cache, instructing it to increase the priority of the access request to address 0*08, so that instruction 2 can complete execution as quickly as possible, reducing the waiting time of instructions 3, 4, and 5 in the reorder buffer and avoiding performance degradation due to blocking of the reorder buffer.

[0085] Therefore, corresponding to Figure 5 In scenarios where this disclosure provides an embodiment, by increasing the priority of access requests associated with the state of the reorder buffer, the processing device can optimize the response speed of the processing device to instructions waiting in the reorder buffer, thereby improving the performance of the processing device.

[0086] Next, refer to Figure 6 This describes yet another example scenario of adjusting the priority level of an access request. In this example scenario, the processing apparatus further includes a processor core, which includes an instruction fetch unit, wherein the priority update command for the first access request is at least partially associated with a branch prediction result corresponding to the instruction fetch unit.

[0087] For example, such as Figure 6 As shown, when the instruction fetch module detects a branch direction prediction error and an instruction buffer miss, it escalates the address request. Assume... Figure 6 The processor device illustrated in the diagram executes the following pseudocode.

[0088] #####################################################

[0089] If X>5, A=A+3; #Branch ①

[0090] Else B = B - 3; #Branch ②

[0091] #####################################################

[0092] Regarding the pseudocode described above, the branch prediction unit in the processing device might predict that the program segment is more likely to proceed to branch ①. Therefore, the branch prediction unit might instruct the instruction fetch unit to prefetch data A. However, in reality, the program segment should execute branch ②, meaning the branch prediction result corresponding to the instruction fetch unit is incorrect. At this point, the L1 buffer only contains data A, not data B, resulting in a miss for the access request to fetch data B. In this situation, the instruction fetch unit will, based on the branch prediction result, instruct the miss history register to send a priority update command to the L2 buffer to indicate an increase in the priority of the access request to fetch data B. Optionally, the instruction fetch unit might also, based on the branch prediction result, instruct the miss history register to send a priority update command to the L2 buffer to indicate a decrease in the priority of the access request to fetch data A.

[0093] Therefore, corresponding to Figure 6In scenarios where branch prediction errors occur, embodiments of this disclosure can improve the performance of the processing device by prioritizing access requests associated with branch prediction results, thereby optimizing the processing device to quickly compensate for losses caused by branch prediction errors.

[0094] Next, refer to Figure 7 This describes yet another example scenario of adjusting the priority level of an access request. In this example scenario, the processing apparatus further includes a processor core, which includes an instruction fetch unit and a reordering buffer. The priority update command for the first access request is at least partially associated with the state of the reordering buffer and the branch prediction result corresponding to the instruction fetch unit.

[0095] For example, such as Figure 7 As shown, there exists a situation where, although the instruction fetch module detects a branch direction prediction error, there are instructions that need to be fetched from the same address in both the incorrect and correct branch directions. Assume... Figure 7 The processor device illustrated in the diagram executes the following pseudocode.

[0096] #####################################################

[0097] if X>5# Branch ①

[0098] A = A + 3 # Instruction 0, data A needs to be accessed.

[0099] B = B + 5 # Instruction 1, data B needs to be accessed.

[0100] C = C + 2 # Instruction 2, requires access to data C

[0101] else#branch ②

[0102] A = A + 5 # Instruction 3, data A needs to be accessed.

[0103] D = D + 5 # Instruction 4, data D needs to be accessed.

[0104] E = E + 2 # Instruction 5, data E needs to be accessed.

[0105] #####################################################

[0106] Regarding the pseudocode described above, the branch prediction unit in the processing device might predict that the program segment is more likely to go to branch ①. Therefore, the branch prediction unit might instruct the instruction fetch unit to prefetch data A, B, and C. However, in reality, the program segment should execute branch ②, meaning that the branch prediction result corresponding to the instruction fetch unit is incorrect at this point.

[0107] refer to Figure 7 The reordering buffer also records each instruction sequentially and waits for each instruction to complete before refreshing its execution result. Correspondingly, in Figure 7 In the reordering buffer, instructions 0-2 are instructions on the wrong path, and instructions 3-5 are instructions on the correct path.

[0108] Considering that the data storage addresses corresponding to instructions 3-5 and instructions 0-2 overlap—for example, both instructions 3 and 0 need to access the address where data A is stored—if we refer to... Figure 6 In the scenario described, directly downgrading instructions 0-2 may cause instruction 3 to wait a long time to obtain data A, resulting in the reordering buffer never being refreshed.

[0109] Therefore, in response to Figure 7 In the scenario shown, for instructions 3-5, the miss history register can be iterated to check if any access requests for data A, data D, and data E have been issued, or if any unsent access requests for data A, data D, and data E have been generated. After the iteration, in response to the determination that there are access requests requesting access to the same address, the 'new request' flag of the access request can be set to 1. For example, in the above example, the 'new request' flag of the access request for accessing data A can be set to 1. If the access request for accessing data A has already been sent to the L2 buffer, a priority update request can be sent to indicate that the priority level of the access request has been increased. If the access request for accessing data A has not yet been sent to the L2 buffer, the priority field of the access request can be directly modified to set it to a higher priority level.

[0110] Furthermore, since the process of traversing the miss history registers may determine that no access requests have been issued for data D and data E. Because data D and data E are necessary for the execution of this program segment, access requests for data D and data E need to be generated. In some examples, the priority level of the access requests for data D and data E can be directly set to high. In other examples, priority update requests can be directly generated, indicating that the priority level of the access requests for data D and data E be increased.

[0111] Then, for instructions 0-2, the miss history register is traversed to check whether any access requests for data A, data B, and data C have been issued, or whether any unsent access requests for data A, data B, and data C have been generated. During the traversal, for access requests for data A, since the 'new request' flag is 1, the traversal process does not trigger a priority change for that access request. However, for access requests for data B and data C, since the flags for these two access requests are 0, the traversal process will trigger a priority change for the access requests for data B and data C.

[0112] For example, correspondingly, based on the fact that the flags for the access requests for data B and data C are both 0, it can be determined that data B and data C are no longer needed, or that the urgency of data B and data C is not high. If the access requests for data B / C have not yet been sent to the L2 buffer, the priority field of the access request can be directly modified to set it to a lower priority level, or the access request can be deleted directly. If the access requests for data B / C have already been sent to the L2 buffer, a priority update request can be sent to indicate that the priority level of these two access requests be reduced.

[0113] Therefore, corresponding to Figure 7 In scenarios where the processor core depends on access requests (e.g., access requests for data A, data D, and data E), the embodiments of this disclosure can prioritize processing access requests that the processor core depends on, reduce latency in critical data paths, and improve processor performance.

[0114] Figure 8 This is a schematic diagram of the structure of a processing apparatus provided in at least one embodiment of the present disclosure.

[0115] For example, at least one embodiment of this disclosure provides a processing apparatus 80, such as Figure 8 As shown. The processing device 80 includes a processor core 801 and a multi-level buffer memory 802. The processor core 801 and the multi-level buffer memory 802 are communicatively connected to each other. For example, the processor core 801 includes an L1 buffer memory, an instruction fetch unit, and a reorder buffer. The multi-level buffer memory includes the aforementioned L2 buffer memory, L3 buffer memory, and secondary storage. Each level of buffer memory may optionally include a miss history register.

[0116] For example, processor core 801 can be a central processing unit (CPU), a digital signal processor (DSP), or other processing units with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) can be an x86 or ARM architecture. Processor core 801 can be a general-purpose processor core or a dedicated processor core, and can control other components in processing device 80 to perform desired functions.

[0117] For example, the multi-level buffer memory 802 can be volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0118] For example, each level of buffer memory is configured to, in response to receiving an access request in the current level of buffer memory, determine the priority level corresponding to the first access request; and, based on the priority level corresponding to the first access request, determine the order in which the buffer memory processes the first access request or the second access request in a pipelined manner. For example, each level of buffer memory can implement operations S301 to S302, and the specific implementation methods can be referred to the relevant descriptions of operations S301 to S302, which will not be repeated here.

[0119] It should be noted that each level of the buffer memory can implement operations S301 to S302 through software, hardware, firmware, or any combination thereof. For example, each level of the buffer memory can correspondingly include a priority determination circuit and a sequence determination circuit to implement operations S301 and S302, respectively. The embodiments of this disclosure do not limit their specific implementation.

[0120] For example, in at least one embodiment of this disclosure, each level of the buffer memory further includes an arbitrator. The arbitrator is communicatively connected to the request queue. For example, in one example, the arbitrator, as an implementation of a sequence determination circuit, is configured to determine, at least in part, the order in which the buffer memory processes the first access request or the second access request in a pipelined manner based on the priority level corresponding to the first access request.

[0121] It should be noted that, Figure 8The processing device 80 shown is merely exemplary. The processing device may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit is not limited and can be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.

[0122] Figure 9 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 9 The electronic device 900 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0123] For example, such as Figure 9 As shown, in some examples, electronic device 900 includes a processing unit (e.g., a central processing unit core, a graphics processing unit core, etc.) 901, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 902 or a program loaded from storage device 908 into random access memory (RAM) 903. RAM 903 also stores various programs and data required for the operation of the computer system. The processing unit 901, ROM 902, and RAM 903 are connected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.

[0124] For example, the following components can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909 including, for example, network interface cards such as LAN cards, modems, etc. Communication device 909 allows processing device 900 to communicate wirelessly or wiredly with other devices to exchange data, performing communication processing via networks such as the Internet. Drive 310 is also connected to I / O interface 905 as needed. Removable media 9011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 9010 as needed so that computer programs read from them can be installed into storage device 908 as needed. Although Figure 9An electronic device 900 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0125] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 909 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0126] For example, the electronic device 900 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, or navigator, or any combination of processing devices and hardware. The embodiments disclosed herein do not limit this.

[0127] For example, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 909, or installed from a storage device 908, or installed from a ROM 902. When the computer program is executed by a processing device 901, the method 30 disclosed in embodiments of this disclosure is performed.

[0128] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0129] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0130] The aforementioned computer-readable medium may be included in the aforementioned processing device 400 / processing device 80 / processing device 901; or it may exist independently and not be assembled into the processing device 400 / processing device 80 / processing device 901.

[0131] At least one embodiment of this disclosure also provides a non-transitory readable storage medium. Figure 10This is a schematic block diagram of a non-transitory readable storage medium provided in at least one embodiment of this disclosure. Figure 10 As shown, a non-transiently readable storage medium 150 stores computer instructions 111, which, when executed by the processor core, perform one or more steps of the method 30 described above.

[0132] For example, the non-transitory readable storage medium 150 can be any combination of one or more computer-readable storage media. For instance, one computer-readable storage medium includes computer-readable program code for determining a priority level corresponding to the first access request in response to the current level of the buffer receiving an access request; another computer-readable storage medium includes computer-readable program code for determining the order in which the buffer processes the first access request or the second access request in a pipelined manner based on the priority level corresponding to the first access request. Of course, the various program codes described above can also be stored in the same computer-readable medium, and the embodiments of this disclosure do not limit this.

[0133] For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium to perform, for example, the method 30 provided in any embodiment of this disclosure.

[0134] For example, the storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard disk for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media.

[0135] In this disclosure, the term "multiple" means two or more, unless otherwise expressly defined.

[0136] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0137] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method of processing access requests for data in a processing device comprising multiple levels of cache memory and the processing device comprising a processor core, the method comprising: storing, by a current level of cache memory, a first access request into a request queue corresponding to the current level of cache memory; receiving, by the current level of cache memory, a priority update command for the first access request from the processor core or a higher level of cache memory, determining, by the current level of cache memory, a priority corresponding to the first access request based on the priority update command for the first access request; and determining, by an arbiter of the cache memory, an order in which the first access request or a second access request is processed in a pipelined manner based on the priority corresponding to the first access request. The first access request comprises a priority field, and the determining the priority corresponding to the first access request comprises determining the priority corresponding to the first access request based on a priority indicated by the priority field in the first access request.

2. The method of claim 1, wherein, The determining, by the arbiter of the cache memory, the order in which the first access request or a second access request is processed in a pipelined manner based on the priority corresponding to the first access request comprises:

3. The method of claim 1, wherein, adjusting a priority of an access response based on the priority corresponding to the first access request in response to the response queue of the cache memory comprising the access response and the access response comprising data requested by the first access request. The determining, by the arbiter of the cache memory, the order in which the first access request or a second access request is processed in a pipelined manner based on the priority corresponding to the first access request comprises:

4. The method of claim 1, wherein, adjusting a priority corresponding to a second access request based on the priority corresponding to the first access request in response to the request queue of the cache memory comprising the second access request and the second access request and the received first access request both requesting access to a same address, and determining an order in which the second access request is processed in the cache memory in a pipelined manner based on the adjusted priority corresponding to the second access request. The determining, by the arbiter of the cache memory, the order in which the first access request or a second access request is processed in a pipelined manner based on the priority corresponding to the first access request comprises: in response to the priority corresponding to the first access request being a high priority, the cache memory will preferentially process the first access request in a pipelined manner.

5. The method of claim 1, wherein, The determining, by the arbiter of the cache memory, the order in which the first access request or a second access request is processed in a pipelined manner based on the priority corresponding to the first access request comprises:

6. The method of claim 1, wherein, in response to the first access request missing in the current level of the cache memory, recording, by the current level of the cache memory, the first access request and the priority corresponding to the first access request in a miss history register thereof; and sending, by the current level of the cache memory, the first access request to a lower level of cache memory in response to the first access request and the priority corresponding to the first access request. ​ 7. A processing device comprising: a processor core; a multi-level cache memory; wherein the processor core or the multi-level cache memory is configured to perform the method of any of claims 1-6.

8. An electronic device comprising the processing device of claim 7.

9. A non-transitory readable storage medium having stored thereon computer instructions, wherein, the computer instructions, when executed by a processing device, perform the method of any of claims 1-6.

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