A data processing method, device, system, electronic device, and storage medium

Abstract

Embodiments of the present disclosure provide a data processing method, device, system, electronic device and storage medium. The method comprises: sending, to a second chip, first processing data processed by a first processing unit of a first chip; the second chip and the first chip are chips on a first mainboard, and a chip priority of the second chip is lower than a chip priority of the first chip; sending, to the second chip, a first synchronization instruction; the first synchronization instruction comprises first state information of the first processing unit processing the first processing data, and is used to instruct a second processing unit of the second chip to process the first processing data according to the first state information; if it is detected that the first chip is in an abnormal state, sending, to the second chip, a takeover processing instruction; the takeover processing instruction is used to instruct a takeover chip in the second chip to send a second synchronization instruction to a non-takeover chip in the second chip. Through the data processing method of the embodiments of the present disclosure, the hardware resource utilization rate can be improved, the cost can be reduced, and the control efficiency is high.

Description

Technical Field

[0001] This invention relates to the field of chips, and more particularly to a data processing method, apparatus, system, electronic device, and storage medium. Background Technology

[0002] With the continuous development of automotive and autonomous driving technologies, onboard computing units have gradually become key components in vehicle-assisted driving systems. These units process data collected by vehicle sensors such as cameras, millimeter-wave radar, and lidar, providing the results for intelligent decision-making in autonomous driving. As the levels and demands of autonomous driving continue to evolve, the total amount of onboard sensor data increases, placing increasingly higher demands on the computing power and performance of the computing unit's chips. When a single chip cannot meet the computing power requirements, multiple chips need to be cascaded.

[0003] Current methods using PCIe (Peripheral Component Interconnect Express) switching networks for chip data exchange are prone to link failures, which can easily lead to restarts of the switching network controller or even the entire cascaded chip, resulting in data loss or system crashes. To address chip failures, current methods employ multiple master control boards for mirrored backup, performing hot backup switching in case of master board failure. However, this method suffers from low hardware resource utilization, high cost, and the risk of unreliable inter-board interconnection. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this disclosure provides a data processing method, apparatus, system, electronic device, and storage medium, which can improve hardware resource utilization, reduce costs, and achieve high control efficiency.

[0005] This application provides a data processing method, comprising: sending first processed data processed by a first processing unit of a first chip to a second chip; the second chip and the first chip are chips on a first motherboard, and the chip priority of the second chip is lower than that of the first chip; sending a first synchronization instruction to the second chip; the first synchronization instruction includes first status information of the first processing unit processing the first processed data, and the first synchronization instruction is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information; if an abnormal state is detected in the first chip, sending a takeover processing instruction to the second chip; the takeover processing instruction is used to instruct a takeover chip in the second chip to send a second synchronization instruction to a non-takeover chip in the second chip, the second synchronization instruction includes takeover status information of the third processing unit of the takeover chip processing the first processed data, and the second synchronization instruction is used to instruct a fourth processing unit of the non-takeover chip to process the first processed data according to the takeover status information; wherein, the takeover chip is determined from the second chip according to chip priority.

[0006] Optionally, the first chip and the second chip are system chips connected via a high-speed serial computer expansion bus interface.

[0007] Optionally, after sending the takeover processing instruction to the second chip, the method further includes: sending a takeover operation instruction to the takeover chip; the takeover operation instruction includes first operation data operated by the first operation unit of the first chip, and the takeover operation instruction is used to instruct the takeover operation unit of the takeover chip to operate on the first operation data.

[0008] Optionally, the first chip and the second chip share the same computing cache space. After sending the takeover processing instruction to the second chip, the method further includes: sending a takeover computing instruction to the takeover chip; the takeover computing instruction is used to instruct the takeover chip to read the first computing data operated by the first computing unit of the first chip from the computing cache space, and to instruct the takeover computing unit of the takeover chip to operate on the first computing data.

[0009] Optionally, after sending the first synchronization instruction to the second chip, the method further includes: if an overload is detected in the first arithmetic unit of the first chip, determining auxiliary arithmetic data from the first arithmetic data; sending an auxiliary arithmetic instruction to the second chip; the auxiliary arithmetic instruction includes auxiliary arithmetic data, and the auxiliary arithmetic instruction is used to instruct the auxiliary arithmetic unit of the auxiliary chip in the second chip to perform arithmetic operations on the auxiliary arithmetic data; wherein the auxiliary chip is determined from the second chip according to chip priority.

[0010] Optionally, after sending the takeover processing instruction to the takeover chip, the method further includes: if both the first chip and the second chip are detected to be in an abnormal state, sending a supervisor operation instruction to the supervisor chip of the second motherboard; the supervisor operation instruction includes the first operation data operated by the first operation unit of the first chip, and the supervisor operation instruction is used to instruct the supervisor operation unit of the supervisor chip to operate the first operation data; wherein, the supervisor chip is determined from the takeover motherboard according to the chip priority, and the takeover motherboard is determined from the second motherboard according to the motherboard priority; the second motherboard and the first motherboard are connected.

[0011] Optionally, after sending the takeover processing instruction to the takeover chip, the method further includes: if an overload is detected in the reference arithmetic unit of the reference chip in the second chip, sending a data transfer instruction to the reference chip; the data transfer instruction is used to instruct the reference chip to determine auxiliary arithmetic data from the reference arithmetic data processed by the reference arithmetic unit, and to send the auxiliary arithmetic data to the auxiliary chip; wherein, the chip priority of the reference chip is lower than a preset priority; sending an auxiliary arithmetic instruction to the auxiliary chip of the second motherboard; the auxiliary arithmetic instruction is used to instruct the auxiliary arithmetic unit of the auxiliary chip to process the auxiliary arithmetic data; wherein, the second motherboard and the first motherboard are connected, the auxiliary chip determines the data from the auxiliary motherboard according to the chip priority, and the auxiliary motherboard determines the data from the second motherboard according to the motherboard priority.

[0012] Accordingly, embodiments of this application provide a data processing apparatus, the apparatus comprising:

[0013] The first transmitting unit is used to transmit the first processed data processed by the first processing unit of the first chip to the second chip; the second chip and the first chip are chips on the first motherboard, and the chip priority of the second chip is lower than that of the first chip.

[0014] The second sending unit is used to send a first synchronization instruction to the second chip; the first synchronization instruction includes first status information of the first processing unit processing the first processed data, and the first synchronization instruction is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information.

[0015] The third sending unit is used to send a takeover processing instruction to the second chip if an abnormal state is detected in the first chip. Optionally, the takeover processing instruction is used to instruct the takeover chip in the second chip to send a second synchronization instruction to the non-takeover chip in the second chip. The second synchronization instruction includes takeover status information of the third processing unit of the takeover chip processing the first processed data, and instructs the fourth processing unit of the non-takeover chip to process the first processed data according to the takeover status information. The takeover chip is determined from the second chip according to chip priority.

[0016] Optionally, the first chip and the second chip are system chips connected via a high-speed serial computer expansion bus interface.

[0017] Optionally, the device further includes a fourth transmitting unit, used to send a takeover operation instruction to the takeover chip after sending a takeover processing instruction to the second chip; the takeover operation instruction includes first operation data calculated by the first operation unit of the first chip, and the takeover operation instruction is used to instruct the takeover operation unit of the takeover chip to calculate the first operation data.

[0018] Optionally, the first chip and the second chip share the same computing cache space. The fourth sending unit is used to send a takeover computing instruction to the takeover chip after sending a takeover processing instruction to the second chip. The takeover computing instruction is used to instruct the takeover chip to read the first computing data processed by the first computing unit of the first chip from the computing cache space, and to instruct the takeover computing unit of the takeover chip to process the first computing data.

[0019] Optionally, the device further includes a fifth transmitting unit, configured to, after sending a first synchronization instruction to the second chip, if an overload is detected in the first processing unit of the first chip, determine auxiliary processing data from the first processing data; and send an auxiliary processing instruction to the second chip; the auxiliary processing instruction includes auxiliary processing data, and the auxiliary processing instruction is used to instruct the auxiliary processing unit of the auxiliary chip to process the auxiliary processing data. The auxiliary chip is determined from the second chip according to the chip priority.

[0020] Optionally, the device further includes a sixth transmitting unit, used to send a supervisory operation instruction to the supervisory chip of the second motherboard if, after sending a takeover processing instruction to the takeover chip, both the first chip and the second chip are detected to be in an abnormal state; the supervisory operation instruction includes first operation data processed by the first operation unit of the first chip, and the supervisory operation instruction is used to instruct the supervisory operation unit of the supervisory chip to process the first operation data. The supervisory chip is determined from the takeover motherboard according to chip priority, and the takeover motherboard is determined from the second motherboard according to motherboard priority; the second motherboard and the first motherboard are connected.

[0021] Optionally, the device further includes a seventh transmitting unit, used to send a data transfer instruction to a reference chip after sending a takeover processing instruction to the takeover chip; the data transfer instruction is used to instruct the reference chip to determine auxiliary calculation data from the reference calculation data calculated by the reference calculation unit, and send the auxiliary calculation data to the auxiliary chip; wherein, the chip priority of the reference chip is lower than a preset priority; and to send an auxiliary calculation instruction to the auxiliary chip of the second motherboard; the auxiliary calculation instruction is used to instruct the auxiliary calculation unit of the auxiliary chip to calculate the auxiliary calculation data; wherein, the second motherboard is connected to the first motherboard, the auxiliary chip determines the data from the auxiliary motherboard according to the chip priority, and the auxiliary motherboard determines the data from the second motherboard according to the motherboard priority.

[0022] Accordingly, this application provides a data processing system, which includes a first chip and a second chip. The first chip and the second chip are connected on a first motherboard, and the chip priority of the second chip is lower than that of the first chip.

[0023] Optionally, the first chip is used to send first processed data processed by the first processing unit of the first chip to the second chip; send a first synchronization instruction to the second chip; the first synchronization instruction includes first status information of the first processing unit processing the first processed data, and the first synchronization instruction is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information; if the first chip is detected to be in an abnormal state, a takeover chip is determined from the second chip according to the chip priority; and a takeover processing instruction is sent to the takeover chip.

[0024] Optionally, the second chip includes a takeover chip and a non-takeover chip. The takeover chip is used to receive takeover processing instructions and send a second synchronization instruction to the non-takeover chip. The second synchronization instruction includes takeover status information of the third processing unit of the takeover chip processing the first processing data, and the second synchronization instruction is used to instruct the fourth processing unit of the non-takeover chip to process the first processing data according to the takeover status information.

[0025] Accordingly, this disclosure provides an electronic device, which includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The processor loads and executes the at least one instruction, at least one program, code set, or instruction set to implement the above-described data processing method.

[0026] Accordingly, embodiments of this disclosure provide a computer-readable storage medium storing at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, at least one program, code set, or instruction set is loaded and executed by a processor to implement the above-described data processing method.

[0027] The embodiments of this application have the following beneficial effects:

[0028] (1) In the event of an abnormality in the main chip, a takeover chip is determined from the chips cascaded on the first motherboard according to the preset priority, and the takeover chip is controlled to take over the operation and processing functions of the main chip. This main-backup switching method does not require the use of multiple motherboards as backups, thereby achieving high hardware resource utilization, low cost, and high control efficiency.

[0029] (2) By synchronizing the processing data in multiple cascaded chips and flexibly scheduling the computing data in the entire motherboard according to the chip priority, the system can be decentralized to improve the reliability of the processing computing system in a single motherboard.

[0030] (3) By identifying the auxiliary chip and distributing the overloaded computing data to the auxiliary chip, the stability of the computing system in the motherboard can be improved and individual chips can be prevented from running under overload.

[0031] (4) By interconnecting the first motherboard and one or more second motherboards, and determining the target chip from the second motherboard to perform standby or auxiliary computing functions according to the preset priority, without having to enable all the chips of the entire second motherboard, the minimum number of chips can be enabled while ensuring the system functions and avoiding computing power redundancy to the greatest extent. Attached Figure Description

[0032] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram illustrating an application scenario of a data processing method provided in an embodiment of this application;

[0034] Figure 2 This is a first flowchart illustrating a data processing method provided in an embodiment of this application;

[0035] Figure 3 This is a schematic diagram of the second process of a data processing method provided in an embodiment of this application;

[0036] Figure 4 This is a schematic diagram of the third process of a data processing method provided in an embodiment of this application;

[0037] Figure 5 This is a schematic diagram of the fourth process of a data processing method provided in an embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0039] Figure 7a This is a first structural schematic diagram of a data processing system provided in an embodiment of this application;

[0040] Figure 7b This is a schematic diagram of the second structure of a data processing system provided in an embodiment of this application;

[0041] Figure 7c This is a schematic diagram of the third structure of a data processing system provided in an embodiment of this application;

[0042] Figure 8 This is a hardware structure block diagram of a server for a data processing method provided in an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely one embodiment of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] The term "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device / system or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having” / “being” and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system / apparatus, product or device that includes a series of steps or units / modules is not necessarily limited to those steps or units / modules that are explicitly listed, but may include other steps or units / modules that are not explicitly listed or that are inherent to such process, method, product or device.

[0045] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of a data processing method provided in an embodiment of this application. For example... Figure 1 As shown, it includes a vehicle 101 and one or more sensors 1011 and one or more controllers 1012 contained in the vehicle 101.

[0046] Optionally, vehicle 101 may include sensor 1011 for sensing the surrounding environment. Sensor 2110 may include one or more of the following sensors: ultrasonic sensor, millimeter-wave radar, lidar (LiDAR), vision camera, and infrared camera. The camera may be mounted at the front, rear, or other locations of the vehicle. In an optional embodiment, the ultrasonic sensor, millimeter-wave radar, lidar (LiDAR), vision camera, and infrared camera can acquire perception data, enabling controller 1012 to analyze the acquired perception data for determining autonomous driving decisions.

[0047] Optionally, vehicle 101 may include controller 1012. Controller 1012 may include a processor that communicates with various types of computer-readable storage devices or media, such as a central processing unit (CPU) or graphics processing unit (GPU), or other dedicated processors. The computer-readable storage device or media may include any non-transitory storage device, which can be any storage device that is non-transitory and capable of storing data. Some data in the computer-readable storage device or media represents executable instructions used by controller 1012 to control the vehicle. In an optional embodiment, controller 1012 may include a first chip and a second chip, which may be chips on a first motherboard, with the second chip having a lower chip priority than the first chip. The first chip can send first processed data processed by the first processing unit of the first chip to the second chip; and send a first synchronization instruction to the second chip. The first synchronization instruction includes first status information of the first processing unit processing the first processed data, and is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information. If an abnormal state is detected in the first chip, a takeover processing instruction is sent to the second chip. The takeover processing instruction is used to instruct the takeover chip in the second chip to send a second synchronization instruction to the non-takeover chip in the second chip. The second synchronization instruction includes takeover status information of the third processing unit of the takeover chip processing the first processed data, and is used to instruct the fourth processing unit of the non-takeover chip to process the first processed data according to the takeover status information. Optionally, the first processed data can be sensing data acquired by sensor 1011.

[0048] In addition, it should be noted that, Figure 1 The example shown is merely one application environment of the data processing method provided in this disclosure. In practical applications, other application environments may also be included. This embodiment does not limit this. The vehicle in this disclosure may include... Figure 1 The vehicle 101 shown may have one or more of the following structures or functions.

[0049] The following describes an exemplary process of a data processing method provided in this application. Figure 2 This is a first flowchart illustrating a data processing method provided in an embodiment of this application. This specification provides the method or process steps shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer steps may be included. The order of steps listed in the embodiments is merely one of many execution orders and does not represent the only execution order. In actual execution, the method or process shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment). Specifically, as shown... Figure 2 As shown, the execution entity of this exemplary process can be a first chip, and the process includes:

[0050] S201: Send the first processed data processed by the first processing unit of the first chip to the second chip.

[0051] Optionally, the second chip and the first chip can be chips on the first motherboard, and the chip priority of the second chip can be lower than that of the first chip.

[0052] Optionally, the first chip and the second chip can be SoC (System on a Chip) chips connected via a PCIe interface. In one optional implementation, the first chip and the second chip can be automotive chips, which can be used for vehicle-related data processing and computation, such as autonomous driving.

[0053] Optionally, there can be one first chip and one or more second chips, which can be cascaded to form a network. Correspondingly, each first chip or each second chip can be connected to a matching FPGA (Field Programmable Gate Array). Optionally, the FPGA can be used for temporary storage of data processed by the first or second chip, and can also serve as a data transmission and reception path when the first or second chip communicates with other chips, and for temporary storage of transmitted and received data.

[0054] Optionally, the primary chip can refer to the chip with the highest priority among the chips currently in normal or working state on the first motherboard. Initially, both the first and second chips can be in normal state. Based on the higher priority of the first chip compared to all second chips, the first chip can serve as the primary chip in the entire chip cascade system of the first motherboard. With the first chip as the primary chip, one or more second chips can serve as non-primary chips, and the PCIe path corresponding to the first chip can act as the primary path for data communication with one or more second chips. Optionally, this data communication can be transmitted from the PCIe path to one or more second chips via the FPGA corresponding to the first chip.

[0055] In one specific implementation, the first processing unit and the second processing unit can be used for business logic processing and control. When the first chip is used as the primary chip, the processing data in the first chip and the second chip can be mirrored and backed up. Specifically, the first processing data processed by the first processing unit of the first chip can be sent to the second chip. Optionally, the first processing data can be sent to the second chip via the on-board switching network of the first motherboard. Optionally, this data transmission can be via a high-speed bus, such as an SGMII (Serial Gigabit Media Independent Interface) high-speed bus. The switching network can be a Fabric (flat network architecture) switching network.

[0056] In one optional implementation, the first processing unit and the second processing unit can serve as carriers of the application layer and the human-computer interaction layer. When the first chip is the main chip, the operating state of the first processing unit of the first chip can be consistent with the operating state of the second processing unit of the second chip.

[0057] Optionally, the processing unit in this embodiment includes a first processing unit and a second processing unit, which may be a CPU (Central Processing Unit), and its operating state may be an interaction state between the CPU and the application layer. Optionally, the operating state of the first processing unit can be sent to the second chip through the on-board switching network of the first motherboard; after receiving the operating state of the first processing unit, the second chip can control the operating state of the second processing unit to be consistent with the operating state of the first processing unit. Optionally, this data transmission can be via a high-speed bus, such as an SGMII high-speed bus. The switching network may be a Fabric switching network.

[0058] S202: Send the first synchronization command to the second chip.

[0059] Optionally, the first synchronization instruction may include first status information of the first processing unit processing the first processed data, and the first synchronization instruction may be used to instruct the second processing unit of the second chip to process the first processed data according to the first status information.

[0060] Optionally, the first synchronization command can be sent via a high-speed bus, such as the SGMII high-speed bus.

[0061] Optionally, the first state information may include data processing states such as idle state, running state, and scheduling state.

[0062] S203: If the first chip is detected to be in an abnormal state, a takeover processing command is sent to the second chip.

[0063] Optionally, the takeover processing instruction can be used to instruct the takeover chip in the second chip to send a second synchronization instruction to the non-takeover chip in the second chip. The second synchronization instruction includes the takeover status information of the third processing unit of the takeover chip processing the first processing data, and the second synchronization instruction is used to instruct the fourth processing unit of the non-takeover chip to process the first processing data according to the takeover status information.

[0064] Optionally, the takeover chip can be determined from the second chip based on chip priority. Optionally, each chip in the second chip can determine the takeover chip based on chip priority, wherein after determining itself as the takeover chip, the takeover chip can send a second synchronization instruction to the non-takeover chips based on the received takeover processing instruction. Optionally, the chip priority can be pre-stored in the flash memory of the first chip or the second chip.

[0065] The number of second chips can be one or more. In an embodiment where there is only one second chip, the second chip is the takeover chip; in an embodiment where there are multiple second chips, the chip with a priority greater than or equal to a preset priority can be designated as the takeover chip. Optionally, the formula for determining the preset priority can be: Preset priority = Chip priority of the first chip - 1.

[0066] The takeover chip is determined from the second chip by filtering chips in descending order of priority, selecting the chip with the highest priority from the chips in the second chip that are in a normal state. In an optional implementation, determining the takeover chip from the second chip based on chip priority may include determining the takeover chip from the second chip based on both chip priority and chip state. Optionally, if the chip priority of the second chip is equal to a preset priority and it is in a normal state, then the second chip is determined as the takeover chip; or, if the chip priority of the second chip is equal to the preset priority and it is in an abnormal state, then the chip in the second chip with a chip priority equal to (preset priority - 1) is determined as the takeover chip.

[0067] Optionally, the takeover chip can refer to the main chip in the cascaded chip system of the first motherboard after the first chip malfunctions.

[0068] In one alternative implementation, the takeover instruction can be an interrupt signal. If the first chip is in an abnormal state, it can send an interrupt signal to the second chip. Optionally, the first chip can also send an interrupt signal to the FPGA corresponding to it.

[0069] Optionally, after receiving the takeover processing instruction, the takeover chip can send a second synchronization instruction to the non-takeover chip in the second chip. The second synchronization instruction includes takeover status information of the third processing unit of the takeover chip processing the first processed data, and instructs the fourth processing unit of the non-takeover chip to process the first processed data according to the takeover status information. Optionally, the non-takeover chip can be a chip in the second chip whose chip priority is lower than that of the takeover chip.

[0070] Optionally, the takeover status information may include data processing status such as idle status, running status, and scheduling status.

[0071] Optionally, after the takeover chip receives the takeover processing instruction, the FPGA corresponding to the takeover chip can obtain the PCIe transmit and receive data synchronized with the FPGA corresponding to the first chip, and schedule the non-takeover chips based on the FPGA transmit and receive data.

[0072] In an optional implementation, the computing unit in this application embodiment, including the first computing unit of the first chip or the takeover computing unit of the takeover chip, can be an NPU (Nueral-network Processing Unit) or a DSP (Digital Signal Processing) unit. The first computing unit, the takeover computing unit, or the second computing unit of the second chip can be used for the computational analysis required for decoding video, millimeter-wave radar, and lidar data. The NPU or DSP unit, as a data processing computing power unit, can be used to perform artificial intelligence calculations on the acquired and decoded video stream data, millimeter-wave radar data, and lidar data according to a preset algorithm. Its computing power can be centrally scheduled via a high-speed bus.

[0073] Optionally, after step S204, the data processing method may further include: sending a takeover operation instruction to the takeover chip; the takeover operation instruction includes first operation data operated by the first operation unit of the first chip, and the takeover operation instruction is used to instruct the takeover operation unit of the takeover chip to operate the first operation data. In an optional embodiment, the takeover operation instruction may be an interrupt signal. When the first chip is in an abnormal state, the first chip may send an interrupt signal to the second chip. Optionally, the first chip may also send an interrupt signal to the FPGA corresponding to the first chip. Optionally, the operation data processed by the operation unit includes data such as video, millimeter-wave radar, and lidar, which may be cached via the DRAM (Dynamic Random Access Memory) connected to the FPGA corresponding to the chip. That is, the first operation data may be stored in the DRAM connected to the FPGA corresponding to the first chip. The takeover operation instruction including the first operation data may be sent to the takeover chip via the PCIe bus, and after receiving the first operation data, the takeover chip may cache the first operation data in the DRAM connected to the FPGA corresponding to the takeover chip and perform operation on the first operation data. Optionally, when the takeover chip is also in an abnormal state, the takeover chip can be re-determined in step S203, and the data processing and operation can continue to be performed based on the newly determined takeover chip.

[0074] Optionally, the first chip and the second chip can share a computing cache space. After sending the takeover processing instruction to the second chip, the method further includes: sending a takeover computing instruction to the takeover chip; the takeover computing instruction is used to instruct the takeover chip to read the first computing data processed by the first computing unit of the first chip from the computing cache space, and to instruct the takeover computing unit of the takeover chip to process the first computing data. In an optional embodiment, the takeover computing instruction can be an interrupt signal. When the first chip is in an abnormal state, the first chip can send an interrupt signal to the second chip. Optionally, the first chip can also send an interrupt signal to the FPGA corresponding to the first chip. Optionally, the computing data processed by the first motherboard, including video, millimeter-wave radar, lidar, and other data, can optionally be cached via the DRAM connected to the FPGA corresponding to the chip. That is, all computing data of the first chip and the second chip can be stored together in the DRAM connected to the FPGA, and the takeover chip can directly read the first computing data from the shared computing cache space and perform computing on the first computing data. Optionally, when the takeover chip is also in an abnormal state, the takeover chip can be re-determined in step S203, and the data processing and computing operations can continue to be performed based on the newly determined takeover chip.

[0075] Optionally, after the first chip enters an abnormal state, it can perform a fault restart operation. Optionally, during the fault restart process of the first chip, the FPGA corresponding to the first chip can or may not perform a restart operation. If the FPGA corresponding to the first chip does not perform a restart operation, the PCIe controller interfaced with the first chip only performs communication initialization operations. If the FPGA corresponding to the first chip performs a restart operation, the restart of the FPGA corresponding to the first chip is completed before the restart of the first chip. At this time, the FPGA corresponding to the first chip can receive the cached computation or processing data in the FPGA corresponding to the takeover chip, and can cache the data in the connected DRAM. After the restart of the first chip is complete, the first chip can be re-set as the primary chip, and the takeover chip is demoted to a non-primary chip, with the computation data being processed preferentially by the first chip.

[0076] The data processing method provided in this application embodiment can, in the event of a failure of the primary chip, determine a takeover chip among the cascaded chips on the motherboard according to a preset priority, and control the takeover chip to take over the computing and processing functions of the primary chip. This primary / standby switching method eliminates the need for multiple motherboards as backups, thereby achieving high hardware resource utilization, low cost, and high control efficiency. Furthermore, by synchronizing the processed data across multiple cascaded chips and flexibly scheduling it centrally across the entire motherboard according to chip priority, the reliability of the processing and computing system within a single motherboard can be improved.

[0077] Figure 3 This is a schematic diagram of the second process of a data processing method provided in an embodiment of this application. The following is based on... Figure 3 The exemplary process following step S202 is further described. Optional, such as... Figure 3 As illustrated, the exemplary process includes:

[0078] S301: If the first arithmetic unit of the first chip is detected to be overloaded, auxiliary arithmetic data is determined from the first arithmetic data.

[0079] Optionally, the auxiliary calculation data to be sent to the auxiliary chip can be determined from the first calculation data.

[0080] In one optional implementation, the overload of the first arithmetic unit can be determined; based on the overload, auxiliary arithmetic data can be determined from the first arithmetic data. The total amount of auxiliary arithmetic data can be greater than the overload.

[0081] S302: Send auxiliary calculation instructions to the second chip.

[0082] Optionally, the auxiliary operation instructions may include auxiliary operation data, and the auxiliary operation instructions may be used to instruct the auxiliary operation unit of the auxiliary chip to perform operations on the auxiliary operation data.

[0083] Since the computing power of the first processing unit of the first chip is limited, an auxiliary chip can be determined from the second chip based on chip priority when the first processing unit is overloaded. Optionally, the auxiliary chip can be determined from the second chip based on chip priority. Optionally, each chip in the second chip can determine the auxiliary chip based on chip priority, wherein after determining itself as an auxiliary chip, the auxiliary chip can perform auxiliary calculations based on received auxiliary calculation instructions. Optionally, the chip priority can be pre-stored in the flash memory of the first chip or the second chip.

[0084] Optionally, the number of second chips can be one or more. In an embodiment where there is only one second chip, the second chip is an auxiliary chip; in an embodiment where there are multiple second chips, the chip with a priority greater than or equal to a preset priority can be designated as an auxiliary chip. Optionally, the formula for determining the preset priority can be: Preset priority = Chip priority of the first chip - 1.

[0085] Optionally, the auxiliary chip can be determined from the second chip by filtering according to chip priority from high to low, selecting the chip with the highest priority from the chips in the second chip that are in a normal state as the auxiliary chip. The number of auxiliary chips can be one or more. In an optional embodiment, determining the auxiliary chip from the second chip based on chip priority can include: determining the auxiliary chip from the second chip based on chip priority and chip state. Optionally, if the chip priority of the second chip is equal to a preset priority and is in a normal state, then the second chip is determined as the auxiliary chip; or; if the chip priority of the second chip is equal to the preset priority and is in an abnormal state, then the chip in the second chip with a chip priority equal to (preset priority - 1) is determined as the auxiliary chip.

[0086] Optionally, the auxiliary chip can refer to a chip in the second chip that assists the first arithmetic unit in performing data operations after the first arithmetic unit of the first chip is overloaded.

[0087] Optionally, auxiliary operation instructions, including auxiliary operation data, can be sent to the auxiliary chip via the PCIe bus. The auxiliary operation data sent to the auxiliary chip can be buffered in the DRAM connected to the FPGA corresponding to the auxiliary chip, and then performed by the auxiliary operation unit of the auxiliary chip. Optionally, the auxiliary operation instructions can be sent via a high-speed bus, such as the SGMII high-speed bus.

[0088] In this embodiment of the application, by identifying the auxiliary chip and distributing the overloaded computing data to the auxiliary chip, the stability of the computing system within the motherboard can be improved, and individual chips can be prevented from operating under overload.

[0089] Figure 4 This is a schematic diagram of the third process of a data processing method provided in an embodiment of this application. The following is based on... Figure 4 The exemplary process following step S204 is further described. In an optional implementation, the second motherboard can be connected to the first motherboard and take over the processing functions of the first motherboard when it is in an abnormal state. Optionally, as... Figure 4 As illustrated, the exemplary process includes:

[0090] S401: If both the first chip and the second chip are detected to be in an abnormal state, send a supervisor operation instruction to the supervisor chip of the second motherboard.

[0091] Optionally, the supervisory operation instruction may include first operation data operated by the first operation unit of the first chip, and the supervisory operation instruction may be used to instruct the supervisory operation unit of the supervisory chip to operate on the first operation data.

[0092] Optionally, the takeover motherboard can be determined from the second motherboard based on motherboard priority.

[0093] Optionally, the second motherboard can be connected to the first motherboard. The first and second motherboards can be connected via a GE (Gigabit Ethernet) bus to achieve data interconnection and computing power scheduling between the motherboards.

[0094] Optionally, there can be one first motherboard and one or more second motherboards. The structures of the first and second motherboards can be identical. Specifically, the chip priority settings of the chips in the first motherboard can be the same as those of the chips in the second motherboard, and the number of chips in the first and second motherboards can also be the same.

[0095] Optionally, the takeover motherboard can be determined from the second motherboards based on motherboard priority. Optionally, each motherboard in the second motherboard can be designated as the takeover motherboard based on its motherboard priority. The motherboard priority can be pre-stored in the flash memory of either the first or second motherboard. In an embodiment where there is only one second motherboard, the second motherboard is the takeover motherboard; in an embodiment where there are multiple second motherboards, the motherboard with a priority greater than or equal to a preset priority can be designated as the takeover motherboard. Optionally, the formula for determining the preset priority can be: Preset priority = Motherboard priority of the first motherboard - 1.

[0096] Optionally, the takeover motherboard can be determined from the second motherboard by filtering motherboards in descending order of priority, selecting the motherboard with the highest priority from the motherboards in the normal state as the takeover motherboard. In one optional implementation, determining the takeover motherboard from the second motherboard based on motherboard priority can include determining the takeover motherboard from the second motherboard based on both motherboard priority and motherboard state. Optionally, if the motherboard priority of the second motherboard is equal to a preset priority and is in a normal state, then the second motherboard is determined as the takeover motherboard; or, if the motherboard priority of the second motherboard is equal to the preset priority and is in an abnormal state, then the motherboard in the second motherboard with a motherboard priority equal to (preset priority - 1) is determined as the takeover motherboard.

[0097] Optionally, the takeover motherboard can refer to the primary motherboard in a cascaded motherboard system after the primary motherboard malfunctions.

[0098] Optionally, the supervisor chip can be determined from the control motherboard based on chip priority. Optionally, the method for determining the supervisor chip from the chips on the control motherboard can be consistent with the method for determining the control chip from the second chip described above. Optionally, the supervisor chip can be determined from the chips on the control motherboard by filtering according to chip priority from high to low, selecting the chip with the highest priority from the chips on the control motherboard that are in normal condition as the supervisor chip.

[0099] Optionally, the supervisory operation instruction can be sent from the first chip on the first motherboard to the supervisory chip that takes over the motherboard via the GE bus. After receiving the supervisory operation instruction containing the first operation data, the supervisory chip can control the supervisory operation unit to perform the first operation data. Optionally, the supervisory operation instruction including the first operation data can be sent to the supervisory chip via the PCIe bus, and after receiving the first operation data, the supervisory chip can cache the first operation data in the DRAM connected to the FPGA corresponding to the supervisory chip, and perform the operation on the first operation data. Optionally, when the supervisory chip is also in an abnormal state, other chips on the same motherboard besides the supervisory chip can re-determine the supervisory chip, and the data processing and operation operations can continue to be performed based on the newly determined supervisory chip.

[0100] Figure 5 This is a schematic diagram of the fourth process of a data processing method provided in an embodiment of this application. The following is based on... Figure 5 The exemplary process following step S204 is further described. In an optional implementation, the second motherboard can be connected to the first motherboard and assist the first motherboard in performing computational functions when the first motherboard is in a computational overload state. Optional features include... Figure 5 As illustrated, the exemplary process includes:

[0101] S501: If the reference arithmetic unit of the reference chip in the second chip is detected to be overloaded, a data transfer instruction is sent to the reference chip.

[0102] Optionally, the data transfer instruction can be used to instruct the reference chip to determine auxiliary operation data from the reference operation data operated on by the reference operation unit, and to send the auxiliary operation data to the auxiliary chip.

[0103] Optionally, the method for determining auxiliary computation data from the reference computation data can be the same as the method for determining auxiliary computation data from the first computation data described above. Optionally, the load overload of the reference computation unit can be determined; based on the load overload, auxiliary computation data can be determined from the reference computation data. The total amount of auxiliary computation data can be greater than the load overload.

[0104] Optionally, the reference chip's priority can be less than or equal to a preset priority. The preset priority can be the lowest chip priority in the first motherboard. The overload state of the reference chip can be used to characterize the overload state of the first motherboard. Specifically, if the reference computing unit of the reference chip is overloaded, then the computing load of the entire first motherboard is overloaded.

[0105] Optionally, data transfer instructions and auxiliary computation data can be sent to the reference chip and the auxiliary chip respectively via the PCIe bus. After receiving the auxiliary computation data, the auxiliary chip can cache the auxiliary computation data in the DRAM connected to the FPGA corresponding to the auxiliary chip. Optionally, when the auxiliary chip is also in an abnormal state, the auxiliary chip can be re-determined in step S402, and data processing and computation operations can continue to be performed based on the newly determined auxiliary chip.

[0106] S502: Sends auxiliary calculation instructions to the auxiliary chip of the second motherboard.

[0107] Optionally, auxiliary operation instructions can be used to instruct the auxiliary operation unit of the auxiliary chip to perform auxiliary operation data.

[0108] Optionally, the second motherboard can be connected to the first motherboard. The first and second motherboards can be connected via a GE (Gigabit Ethernet) bus to achieve data interconnection and computing power scheduling between the motherboards.

[0109] Optionally, there can be one first motherboard and one or more second motherboards. The structures of the first and second motherboards can be identical. Specifically, the chip priority settings of the chips in the first motherboard can be the same as those of the chips in the second motherboard, and the number of chips in the first and second motherboards can also be the same.

[0110] Optionally, the auxiliary chip can be determined from the auxiliary motherboard based on chip priority, and the auxiliary motherboard can be determined from the second motherboard based on motherboard priority. Optionally, the method for determining the auxiliary chip from the chips of the auxiliary motherboard can be the same as the method for determining the auxiliary chip from the second motherboard described above. Optionally, the auxiliary chip can be determined from the chips of the auxiliary motherboard by filtering in descending order of chip priority, selecting the chip with the highest chip priority from the chips of the auxiliary motherboard that are in normal condition as the auxiliary chip.

[0111] In embodiments where there is only one second motherboard, the second motherboard is an auxiliary motherboard; in embodiments where there are multiple second motherboards, the motherboard with a priority greater than or equal to a preset priority among the second motherboards can be designated as an auxiliary motherboard. Optionally, the formula for determining the preset priority can be: Preset priority = Motherboard priority of the first motherboard - 1.

[0112] Optionally, the auxiliary motherboard can be determined from the second motherboard by filtering according to motherboard priority from high to low, selecting the motherboard with the highest priority from the motherboards in normal condition in the second motherboard as the auxiliary motherboard. In an optional implementation, determining the auxiliary motherboard from the second motherboard based on motherboard priority may include: determining the auxiliary motherboard from the second motherboard based on motherboard priority and motherboard status. Optionally, if the motherboard priority of the second motherboard is equal to a preset priority and is in a normal condition, then the second motherboard is determined as the auxiliary motherboard; or; if the motherboard priority of the second motherboard is equal to the preset priority and is in an abnormal condition, then the motherboard in the second motherboard with a motherboard priority equal to (preset priority - 1) is determined as the auxiliary motherboard.

[0113] Optionally, the auxiliary motherboard can refer to a motherboard in a cascaded motherboard system that assists the first motherboard in performing calculations after the first motherboard's computing load becomes overloaded.

[0114] Optionally, auxiliary operation instructions can be sent from the first chip on the first motherboard to the auxiliary chip on the auxiliary motherboard via the GE bus. After receiving the auxiliary operation instructions, the auxiliary chip can control the auxiliary operation unit to perform operations on the auxiliary operation data, that is, to perform operations on the auxiliary operation data cached in the DRAM connected to the FPGA corresponding to the auxiliary chip. Optionally, when the auxiliary chip is also in an abnormal state, a new auxiliary chip can be determined on the second motherboard, and data processing and operation can continue to be performed based on the newly determined auxiliary chip.

[0115] In one optional implementation, when the first motherboard is in a normal state, the first chip can send the first processed data processed by the first processing unit to the processing units of each chip on the second motherboard, so that the processed data of all chips are in a mirror backup relationship. If all chips on the first motherboard are in an abnormal or faulty state, a takeover motherboard can be determined according to the motherboard priority, and a takeover chip can be determined from the takeover motherboard according to the chip priority, serving as the newly determined primary chip; simultaneously, the takeover motherboard takes over the processing work from the first motherboard. The specific workflow of the takeover chip in the takeover motherboard can be found in the description of step S103, and will not be repeated here.

[0116] In this embodiment of the application, by interconnecting the first motherboard and one or more second motherboards, and determining the target chip from the second motherboard to perform standby or auxiliary computing functions according to a preset priority, without having to enable all chips on the entire second motherboard, the minimum number of chips can be enabled while ensuring system functionality, and computing power redundancy can be avoided to the greatest extent.

[0117] Accordingly, this application provides a data processing apparatus. Figure 6 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Figure 6 As illustrated, the data processing device 600 for the first chip may include:

[0118] The first transmitting unit 601 is used to transmit first processed data processed by the first processing unit of the first chip to the second chip. Optionally, the second chip and the first chip are chips on the first motherboard, and the chip priority of the second chip is lower than that of the first chip.

[0119] The second sending unit 602 is used to send a first synchronization instruction to the second chip. Optionally, the first synchronization instruction includes first status information of the first processing unit processing the first processed data, and the first synchronization instruction is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information.

[0120] The third sending unit 603 is configured to send a takeover processing instruction to the second chip if an abnormal state is detected in the first chip. Optionally, the takeover processing instruction instructs the takeover chip in the second chip to send a second synchronization instruction to the non-takeover chip in the second chip. The second synchronization instruction includes takeover status information of the third processing unit of the takeover chip processing the first processed data, and instructs the fourth processing unit of the non-takeover chip to process the first processed data according to the takeover status information. The takeover chip can be determined from the second chip based on chip priority.

[0121] Optionally, the first chip and the second chip are system chips connected via a high-speed serial computer expansion bus interface.

[0122] Optionally, the device further includes a fourth transmitting unit, used to send a takeover operation instruction to the takeover chip after sending a takeover processing instruction to the second chip; the takeover operation instruction includes first operation data calculated by the first operation unit of the first chip, and the takeover operation instruction is used to instruct the takeover operation unit of the takeover chip to calculate the first operation data.

[0123] Optionally, the first chip and the second chip share the same computing cache space. The fourth sending unit is used to send a takeover computing instruction to the takeover chip after sending a takeover processing instruction to the second chip. The takeover computing instruction is used to instruct the takeover chip to read the first computing data processed by the first computing unit of the first chip from the computing cache space, and to instruct the takeover computing unit of the takeover chip to process the first computing data.

[0124] Optionally, the device further includes a fifth transmitting unit, configured to, after sending a first synchronization instruction to the second chip, if an overload is detected in the first processing unit of the first chip, determine auxiliary processing data from the first processing data; and send an auxiliary processing instruction to the second chip; the auxiliary processing instruction includes auxiliary processing data, and the auxiliary processing instruction is used to instruct the auxiliary processing unit of the auxiliary chip to process the auxiliary processing data. The auxiliary chip is determined from the second chip according to the chip priority.

[0125] Optionally, the device further includes a sixth transmitting unit, used to send a supervisory operation instruction to the supervisory chip of the second motherboard if, after sending a takeover processing instruction to the takeover chip, both the first chip and the second chip are detected to be in an abnormal state; the supervisory operation instruction includes first operation data processed by the first operation unit of the first chip, and the supervisory operation instruction is used to instruct the supervisory operation unit of the supervisory chip to process the first operation data. The supervisory chip is determined from the takeover motherboard according to chip priority, and the takeover motherboard is determined from the second motherboard according to motherboard priority; the second motherboard and the first motherboard are connected.

[0126] Optionally, the device further includes a seventh transmitting unit, used to send a data transfer instruction to a reference chip after sending a takeover processing instruction to the takeover chip; the data transfer instruction is used to instruct the reference chip to determine auxiliary calculation data from the reference calculation data calculated by the reference calculation unit, and send the auxiliary calculation data to the auxiliary chip; wherein, the chip priority of the reference chip is lower than a preset priority; and to send an auxiliary calculation instruction to the auxiliary chip of the second motherboard; the auxiliary calculation instruction is used to instruct the auxiliary calculation unit of the auxiliary chip to calculate the auxiliary calculation data; wherein, the second motherboard is connected to the first motherboard, the auxiliary chip determines the data from the auxiliary motherboard according to the chip priority, and the auxiliary motherboard determines the data from the second motherboard according to the motherboard priority.

[0127] The device and method embodiments of this application may be based on the same concept.

[0128] Accordingly, embodiments of this application also provide a data processing system. Figure 7a This is a first structural schematic diagram of a data processing system 700a provided in an embodiment of this application.

[0129] like Figure 7a As illustrated, optionally, the data processing system 700a may include a first chip 710a, a second chip, and FPGAs corresponding to the first chip 710a and the second chip, respectively. The second chip may include a control chip 720a and a non-control chip 730a. The FPGA corresponding to the first chip 710a may be FPGA1 711a, the FPGA corresponding to the control chip 720a may be 721a, and the FPGA corresponding to the non-control chip may be 731a.

[0130] Optionally, the first chip 710a, the takeover chip 720a, and the non-takeover chip 730a can be SoC chips connected to the first motherboard via a PCIe interface. The chip priority of the takeover chip 720a and the non-takeover chip 730a can be lower than that of the first chip 710a. Each of the first chip 710a, the takeover chip 720a, or the non-takeover chip 730a can be connected to a matching FPGA. The FPGA can be used for temporary storage of data processed by the chip, and can also be used as a data transmission and reception path when the chip communicates with other chips, and for temporary storage of transmitted and received data. Optionally, the first chip 710a can be connected to FPGA1 711, the takeover chip 720a can be connected to FPGA2 721, and the non-takeover chip 730a can be connected to FPGA3 731.

[0131] In one alternative implementation, the first chip 710a and the chip including the takeover chip 720a and the non-takeover chip 730a can be automotive chips used for vehicle-related data processing and computation, such as autonomous driving.

[0132] Optionally, the first chip 710a can be used to send first processed data processed by the first processing unit of the first chip 710a to the second chip; send a first synchronization instruction to the second chip; the first synchronization instruction includes first status information of the first processing unit processing the first processed data, and the first synchronization instruction is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information; if an abnormal state is detected in the first chip, a takeover processing instruction is sent to the second chip. After receiving the takeover processing instruction, the chip in the second chip can determine itself as the takeover chip 720a or the non-takeover chip 730a based on its chip priority.

[0133] Optionally, after receiving the takeover processing instruction, the takeover chip 720a may send a second synchronization instruction to the non-takeover chip 730. The second synchronization instruction includes the takeover status information of the third processing unit of the takeover chip 720a in processing the first processing data. The second synchronization instruction is used to instruct the fourth processing unit of the non-takeover chip 730 to process the first processing data according to the takeover status information.

[0134] The following is based on Figure 7b This application further describes a data processing system provided by an embodiment.

[0135] Figure 7b This is a second structural schematic diagram of a data processing system 700b provided in an embodiment of this application.

[0136] like Figure 7b As illustrated, optionally, the data processing system 700b may include a first chip 710b, a second chip, FPGAs corresponding to the first chip 710b and the second chip respectively, and DRAMs connected to each FPGA respectively. The second chip may include a takeover chip 720b and a non-takeover chip 730b. The FPGA corresponding to the first chip 710b may be FPGA1 711b, the FPGA corresponding to the takeover chip 720b may be 721b, and the FPGA corresponding to the non-takeover chip may be 731b. DRAM1 712b may be connected to FPGA1 711b, DRAM2 722b may be connected to FPGA2 721b, and DRAM3 732b may be connected to FPGA3 731b.

[0137] Optionally, the computational data processed by the computing units of the first chip 710b, the takeover chip 720b, and the non-takeover chip 730b, including data such as video, millimeter-wave radar, and lidar, can be cached via DRAM1 712b, DRAM2 732b, and DRAM3 732b corresponding to the first chip 710b, the takeover chip 720b, and the non-takeover chip 730b. Specifically, the first computational data processed by the first chip 710b can be stored in DRAM1 712b. In an embodiment where the first chip 710b malfunctions, the first computational data can be sent to the takeover chip 720b via the PCIe bus, and after receiving the first computational data, the takeover chip 720b can cache the first computational data in DRAM 722b and perform computation on the first computational data. In an embodiment where both the first chip 710b and the takeover chip 720b are overloaded, the non-takeover chip 730b can be identified as an auxiliary chip. Auxiliary computing data can be sent to the non-takeover chip 730b via the PCIe bus. After receiving the auxiliary computing data, the non-takeover chip 730b can cache the auxiliary computing data in DRAM 732b and perform calculations on the first computing data.

[0138] The details of the first chip 710b, the control chip 720b, the non-control chip 730b, and FPGA1 711b, FPGA2 721b, and FPGA3 731b can be found in the above text. Figure 7a The descriptions of the first chip 710a, the control chip 720a, the non-control chip 730a, and FPGA1 711a, FPGA2 721A, and FPGA3 731a will not be repeated here.

[0139] It is important to note that, such as Figure 7a and Figure 7b The system architecture illustrated is merely an example. In other alternative embodiments, the data processing system provided in this application may also include... Figure 7a or Figure 7b One or more of each of the structures illustrated.

[0140] Figure 7c This is a third structural schematic diagram of a data processing system 700c provided in an embodiment of this application.

[0141] like Figure 7a or Figure 7b The system can be extended beyond a single motherboard. Through the use of Fabric switching meshes with higher switching capacity, and GE or 10GE SERDE buses, such as XAUI, inter-board data communication and computing power scheduling can be achieved. Optionally, in Figure 7cThe diagram shows multiple motherboard types, each of which may include the following internal structures: Figure 7a or Figure 7b The diagram shows the internal structure of the plate.

[0142] As shown in Figure 7, motherboards 0 through n can be configured according to certain strategies. Motherboard 0 can be designated as the current primary controller, and SoC0 can be the primary SoC of the primary controller. Motherboards 1 through n can be designated as backup controllers, with their cascaded SoC chips serving as primary and backup SoC chips in the backup controllers according to chip priority. Optionally, the motherboards can be interconnected via high-speed buses such as GEserdes or 10GXAUI to form a SoC computing power cluster with unified scheduling based on a hierarchical strategy. If the primary motherboard or primary SoC malfunctions, the next-level motherboard or SoC will take over according to a preset strategy, ensuring the cascaded motherboard system always maintains normal operation.

[0143] The system and method embodiments of this application may be based on the same concept.

[0144] Accordingly, this disclosure also provides an electronic device, which includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The processor loads and executes the at least one instruction, at least one program, code set, or instruction set to implement the above-described data processing method.

[0145] The methods and embodiments provided in this application can be executed on a computer terminal, server, or similar computing device. Taking running on a server as an example, Figure 8 This is a hardware structure block diagram of the server for the data processing method provided in this application embodiment. For example... Figure 8As shown, the server 800 can vary significantly due to different configurations or performance. It may include one or more Central Processing Units (CPUs) 810 (CPUs 810 may include, but are not limited to, microprocessors (MCUs) or programmable logic devices (FPGAs), a memory 830 for storing data, and one or more storage media 820 (e.g., one or more mass storage devices) for storing application programs 823 or data 822. The memory 830 and storage media 820 may be temporary or persistent storage. The program stored in the storage media 820 may include one or more modules, each module may include a series of instruction operations on the server. Furthermore, the CPU 810 may be configured to communicate with the storage media 820 and execute the series of instruction operations stored in the storage media 820 on the server 800. Server 800 may also include one or more power supplies 850, one or more wired or wireless network interfaces 850, one or more input / output interfaces 840, and / or one or more operating systems 821, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0146] The input / output interface 840 can be used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of server 800. In one example, the input / output interface 840 includes a network interface controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the input / output interface 840 may be a radio frequency (RF) module for wireless communication with the Internet.

[0147] Those skilled in the art will understand that Figure 8 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, server 800 may also include... Figure 8 The more or fewer components shown, or having the same Figure 8 The different configurations shown.

[0148] This application provides a storage medium that can be located in a server to store at least one instruction, at least one program, code set, or instruction set related to the data processing method in the method embodiment. The at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the above-described data processing method.

[0149] Optionally, in this embodiment, the storage medium may be located at at least one of the multiple network servers in a computer network. Alternatively, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), portable hard drives, magnetic disks, or optical disks.

[0150] In this invention, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the connection within two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0151] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, while this specification describes specific embodiments, other embodiments are also within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in the order shown in different embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require a specific order or sequence of connections to achieve the desired results; in some implementations, parallel processing of multiple tasks is possible or may be advantageous.

[0152] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of the apparatus / system are relatively simple in description because they are based on similarity to the method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0153] The above are preferred embodiments of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A data processing method, characterized in that, The method includes: The first processed data processed by the first processing unit of the first chip is sent to the second chip; the second chip and the first chip are chips on the first motherboard, and the chip priority of the second chip is lower than that of the first chip; Send a first synchronization instruction to the second chip; the first synchronization instruction includes first status information of the first processing unit processing the first processed data, and the first synchronization instruction is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information. If the first chip is detected to be in an abnormal state, a takeover processing instruction is sent to the second chip. The takeover processing instruction is used to instruct the takeover chip in the second chip to send a second synchronization instruction to the non-takeover chip in the second chip. The second synchronization instruction includes the takeover status information of the third processing unit of the takeover chip processing the first processed data, and the second synchronization instruction is used to instruct the fourth processing unit of the non-takeover chip to process the first processed data according to the takeover status information. The takeover chip is determined from the second chip according to the chip priority.

2. The data processing method according to claim 1, characterized in that, The first chip and the second chip are connected via a high-speed serial computer expansion bus interface.

3. The data processing method according to claim 1, characterized in that, After sending the takeover processing command to the second chip, the method further includes: A takeover operation instruction is sent to the takeover chip; the takeover operation instruction includes first operation data calculated by the first operation unit of the first chip, and the takeover operation instruction is used to instruct the takeover operation unit of the takeover chip to calculate the first operation data.

4. The data processing method according to claim 1, characterized in that, The first chip and the second chip share a common processing cache space. After sending the takeover processing instruction to the second chip, the method further includes: A takeover operation instruction is sent to the takeover chip; the takeover operation instruction is used to instruct the takeover chip to read the first operation data operated by the first operation unit of the first chip from the operation cache space, and to instruct the takeover operation unit of the takeover chip to operate on the first operation data.

5. The data processing method according to claim 1, characterized in that, After sending the first synchronization command to the second chip, the method further includes: If the first processing unit of the first chip is detected to be overloaded, auxiliary processing data is determined from the first processing data; Send an auxiliary operation instruction to the second chip; the auxiliary operation instruction includes the auxiliary operation data, and the auxiliary operation instruction is used to instruct the auxiliary operation unit of the auxiliary chip in the second chip to operate on the auxiliary operation data; wherein, the auxiliary chip is determined from the second chip according to the chip priority.

6. The data processing method according to claim 1, characterized in that, After sending the takeover processing command to the takeover chip, the method further includes: If both the first chip and the second chip are detected to be in an abnormal state, a supervisor operation instruction is sent to the supervisor chip of the second motherboard; the supervisor operation instruction includes the first operation data processed by the first operation unit of the first chip, and the supervisor operation instruction is used to instruct the supervisor operation unit of the supervisor chip to process the first operation data; The master chip is determined from the control motherboard according to the chip priority, and the control motherboard is determined from the second motherboard according to the motherboard priority; the second motherboard and the first motherboard are connected.

7. The data processing method according to claim 1, characterized in that, After sending the takeover processing command to the takeover chip, the method further includes: If an overload is detected in the reference arithmetic unit of the reference chip in the second chip, a data transfer instruction is sent to the reference chip; the data transfer instruction is used to instruct the reference chip to determine auxiliary arithmetic data from the reference arithmetic data processed by the reference arithmetic unit, and to send the auxiliary arithmetic data to the auxiliary chip; wherein, the chip priority of the reference chip is lower than the preset priority; An auxiliary operation instruction is sent to the auxiliary chip of the second motherboard; the auxiliary operation instruction is used to instruct the auxiliary operation unit of the auxiliary chip to perform the auxiliary operation data; wherein, the second motherboard and the first motherboard are connected, the auxiliary chip is determined from the auxiliary motherboard according to the chip priority, and the auxiliary motherboard is determined from the second motherboard according to the motherboard priority.

8. A data processing apparatus, characterized in that, The device includes: The first transmitting unit is used to transmit first processed data processed by the first processing unit of the first chip to the second chip; The second chip and the first chip are chips on the first motherboard, and the chip priority of the second chip is lower than that of the first chip. The second sending unit is used to send a first synchronization instruction to the second chip; the first synchronization instruction includes first status information of the first processing unit processing the first processed data, and the first synchronization instruction is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information. The third sending unit is configured to send a takeover processing instruction to the second chip if the first chip is detected to be in an abnormal state. The takeover processing instruction is configured to instruct the takeover chip in the second chip to send a second synchronization instruction to the non-takeover chip in the second chip. The second synchronization instruction includes takeover status information of the third processing unit of the takeover chip processing the first processed data, and the second synchronization instruction is configured to instruct the fourth processing unit of the non-takeover chip to process the first processed data according to the takeover status information. The takeover chip is determined from the second chip according to the chip priority.

9. A data processing system, characterized in that, The system includes a first chip and a second chip, which are connected on a first motherboard. The chip priority of the second chip is lower than that of the first chip. The first chip is used to send first processed data processed by the first processing unit of the first chip to the second chip. Send a first synchronization instruction to the second chip; the first synchronization instruction includes first status information of the first processing unit processing the first processed data, and the first synchronization instruction is used to instruct the second processing unit of the second chip to process the first processed data according to the first status information. If the first chip is detected to be in an abnormal state, a takeover processing command is sent to the second chip; The second chip includes a takeover chip and a non-takeover chip. The takeover chip is determined from the second chip according to the chip priority. The takeover chip is used to receive the takeover processing instruction and send a second synchronization instruction to the non-takeover chip. The second synchronization instruction includes takeover status information of the third processing unit of the takeover chip processing the first processed data. The second synchronization instruction is used to instruct the fourth processing unit of the non-takeover chip to process the first processed data according to the takeover status information.

10. An electronic device, characterized in that, The electronic device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the data processing method according to any one of claims 1-7.

11. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the data processing method according to any one of claims 1-7.

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