Method for predicting lifetime of power semiconductor module, terminal device, and storage medium

Abstract

The application discloses a kind of life prediction method of power semiconductor module, terminal equipment and storage medium, determine the service life influencing factor of power semiconductor device under the operation of power cycle condition;From the influence factor, construct training data set, and the data in training data set is normalized, the training data set after normalization is used to train deep convolutional neural network, and the life prediction model is obtained.The present application considers the individual and mutual influence of characteristic parameters on service life, and produces more accurate prediction results.

Description

Technical Field

[0001] This invention relates to the field of lifetime prediction for power semiconductor modules (such as IGBTs and SiC MOSFETs), and in particular to a method for lifetime prediction of power semiconductor modules, a terminal device, and a storage medium. Background Technology

[0002] Power semiconductor modules are the foundation and core of power electronic systems, leading to their widespread application in various fields. However, during long-term, repeated power cycling, factors such as load stress and external conditions can cause malfunctions and failures in their packaging structure. Solder layer failure accounts for 60% of package failures in power semiconductor modules; once the solder layer fails, the entire module's performance is affected. Therefore, rapid and accurate prediction of power semiconductor module lifespan is essential. Lifespan prediction results can aid in the design and selection of system structures and parameters according to reliability requirements during the system design phase, and can also provide advance knowledge of the power semiconductor module's operational lifespan under application conditions.

[0003] Existing lifetime prediction methods for power semiconductor modules can be categorized into physical model-based lifetime prediction methods, analytical model-based lifetime prediction methods, and data-driven lifetime prediction methods. Analytical model-based lifetime prediction methods calculate the number of failure cycles N based on various factors such as temperature fluctuations, average junction temperature, frequency, and bond wire current. f The main problem with estimating module lifetime is its high dependence on junction temperature measurements. Physical model-based lifetime prediction methods do not require knowledge of temperature cycling parameters; instead, they rely on the stress-strain deformation failure mechanism within the module. However, when the failure mechanism of a power semiconductor module is highly complex, model-based lifetime prediction methods become inapplicable. In contrast, data-driven lifetime prediction methods require neither prior knowledge nor explicit mathematical forms to capture complex solder layer degradation patterns. They are also highly versatile, quick to deploy, and accurate, simply requiring the extracted solder layer health characteristics to be input into a data-driven model to output the power semiconductor module's lifetime. Therefore, data-driven lifetime prediction methods are superior to those based on physical or analytical models.

[0004] Current accelerated aging methods mainly include power cycling and thermal cycling. Power cycling involves applying periodic heating power to the power semiconductor module to change its temperature, allowing it to cool between two heating pulses. Due to internal heating causing uneven temperature distribution, similar to real-world application conditions, a significant temperature gradient forms within the structure, depending on the thermal resistance of different layers and the applied heating power. Thermal cycling subjectes the power semiconductor module to a wide range of temperature fluctuations. The module itself does not consume power to generate heat, requiring a sufficiently long cycle time. After reaching a steady state, the module's temperature distribution is uniform throughout its entire structure. Currently, reliability research is trending towards condition monitoring, lifetime prediction, and active thermal management, requiring consideration of actual operating conditions; therefore, power cycling has become a research hotspot.

[0005] Solder layer size, chip size, solder layer material composition, module operating conditions, and other interrelated factors can lead to solder layer failure under long-term power cycling. All these parameters affect module lifespan and cause performance degradation to varying degrees. Because multiple factors are involved, incorporating all factors into a single lifetime prediction model is difficult. Existing lifetime prediction methods typically use a different prediction model for each power semiconductor module, making accurate lifetime prediction for different power semiconductor modules over a short period of time extremely complex. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for predicting the lifetime of power semiconductor modules, a terminal device and a storage medium, in order to address the shortcomings of the existing technology and solve the problem of poor universality of the existing prediction models.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a method for predicting the lifetime of a power semiconductor module, comprising the following steps:

[0008] Identify the factors affecting the lifespan of power semiconductor devices under power cycling conditions; these factors include junction temperature fluctuations during the aging process of the power semiconductor device. The highest junction temperature during the aging process of power semiconductor devices Collector injection current Circuit turn-on time Shutdown time The chip solder layer and the three-dimensional dimensions of the chip, the mass density, coefficient of thermal expansion, melting point, Young's modulus, Poisson's ratio, thermal conductivity and specific heat capacity of the chip layer, chip solder layer and copper layer on DBC;

[0009] A training dataset is constructed based on the aforementioned influencing factors, and the data in the training dataset is normalized. A deep convolutional neural network is then trained using the normalized training dataset to obtain a lifespan prediction model.

[0010] This invention considers the following behaviors to determine influencing factors: Mismatch in thermal expansion coefficients between different layers within the module leads to alternating thermomechanical stress and accumulated inelastic strain in the solder layer during power cycling. This inelastic strain causes crack initiation and propagation in the solder, ultimately leading to module failure. During the dwell time at the highest junction temperature, the solder layer undergoes both time-invariant plastic deformation and time-varying creep deformation. These two types of inelastic strain accumulate in each power cycle, and fatigue failure occurs when the accumulated inelastic strain reaches a certain level. The cooling phase causes a sharp change in stress, which provides conditions for the formation of fatigue cracks in the solder interconnects. Therefore, the longer the cooling time and turn-on time, the higher the point at which stress changes begin, the greater the stress change, and the faster the module fails. A larger solder volume results in greater elastic and inelastic strain in the solder material, leading to accelerated degradation. Young's modulus and Poisson's ratio reflect a solid material's resistance to deformation and lateral deformation, respectively; therefore, they are also factors influencing material deformation. Thermal conductivity decreases as voids appear in the solder layer, reducing heat transfer efficiency. These voids cause uneven heat distribution within the chip, leading to hot spots on the chip surface and consequently, an increase in junction temperature. Specific heat capacity is the amount of heat absorbed or released per unit mass of material when its temperature changes by a unit amount; the higher the solder density, the smaller the temperature rise required to absorb the same amount of heat. Therefore, this invention identifies the influencing factor as junction temperature fluctuations during the aging process of power semiconductor devices. The highest junction temperature during the aging process of power semiconductor devices Collector injection current Circuit turn-on time Shutdown time The invention considers the three-dimensional dimensions of the chip solder layer and the chip itself, as well as the mass density, coefficient of thermal expansion, melting point, Young's modulus, Poisson's ratio, thermal conductivity, and specific heat capacity of the chip layer, chip solder layer, and copper layer on the DBC. This invention fully considers the combined influence of various factors on the lifespan of power semiconductor modules, improving the versatility of the prediction model.

[0011] In order to further improve the accuracy of the lifespan prediction model, the present invention further includes: obtaining a test dataset and using the test dataset to test the lifespan prediction model.

[0012] Different features often have different dimensions, resulting in significant differences in their numerical values. Therefore, to eliminate the potential impact of differences in dimensions and value ranges between features, data normalization is necessary. The specific implementation process for normalizing data in the training dataset includes: converting the data in the training dataset into a two-dimensional image composed of pixels, and then normalizing the two-dimensional image.

[0013] The formula for the normalization process is: [a, b] is a defined range where a and b are constants, and b > a. For the pixel values ​​of a two-dimensional image, These are the pixel values ​​after normalization.

[0014] The deep convolutional neural network includes a convolutional neural network module and a fully connected neural network module, wherein the output layer of the convolutional neural network module is connected to the input layer of the fully connected neural network module.

[0015] The convolutional neural network module includes a convolutional layer, a linear rectified layer, a pooling layer, and a flat cell connected in sequence.

[0016] The fully connected neural network module includes an input layer, three hidden layers connected in series, and an output layer.

[0017] The process of training a deep convolutional neural network using a normalized training dataset includes: using the normalized training dataset as input to the convolutional neural network module and the fully connected neural network module, updating the weights and bias parameters of the deep convolutional neural network, and training the deep convolutional neural network.

[0018] Input parameters can individually or collectively affect the lifespan of power semiconductor modules. Therefore, to fully capture both individual and collective effects of input parameters, the training set propagation process includes two paths. In the first path, the training dataset undergoes convolution, activation, and pooling before being input into a fully connected neural network, effectively representing how each input parameter collectively influences the lifespan of the power semiconductor module. In the second path, the training dataset is directly input into the fully connected neural network, representing how each input parameter individually affects the lifespan of the power semiconductor module. This invention considers both individual and collective effects of input parameters, thereby generating more accurate prediction results.

[0019] In this invention, the specific implementation process for updating the weights and bias parameters of a deep convolutional neural network includes:

[0020] Each M sets of training data is taken as a minimum batch, and the training dataset is divided into N minimum batches.

[0021] For each of the minimum batches, perform gradient updates and mean the updated gradients;

[0022] Based on the mean-normalized gradient, the Adam algorithm is used to update the weights and bias parameters of the deep convolutional neural network.

[0023] This invention combines the mini-batch gradient descent method with the Adam algorithm to effectively update network weights. On the one hand, the mini-batch gradient descent method accelerates network training and requires less memory; on the other hand, the Adam algorithm optimizes the algorithm by reducing oscillations through an exponentially weighted average of the gradients.

[0024] As an inventive concept, the present invention also provides a terminal device comprising a processor and a memory; the memory storing computer programs / instructions; the processor executing the computer programs / instructions stored in the memory; the computer programs / instructions being configured to implement the steps of the method of the present invention.

[0025] As an inventive concept, the present invention also provides a computer storage medium having a computer program / instruction stored thereon; when the computer program / instruction is executed by a processor, it implements the steps of the method of the present invention.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0027] (1) The input parameter framework (influencing factor set) proposed in this invention has good versatility and can be applied to various power semiconductor modules to complete lifetime prediction.

[0028] (2) At the algorithm level, the lifetime prediction method proposed in this invention cleverly combines the mini-batch gradient descent method with the Adam algorithm to effectively update the network weights. On the one hand, the mini-batch gradient descent method speeds up network training and requires less memory; on the other hand, the Adam algorithm optimizes the algorithm by reducing oscillations through exponential weighted averaging of gradients.

[0029] (3) The lifetime prediction method proposed in this invention is the first to propose lifetime prediction for power semiconductor modules under power cycling conditions at the prediction object level.

[0030] (4) The lifetime prediction method proposed in this invention captures the cross-correlation of feature parameters through convolution and pooling processes, thereby taking into account the individual and mutual influence of feature parameters on lifetime and producing more accurate prediction results. Attached Figure Description

[0031] Figure 1 This is a flowchart of a method according to an embodiment of the present invention;

[0032] Figure 2 It is the input parameter framework for deep convolutional neural networks;

[0033] Figure 3 This is a diagram of the algorithm framework for deep convolutional neural networks;

[0034] Figure 4 This is a comparison chart of predicted and actual values ​​according to an embodiment of the present invention. Detailed Implementation

[0035] Combination Figure 1 The main implementation steps of this invention are as follows:

[0036] S1: Determine which parameters affect the lifespan of power semiconductor devices operating under power cycling conditions;

[0037] Furthermore, in step S1, the parameters affecting the lifespan of the power semiconductor device under power cycling conditions are determined. The specific determination process is as follows:

[0038] S101: Mismatch in the coefficients of thermal expansion between different layers within the module will cause the solder layer to be subjected to alternating thermomechanical stress and cumulative inelastic strain under power cycling. Inelastic strain will cause cracks in the solder to initiate and propagate, ultimately leading to module failure.

[0039] S102: During the dwell time at the highest junction temperature, the solder layer will undergo plastic deformation that does not change with time and creep deformation that changes with time. These two types of inelastic strain will accumulate in each power cycle. When the inelastic strain accumulates to a certain extent, the solder layer will fail due to fatigue.

[0040] S103: The cooling stage causes a sharp change in stress, which provides conditions for the formation of fatigue cracks in solder interconnects. Therefore, the longer the cooling time and turn-on time, the higher the point at which stress changes begin, the greater the amount of stress change, and the faster the module fails.

[0041] S104: The larger the solder volume, the greater the elastic and inelastic strain generated in the solder material, leading to accelerated degradation. Young's modulus and Poisson's ratio reflect the solid material's resistance to deformation and lateral deformation, respectively; therefore, they are also factors affecting material deformation.

[0042] S105: Thermal conductivity decreases as voids appear in the solder layer, reducing heat transfer efficiency. These voids cause uneven heat distribution within the chip, leading to hot spots on the chip surface and consequently, an increase in junction temperature. Specific heat capacity is the amount of heat absorbed or released per unit mass of material when its temperature changes by a unit amount; the higher the solder density, the smaller the temperature rise required to absorb the same amount of heat.

[0043] S106: Therefore, the factors affecting the lifespan of power semiconductor modules include: junction temperature fluctuations during the module aging process. The highest junction temperature during the module aging process Collector injection current Circuit turn-on time Shutdown time The chip solder layer and the three-dimensional dimensions of the chip, the mass density, coefficient of thermal expansion, melting point, Young's modulus, Poisson's ratio, thermal conductivity and specific heat capacity of each layer of materials in the chip layer, chip solder layer and copper layer on DBC.

[0044] S2: Based on the parameter type determined in step S1, collect the corresponding parameters and lifespan of a certain power semiconductor module as a set of data in the training dataset;

[0045] S3: Repeat step S2 to collect 100 sets of data as the training dataset;

[0046] Furthermore, one set of training data (using Infineon's FS150R12KT4 IGBT module as an example) is shown in Table 1. Of the 100 sets of data collected, 80 sets were used for training and 20 sets were used for testing.

[0047] Table 1. Examples of a set of training datasets

[0048]

[0049] S4: Based on the input parameter framework established in step S2, collect the corresponding input parameters of a certain power semiconductor module to construct a set of data in the training dataset;

[0050] S5: Directly inputting training data into the neural network is not appropriate. Preprocessing the training data is necessary first. The minimum-maximum scaling formula should be used to scale the parameters to a predefined range of [0.2, 0.8].

[0051]

[0052] S6: Building the framework for deep convolutional neural networks;

[0053] Furthermore, the specific steps for building a deep convolutional neural network framework are as follows:

[0054] S601: Determine the basic structure of a deep convolutional neural network, including: a convolutional neural network module followed by a fully connected neural network module;

[0055] Furthermore, in step 601, the convolutional neural network module includes a convolutional layer, a linear rectified layer, a pooling layer, and a flattened unit; the deep neural network module includes an input layer (316 neurons), three hidden layers (640, 580, and 500 neurons respectively), and an output layer (one neuron).

[0056] S602: Determine the propagation path of the training dataset for the deep convolutional neural network. Input parameters can individually or collectively affect the lifespan of the power semiconductor module. Therefore, to fully capture both individual and collective effects of the input parameters, the propagation process of the training set includes two paths. In the first path, the training dataset is convolved, activated, and pooled before being input into the fully connected neural network, which is equivalent to each input parameter collectively affecting the lifespan of the power semiconductor module. In the second path, the training dataset is directly input into the fully connected neural network, which is equivalent to each input parameter individually affecting the lifespan of the power semiconductor module. This considers both individual and collective effects of the input parameters, resulting in more accurate prediction results. The constructed network framework is as follows: Figure 3 As shown.

[0057] S7: Preparations before training the network;

[0058] Furthermore, the preparatory work consists of two parts, and the specific process is as follows:

[0059] S701: Initialize network weights and momentum;

[0060] The initialization of network weights requires adjusting the convolution kernel value W. C The weights W1 between the input layer and the first hidden layer, W2 between the first hidden layer and the second hidden layer, W3 between the second hidden layer and the third hidden layer, and W4 between the third hidden layer and the output layer. o Configure the settings. C A matrix set to an 80x80 standard normal distribution; W1, W2, W3, W o The initialization is based on a uniformly distributed Xavier initialization, from Randomly selected from the options, we have:

[0061]

[0062] in, This represents the number of neurons in the current layer connected by the weighted connection line. This represents the number of neurons in the layer following the current layer that are connected by the weighted connection line.

[0063] The initial momentum can be set to zero matrices of the corresponding dimensions.

[0064] S702: Set the optimization algorithm during network training;

[0065] In this embodiment, the network weights and bias parameters are updated by combining the Mini-Batch gradient descent method with the Adam algorithm. The specific process of this combination is as follows:

[0066] (1) First, in this embodiment of the invention, a total of 100 sets of data were collected, and 80 sets of data were used as the training dataset. Mini-Batch=4 was set, that is, every 4 sets of data were a "minimum batch", and a total of 20 "minimum batches" were formed. Each time the parameters were updated, only this small portion of samples were calculated.

[0067] (2) Next, perform gradient update for each "minimum batch", gradient dw( , , , , The update formula for ) is:

[0068] ;

[0069] Where delta_x, delta1, delta2, delta3, and delta0 represent the backpropagation errors of the convolution kernel, the first hidden layer, the second hidden layer, the third hidden layer, and the output layer, respectively; y1, y2, y3, and x_flattened represent the output values ​​of the neuron nodes after data activation at the first hidden layer, the second hidden layer, the third hidden layer, and the output layer, respectively.

[0070] (3) Since Mini-Batch=4, each group of “minimum batch” will be updated four times. According to the gradient update formula given in (2), each gradient update is an accumulation process. Therefore, the gradient needs to be averaged, i.e. dw=dw / (Mini-Batch).

[0071] (4) The Adam algorithm is used to update the weights. The weight update formula is as follows:

[0072] ;

[0073] in, The learning rate; , These are the first-order and second-order exponentially shifted weighted decay rates of the gradient, respectively. It represents the number of updated steps; , gradients The first and second moments; , They are respectively , Bias correction; It is a very small number, so the denominator must be zero.

[0074] In this embodiment, the following settings are made: S8: Repeatedly train the proposed deep convolutional neural network using the processed training dataset;

[0075] In this embodiment, we set up 10 repeated training iterations. The detailed training steps include: data association, data flattening, data transfer in the fully connected neural network, error backpropagation, and weight update. Furthermore, the specific process of training the deep convolutional neural network is as follows:

[0076] S801: The data association includes three processes: convolution, data activation, and downsampling (pooling);

[0077] (1) Convolution process

[0078] The convolution process involves performing a convolution operation between the convolution kernel and the two-dimensional image of the input parameters. Specifically, the convolution kernel slides to all positions on the two-dimensional image of the input parameters, and at each position, the inner product of the pixels in the two-dimensional image and the pixels in the convolution kernel is calculated. In this embodiment, the size of the convolution kernel is set to 3*3*80, meaning the kernel has 80 channels and consists of several two-dimensional images composed of 3*3 pixels. The size of the two-dimensional image of the input parameters is set to 8 rows and 4 columns. The stride is 1. The calculation formula is:

[0079]

[0080] Among them, W C The convolution kernel matrix, The input parameter is a two-dimensional image matrix.

[0081] It should be noted that:

[0082] 1. Local Connectivity: In this embodiment, during convolution, neurons are locally connected in the spatial dimension (i.e., each neuron in the convolution kernel is only connected to a portion of the input neuron's region), but fully connected in the depth dimension (i.e., every neuron in each channel is connected to the input neuron). For the two-dimensional image itself, local pixel correlations are also strong. This local connectivity ensures that the learned convolution kernel has the strongest response to local input features.

[0083] 2. Weight sharing: The convolution kernel used in the convolution operation is shared, and all kernels have a weight of W. CThis significantly reduces the number of parameters. The local connectivity and weight sharing in convolutional layers greatly reduce the number of parameters that need to be learned, which is also beneficial for training large-scale convolutional neural networks.

[0084] (2) Data activation

[0085] Data activation involves applying a non-linear mapping to the output of the convolution process. In this embodiment, the ReLU function (a non-saturating linear unit) is used, and the corresponding calculation formula is as follows:

[0086]

[0087] The ReLU function accelerates network training, reduces computational complexity, is more robust to various disturbances, and avoids the gradient vanishing problem to some extent.

[0088] (3) Downsampling

[0089] The main function of downsampling is to reduce the computational load by decreasing the size of the parameters, and it can also control overfitting to some extent. In this embodiment, mean pooling is used, which takes the average of four points. The corresponding calculation formula is:

[0090]

[0091] S902: Data flattening;

[0092] In this embodiment, the input parameter matrix is ​​processed through convolution, data activation, and downsampling (pooling) in the first path of the deep convolutional network, resulting in an 80-channel 3x1 matrix as the output. The input parameter matrix is ​​then directly fed into the fully connected neural network through the second path of the deep convolutional network. Since the fully connected neural network requires a vector as input, both inputs need to undergo dimensionality processing, i.e., flattened into a vector before being input into the fully connected neural network.

[0093] S903: Data transfer in a fully connected neural network;

[0094] S904: Error backpropagation;

[0095] In the backpropagation of the error, the loss function is the sum of squared error function, and the corresponding formula is:

[0096]

[0097] S905: Weight update;

[0098] S10: After training is complete, the accuracy of the training results needs to be checked. The remaining 20 sets of data are used as the test set and input into the trained network to output the corresponding prediction results.

[0099] The correlation coefficient and root mean square error are used to evaluate the prediction performance. With root mean square error The expressions are as follows:

[0100]

[0101] in, , , These are the average of the predicted value, the actual value, and the actual value, respectively. The value is between [0 1] A value of 1 indicates a perfect fit.

[0102] S11: Determine whether to perform accuracy improvement. If the network trained in this embodiment of the invention can accurately predict the lifespan of a power semiconductor module under a certain operating condition, then no accuracy improvement is needed; otherwise, the algorithm needs to be improved, and improvements can be made from aspects such as network structure and weight update algorithm. Figure 4 A comparison chart of the predicted results and actual values ​​of the method in this embodiment of the invention is provided, along with the correlation coefficient of the test results. This demonstrates that the method in the embodiments of the present invention achieves perfect prediction to a certain extent.

[0103] It should also be noted that the method proposed in this embodiment of the invention is universal, that is, after the network is trained, it can predict the lifetime of power semiconductor modules under any operating condition, only requiring the determination of operating condition parameters, material parameters, and size parameters.

[0104] The embodiments of the present invention have been described in detail above, but the content described is only a preferred embodiment of the present invention and should not be considered as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should still fall within the scope of this patent. After reading this invention, any modifications of the present invention in various equivalent forms by those skilled in the art fall within the scope defined by the appended claims. Unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

Claims

1. A method for predicting the lifetime of a power semiconductor module, characterized in that, Includes the following steps: Identify the factors affecting the lifespan of power semiconductor devices under power cycling conditions; these factors include junction temperature fluctuations during the aging process of the power semiconductor device. The highest junction temperature during the aging process of power semiconductor devices Collector injection current Circuit turn-on time Shutdown time The chip solder layer and the three-dimensional dimensions of the chip, the mass density, coefficient of thermal expansion, melting point, Young's modulus, Poisson's ratio, thermal conductivity and specific heat capacity of the chip layer, chip solder layer and copper layer on DBC; A training dataset is constructed based on the aforementioned influencing factors, and the data in the training dataset is normalized. A deep convolutional neural network is then trained using the normalized training dataset to obtain a lifespan prediction model. The deep convolutional neural network includes a convolutional neural network module and a fully connected neural network module. The output layer of the convolutional neural network module is connected to the input layer of the fully connected neural network module. The convolutional neural network module includes a convolutional layer, a linear rectified layer, a pooling layer, and a flattened unit connected in sequence. The fully connected neural network module includes an input layer, three hidden layers connected in series, and an output layer connected in sequence. The process of training a deep convolutional neural network using a normalized training dataset includes: using the normalized training dataset as input to the convolutional neural network module and the fully connected neural network module, updating the weights and bias parameters of the deep convolutional neural network, and training the deep convolutional neural network; setting the propagation process of the training dataset to include two paths, the first path inputting the training dataset into the fully connected neural network after convolution, activation, and pooling; the second path directly inputting the training dataset into the fully connected neural network.

2. The lifespan prediction method for power semiconductor modules according to claim 1, characterized in that, The specific implementation process of normalizing the data in the training dataset includes: converting the data in the training dataset into a two-dimensional image composed of pixels, and normalizing the two-dimensional image.

3. The lifespan prediction method for power semiconductor modules according to claim 2, characterized in that, The formula for the normalization process is: [a, b] is a defined range where a and b are constants, and b > a. For the pixel values ​​of a two-dimensional image, These are the pixel values ​​after normalization.

4. The lifespan prediction method for power semiconductor modules according to claim 1, characterized in that, The specific implementation process of updating the weights and bias parameters of a deep convolutional neural network includes: Each M sets of training data is used as a minimum batch, and the training dataset is divided into N minimum batches. For each of the minimum batches, perform gradient updates and mean the updated gradients; Based on the mean-normalized gradient, the Adam algorithm is used to update the weights and bias parameters of the deep convolutional neural network.

5. The lifespan prediction method for power semiconductor modules according to claim 1, characterized in that, Also includes: Obtain a test dataset and use the test dataset to test the lifetime prediction model.

6. A terminal device, characterized in that, It includes a processor and a memory; the memory stores computer programs / instructions; the processor executes the computer programs / instructions stored in the memory; the computer programs / instructions are configured to implement the steps of the method according to any one of claims 1 to 5.

7. A computer storage medium having a computer program / instruction stored thereon; characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1 to 5.

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