Treatment device and method for conditioning a gas stream

Abstract

The present disclosure relates to processing apparatuses and methods for regulating gas flow. One method includes initiating a gas flow of a first gas parallel to a wall of an interface module to create an air curtain across an opening defined in the wall. The method includes moving an interface door to uncover the opening, wherein the air curtain prevents a second gas within the interface module from passing through the opening. The method includes transferring a semiconductor wafer through the opening and moving the interface door to cover the opening. The method includes discontinuing the gas flow of the first gas after moving the interface door to cover the opening.

Description

Technical Field

[0001] This disclosure relates to processing apparatus and methods for regulating gas flow. Background Technology

[0002] Typically, material handling (e.g., wafer handling during semiconductor manufacturing) utilizes one or more chambers. For example, a storage chamber stores wafers, a transfer chamber transports wafers between chambers, and a processing chamber is where wafers are processed. During semiconductor manufacturing, wafers often undergo multiple manufacturing processes in different processing chambers. Summary of the Invention

[0003] According to one aspect of this disclosure, a method for regulating gas flow is provided, comprising: initiating a gas flow of a first gas parallel to a wall of an interface module to create an air curtain across an opening defined in the wall; moving an interface gate to expose the opening, wherein the air curtain prevents a second gas within the interface module from passing through the opening; transferring a semiconductor wafer through the opening; moving the interface gate to cover the opening; and terminating the gas flow of the first gas after moving the interface gate to cover the opening.

[0004] According to one aspect of this disclosure, a method for regulating a gas flow is provided, comprising: supplying a gas flow into a housing disposed within a transfer chamber of an interface module for transferring a semiconductor wafer; passing the gas flow through a first layer in the housing, wherein the first layer defines a plurality of first apertures; and after passing the gas flow through the first layer, passing the gas flow through a second layer in the housing, wherein the second layer defines a plurality of polygonal second apertures to create a laminar air curtain flowing out of the housing from the gas flow within the housing.

[0005] According to one aspect of this disclosure, an apparatus for regulating a gas flow is provided, comprising: a memory including processor-executable instructions; and one or more processors operatively coupled to the memory, performing the following operations upon execution of the processor-executable instructions: detecting a front-opening unified pod (FOUP) docking with a loading port adjacent to an interface module; controlling a gas supply source to initiate a gas flow, wherein the gas flow creates a laminar air curtain across an opening defined in the interface module; after controlling the gas supply source to initiate the gas flow, controlling an interface gate of the interface module adjacent to the FOUP to expose the opening; controlling an operating machine to transfer a semiconductor wafer between the FOUP and the interface module through the opening; controlling the interface gate to cover the opening; and after controlling the interface gate to cover the opening, controlling the gas supply source to stop the gas flow. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features can be increased or decreased arbitrarily for ease of discussion.

[0007] Figure 1A This is a side view of a processing apparatus according to some embodiments, and Figure 1B This is a front view of a processing apparatus according to some embodiments.

[0008] Figure 2 This is a perspective view of a processing apparatus according to some embodiments.

[0009] Figure 3A This is a perspective view of a processing apparatus according to some embodiments, and Figure 3B This is a schematic front view of a processing apparatus according to some embodiments.

[0010] Figure 4 This is a schematic front view of a processing apparatus according to some embodiments.

[0011] Figures 5A-5D This is a schematic diagram of a processing apparatus according to some embodiments.

[0012] Figure 6 This is a detailed schematic diagram of a processing apparatus according to some embodiments.

[0013] Figures 7A-7G This is a schematic diagram of a processing apparatus according to some embodiments.

[0014] Figure 8 This is a perspective view of a processing apparatus according to some embodiments.

[0015] Figure 9 This is a perspective view of a processing apparatus according to some embodiments.

[0016] Figure 10 These are illustrations of example components of a device according to some embodiments.

[0017] Figure 11 Example methods according to some embodiments are shown.

[0018] Figure 12 Example methods according to some embodiments are shown.

[0019] Figure 13 Example methods according to some embodiments are shown. Detailed Implementation

[0020] The following disclosure provides several different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, spatially related terms (e.g., "below," "below," "down," "above," "up") may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein will be interpreted accordingly. Additionally, relational terms such as "connected to," "adjacent to," and "coupled to" may be used herein to describe both direct and indirect relationships. "Direct" connection, adjacency, or coupling may refer to a relationship without intermediate components, devices, or structures. "Indirect" connection, adjacency, or coupling may refer to a relationship with intermediate components, devices, or structures.

[0022] During semiconductor device manufacturing, semiconductor wafers undergo various processes (e.g., wet etching, dry etching, ashing, stripping, metal plating, and / or chemical mechanical polishing) in different processing chambers. During the intervals between these processes, wafers are typically batched and temporarily stored in wafer storage devices (also known as carriers). Each batch of wafers can be stacked vertically within the wafer storage device and supported by a support frame with multiple individual wafer racks or wafer bays within the device. These wafer storage devices, often referred to as front-opening unified pods (FOUPs), provide a humidity- and contaminant-controlled environment to maintain the integrity of the wafer and / or the fabrication layers on and within the wafer. These wafer storage devices are typically kept in an ultra-clean environment.

[0023] Moisture from other processing modules (e.g., interface modules) may enter the wafer storage device during wafer docking and loading between modules. Interface modules (e.g., facility interface or device front-end module (EFEM)) may have different levels of moisture or contaminants than the wafer storage device. Moisture can enter the wafer storage device and react with residual materials on the wafer (e.g., residual materials from different wafer processes), creating defects in the fabrication layers on the wafer. These defects can lead to defective semiconductor devices and thus production yield losses. For example, the wafer may undergo an etching process using tetrafluoromethane (CF4) as an etchant and may have perovskite ((NH4)2SiF6) as residual material. Perovskite can react with moisture in the form of water vapor to produce ammonia (NH3) and hydrofluoric acid (HF), which can remove some of the fabrication layer material from the wafer and create defects in the fabrication layers. In another example, moisture and / or oxygen can cause oxidation or loss of copper on the wafer stored within the wafer storage device.

[0024] Wafers can undergo additional processes and / or technologies to reduce size, increase yield, etc. For example, wafers can be washed with water between manufacturing operations, which can introduce residual moisture on or around the wafer. This residual moisture, in the form of water vapor, can be transferred to the environment of the interface module and subsequently into connected wafer storage devices. Multiple wafer storage devices corresponding to wafers at different processing stages can be connected to the interface module and provide a source for moisture transfer.

[0025] In addition to moisture, contaminants in the form of particulate matter and / or chemical gases from the interface module can also enter the wafer memory device and may lead to defective wafers, resulting in defective semiconductor devices. These contaminants (which may originate from chemicals discharged from the manufacturing layer material) can adhere to the inner surface of the interface module and are subsequently transferred back to the wafer during subsequent process operations as the wafer is removed and returned to the wafer memory device.

[0026] This disclosure provides example processing apparatus and methods configured to suppress and / or reduce the entry of moisture and / or contaminants present in an interface module into a wafer memory device or other connectivity module. In some embodiments, the example processing apparatus for a wafer includes a flow conditioning unit located above an opening defined in a wall. The flow conditioning unit may include one or more gas nozzles and a first layer at a first distance below the gas nozzles. The first layer may define a first aperture having a first aperture size. A second layer may be disposed at a second distance below the one or more gas nozzles and define a second aperture having a second aperture size greater than the first aperture size. The one or more gas nozzles may provide a gas flow to the first layer, and the first layer may disperse the gas flow directed to the second layer. The second layer may then guide the gas flow across the opening defined in the wall in a direction parallel to the wall.

[0027] The example processing apparatus and methods disclosed herein suppress and / or reduce the entry of moisture and / or contaminants present in the interface module into one or more connected wafer memory devices, and also provide air barriers to maintain environmental separation between the interface module and the one or more wafer memory devices. As a result, these example processing apparatus and methods improve the throughput of processed wafers by improving the environment of the wafer memory devices, and improve production yield due to the reduction of defective wafers. In some embodiments, openings defined in the walls of the transfer chamber provide vertical air curtains to maintain environmental separation.

[0028] Figure 1A This is a schematic diagram of a processing apparatus 100 according to some embodiments. Figure 1B It is according to some embodiments along Figure 1A The diagram shows a processing apparatus 100 as captured by line BB. In some embodiments, the processing apparatus 100 includes a flow conditioning unit 102 within a module (e.g., interface module 104) for processing wafer 106. In some embodiments, the processing apparatus 100 includes one or more processing devices and / or modules, such as wafer storage device 108, load port 110, load locking module 112, and processing module 114. The number of processing devices and / or modules can vary depending on the different manufacturing processes associated with semiconductor wafer processing. In some embodiments, the processing apparatus 100 can be provided in a large-space cleanroom that provides a cleanroom environment with lower particulate concentration and lower relative humidity than the surrounding environment.

[0029] According to some embodiments, the processing apparatus 100 is configured to perform a manufacturing process involving processing of one or more wafers (e.g., wafer 106 or multiple wafers 107). In some embodiments, the interface module 104 includes an operating machine 109, such as a robotic arm, a track-based extension member, or other mechanical device. The operating machine 109 is configured to transfer wafer 106 between wafer storage device 108 and the interface module for processing. Wafer 106 processed by the processing apparatus 100 may include multiple layers, such as semiconductor layers, conductor layers, and / or insulating layers. In some embodiments, wafer 106 may include one or more semiconductor layers, conductor layers, and / or insulating layers. Semiconductor layers may include: basic semiconductors having crystalline, polycrystalline, amorphous, and / or other suitable structures, such as silicon or germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; any other suitable materials; and / or combinations thereof. In some embodiments, the semiconductor combination may take the form of a mixture or gradient, such as a substrate where the ratio of Si to Ge varies at different locations. In some embodiments, wafer 106 may include layered semiconductors. Examples include: layering of semiconductor-on-insulator (SOI) layers, such as for creating silicon-on-insulator (“SOI”) substrates, silicon-on-sapphire (SOI) substrates, silicon-germanium-on-insulator (SOI) substrates; or layering of semiconductor-on-glass (“TFT”) layers to create thin-film transistors (“TFT”). Wafer 106 may undergo numerous processing operations, such as photolithography, etching, and / or doping, before forming a complete die.

[0030] In some embodiments, the processing apparatus 100 includes a processing module 114, which may be one of a plurality of processing modules, and the processing module may be configured to perform any manufacturing process on the wafer 106. Wafer manufacturing processes include: deposition, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and / or other deposition processes; etching (e.g., wet etching, dry etching, plasma etching, reactive ion etching (RIE), atomic layer etching (ALE), buffered oxide etching, ion beam polishing, etc.); photolithography (e.g., photolithography); ion implantation (e.g., embedding dopants in material regions); surface passivation; thermal treatment (e.g., rapid thermal annealing, in-furnace annealing, thermal oxidation, etc.); cleaning, such as wet cleaning treatments (e.g., cleaning with solvents such as acetone, trichloroethylene, ultrapure water), rinsing, and / or plasma ashing; chemical mechanical polishing or chemical mechanical planarization (CMP); testing; any procedures involved in wafer processing; and / or any combination of procedures. According to one example, processing module 114 is shown as an example CVD module that receives wafer 106 from loading and locking module 112 through chamber door 116 for placement and processing on stage 118. Source reactive material and carrier gas 120 can be received from auxiliary processing chamber 122 for processing wafer 106.

[0031] A load-locking module 112 is disposed between the processing module 114 and the interface module 104. The load-locking module 112 is configured to maintain the environment within the processing module 114 by being isolated from the interface module 104. In some embodiments, the load-locking module 112 receives the wafer 106 through an interface door 115 of the interface module 104 or a chamber door 116 of the processing module 114. The load-locking module 112 is sealed when the wafer 106 is inserted into it. The load-locking module 112 is configured to create a load-locking environment compatible with the processing module 114 and / or the interface module 104 based on processing operations associated with the wafer 106. The load-locking environment can be controlled by varying the gas content within the load-locking module 112, for example, by adding gas, venting, creating a vacuum, and / or other procedures for regulating the load-locking environment. The load-locking module 112 may include one or more pumps (not shown) for venting gases, such as corrosive gases, from the interior chamber of the load-locking module 112. One or more pumps in the load-lock module 112 may be centrifugal pumps, air-cooled pumps (ACP), roots vacuum pumps (RUVAC), or other types of pumps to eliminate corrosive gases, supply inert gases, and / or create a vacuum in the load-lock environment. Once a suitable environment is achieved within the load-lock module 112, the wafer 106 may be transferred to the interface module 104 or the processing module 114. In some embodiments, another processing module, such as a cluster tool module, or one or more other tools, tool components, tool interfaces, adjacent tools, or neighboring tools may be provided between the load-lock module 112 and the interface module 104.

[0032] In some embodiments, the processing device 100 includes a loading port 110 adjacent to the interface module 104. The loading port 110 is configured to receive a wafer storage device 108. In some embodiments, an overhead hoist transport (OHT) (not shown) transfers the wafer storage device 108 from another module (e.g., a storage container (not shown)) to the loading port 110. In some embodiments, the loading port 110 may be connected to a remote load locking (RLL) module (not shown) to receive one or more wafers. For example, mechanical devices may be used to transfer wafers between the loading port 110 and the remote load locking (RLL) module. In some embodiments, the loading port 110 provides an ultra-clean environment to the wafer storage device 108. The ultra-clean environment can be controlled by varying the gas content within the wafer storage device 108, for example by adding gas, venting, creating a vacuum, and / or other procedures for regulating and / or maintaining the ultra-clean environment. In one example, venting from the wafer storage device 108 may be performed, for example, to create vacuum conditions, near-vacuum conditions (e.g., less than 10). -4(Torch) or relative vacuum conditions (e.g., less than 10) -2 (Tolerance). In one example, venting can be performed before, after, and / or during the addition of a gas to the wafer storage device 108. In one example, the added gas can be N2, Ar, clean dry air (CDA), another type of inert gas, or another type of added gas. In one example, the CDA can have: H2O < 1 / 1 billion (ppb); H2O, CO2 < 1 mg of solute (ppt) in 1000 mg solution, where acids, organics and other compounds < 1 ppt, and bases < 5 ppt; H2O, CO, CO2, non-methane hydrocarbons (NMHC) < 1 ppb; or other purity levels.

[0033] In some embodiments, wafer storage device 108 is disposed on top of loading port 110 and adjacent to interface module 104. For example, wafer storage device 108 may be locked to the top surface of loading port 110. In some embodiments, wafer storage device 108 is configured as a Standard Mechanical Interface (SMIF) or FOUP to hold multiple wafers 107. The wafer storage device includes a storage device door 124 that opens to transfer wafers from the multiple wafers 107 to interface module 104. The multiple wafers 107 may be configured for batch processing, such as being vertically stacked in wafer storage device 108. In one example, wafer storage device 108 may include multiple support frames having multiple individual wafer racks or wafer bays to hold the multiple wafers 107. In one example, wafer storage device 108 may include a movable cassette to hold the multiple wafers 107. In some embodiments, wafer storage device 108 is configured to provide an ultra-clean environment, such as a humidity and contaminant-controlled environment, to maintain the integrity of the multiple wafers 107.

[0034] In some embodiments, the loading port 110 is in gas communication with the wafer memory device 108 to provide an ultra-clean environment within the wafer memory device 108. Gas can be introduced into the wafer memory device 108 through the gas inlet via the loading port 110, and gas can be discharged from the wafer memory device 108 through the gas outlet. In one example, the wafer memory device 108 includes a diffuser or one or more other ventilation panels located within the inner chamber of the wafer memory device to deliver the input gas at different locations within the wafer memory device 108. In one example, the wafer memory device 108 includes a panel cleaning diffuser, such as an ultra-high molecular weight polyethylene (UPE) plate, to deliver and diffuse the input gas at different locations within the wafer memory device 108. In some embodiments, the loading port 110 is in gas communication with the wafer memory device 108 to provide a humidity level of less than 10% relative humidity (RH) within the wafer memory device 108. In some embodiments, the humidity level within the wafer memory device 108 is less than 5% RH or less than 1% RH. In some embodiments, the humidity level within the wafer memory device 108 is substantially undetectable. The ultra-clean environment within the wafer storage device 108 may be affected by the introduction of contaminants and / or humidity, for example, when the storage device door 124 is opened to transfer one or more wafers of the plurality of wafers 107 to the interface module 104.

[0035] In some embodiments, interface module 104 is positioned adjacent to load port 110, wafer storage device 108, and load locking module 112. In some embodiments, interface module 104 is configured as a facility interface, EFEM, or other type of interface for transferring wafer 106 from wafer storage device 108 to another module and / or device (e.g., load locking module 112 or another wafer storage device). Interface module 104 may be located within a cleanroom (not shown), which itself provides a certain level of cleanliness and / or humidity. Interface module 104 may be configured to provide a microenvironment with a higher level of cleanliness and / or a lower level of humidity compared to the cleanroom. For example, the temperature within the microenvironment may be maintained at a consistent temperature, such as between 20°C and 25°C (e.g., 22°C), and a consistent humidity level, such as between 20%RH and 45%RH, between 25%RH and 35%RH, or approximately 30%RH. The humidity level of the microenvironment may vary during multiple processing cycles of wafer 107. In some embodiments, interface module 104 includes a transfer chamber 126 defining a transfer space 127. The transfer chamber 126 of interface module 104 can receive gas 125 from the cleanroom environment via the top portion 138 of interface module 104 and deliver the gas 125 using a fan filter unit 132 to create a gas flow 139 within the transfer chamber 126. In one example, the fan filter unit 132 can operate for a period of time, such as 15 minutes or longer, before the introduction of multiple wafers 107, and the humidity level of the transfer chamber 126 can be stabilized at approximately 25% RH. However, when a batch of multiple wafers 107 has received its most recent cleaning cycle and has subsequently been transferred to the transfer chamber 126, residual moisture may cause fluctuations in the humidity level within the transfer chamber 126, for example, increasing the humidity level above 35% RH. During repeated cycles and processing of multiple wafers 107, the build-up and / or fluctuations of moisture within the transfer chamber 126 may outpace the ability of the fan filter unit 132 to normalize environmental conditions. In some embodiments, the microenvironment within the transfer chamber 126 of the interface module 104 is configured to provide a level of environmental separation between the multiple wafers 107 and sources of contamination and / or cross-contamination (e.g., contamination from human operators).

[0036] In some embodiments, interface module 104 includes a transfer chamber 126 having a wall 128 adjacent to loading port 110 and wafer storage device 108. Wall 128 defines an opening 130 that can be sealed by operation of interface door 131. Interface door 131 can be opened to allow operating machine 109 to transfer wafer 106 through opening 130 for processing. In some embodiments, interface module 104 includes a fan filter unit 132 to create and / or maintain a microenvironment within transfer chamber 126 of interface module 104. Fan filter unit 132 includes a fan unit 134 and a filter unit 136. Fan unit 134 draws in air through top portion 138 of interface module 104, filters the air by filter unit 136, and then introduces the air into transfer chamber 126 of interface module 104. Air from transfer chamber 126 is then exhausted through bottom portion 140 of interface module 104. In some embodiments, an exhaust pump (not shown) is configured to exhaust air from the transfer chamber 126 through the bottom portion 140 of the interface module 104. In some embodiments, a plurality of fan filter units are configured to draw in air through the top portion 138 of the interface module 104, and a plurality of exhaust pumps are configured to exhaust air through the bottom portion 140 of the interface module 104. The fan filter unit 132 and the exhaust pumps of the interface module 104 cooperate to convey air in the transfer chamber as a gas flow 139 in a downward direction.

[0037] In some embodiments, the interface module 104 includes a flow regulating unit 102 located above an opening 130 defined in a wall 128 of the interface module 104. In some embodiments, the flow regulating unit 102 includes a gas nozzle 142 for delivering gas 143 to the flow regulating unit 102. In some embodiments, gas 143 is at least one of the following: N2, Ar, clean dry air (CDA), another type of inert gas, or another type of additive gas. In one example, CDA may have: H2O < 1 / 1 billion (ppb); H2O, CO2 < 1 mg of solute (ppt) in a 1000 mg solution, wherein acids, organics and other compounds < 1 ppt, and bases < 5 ppt; H2O, CO, CO2, NMHC < 1 ppb; or other purity levels.

[0038] In some embodiments, the flow control unit 102 includes one or more gas nozzles (e.g., gas nozzle 142) and one or more layers (e.g., a first layer 144, a second layer 146, and / or a third layer 148). In some embodiments, the first layer 144 is disposed at a first distance below the gas nozzle 142, and the second layer 146 is disposed at a second distance below the gas nozzle 142, greater than the first distance. As described in more detail below, the first layer 144 defines a first aperture having a first aperture size, and the second layer 146 defines a second aperture having a second aperture size greater than the first aperture size. The gas nozzle 142 receives gas 143 and provides a gas flow to the first layer 144. The first layer 144 disperses the gas flow directed to the second layer 146. The second layer 146 then guides the gas flow across the opening 130 in a direction parallel to the wall 128. In some embodiments, the gas flow creates a vertical air curtain guided across the opening 130. In some embodiments, the third layer 148 is disposed at a third distance below the gas nozzle 142, greater than the first distance but less than the second distance. The third layer 148 defines a third aperture, the third aperture size of which is smaller than the first aperture size of the first aperture in the first layer. In some embodiments, an extension plate 150a is disposed below the second layer 146 to restrict gas flow across the opening 130. In some embodiments, a pair of extension plates 150a, 150b are provided below the second layer 146 to restrict gas flow across the opening 130.

[0039] In some embodiments, the gas nozzle 142 is made of a metallic material (e.g., aluminum, stainless steel, etc.), a dielectric material (e.g., quartz, alumina, silicon nitride, etc.), a polymer material, a ceramic material, other suitable materials, and / or combinations thereof. Examples of suitable polymers include fluoropolymers, polyetherimides, polycarbonates, polyetheretherketones (PEEK), polytetrafluoroethylene (PTFE), polyoxymethylene (POM), polyimides, and / or other suitable polymers. Examples of ceramic materials include alumina, cerium oxide, yttrium oxide, zirconium oxide, and / or other suitable ceramic materials. Examples of quartz materials include fused silica, fused silica, quartz glass, and / or other suitable quartz materials.

[0040] like Figure 1B As shown, according to some embodiments, the processing device 100 is along... Figure 1AThe front view is shown as a cut-off line BB. The processing apparatus 100 is shown with the interface gate 131 of the interface module 104 in an open position and the memory device gate 124 of the wafer memory device 108 in an open position. With the memory device gate 124 and the interface gate 131 open, the operating machine 109 can transfer one or more of a plurality of wafers 107 between the wafer memory device 108 and the transfer chamber 126 of the interface module 104. In some embodiments, the flow conditioning unit 102 includes a housing 152 defining a flow conditioning chamber 154. In some embodiments, the housing 152 supports a plurality of gas nozzles 153 above the flow conditioning chamber 154, including gas nozzles 142, to provide a gas flow to the first layer 144. In some embodiments, an extension plate 150a is connected to a side 156a of the housing 152 to restrict gas flow across the opening 130. In some embodiments, an extension plate 150b is connected to a side 156b of the housing 152 to restrict gas flow across the opening 130. In some embodiments, expansion plates 150a, 150b are configured as baffles to prevent ambient airflow from the transfer chamber 126 from entering the wafer memory device 108 when the memory device door 124 is in the open position. In one example, the difference between the ultra-clean environment within the wafer memory device 108 and the microenvironment within the transfer chamber 126 when the memory device door 124 is open can cause turbulent gas flow around the opening 130, which is reduced by the expansion plates 150a, 150b. In one example, the gas flow 139 within the transfer chamber 126 created by the fan filter unit 132 can interact with the wall 128, other sidewalls of the transfer chamber 126, the operating machine 109, other components within the transfer chamber 126, and / or the gas flow 139 itself to cause turbulent gas flow around the opening 130. In some embodiments, this turbulent gas flow around the opening 130 is reduced by the expansion plates 150a, 150b. In some embodiments, the extension plates 150a, 150b of the flow conditioning unit 102 and the housing 152 cooperate to form a canopy for reducing turbulent gas flows from around the opening 130. In some embodiments, the canopy formed by the housing 152 and the extension plates 150a, 150b cooperates with a vertical air curtain exiting from the second layer 146 across the opening 130 to maintain environmental separation between the inner chamber and the transfer chamber 126 of the wafer memory device 108. In some embodiments, the vertical air curtain can prevent gas flows 139 from entering the wafer memory device 108, thereby reducing the introduction of humidity and / or contaminants into the ultra-clean environment of the wafer memory device 108. Other arrangements and / or configurations of the processing apparatus 100 (including the interface module 104 and the flow conditioning unit 102) are within the scope of this disclosure.

[0041] Figure 2This is a perspective view of a processing apparatus 100 according to some embodiments. In some embodiments, the processing apparatus 100 includes a plurality of loading ports 202 (including loading port 110) and a plurality of wafer memory devices 204 (including wafer memory devices 108) arranged adjacent to an interface module 104. A plurality of flow conditioning units 206 (including flow conditioning units 102) are arranged above a plurality of openings defined in a wall 128 of the interface module 104. In some embodiments, a plurality of fan filter units 208 (including fan filter units 132) draw in air through a top portion 138 of the interface module 104 to create a microenvironment within a transfer chamber 126 of the interface module 104. An exhaust pump 210 draws in air from the transfer chamber 126 through a bottom portion 140 of the interface module 104 and exhausts air from the transfer chamber 126 through an exhaust port 212. According to various examples, the exhaust pump 210 may include one or more pumps, and / or may utilize a variety of pumping technologies, such as a positive displacement pump, a momentum transfer pump, a regenerative pump, and / or an entrapment pump. The exhaust pump 210 may include various pumps configured in series and / or parallel according to the respective size and / or number of multiple wafer memory devices 204, which will be configured to interface with the interface module 104.

[0042] In some embodiments, the interface module 104 is disposed in a large-space cleanroom (not shown) that provides a cleanroom environment with a lower particulate concentration and lower relative humidity than the surrounding environment. In some embodiments, a plurality of fan filter units 208 receive air from the cleanroom, and an exhaust pump 210 discharges air from the transfer chamber 126 of the interface module 104 into the cleanroom. In some embodiments, the plurality of fan filter units 208 receive gas from a source outside the cleanroom, and the exhaust pump 210 discharges gas from the transfer chamber 126 of the interface module 104 to an external storage tank outside the cleanroom. Other arrangements and / or configurations of the plurality of fan filter units 208 and the exhaust pump 210 are within the scope of this disclosure.

[0043] In some embodiments, the processing apparatus 100 includes a gas supply source 214 to deliver gas 143 to each of a plurality of flow regulation units 206 via a gas valve 216 and a gas conduit 218. For example, the gas conduit 218 is connected to each of the plurality of flow regulation units 206 via a gas interface 220. In some embodiments, one or more gas valves (e.g., gas valve 216) each control the gas flow within a section of the gas conduit 218 corresponding to each of the plurality of flow regulation units 206. For example, one or more gas interfaces (e.g., gas interface 220) may be associated with each of the plurality of flow regulation units 206 to supply gas 143 to each. In some embodiments, gas 143 flows down from each of the plurality of flow regulation units 206 through a corresponding opening in the wall 128 of the interface module 104, and then each corresponding interface gate is opened to receive a wafer. In some embodiments, the interface gates of the interface module 104 operate independently to receive a corresponding wafer from a plurality of wafer storage devices 204.

[0044] In some embodiments, the processing apparatus 100 includes a gas supply source 224 (e.g., a second gas supply source) to deliver gas 225 to each of the plurality of loading ports 202 via a gas valve 226 and a gas conduit 228. For example, the gas conduit 228 is connected to each of the plurality of flow control units 206 via a corresponding gas interface (not shown). In some embodiments, the gas 225 purges each of the plurality of wafer memory devices 204 as it docks with each of the plurality of loading ports 202. In some embodiments, one or more exhaust pumps (e.g., exhaust pump 230) are connected to each of the plurality of wafer memory devices 204 and / or exhaust gas therefrom to create and / or maintain a corresponding ultra-clean environment therein. In some embodiments, gas from each of the plurality of wafer memory devices 204 is exhausted through one or more exhaust ports (e.g., exhaust port 232).

[0045] In some embodiments, the processing apparatus 100 includes a controller 240 for controlling at least one of the following: a plurality of loading ports 202, a plurality of wafer memory devices 204, a plurality of flow control units 206, a plurality of fan filter units 208, an exhaust pump 210, an exhaust pump 230, a gas valve 216, or a gas valve 226. In one example, the controller 240 controls the gas valve 216 corresponding to the gas source 214 to initiate a gas flow to the first layer 144 of the flow control unit 102, such that an opening 130 in the trans-wall 128 forms an air curtain before the memory device door 124 of the wafer memory device 108 is opened and before the interface door 115 of the interface module 104 (located in front of the wafer memory device 108) is opened. The controller 240 communicates with the loading port 110 to control the opening of the memory device door 124 of the wafer memory device 108. Controller 240 communicates with interface module 104 to control the opening of interface gate 115 of interface module 104. In one example, when storage device gate 124 and interface gate 115 are open, controller 240 controls operating machine 109 to retrieve one or more of wafers 106 and / or multiple wafers 107 from wafer storage device 108. In one example, when storage device gate 124 and interface gate 115 are open, controller 240 controls operating machine 109 to transfer one or more of wafers 106 and / or multiple wafers 107 to wafer storage device 108. After retrieving and / or transferring one or more wafers, controller 240 communicates with load port 110 to control the closing of storage device gate 124 of wafer storage device 108. Controller 240 communicates with interface module 104 to control the closing of interface gate 115 of interface module 104. Then, the controller 240 controls the gas valve 216 corresponding to the gas supply source 214 to stop the gas flow in the first layer 144 of the flow regulating unit 102, thereby stopping the formation of an air curtain across the opening 130.

[0046] In some embodiments, controller 240 controls gas valve 226 corresponding to gas source 224 to initiate gas purging within wafer storage device 108 prior to initiating a transfer of one or more of wafers 106 and / or multiple wafers 107 between wafer storage device 108 and interface module 104. In some embodiments, one or more gas valves (e.g., gas valve 226) respond to controller 240 to each control the gas flow within a gas conduit 228 section corresponding to each of the multiple load ports 202. In some embodiments, one or more gas valves (e.g., gas valve 216) respond to controller 240 to each control the gas flow within a gas conduit 218 section corresponding to each of the multiple flow regulating units 206. In some embodiments, the flow of gas 143 to each of the multiple flow regulating units 206 is individually controlled. In some embodiments, the flow of gas 143 to each of the multiple flow regulating units 206 is collectively controlled such that two or more of the multiple flow regulating units 206 simultaneously receive the flow of gas 143. Other arrangements and / or configurations for controlling the interface module 104, multiple loading ports 202, multiple wafer storage devices 204, multiple flow regulation units 206, the flow of gas 143 from gas supply source 214 and / or the flow of gas 225 from gas supply source 224 are within the scope of this disclosure.

[0047] Figure 3A This is a perspective view of a processing apparatus 100 including a flow adjustment unit 102 according to some embodiments, and Figure 3B This is a schematic front view of a processing apparatus 100 including a flow conditioning unit 102 according to some embodiments. In some embodiments, the housing 152 is configured to hold a first layer 144, a second layer 146, and / or a third layer 148 above an opening 130 in the wall 128 of the interface module 104. In some embodiments, the first layer 144, the second layer 146, and / or the third layer 148 are configured to provide an air curtain 301 across the opening 130, such as a downwardly directed vertical air curtain, to suppress the wafer memory device 108 (e.g., Figure 1A(As shown) contamination. When gas 143 from multiple gas nozzles 153 (e.g., gas nozzles 142) is present, the gas can present a turbulent airflow. The multiple gas nozzles 153 deliver gas 143 to the inner chamber 302 of the housing 152 under the control of the controller 240. In some embodiments, gas 143 is supplied at a flow rate greater than 30 liters per minute (LPM) (e.g., between 35 LPM and 50 LPM, or between 40 LPM and 45 LPM). Gas 143 flows through the housing 152 and creates an air curtain 301 in front of the opening 130. In some embodiments, the flow rate of the air curtain 301 is less than the flow rate of the microenvironment provided by the fan filter unit 132 to the interface module 104. One or more gas sensors (e.g., a first gas sensor 304 or a second gas sensor 306) may be placed in at least one of the following locations: inside the housing 152, below the housing 152, or attached to an extension plate 150a, 150b below the housing, to monitor the flow rate of gas 143 output through the second layer 146. In some embodiments, one or more gas sensors may transmit outlet flow rate information to the controller 240.

[0048] In some embodiments, the first gas sensor 304 or the second gas sensor 306 is at least one of a Pirani heat loss gauge and / or an atmospheric reference gauge for measuring outlet flow rate information and transmitting it to the controller 240. The Pirani heat loss gauge may be configured as a thin metal wire, such as nickel, suspended in the tube. The thin metal wire may change the potential across a Wheatstone bridge circuit in response to the pressure and / or outlet flow rate of the gas 143. In one example, the first gas sensor 304 or the second gas sensor 306 may be configured as a microelectromechanical system (MEMS) Pirani vacuum sensor. The first gas sensor 304 or the second gas sensor 306 may be configured to provide an absolute outlet flow rate measurement or a relative flow rate measurement, which is transmitted to the controller 240 for comparison with the supply gas pressure output from the gas supply source 214. In one example, the first gas sensor 304 or the second gas sensor 306 is configured as a capacitive pressure gauge for measuring the absolute and / or relative outlet flow rate of gas 143, or is configured as a combination of a Pirani pressure gauge and a capacitive pressure gauge. In the presence of water vapor, the Pirani pressure gauge may alter the detected pressure and / or flow rate (e.g., by 60% compared to a capacitive pressure gauge). In some embodiments, a combination of a Pirani pressure gauge and a capacitive pressure gauge is provided to transmit the outlet flow rate of gas 143 and moisture information corresponding to the %RH of gas 143 exiting from the second layer 146. In some embodiments, the first gas sensor 304 detects a first flow rate of gas 143 exiting through the second layer 146 at a first location, and the second gas sensor 306 detects a second flow rate of gas 143 exiting through the second layer 146 at a second location. The controller 240 analyzes fluctuations in the measurements detected by the first gas sensor 304 and / or the second gas sensor 306, such as fluctuations present during the initial supply of gas 143 to the housing 152. When laminar flow of gas 143 and / or air curtain 301 is achieved from housing 152, fluctuations in the detected measurement results can be reduced to below a threshold, for example, less than 10%. When the detected measurement results are below the threshold, controller 240 can initiate and / or perform subsequent operations, such as opening memory device gate 124 of wafer memory device 108, opening interface gate 131 of interface module 104, and / or transferring wafer 106 using operating machine 109. Other arrangements and / or configurations of the first gas sensor 304 and / or the second gas sensor 306 are within the scope of this disclosure.

[0049] In some embodiments, the housing 152 holds a first layer 144, a second layer 146, and / or a third layer 148 above the opening 130. In some embodiments, the first layer 144 has a first thickness AL1, the second layer 146 has a second thickness AL2, and the third layer 148 has a third thickness AL3. In some embodiments, the first thickness AL1 of the first layer 144 is between 1 millimeter (mm) and 20 centimeters (cm), for example, between 5 mm and 10 cm, between 1 cm and 8 cm, or about 5 cm. The first thickness AL1 can vary depending on the type and flow rate of the gas 143 and / or the number of flow layers held within the housing 152. In some embodiments, such as Figure 3B As shown, the first layer 144 is located at a first distance D1 below the gas nozzle 142.

[0050] In some embodiments, the second layer 146 is held within the housing 152 below the first layer 144. In some embodiments, the second thickness AL2 of the second layer 146 is between 1 mm and 30 cm, for example between 5 mm and 20 cm, between 1 cm and 15 cm, or about 10 cm. The second thickness AL2 can be varied depending on the type and flow rate of the gas 143 to be transmitted through the second layer 146, the number of flow layers configured above the second layer 146, and / or the distance of the second layer 146 above the opening 130 in the wall 128 of the interface module 104. In some embodiments, such as Figure 3B As shown, the second layer 146 is located below the gas nozzle 142 at a second distance D2 greater than the first distance D1. In some embodiments, such as Figure 3B As shown, the first layer 144 is separated from the second layer 146 by a separation distance SD greater than zero.

[0051] In some embodiments, the third layer 148 is held within the housing 152 between the first layer 144 and the second layer 146. In some embodiments, the third thickness AL3 of the third layer 148 is between 1 mm and 20 cm, for example between 5 mm and 10 cm, between 1 cm and 8 cm, or about 5 cm. The third thickness AL3 can vary depending on the type and flow rate of the gas 143 and / or the number of flow layers held within the housing 152. In some embodiments, such as Figure 3B As shown, the third layer 148 is located at a third distance D3 below the gas nozzle 142, wherein the third distance D3 is greater than the first distance D1 but less than the second distance D2. Other arrangements and / or configurations of the layer thickness and / or layer spacing below the gas nozzle 142 are within the scope of this disclosure.

[0052] In some embodiments, expansion plates 150a, 150b are disposed below the second layer 146 to restrict the gas 143 exiting through the second layer 146 and to restrict the air curtain 301 across the opening 130. The opening 130 has an opening length OOl and an opening width OOw. In some embodiments, each of the expansion plates 150a, 150b has an expansion plate length EPl and an expansion plate depth EPd, and is spaced apart by an expansion plate width EPw. The expansion plate length EPl is greater than the opening length OOl and the expansion plate width EPw is greater than the opening width OOw, such that the expansion plates 150a, 150b frame the opening 130. In some embodiments, a housing 152 provides a shield over the opening 130 and is wider than the opening width OOw. In some embodiments, the expansion plates 150a, 150b have a sufficient expansion plate length EPl that extends from the housing 152 beyond the bottom horizontal plane of the opening 130. In some embodiments, the expansion board width EPw is wider than the width of the memory device gate 124 of the wafer memory device 108, such that the expansion boards 150a and 150b do not obstruct the opening of the memory device gate 124, do not obstruct the opening of the interface gate 131, and do not interfere with the transfer of the wafer 106 by the operating machine 109. In some embodiments, the expansion board depth EPd of the expansion boards 150a and 150b is configured not to obstruct the operating space of the operating machine 109 within the transfer chamber 126 of the interface module 104. For example, the expansion board depth EPd of the expansion boards 150a and 150b is not greater than 15 cm. In some embodiments, the expansion board depth EPd is configured to have sufficient depth to confine the air curtain 301 around the opening 130. For example, the expansion board depth EPd is not less than 2 cm. Other arrangements and / or configurations of the dimensions of the expansion boards 150a and 150b are within the scope of this disclosure.

[0053] Figure 4 This is a schematic front view of a processing apparatus 100 including a flow regulating unit 102 according to some embodiments. In some embodiments, gas nozzles 142 and / or multiple gas nozzles 153 can be drawn from... Figure 2 The gas supply source 214 shown receives a gas flow 400 from gas 143. Gas nozzle 142 and / or multiple gas nozzles 153 provide a first gas flow 402 to a first layer 144. The first layer 144 disperses the first gas flow 402 to generate a second gas flow 404 directed to a second layer 146. The second layer 146 directs the second gas flow 404, for example, in a direction parallel to the wall 128 of the interface module 104, to generate a third gas flow 406 directed across the opening 130. In some embodiments, the third layer 148 receives the second gas flow 404 from the first layer 144 and generates a fourth gas flow 408 directed to the second layer 146.

[0054] In some embodiments, a first gap 420 is spaced between a first layer 144 and a third layer 148 within the housing 152, the first gap 420 having a first gap distance G1, and a second gap 422 is spaced between the third layer 148 and a second layer 146 within the housing 152, the second gap 422 having a second gap distance G2. In some embodiments, the first gap distance G1 is a non-zero number between 1 mm and 10 cm, for example, 1 cm. In some embodiments, the second gap distance G2 is a non-zero number between 1 mm and 10 cm, for example, 1 cm. In some embodiments, the first gap 420 is provided such that the first layer 144 does not directly contact the third layer 148, and the second gap 422 is provided such that the third layer 148 does not directly contact the second layer 146. The first gap 420 enhances the laminar flow of the second gas flow 404 between the first layer 144 and the third layer 148. The second gap 422 enhances the laminar flow of the fourth gas flow 408 between the third layer 148 and the second layer 146. Other arrangements and / or configurations of a first gap 420 having a first gap distance G1 and a second gap 422 having a second gap distance G2 are within the scope of this disclosure.

[0055] In some embodiments, the first layer 144 is a porous layer defining a first aperture 410 having a first aperture diameter AD1 corresponding to a first aperture size. In some embodiments, the first layer 144 defines a second aperture 412 having a second aperture diameter AD2 corresponding to a second aperture size. In some embodiments, the first layer 144 defines a plurality of apertures including the first aperture 410 and the second aperture 412, wherein the size of each of the plurality of apertures is greater than or equal to the second aperture 412 but less than or equal to the first aperture 410. In some embodiments, the plurality of apertures of the first layer 144 have at least one of a regular shape or an irregular shape, and their sizes range between and / or equal to the sizes of the first aperture 410 and the second aperture 412. For example, the first layer 144 includes an irregular aperture 409 having an irregular shape. In some embodiments, the first layer 144 includes a plurality of apertures of a second size, with different distances between adjacent apertures. For example, the first layer 144 defines a first aperture 411a of a second size, a second aperture 411b of a second size, a third aperture 411c of a second size, and a fourth aperture 411d of a second size. The third aperture 411c of the second size is adjacent to the first aperture 410, and the fourth aperture 411d of the second size is adjacent to the first aperture 410. The first aperture 410 and the second aperture 411c of the second size are spaced apart by a first distance SSD1, and the first aperture 410 and the fourth aperture 411d of the second size are spaced apart by a second distance SSD2. In some embodiments, the first distance SSD1 is less than the second distance SSD2. In some embodiments, the first distance SSD1 is not equal to the second distance SSD2. In some embodiments, the first distance SSD1 is equal to the second distance SSD2.

[0056] In some embodiments, the pore size of the first layer 144 is configured such that portions of its sides do not have a continuous distance from the sides of other pore sizes of the first layer. In some embodiments, the first layer 144 is a porous layer, such as a porous ultra-high molecular weight polyethylene (UPE) material, defining a plurality of pore sizes including a first pore size 410 and a second pore size 412. In some embodiments, the first layer 144 is a non-porous material, such as a ridged or semi-rigid plate in which a plurality of pore sizes are formed. In some embodiments, the first layer 144 is: a metal, such as stainless steel or aluminum; a non-metallic material, such as PTFE, PEEK, or POM; or another material that does not generate dust, particles, and / or volatiles and has a low coefficient of friction for gas passage therethrough. In some embodiments, the first layer 144 is a mesh material, such as a sieve or a combination of randomly formed and connected fibers, or a combination of one or more mesh materials, defining a plurality of pore sizes, such as a first pore size 410 or a second pore size 412. In some embodiments, the first pore size diameter AD1 is less than or equal to 5 cm, and the second pore size diameter AD2 is less than the first pore size diameter AD1. In some embodiments, the first layer 144 defines a first aperture 410 having a first shape and a second aperture 412 having a second shape different from the first shape.

[0057] In some embodiments, the second layer 146 defines a third aperture 414 having a third aperture diameter AD3 corresponding to the third aperture size. In some embodiments, the third aperture size of the third aperture 414 is larger than the first aperture size of the first aperture 410. In some embodiments, the second layer 146 is a rigid mesh structure defining a plurality of apertures (including the third aperture 414), wherein the size of each of the plurality of apertures is larger than the size of the first aperture 410. In some embodiments, the second layer 146 defines a plurality of apertures (including the third aperture 414) arranged in a mesh pattern, such as a plurality of apertures in an n×m matrix. In some embodiments, the second layer 146 defines a plurality of apertures arranged in an n×m mesh pattern, where n is an integer greater than or equal to 2, and m is an integer greater than or equal to 2. In some embodiments, the third aperture diameter AD3 of the third aperture 414 is larger than the first aperture diameter AD1 of the first aperture 410. In some embodiments, the third aperture 414 has a polygonal shape. In one example, the polygonal shape of the third aperture 414 is a regular polygon. In some embodiments, the first aperture diameter AD1 of the first aperture 410 in the first layer 144 is smaller than the side length SL of the side 418 defining the third aperture 414 in the second layer 146. In some embodiments, the first layer 144 has a first number of apertures, and the second layer 146 has a second number of apertures smaller than the first number of apertures. In some embodiments, the first layer 144 has a first number of apertures, the second layer 146 has a second number of apertures smaller than the first number of apertures, and the third layer 148 has a third number of apertures larger than the first number of apertures.

[0058] In some embodiments, the third layer 148 is a porous layer defining a fourth pore diameter 416 having a fourth pore diameter AD4 corresponding to the fourth pore diameter size. In some embodiments, the third layer 148 is a UPE porous material defining a plurality of pore diameters including the fourth pore diameter 416. In some embodiments, the third layer 148 is a non-porous material, such as a ridged or semi-rigid plate in which a plurality of pore diameters are formed. In some embodiments, the third layer 148 is: a metal, such as stainless steel or aluminum; a non-metallic material, such as PTFE, PEEK, or POM; or another material that does not generate dust, particles, and / or volatiles and has a low coefficient of friction for gas passage therethrough. In some embodiments, the third layer 148 is a mesh material, such as a sieve or a combination of randomly formed and connected fibers, or a combination of one or more mesh materials defining a plurality of pore diameters, such as the fourth pore diameter 416. In some embodiments, the fourth pore diameter AD4 of the fourth pore diameter 416 is smaller than the second pore diameter AD2 of the second pore diameter 412. In some embodiments, the third layer 148 defines a plurality of apertures (including a fourth aperture 416), wherein the size of each of the plurality of apertures is smaller than the size of the second aperture 412. In some embodiments, the plurality of apertures in the third layer 148 have at least one of a regular shape or an irregular shape, and their size ranges smaller than the size of the second aperture 412.

[0059] In some embodiments, the plurality of apertures in the third layer 148 have at least one of regular or irregular shapes, and their size range is smaller than that of the second aperture 412 of the first layer 144. For example, the third layer 148 includes an irregular aperture 415 having an irregular shape. In some embodiments, the third layer 148 includes a plurality of apertures of a third size, wherein the distance between adjacent apertures is different. For example, the third layer 148 defines a first aperture 417a of a third size, a second aperture 417b of a third size, a third aperture 417c of a third size, and a fourth aperture 417d of a third size. The third aperture 417c of a third size is adjacent to the fourth aperture 416, and the fourth aperture 417d of a third size is adjacent to the fourth aperture 416. The fourth aperture 416 is spaced apart from the third aperture 417c by a third distance SSD3, and the fourth aperture 416 is spaced apart from the fourth aperture 417d of a third size by a fourth distance SSD4. In some embodiments, the third distance SSD3 is smaller than the fourth distance SSD4. In some embodiments, the third distance SSD3 is not equal to the fourth distance SSD4. In some embodiments, the third distance SSD3 is equal to the fourth distance SSD4. Other arrangements and / or configurations of the first layer 144, the second layer 146, and / or the third layer 148 are within the scope of this disclosure.

[0060] Figures 5A-5D This is a schematic diagram of a processing apparatus 100 including a second layer 146 according to some embodiments. For example... Figure 5A As shown, according to some embodiments, the second layer 146 of the processing device 100 includes a plurality of apertures, which are represented by aperture segments 500. In some embodiments, the second layer 146 includes aperture segments 500 arranged in a grid pattern defined by a grid 504. The grid pattern is a network of intersecting parallel lines that repeat in a regular manner. For example, as Figure 5A As shown, grid 504 defines a grid pattern including the intersections of parallel lines, where each aperture in aperture segment 500 corresponds to an intersection of the parallel lines. In some embodiments, aperture segments 500 are arranged in an n×m matrix, where n is an integer greater than 2, corresponding to the number of apertures on the horizontal axis of grid 504, and m is an integer greater than 2, corresponding to the number of apertures on the vertical axis of grid 504. For example, as... Figure 5A As shown, each aperture in aperture segment 500 is arranged in an n×m matrix, where n=5 and m=6. Grid 504 and aperture segments 500 corresponding to the grid pattern defined by grid 504 are repeated laterally on the second layer 146.

[0061] In some embodiments, the aperture segment 500 includes a first aperture 502 configured as a polygon. For example, the first aperture 502 is configured as a regular hexagon, including six sides 506a-f, wherein each side has a side length SL1. In some embodiments, the first aperture 502 is laterally adjacent to six second apertures 503a-f, each second aperture 503a-f being configured as a regular hexagon such that at least one side of the first aperture 502 is contiguous with at least one side of each second aperture 503a-f.

[0062] In some embodiments, the layer above the second layer 146 (e.g., within the housing 152 of the flow conditioning unit 102) is configured to define an aperture having a corresponding aperture diameter having a side length SL1 smaller than that of the first aperture 502. In one example, reference... Figure 4 The diameter AD1 of the first aperture 410 of the first layer 144 is smaller than the side length SL1 of the first aperture 502 of the second layer 146. In one example, refer to... Figure 4 The second aperture diameter AD2 of the second aperture 412 in the first layer 144 is smaller than the side length SL1 of the first aperture 502 in the second layer 146. In one example, refer to... Figure 4 The fourth aperture diameter AD4 of the fourth aperture 416 of the third layer 148 is smaller than the side length SL1 of the first aperture 502 of the second layer 146. Other arrangements and / or configurations of the plurality of apertures of the second layer 146 (represented by aperture segment 500 and including the first aperture 502) are within the scope of this disclosure.

[0063] like Figure 5BAs shown, according to some embodiments, the second layer 146 of the processing apparatus 100 includes a plurality of apertures, which are represented by aperture segments 500. In some embodiments, in the second layer 146, the aperture segments 500 are arranged in a grid pattern. A grid 504 defines a grid pattern that includes intersections of parallel lines, wherein each aperture in the aperture segment 500 corresponds to an intersection of parallel lines. In some embodiments, the aperture segments 500 are arranged in an n×m matrix, where n is an integer greater than 2, corresponding to the number of apertures on the horizontal axis of the grid 504, and m is an integer greater than 2, corresponding to the number of apertures on the vertical axis of the grid 504. For example, each aperture in the aperture segment 500 is arranged in an n×m matrix, where n = 8 and m = 4. The grid 504 and the aperture segments 500 corresponding to the grid pattern defined by the grid 504 are repeated laterally on the second layer 146.

[0064] In some embodiments, the aperture segment 500 includes a first aperture 512 configured as a polygon. For example, the first aperture 512 is configured as an equilateral triangle, including three sides 516a-c, each side having a side length SL1. In some embodiments, the first aperture 512 is laterally adjacent to three second apertures 513a-c, such that at least one side of the first aperture 512 is contiguous with at least one side of the second apertures 513a-c.

[0065] In some embodiments, the layer above the second layer 146 (e.g., within the housing 152 of the flow regulating unit 102) is configured to define an aperture having a corresponding aperture diameter having a side length SL1 smaller than the first aperture 512. In one example, reference... Figure 4 The diameter AD1 of the first aperture 410 of the first layer 144 is smaller than the side length SL1 of the first aperture 512 of the second layer 146. In one example, refer to... Figure 4 The second aperture diameter AD2 of the second aperture 412 in the first layer 144 is smaller than the side length SL1 of the first aperture 512 in the second layer 146. In one example, refer to... Figure 4 The fourth aperture diameter AD4 of the fourth aperture 416 of the third layer 148 is smaller than the side length SL1 of the first aperture 512 of the second layer 146. Other arrangements and / or configurations of the plurality of apertures of the second layer 146 (represented by aperture segment 500 and including the first aperture 512) are within the scope of this disclosure.

[0066] like Figure 5CAs shown, according to some embodiments, the second layer 146 of the processing device 100 includes a plurality of apertures, which are represented by aperture segments 500. In some embodiments, in the second layer 146, the aperture segments 500 are arranged in a grid pattern. The grid 504 includes intersections of parallel lines, wherein each aperture in the aperture segment 500 corresponds to an intersection of parallel lines. In some embodiments, the aperture segments 500 are arranged in an n×m matrix, where n is an integer greater than 2, corresponding to the number of apertures on the horizontal axis of the grid 504, and m is an integer greater than 2, corresponding to the number of apertures on the vertical axis of the grid 504. For example, each aperture in the aperture segment 500 is arranged in an n×m matrix, where n = 12 and m = 3. The grid 504 and the aperture segments 500 corresponding to the grid pattern defined by the grid 504 are repeated laterally on the second layer 146.

[0067] In some embodiments, the aperture segment 500 includes a first aperture 522 configured as a polygon. For example, the first aperture 522 is configured as a regular rhombus, including four sides 526a-d, each side having a side length SL1. In some embodiments, the first aperture 522 is laterally adjacent to four second apertures 523a-d, such that at least one side of the first aperture 522 is contiguous with at least one side of the second apertures 523a-d.

[0068] In some embodiments, the layer above the second layer 146 (e.g., within the housing 152 of the flow regulating unit 102) is configured to define an aperture having a corresponding aperture diameter having a side length SL1 smaller than the first aperture 522. In one example, reference... Figure 4 The diameter AD1 of the first aperture 410 of the first layer 144 is smaller than the side length SL1 of the first aperture 522 of the second layer 146. In one example, refer to... Figure 4 The second aperture diameter AD2 of the second aperture 412 in the first layer 144 is smaller than the side length SL1 of the first aperture 522 in the second layer 146. In one example, refer to... Figure 4 The fourth aperture diameter AD4 of the fourth aperture 416 of the third layer 148 is smaller than the side length SL1 of the first aperture 522 of the second layer 146. Other arrangements and / or configurations of the plurality of apertures of the second layer 146 (represented by aperture segment 500 and including the first aperture 522) are within the scope of this disclosure.

[0069] like Figure 5DAs shown, according to some embodiments, the second layer 146 of the processing apparatus 100 includes a plurality of apertures, which are represented by aperture segments 500. In some embodiments, in the second layer 146, the aperture segments 500 are arranged in a grid pattern. The grid 504 includes intersections of parallel lines, wherein each aperture in the aperture segment 500 corresponds to an intersection of parallel lines. In some embodiments, the aperture segments 500 are arranged in an n×m matrix, where n is an integer greater than 2, corresponding to the number of apertures on the horizontal axis of the grid 504, and m is an integer greater than 2, corresponding to the number of apertures on the vertical axis of the grid 504. For example, each aperture in the aperture segment 500 is arranged in an n×m matrix, where n = 5 and m = 5. The grid 504 and the aperture segments 500 corresponding to the grid pattern defined by the grid 504 are repeated laterally on the second layer 146.

[0070] In some embodiments, the aperture segment 500 includes a first aperture 532 configured as a polygon. For example, the first aperture 522 is configured as a regular rectangle, including four sides 536a-d, wherein sides 536a and 536c have side length SL1, and sides 536b and 536d have side length SL2. In some embodiments, the first aperture 532 is laterally adjacent to six second apertures 533a-f, such that at least one side of the first aperture 532 is contiguous with at least one side of the second apertures 533a-f.

[0071] In some embodiments, the layer above the second layer 146 (e.g., within the housing 152 of the flow regulating unit 102) is configured to define an aperture having a corresponding aperture diameter having a side length SL1 smaller than the first aperture 532. In one example, reference... Figure 4 The diameter AD1 of the first aperture 410 of the first layer 144 is smaller than the side length SL1 of the first aperture 532 of the second layer 146. In one example, refer to... Figure 4 The second aperture diameter AD2 of the second aperture 412 in the first layer 144 is smaller than the side length SL1 of the first aperture 532 in the second layer 146. In one example, refer to... Figure 4 The fourth aperture diameter AD4 of the fourth aperture 416 of the third layer 148 is smaller than the side length SL1 of the first aperture 532 of the second layer 146. Other arrangements and / or configurations of the plurality of apertures of the second layer 146 (represented by aperture segment 500 and including the first aperture 532) are within the scope of this disclosure.

[0072] Figure 6 This is a detailed schematic diagram of a processing apparatus 100 including a second layer 146 according to some embodiments. In some embodiments, as shown in reference... Figure 3AAs shown, the second layer 146 has a second thickness AL2, and is between 1 mm and 30 cm, for example between 5 mm and 20 cm, between 1 cm and 15 cm, or about 10 cm. In some embodiments, the second layer 146 includes a structural mesh 601 to define a plurality of apertures therein. Each aperture defined by the structural mesh 601 has a depth corresponding to the second thickness AL2 of the second layer 146. In one example, the second thickness AL2 of the second layer 146 is the same on the horizontal plane of the second layer 146. In one example, the second thickness AL2 can be varied depending on the type and flow rate of the gas 143 to be conveyed through the second layer 146, the number of flow layers configured above the second layer 146, and / or the distance of the second layer 146 above the opening 130 in the wall 128 of the interface module 104.

[0073] In some embodiments, the second layer 146 includes a first aperture 602, a second aperture 604, a third aperture 606, and a fourth aperture 608. The second aperture 604 is defined by a first side 610 and a second side 612. The third aperture 606 is defined by a third side 614, and the fourth aperture 608 is defined by a fourth side 616. The first side 610 is adjacent to the third side 614. The second side 612 is adjacent to the fourth side 616. The first side 610 and the third side 614 are separated by a first distance SW1. The third side 614 and the fourth side 616 are separated by a second distance SW2. In some embodiments, the first distance SW1 is equal to the second distance SW2.

[0074] In some embodiments, the first side 610 has a first length S1, the second side 612 has a second length S2, the third side 614 has a third length S3, and the fourth side 616 has a fourth length S4. In some embodiments, the first length S1 is equal to the third length S3. In some embodiments, the second length S2 is equal to the fourth length S4. In some embodiments, the first distance SW1 is constant between the first side 610 and the third side 614 along the first length S1 and the third length S3. In some embodiments, the second distance SW2 is constant between the second side 612 and the fourth side 616 along the second length S2 and the fourth length S4. In some embodiments, the first aperture 602, the second aperture 604, the third aperture 606, and the fourth aperture 608 have the same shape. In some embodiments, the first aperture 602, the second aperture 604, the third aperture 606, and the fourth aperture 608 have the same side length. In some embodiments, the spacing between the first aperture 602 and the second aperture 604 is the same as the spacing between the third aperture 606 and the fourth aperture 608. In some embodiments, the spacing between the first aperture 602 and the second aperture 604, the second aperture 604 and the third aperture 606, the third aperture 606 and the fourth aperture 608, and the fourth aperture 608 and the first aperture 602 is the same. In some embodiments, the spacing between the first aperture 602 and the second aperture 604, the second aperture 604 and the third aperture 606, the third aperture 606 and the fourth aperture 608, and the fourth aperture 608 and the first aperture 602 is less than or equal to 5 mm. Other arrangements and / or configurations of the first aperture 602, the second aperture 604, the third aperture 606, and the fourth aperture 608 are within the scope of this disclosure.

[0075] Figures 7A-7G This is a schematic diagram of a processing apparatus 100 according to some embodiments. Figures 7A-7F A sequence of operations that can be executed by the processing device 100 is shown. For example, the processing device 100 can execute the shown sequence of operations in response to control by the controller 240, as referenced above. Figure 4 As described above. In one example, as described above, the processing device 100 is configured in a cleanroom with a cleanroom environment. In one example, the fan unit 134 of the fan filter unit 132 continuously operates to provide a first gas flow 702 to the transfer chamber 126 of the interface module 104, which provides a microenvironment as described above. The gas 700 within the transfer chamber 126 circulates downwards through the transfer chamber 126. Reference Figure 7AIn some embodiments, wafer storage device 108 includes a plurality of wafers 107 for processing by interface module 104. Storage device gates 124 of wafer storage device 108 are in a closed position to protect the plurality of wafers 107 from contamination, such as contamination by moisture, dust, particles, volatiles, and / or other types of contamination. In some embodiments, wafer storage device 108 is configured to maintain an ultra-clean FOUP environment, as described above, to accommodate the plurality of wafers 107. Wafer storage device 108 is loaded onto loading port 110. In one example, wafer storage device 108 may be loaded onto loading port 110 by a human operator. In another example, wafer storage device may be loaded onto loading port 110 via a mechanical device (e.g., OHT).

[0076] refer to Figure 7B In some embodiments, the wafer memory device is connected to the load port 110. In some embodiments, the interface module 104 may interface with multiple wafer memory devices and / or other processing modules, as referenced above. Figure 1A As shown in Figure 3. For example, loading and docking of wafer storage device 108 at loading port 110 can be transmitted to controller 240 via loading port 110. The docking of wafer storage device 108 can enter a queue maintained by controller 240 for subsequent batch processing of multiple wafers 107 by interface module 104. When multiple wafers 107 within wafer storage device 108 are queued for processing by controller 240, controller 240 confirms that wafer storage device 108 is sealed relative to loading port 110 and interface module 104, and then controls interface door 131 to open. In some embodiments, controller 240 can control interface door 131 to open after air curtain 301 is created, as referenced below. Figure 7C The memory device door 124 of the wafer memory device remains closed. In some embodiments, movement of any component within the interface module 104 (e.g., interface door 131) can generate fluctuations and / or turbulence within the microenvironment of the transfer chamber 126. After a period of time, such fluctuations and / or turbulence dissipate, for example, through the continued movement of air guided downward within the transfer chamber 126 by the fan filter unit 132.

[0077] refer to Figure 7C In some embodiments, before processing multiple wafers 107 within the wafer storage device 108, the controller 240 initiates a second gas flow 704 to the flow regulation unit 102, for example, as described above. Figure 3AThe gas 143. The second gas flow 704 creates an air curtain 301, also referred to as an air or gas flow barrier, below the flow conditioning unit 102 and in front of the opening 130. In one example, the air barrier provides laminar airflow across the opening 130 to reduce the likelihood of moisture and / or contaminants entering the ultra-clean environment of the wafer memory device 108 from the microenvironment of the transfer chamber 126. In some embodiments, the controller 240 determines that laminar flow across the opening 130 has been created by the gas 143 before initiating subsequent operations. In one example, the controller 240 waits for a predetermined period of time after initiating the gas flow 143 before initiating subsequent operations. In one example, the controller 240 monitors the air pressure supplied by the gas supply source 214, as referenced above. Figure 2 As described above, and when a predetermined pressure is obtained, subsequent operations are initiated. In one example, the controller 240 monitors data from one or more gas sensors (e.g., referenced above). Figure 3A The presence of the air curtain 301 across the opening 130 is detected by the response of the first gas sensor 304 and / or the second gas sensor 306.

[0078] refer to Figure 7D In some embodiments, the processing apparatus 100 includes a fan unit 134 above a transfer space 127 to provide a first gas flow 702 in the transfer space 127. A flow regulating unit 102 is disposed above an opening 130. A gas nozzle 142 supplies gas 143 to the housing 152 of the flow regulating unit 102. A first layer 144 is located below the gas nozzle 142, and a second layer 146 is located below the first layer 144. Due to the input pressure from the gas 143, the gas nozzle 142 provides a second gas flow 704 to the first layer 144. The first layer 144 disperses the second gas flow 704 to generate a third gas flow 706 directed to the second layer 146. The second layer 146 guides the third gas flow 706 in a direction parallel to the wall 128 to generate a fourth gas flow 708, which is not directed into the opening 130 and inhibits the first gas flow through the opening 130. The fourth gas flow 708 forms an air curtain 301. In some embodiments, the first gas flow 702 has a first velocity, and the second gas flow 704 has a second velocity less than the first velocity. In one example, the second gas flow 704 has a second velocity less than the first velocity to provide laminar airflow across the opening 130 through the air curtain 301. In one example, the first velocity is greater than 50 LPM, for example, between 50 LPM and 100 LPM, or greater than 100 LPM, and the second velocity is greater than 30 LPM, for example, between 35 LPM and 45 LPM.

[0079] refer to Figure 7EIn some embodiments, controller 240 controls the opening of the memory device gate 124 of the wafer memory device 108 while maintaining the presence of the air curtain 301. In some embodiments, controller 240 may control the interface gate 131 to open after the air curtain 301 has been created, as referenced above. Figure 7C The controller 240 then controls the operating machine 109 to cross the air curtain 301 and transfer the wafer 106 from the wafer storage device 108. In some embodiments, the operating machine 109 transfers some or all of a plurality of wafers 107 from the wafer storage device 108 for batch processing by the interface module 104.

[0080] refer to Figure 7F In some embodiments, the controller 240 maintains the presence of the air curtain 301 by keeping the gas 143 flowing toward the flow regulating unit 102 until the controller 240 detects that the memory device gate 124 of the wafer memory device 108 is closed. In one example, the controller 240 receives a signal from the load port 110 indicating that the memory device gate 124 is closed.

[0081] refer to Figure 7G In some embodiments, when the controller 240 detects that the memory device gate 124 of the wafer memory device 108 is closed, the controller stops supplying gas 143 to the flow regulating unit 102 to remove the presence of the air curtain 301. In some embodiments, the controller 240 controls the interface gate 131 to close before stopping the supply of gas 143 to the flow regulating unit 102. In one example, the controller 240 sends a signal to the interface module 104 instructing the interface gate 131 to close. Other arrangements and / or configurations for controlling the interface module 104, the wafer memory device 108, the operating machine 109, the memory device gate 124, the interface gate 131, and / or the gas supply source 214 are within the scope of this disclosure.

[0082] Figure 8 This is a perspective view of a processing apparatus 100 including a flow conditioning unit 102 according to some embodiments. In some embodiments, the flow conditioning unit 102 includes a housing 152 supporting a first layer 144 and a second layer 146. In some embodiments, the housing 152 is configured to hold the first layer 144 and the second layer 146 above an opening 130 in a wall 128 of an interface module 104. In some embodiments, the first layer 144 and the second layer 146 are configured to provide an air curtain 301 across the opening 130, such as a downwardly directed vertical air curtain, to suppress the wafer memory device 108 (e.g., Figure 1A(As shown) contamination. When gas 143 from multiple gas nozzles 153 (e.g., gas nozzle 142) is present, the gas can present a turbulent airflow. The multiple gas nozzles 153 deliver gas 143 to the housing 152 under the control of controller 240. In some embodiments, gas 143 is supplied at a flow rate greater than 30 liters per minute (LPM) (e.g., between 35 LPM and 50 LPM, or between 40 LPM and 45 LPM). In some embodiments, gas 143 is supplied at a flow rate less than that of the fan filter unit 132 of interface module 104. Gas 143 flows through housing 152 and creates an air curtain 301 in front of opening 130.

[0083] In some embodiments, the flow conditioning unit 102 includes a first layer 144. The first layer 144 defines a first aperture 802, as referenced above. Figure 4 The first aperture 410 and / or the second aperture 412, wherein the first aperture 802 has a first aperture size and is positioned at a certain distance below the gas nozzle 142, for example, as described above. Figure 3B The first distance D1 is mentioned. In some embodiments, the second layer 146 defines a second aperture 804, the second aperture 804 having a second aperture size larger than the first aperture 802. The second layer 146 is disposed below the gas nozzle 142 at a second distance D2 greater than the first distance D1. In some embodiments, the gas nozzle 142 provides a first gas flow to the first layer 144, and the first layer 144 disperses the first gas flow to generate a second gas flow directed to the second layer 146. The second layer 146 directs the second gas flow to generate a third gas flow, thereby forming an air curtain 301 not directed into the opening 130. In some embodiments, the third gas flow is directed across the opening 130. In some embodiments, the second layer 146 defines the second aperture 804 as having a second shape different from the first shape of the first aperture 802. In some embodiments, the second aperture 804 has a polygonal shape, such as a regular hexagon, equilateral triangle, regular rectangle, regular rhombus, or another polygonal shape, and the first aperture has a non-polygonal shape, such as a circle, ellipse, curve, or other non-polygonal shape. In some embodiments, when the flow regulating unit 102 has two flow regulating layers, these layers may have different flow rates than embodiments of the flow regulating unit 102 having three or more flow regulating layers. In one example, the flow regulating unit 102 includes a first layer 144, and a second layer 146 can achieve a steady-state laminar flow rate across the air curtain 301 of the opening 130 more quickly because a smaller volume is required to fill the housing 152 before establishing the air curtain 301. Other arrangements and / or configurations of the flow regulating unit 102 having a first layer 144 and a second layer 146 are within the scope of this disclosure.

[0084] Figure 9This is a perspective view of a processing apparatus 100 including a flow conditioning unit 102 according to some embodiments. In some embodiments, the flow conditioning unit 102 includes a first layer 144, a second layer 146, a third layer 148, and one or more additional layers, such as a fourth layer 902, disposed between the second layer 146 and the third layer 148. In some embodiments, the first layer 144 defines one or more apertures, such as a first aperture 904; the second layer 146 defines one or more apertures, such as a second aperture 906; the third layer 148 defines one or more apertures, such as a third aperture 908; and the fourth layer 902 defines one or more apertures, such as a fourth aperture 910. In some embodiments, the size of the second aperture 906 is larger than the size of the first aperture 904, the size of the third aperture 908 is smaller than the size of the first aperture 904, and the size of the fourth aperture 910 is smaller than the size of the third aperture 908. In some embodiments, the first aperture 904 is less than or equal to 5 cm. In some embodiments, the second aperture 906 has a polygonal shape, as referenced above. Figures 5A-5D In some embodiments, a first layer 144 has a first pore size density, a second layer 146 has a second pore size density, a third layer 148 has a third pore size density, and a fourth layer 902 has a fourth pore size density. In some embodiments, the first pore size density is greater than the second pore size density. In some embodiments, the third pore size density is greater than the first pore size density. In some embodiments, the fourth pore size density is greater than the third pore size density. In some embodiments, the fourth pore size density is equal to the third pore size density. In some embodiments where one or more layers (e.g., the fourth layer 902) are disposed between the second layer 146 and the third layer 148, each of the one or more layers has a pore size density greater than the first pore size density.

[0085] In some embodiments, a first layer 144 is disposed at a first distance BN1 below the gas nozzle 142, a second layer 146 is disposed at a second distance BN2 below the gas nozzle 142, a third layer 148 is disposed at a third distance BN3 below the gas nozzle 142, and a fourth layer 902 is disposed at a fourth distance BN4 below the gas nozzle 142. In some embodiments, the second distance BN2 is greater than the first distance BN1. In some embodiments, the third distance BN3 is greater than the first distance BN1 but less than the second distance BN2. In some embodiments, the fourth distance BN4 is greater than the third distance BN3 but less than the second distance BN2. In some embodiments where one or more layers (e.g., the fourth layer 902) are disposed between the second layer 146 and the third layer 148, each of the one or more layers has a relevant distance BNx that is greater than the first distance BN1 but less than the second distance BN2.

[0086] In some embodiments, a first gap AG1 is provided between the first layer 144 and the third layer 148. In one example, the first gap AG1 is greater than 1 mm and less than or equal to 10 cm. In some embodiments, a second gap AG2 is provided between the third layer 148 and the fourth layer 902. In one example, the second gap AG2 is greater than 1 mm and less than or equal to 10 cm. In some embodiments, a third gap AG3 is provided between the fourth layer 902 and the second layer 146. In one example, the third gap AG3 is greater than 1 mm and less than or equal to 10 cm. In some embodiments where one or more layers (e.g., the fourth layer 902) are disposed between the second layer 146 and the third layer 148, each of the one or more layers has an associated gap AGx between adjacent layers that is greater than 1 mm and less than or equal to 10 cm.

[0087] In some embodiments, a first layer 144 has a first thickness W1, a second layer 146 has a second thickness W2, a third layer 148 has a third thickness W3, and a fourth layer 902 has a fourth thickness W4. In some embodiments, the second thickness W2 is greater than the third thickness W3. In some embodiments, the second thickness W2 is greater than the fourth thickness W4. In some embodiments, the first thickness W1 is greater than the third thickness W3. In some embodiments, the first thickness W1 is greater than the fourth thickness W4. In some embodiments where one or more layers (e.g., the fourth layer 902) are disposed between the second layer 146 and the third layer 148, each of the one or more layers has a related thickness Wx that is less than the second thickness W2. Other arrangements and / or configurations of the first layer 144, the second layer 146, the third layer 148, or the fourth layer 902 are within the scope of this disclosure.

[0088] Figure 10 This is a diagram of example components of a device 1000 according to some embodiments. Device 1000 may correspond to a controller 240 for controlling the processing unit 100 and / or the flow regulation unit 102. Figure 10As shown, device 1000 may include bus 1010, processor 1020, memory 1030, storage component 1040, input component 1050, output component 1060, and communication interface 1070. Bus 1010 includes components that allow communication between components of device 1000. Processor 1020 is implemented in hardware, firmware, or a combination of hardware and software. Processor 1020 is a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or another type of processing component. In some embodiments, processor 1020 includes one or more processors that can be programmed to perform functions. Memory 1030 includes random access memory (RAM), read-only memory (ROM), and / or another type of dynamic or static storage device (e.g., flash memory, magnetic storage, and / or optical storage) that stores information and / or instructions for use by processor 1020.

[0089] In some embodiments, storage component 1040 stores information and / or software related to the operation and use of device 1000. For example, storage component 1040 may include a hard disk (e.g., a magnetic disk, optical disk, magneto-optical disk, and / or solid-state disk), an optical disk (CD), a digital versatile disk (DVD), a floppy disk, a cassette tape, a magnetic tape, and / or another type of non-transitory computer-readable medium, and a corresponding drive. Input component 1050 includes components that allow device 1000 to receive information, for example, via user input (e.g., a touchscreen display, keyboard, keys, mouse, buttons, switches, and / or microphone). Alternatively or additionally, input component 1050 may include sensors for sensing information (e.g., a Global Positioning System (GPS) component, an accelerometer, a gyroscope, and / or an actuator). Output component 1060 includes components that provide output information from device 1000 (e.g., a display, a speaker, and / or one or more light-emitting diodes (LEDs)). The communication interface 1070 includes transceiver-like components (e.g., a transceiver and / or separate receiver and transmitter) that enable the device 1000 to communicate with other devices, such as via a wired connection, a wireless connection, or a combination of wired and wireless connections. The communication interface 1070 allows the device 1000 to receive information from and / or provide information to another device. For example, the communication interface 1070 may include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, a radio frequency (RF) interface, a universal serial bus (USB) interface, a Wi-Fi interface, a cellular network interface, etc.

[0090] In some embodiments, device 1000 may perform one or more processes described herein. Device 1000 may perform these processes based on software instructions stored by processor 1020 on a non-transitory computer-readable medium (e.g., memory 1030 and / or storage component 1040). Computer-readable media are defined herein as non-transitory memory devices. Memory devices include memory space within a single physical storage device or memory space distributed across multiple physical storage devices. Software instructions may be read into memory 1030 and / or storage component 1040 via communication interface 1070 from another computer-readable medium or from another device. When executed, software instructions stored in memory 1030 and / or storage component 1040 may cause processor 1020 to perform one or more processes described herein. Alternatively or additionally, hardwired circuitry may be used in place of or in combination with software instructions to perform one or more processes described herein. Therefore, the implementations described herein are not limited to any particular combination of hardware circuitry and software. Examples are provided as follows. Figure 10 The number and arrangement of components are shown. In fact, with... Figure 10 Compared to the components shown, device 1000 may include additional components, fewer components, different components, or components arranged differently. Alternatively, a set of components of device 1000 (e.g., one or more components) may perform one or more functions described as being performed by another set of components of device 1000.

[0091] Figure 11 An example method 1100 according to some embodiments is shown. At 1102, a gas flow of a first gas is initiated parallel to a wall of the interface module to create an air curtain across an opening defined in the wall. For example, in Figure 7C In this configuration, a gas flow of gas 143 is initiated parallel to the wall 128 of the interface module 104 to create an air curtain 301 across an opening 130 defined in the wall 128. At 1104, the interface door is moved to expose the opening. The air curtain prevents a second gas within the interface module from passing through the opening. For example, in... Figure 7C In the middle, the movable interface gate 131 exposes the opening 130, and the air curtain 301 restricts the gas 125 within the interface module from passing through the opening. At 1106, the wafer is transferred through the opening. For example, in Figure 7E In the middle, wafer 106 is transferred through opening 130. At 1108, the interface gate is moved to cover the opening. For example, in... Figure 7G In step 1110, interface gate 131 is moved to cover opening 130. After moving the interface gate to cover the opening, the gas flow of the first gas is stopped. For example, in... Figure 7GIn this embodiment, after the movable interface gate 131 covers the opening 130, the gas flow of gas 143 is stopped. In some embodiments, the example method 1100 is used in conjunction with the processing device 100. The processing device 100 and the example method 1100 may have other embodiments or alternatives, and the example method 1100 is not limited to the processing device 100. The processing device 100 and the exemplary method 1100 can be used to perform one or a combination of other process operations, such as wafer storage, wafer transfer, etching, deposition, processing, etc. Other arrangements, configurations, and / or operations of the example method 1100 are within the scope of this disclosure.

[0092] Figure 12 An example method 1200 according to some embodiments is shown. At 1202, a gas flow is supplied to a housing disposed within a transfer chamber of an interface module for transferring semiconductor wafers. For example, in... Figure 4 In this configuration, gas flow 400 is supplied to a housing 152 disposed within a transfer chamber 126 of an interface module 104 (FIG. 1) for transferring wafer 106 (FIG. 1). At 1204, the gas flow is passed through a first layer in the housing, wherein the first layer defines a plurality of first apertures. For example, in Figure 4 In this configuration, gas flow 400 passes through a first layer 144 in housing 152 to generate a first gas flow 402, wherein the first layer 144 defines a plurality of first apertures 410. At 1206, the gas flow passes through a second layer in the housing after passing through the first layer. The second layer defines a plurality of polygonal second apertures to create a laminar air curtain flowing out of the housing from the gas flow within the housing. For example, in Figure 4 In this process, gas flow 400 passes through a second layer 146 in housing 152 to become a third gas flow 406 after passing through a first layer 144. The second layer 146 defines a plurality of polygonal second apertures, such as a third aperture 414, to create an air curtain 301 exiting housing 152 from the gas flow 400 within housing 152. In some embodiments, example method 1200 is used in conjunction with processing apparatus 100. Processing apparatus 100 and / or example method 1200 may have other embodiments or alternatives, and example method 1200 is not limited to processing apparatus 100. Processing apparatus 100 and / or example method 1200 can be used to perform one or a combination of other process operations, such as wafer storage, wafer transfer, etching, deposition, processing, etc. Other arrangements, configurations, and / or operations of example method 1200 are within the scope of this disclosure.

[0093] Figure 13 An example method 1300 according to some embodiments is shown. At 1302, the front-opening unified pod (FOUP) is detected as docked to the loading port adjacent to the interface module. For example, in Figure 7AIn this process, a wafer storage device 108 (e.g., FOUP) is mated to a loading port 110 adjacent to the interface module 104 for detection. At 1304, a gas supply source is controlled to initiate a gas flow, wherein the gas flow creates a laminar air curtain across an opening defined in the interface module. For example, controlling... Figure 2 Gas supply source 214 to initiate Figure 4 A gas flow 400, wherein the gas flow 400 creates an air curtain 301 across an opening 130 defined in interface module 104 (FIG. 1). At 1306, after initiating the gas flow by controlling the gas supply source, the interface gate of the interface module adjacent to the FOUP is controlled to expose the opening. For example, in Figure 7B In the process, the gas supply source 214 initiates a gas flow of 400 ( Figure 4 Subsequently, the interface gate 131 of the interface module 104 adjacent to the wafer storage device 108 is controlled to expose the opening 130. At 1308, the operating mechanism is controlled to transfer the semiconductor wafer between the FOUP and the interface module through the opening. For example, in Figure 7E In the first stage, the control mechanism 109 transfers the wafer 106 between the wafer storage device 108 and the interface module 104 through the opening 130. At 1310, the interface gate is controlled to cover the opening. At 1312, after controlling the interface gate to cover the opening, the gas supply source is controlled to stop the gas flow. For example, in... Figure 7G In the middle, after the control interface gate 131 covers the opening 130, the control gas supply source 214 ( Figure 2 To stop the gas flow 400 ( Figure 4 In some embodiments, the example method 1300 is used in conjunction with the processing apparatus 100. The processing apparatus 100 and / or the example method 1300 may have other embodiments or alternatives, and the example method 1300 is not limited to the processing apparatus 100. The processing apparatus 100 and / or the example method 1300 can be used to perform one or a combination of other process operations, such as wafer storage, wafer transfer, etching, deposition, processing, etc. Other arrangements, configurations, and / or operations of the example method 1300 are within the scope of this disclosure.

[0094] According to some embodiments, a method includes initiating a gas flow of a first gas parallel to a wall of an interface module to create an air curtain across an opening defined in the wall. The method includes moving an interface gate to expose the opening, wherein the air curtain prevents a second gas within the interface module from passing through the opening. The method includes transferring a semiconductor wafer through the opening and moving the interface gate to cover the opening. The method includes stopping the gas flow of the first gas after moving the interface gate to cover the opening.

[0095] In some embodiments, the method includes: initiating a gas flow of the second gas in a downward direction within the interface module, wherein the gas flow of the first gas has a first flow velocity, and the gas flow of the second gas has a second flow velocity greater than the first flow velocity.

[0096] In some embodiments, the method includes: discharging the first gas and the second gas from a lower portion of the interface module such that the air curtain is held across the opening in a downward direction within the transfer chamber of the interface module.

[0097] In some embodiments, the method includes supplying a gaseous flow of the first gas into a housing within a transfer chamber of the interface module disposed above the opening. The method includes passing the gaseous flow of the first gas through a first layer in the housing, wherein the first layer defines a first aperture. The method includes passing the gaseous flow of the first gas from the first layer through a second layer in the housing, wherein the second layer defines a second aperture having a second aperture size larger than a first aperture size of the first aperture to restrict and deliver the gaseous flow.

[0098] In some embodiments, the second layer defines a third aperture, and the second aperture and the third aperture are arranged in a grid pattern in the second layer.

[0099] In some embodiments, the second layer defines a plurality of apertures, including the second aperture and the third aperture, and the mesh pattern is an n×m matrix of the plurality of apertures.

[0100] In some embodiments, the first layer defines a third aperture, the third aperture having a third shape different from the first shape of the first aperture.

[0101] In some embodiments, the first gas includes a first gas type, and the second gas includes a second gas type different from the first gas type.

[0102] In some embodiments, the first gas has a lower relative humidity than the second gas.

[0103] According to some embodiments, a method includes supplying a gas flow into a housing disposed within a transfer chamber of an interface module for transferring semiconductor wafers. The method includes passing the gas flow through a first layer in the housing, wherein the first layer defines a plurality of first apertures. The method further includes, after passing the gas flow through the first layer, passing the gas flow through a second layer in the housing, wherein the second layer defines a plurality of polygonal second apertures to create a laminar air curtain exiting the housing from the gas flow within the housing.

[0104] In some embodiments, the method includes holding the first layer below at least one gas nozzle within the housing to define a first gap between the at least one gas nozzle and the first layer. The method includes dispersing a gas flow within the first gap before allowing the gas flow through the first layer, and holding the second layer below the first layer within the housing to define a second gap between the first layer and the second layer. The method includes dispersing a gas flow within the second gap before allowing the gas flow through the second layer.

[0105] In some embodiments, the method includes passing the gas flow through a third layer disposed between the first layer and the second layer in the housing, wherein the third layer defines a plurality of third apertures, and each of the first apertures has a diameter larger than the diameter of each of the third apertures in the third layer.

[0106] In some embodiments, each of the plurality of first apertures has a corresponding first diameter that is less than or equal to a first maximum diameter, and each of the plurality of polygonal second apertures has a second diameter that is greater than the first maximum diameter.

[0107] In some embodiments, each of the plurality of first apertures has a corresponding first diameter less than or equal to a first maximum diameter, each of the plurality of polygonal second apertures has a first side having a first side length greater than the first maximum diameter, and each of the plurality of polygonal second apertures has a second side adjacent to the first side of an adjacent polygonal second aperture.

[0108] In some embodiments, the method includes using a pair of extensions extending from the edge of the housing to restrict the laminar air curtain from leaving the housing.

[0109] In some embodiments, a device includes: a memory including processor-executable instructions; and one or more processors operatively coupled to the memory, performing the following operations when executing the processor-executable instructions. The operations include detecting a front-opening unified pod (FOUP) docking with a loading port adjacent to an interface module. The operations include controlling a gas supply source to initiate a gas flow, wherein the gas flow creates a laminar air curtain across an opening defined in the interface module. The operations include, after controlling the gas supply source to initiate the gas flow, controlling an interface gate of the interface module adjacent to the FOUP to expose the opening, the operations including controlling an operating machine to transfer a semiconductor wafer between the FOUP and the interface module through the opening, and controlling the interface gate to cover the opening. The operations include, after controlling the interface gate to cover the opening, controlling the gas supply source to stop the gas flow.

[0110] In some embodiments, the device performs the following operations: after controlling the interface gate to cover the opening, the operation includes controlling a second interface gate of the interface module to open to expose a second opening defined in the interface module. The operation also includes controlling the operating machine to transfer the semiconductor wafer through the second opening.

[0111] In some embodiments, the device performs the following operations: The operation includes detecting a second FOUP docking with a second loading port adjacent to the interface module. The operation includes controlling the gas supply source to initiate a second gas flow, wherein the second gas flow creates a second laminar air curtain across the second opening. The operation includes, after controlling the gas supply source to initiate the second gas flow, controlling a second interface gate of the interface module adjacent to the second FOUP to expose the second opening. The operation includes controlling the operating machine to transfer the semiconductor wafer through the second opening and controlling the second interface gate to cover the second opening. The operation includes, after controlling the second interface gate to cover the second opening, controlling the gas supply source to stop the second gas flow.

[0112] In some embodiments, the device performs the following operations: the operation includes controlling the gas supply source to initiate the gas flow; the operation includes supplying the gas flow into a housing disposed within a transfer chamber of the interface module for transferring the semiconductor wafer; the operation includes passing the gas flow through a first layer in the housing, the first layer defining a plurality of first apertures; the operation includes passing the gas flow through a second layer in the housing after passing through the first layer, the second layer defining a plurality of polygonal second apertures to create the laminar air curtain from the gas flow within the housing.

[0113] In some embodiments, the device performs the following operations: controlling the gas supply source to initiate a gas flow as a first gas flow; and controlling a fan filter unit to initiate a second gas flow within the interface module, wherein the relative humidity of the first gas is lower than that of the second gas.

[0114] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0115] Although the subject matter has been described in language specific to structural features or methodological actions, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing at least some of the claims.

[0116] Various operations are provided in the embodiments herein. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. It will be appreciated that alternative orders have the benefits of this specification. Furthermore, it should be understood that not all operations are necessarily present in every embodiment provided herein. Furthermore, it should be understood that not all operations are necessary in some embodiments.

[0117] It should be recognized that, for the purposes of simplicity and ease of understanding, the layers, features, elements, etc., described herein are shown with respect to each other at specific dimensions, such as structural dimensions or orientations, and in some embodiments their actual dimensions are quite different from those shown herein. Furthermore, various techniques exist for forming the layers, regions, features, elements, etc., described herein, such as at least one of etching techniques, planarization techniques, implantation techniques, doping techniques, spin techniques, sputtering techniques, growth techniques, or deposition techniques such as CVD.

[0118] Furthermore, “exemplary” is used herein to mean as an example, instance, illustration, etc., and is not necessarily advantageous. As used herein, “or” means inclusive “or”, not exclusive “or.” Furthermore, unless otherwise specified or the context explicitly designates it as singular, “a” and “an” as used herein and in the appended claims should generally be interpreted as meaning “one or more.” Furthermore, “at least one of A and B” and / or similar expressions generally refer to A or B or both A and B. Furthermore, within the scope of use of “comprising,” “having,” “possessing,” “with,” or variations thereof, such terms are intended to encompass in a manner similar to the term “comprising.” Furthermore, unless otherwise specified, “first,” “second,” etc., do not imply temporal, spatial, or sequential aspects. Rather, such terms are used only as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0119] Furthermore, although this disclosure has been shown and described with respect to one or more embodiments, equivalent substitutions and modifications will be made by those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This disclosure includes all such modifications and substitutions and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components (e.g., elements, resources, etc.), unless otherwise stated, the terminology used to describe such components is intended to correspond to any component that performs the specified function of said component (e.g., functionally equivalent), even if not structurally equivalent to the disclosed structure. Moreover, although specific features of this disclosure may be disclosed with respect to only one of several embodiments, such features may be combined with one or more other features of other embodiments, as may be desired and advantageous for any given or particular application.

[0120] Example 1. A method for regulating gas flow, comprising:

[0121] A gas flow of the first gas is initiated parallel to the wall of the interface module to create an air curtain across the opening defined in the wall;

[0122] The movable interface door exposes the opening, wherein the air curtain prevents the second gas within the interface module from passing through the opening;

[0123] The semiconductor wafer is transferred through the opening;

[0124] Move the interface door to cover the opening; and

[0125] After the interface gate is moved to cover the opening, the gas flow of the first gas is stopped.

[0126] Example 2. The method described in Example 1 includes:

[0127] Within the interface module, a gas flow of the second gas is initiated in a downward direction, wherein the gas flow of the first gas has a first flow velocity, and the gas flow of the second gas has a second flow velocity greater than the first flow velocity.

[0128] Example 3. The method described in Example 1 includes:

[0129] The first gas and the second gas are discharged from the lower part of the interface module, such that the air curtain is held in the transfer chamber of the interface module in a downward direction across the opening.

[0130] Example 4. The method described in Example 1 includes:

[0131] The gas flow of the first gas is supplied to the housing inside the transfer chamber of the interface module located above the opening;

[0132] The gas flow of the first gas is passed through a first layer in the housing, wherein the first layer defines a first aperture; and

[0133] The gas flow from the first gas in the first layer is passed through a second layer in the housing, wherein the second layer defines a second aperture having a second aperture size larger than the first aperture size, in order to restrict and convey the gas flow.

[0134] Example 5. According to the method described in Example 4, wherein:

[0135] The second layer defines the third aperture, and

[0136] The second aperture and the third aperture are arranged in a grid pattern in the second layer.

[0137] Example 6. According to the method described in Example 5, wherein:

[0138] The second layer defines a plurality of apertures, including the second aperture and the third aperture, and

[0139] The grid pattern is an n×m matrix of the plurality of apertures.

[0140] Example 7. The method according to Example 4, wherein the first layer defines a third aperture having a third shape different from the first shape of the first aperture.

[0141] Example 8. The method according to Example 1, wherein the first gas includes a first gas type, and the second gas includes a second gas type different from the first gas type.

[0142] Example 9. The method according to Example 1, wherein the first gas has a lower relative humidity than the second gas.

[0143] Example 10. A method for regulating a gas flow, comprising:

[0144] The gas flow is supplied to the housing located within the transfer chamber of the interface module used for transferring semiconductor wafers;

[0145] The gas flow is passed through a first layer in the housing, wherein the first layer defines a plurality of first apertures; and

[0146] After the gas flow passes through the first layer, the gas flow passes through a second layer in the housing, wherein the second layer defines a plurality of polygonal second apertures to create a laminar air curtain flowing out of the housing from the gas flow within the housing.

[0147] Example 11. The method described in Example 10 includes:

[0148] The first layer is held within the housing below at least one gas nozzle to define a first gap between the at least one gas nozzle and the first layer;

[0149] Disperse the gas flow within the first gap before allowing the gas flow to pass through the first layer;

[0150] The second layer is held below the first layer within the housing to define a second gap between the first and second layers; and

[0151] The gas flow within the second gap is dispersed before the gas flow passes through the second layer.

[0152] Example 12. The method described in Example 10 includes:

[0153] The gas flow is passed through a third layer disposed between the first and second layers in the housing, wherein the third layer defines a plurality of third apertures, and each of the first apertures has a diameter larger than the diameter of each of the third apertures in the third layer.

[0154] Example 13. The method described in Example 10, wherein:

[0155] Each of the plurality of first apertures has a corresponding first diameter that is less than or equal to the first maximum diameter, and

[0156] Each of the plurality of polygonal second apertures has a second diameter greater than the first maximum diameter.

[0157] Example 14. The method described in Example 10, wherein:

[0158] Each of the plurality of first apertures has a corresponding first diameter that is less than or equal to the first maximum diameter.

[0159] Each of the plurality of polygonal second apertures has a first side, the first side having a first side length greater than the first maximum diameter, and

[0160] Each of the plurality of polygonal second apertures has a second side, which is adjacent to the first side of the adjacent polygonal second aperture in the plurality of polygonal second apertures.

[0161] Example 15. The method described in Example 10 includes:

[0162] The laminar air curtain is restricted from leaving the housing by a pair of extensions extending from the edge of the housing.

[0163] Example 16. A device for regulating gas flow, comprising:

[0164] Memory, including processor-executable instructions; and

[0165] One or more processors, operatively coupled to the memory, perform the following operations when executing processor-executable instructions:

[0166] The front-opening unified pod (FOUP) is detected to be connected to the loading port from the loading port adjacent to the interface module;

[0167] The gas supply source is controlled to initiate a gas flow, wherein the gas flow creates a laminar air curtain across an opening defined in the interface module;

[0168] After controlling the gas supply source to initiate the gas flow, control the interface gate of the interface module adjacent to the FOUP to expose the opening;

[0169] The control and operation machine transfers semiconductor wafers between the FOUP and the interface module through the opening;

[0170] Control the interface gate to cover the opening; and

[0171] After controlling the interface gate to cover the opening, control the gas supply source to stop the gas flow.

[0172] Example 17. The device according to Example 16, wherein the operation includes:

[0173] After controlling the interface gate to cover the opening, the second interface gate of the interface module is opened to expose the second opening defined in the interface module; and

[0174] The operating machine is controlled to transfer the semiconductor wafer through the second opening.

[0175] Example 18. The device according to Example 17, wherein the operation includes:

[0176] The second FOUP is detected to be connected to the second loading port from the second loading port adjacent to the interface module;

[0177] The gas supply source is controlled to initiate a second gas flow, wherein the second gas flow creates a second laminar air curtain across the second opening;

[0178] After controlling the gas supply source to initiate the second gas flow, control the second interface gate of the interface module adjacent to the second FOUP to expose the second opening;

[0179] The machine is controlled to transfer the semiconductor wafer through the second opening;

[0180] Control the second interface gate to cover the second opening; and

[0181] After controlling the second interface gate to cover the second opening, control the gas supply source to stop the second gas flow.

[0182] Example 19. The device according to Example 16, wherein:

[0183] Controlling the gas supply source to initiate the gas flow includes:

[0184] The gas flow is supplied to a housing located within the transfer chamber of the interface module for transferring the semiconductor wafer;

[0185] The gas flow is passed through a first layer in the housing, the first layer defining a plurality of first apertures; and

[0186] The gas flow passes through a second layer in the housing after passing through the first layer, the second layer defining a plurality of polygonal second apertures to create the laminar air curtain from the gas flow within the housing.

[0187] Example 20. The device according to Example 16, wherein the operation includes:

[0188] Controlling the gas supply source to initiate the gas flow, as a first gas flow of the first gas; and

[0189] The fan filter unit is controlled to initiate a second gas flow of a second gas within the interface module, wherein the relative humidity of the first gas is lower than that of the second gas.

Claims

1. A method for regulating gas flow, comprising: A gas flow of the first gas is initiated parallel to the wall of the interface module to create an air curtain across the opening defined in the wall; The movable interface door exposes the opening, wherein the air curtain prevents the second gas within the interface module from passing through the opening; The semiconductor wafer is transferred through the opening; Move the interface door to cover the opening; and After the interface gate is moved to cover the opening, the gas flow of the first gas is stopped. The method further includes: The gas flow of the first gas is supplied to the housing inside the transfer chamber of the interface module located above the opening; The gas flow of the first gas is passed through a first layer in the housing, wherein the first layer defines a first aperture; and The gas flow from the first gas in the first layer is passed through a second layer in the housing, wherein the second layer defines a second aperture having a second aperture size larger than the first aperture size, in order to restrict and convey the gas flow.

2. The method according to claim 1, comprising: Within the interface module, a gas flow of the second gas is initiated in a downward direction, wherein the gas flow of the first gas has a first flow velocity, and the gas flow of the second gas has a second flow velocity greater than the first flow velocity.

3. The method according to claim 1, comprising: The first gas and the second gas are discharged from the lower part of the interface module, such that the air curtain is held in the transfer chamber of the interface module in a downward direction across the opening.

4. The method according to claim 1, wherein: The second layer defines the third aperture, and The second aperture and the third aperture are arranged in a grid pattern in the second layer.

5. The method according to claim 4, wherein: The second layer defines a plurality of apertures, including the second aperture and the third aperture, and The grid pattern is an n × m matrix of the plurality of apertures.

6. The method according to claim 1, wherein, The first layer defines a third aperture, which has a third shape that is different from the first shape of the first aperture.

7. The method according to claim 1, wherein, The first gas includes a first gas type, and the second gas includes a second gas type that is different from the first gas type.

8. The method according to claim 1, wherein, The first gas has a lower relative humidity than the second gas.

9. A method for regulating a gas flow, comprising: The gas flow is supplied to the housing located within the transfer chamber of the interface module used for transferring semiconductor wafers; The gas flow is passed through a first layer in the housing, wherein the first layer defines a plurality of first apertures; and After the gas flow passes through the first layer, the gas flow passes through a second layer in the housing, wherein the second layer defines a plurality of polygonal second apertures to create a laminar air curtain flowing out of the housing from the gas flow within the housing.

10. The method of claim 9, comprising: The first layer is held within the housing below at least one gas nozzle to define a first gap between the at least one gas nozzle and the first layer; Disperse the gas flow within the first gap before allowing the gas flow to pass through the first layer; The second layer is held below the first layer within the housing to define a second gap between the first and second layers; as well as The gas flow within the second gap is dispersed before the gas flow passes through the second layer.

11. The method of claim 9, comprising: The gas flow is passed through a third layer disposed between the first and second layers in the housing, wherein the third layer defines a plurality of third apertures, and each of the first apertures has a diameter larger than the diameter of each of the third apertures in the third layer.

12. The method according to claim 9, wherein: Each of the plurality of first apertures has a corresponding first diameter that is less than or equal to the first maximum diameter, and Each of the plurality of polygonal second apertures has a second diameter greater than the first maximum diameter.

13. The method according to claim 9, wherein: Each of the plurality of first apertures has a corresponding first diameter that is less than or equal to the first maximum diameter. Each of the plurality of polygonal second apertures has a first side, the first side having a first side length greater than the first maximum diameter, and Each of the plurality of polygonal second apertures has a second side, which is adjacent to the first side of the adjacent polygonal second aperture in the plurality of polygonal second apertures.

14. The method of claim 9, comprising: The laminar air curtain is restricted from leaving the housing by a pair of extensions extending from the edge of the housing.

15. A device for regulating gas flow, comprising: Memory, including processor-executable instructions; and One or more processors, operatively coupled to the memory, perform the following operations when executing processor-executable instructions: The front-opening unified pod (FOUP) is detected to be connected to the loading port adjacent to the interface module; The gas supply source is controlled to initiate a gas flow, wherein the gas flow creates a laminar air curtain across an opening defined in the interface module; After controlling the gas supply source to initiate the gas flow, control the interface gate of the interface module adjacent to the FOUP to expose the opening; The control and operation machine transfers semiconductor wafers between the FOUP and the interface module through the opening; Control the interface gate to cover the opening; and After controlling the interface gate to cover the opening, control the gas supply source to stop the gas flow. Controlling the gas supply source to initiate the gas flow includes: The gas flow is supplied to a housing located within the transfer chamber of the interface module for transferring the semiconductor wafer; The gas flow is passed through a first layer in the housing, the first layer defining a plurality of first apertures; and The gas flow passes through a second layer in the housing after passing through the first layer, the second layer defining a plurality of polygonal second apertures to create the laminar air curtain from the gas flow within the housing.

16. The device according to claim 15, wherein, The operation includes: After controlling the interface gate to cover the opening, the second interface gate of the interface module is opened to expose the second opening defined in the interface module; and The operating machine is controlled to transfer the semiconductor wafer through the second opening.

17. The device according to claim 16, wherein, The operation includes: The second FOUP is detected to be connected to the second loading port from the second loading port adjacent to the interface module; The gas supply source is controlled to initiate a second gas flow, wherein the second gas flow creates a second laminar air curtain across the second opening; After controlling the gas supply source to initiate the second gas flow, control the second interface gate of the interface module adjacent to the second FOUP to expose the second opening; The machine is controlled to transfer the semiconductor wafer through the second opening; Control the second interface gate to cover the second opening; and After controlling the second interface gate to cover the second opening, control the gas supply source to stop the second gas flow.

18. The device according to claim 15, wherein, The operation includes: Controlling the gas supply source to initiate the gas flow, as a first gas flow of the first gas; and The fan filter unit is controlled to initiate a second gas flow of a second gas within the interface module, wherein the relative humidity of the first gas is lower than that of the second gas.

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