Display panel, display device

Abstract

The present disclosure provides a display panel and a display device, belonging to the field of display technology. The display panel includes a plurality of pixel circuits, the pixel circuits include a first transistor and a second transistor, the first transistor is a P-type transistor, and the second transistor is an N-type transistor; the display panel also includes: a semiconductor substrate, including: a plurality of first active area groups, which are respectively located in each pixel circuit unit in a one-to-one correspondence, the first active area group includes a plurality of first active areas arranged at intervals, and different first active areas in the first active area group are used to form the channel area of ​​the first transistor of different pixel circuits in the corresponding pixel circuit unit; a plurality of second active area groups, the second active area group is located on one side of the first active area group along the first direction, including a plurality of second active areas arranged at intervals, and different second active areas in the second active area group are used to form the channel area of ​​the second transistor of different pixel circuits in the corresponding pixel circuit unit. The display panel helps to achieve a high PPI design.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the prior art, a display panel includes a plurality of pixel circuits arranged in an array, and the arrangement of transistors and capacitors contained in each pixel circuit is relatively scattered, which cannot meet the high PPI design requirements of the display panel.

[0003] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The purpose of the present disclosure is to provide a display panel and a display device, which are helpful to achieve high PPI design.

[0005] In order to achieve the above-mentioned invention object, the present invention adopts the following technical solutions:

[0006] According to a first aspect of the present disclosure, a display panel is provided, comprising a plurality of pixel circuit units, wherein the pixel circuit units comprise a plurality of pixel circuits, wherein the pixel circuits comprise a first transistor and a second transistor, wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor;

[0007] The display panel further includes:

[0008] A semiconductor substrate including an active region of each transistor, wherein the active region includes:

[0009] A plurality of first active area groups, each of which is located in each of the pixel circuit units in a one-to-one correspondence, wherein the first active area group includes a plurality of first active areas arranged at intervals, and different first active areas in the first active area group are used to form channel areas of the first transistors corresponding to different pixel circuits in the pixel circuit unit;

[0010] A plurality of second active area groups are respectively located in each of the pixel circuit units in a one-to-one correspondence. In the same pixel circuit unit, the second active area group is located on one side of the first active area group along the first direction. The second active area group includes a plurality of second active areas arranged at intervals. Different second active areas in the second active area group are used to form channel regions of the second transistors corresponding to different pixel circuits in the pixel circuit unit.

[0011] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0012] A first conductive layer is provided on one side of the semiconductor substrate, and the first conductive layer comprises:

[0013] a plurality of first conductive portions, wherein an orthographic projection of the first conductive portion on the semiconductor substrate at least partially overlaps with a plurality of the first active areas in the first active area group, and the first conductive portion is used to form a gate of the first transistor corresponding to different pixel circuits in the pixel circuit unit;

[0014] A plurality of second conductive portions, wherein the orthographic projections of the second conductive portions on the semiconductor substrate at least partially overlap with the plurality of second active areas in the second active area group, and the second conductive portions are used to form gates of the second transistors corresponding to different pixel circuits in the pixel circuit unit.

[0015] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a driving transistor, a first electrode of the first transistor is connected to a second electrode of the second transistor and is connected to a data signal terminal, a second electrode of the first transistor is connected to a first electrode of the second transistor and is connected to a gate of the driving transistor; both the gate of the first transistor and the gate of the second transistor are connected to a gate driving signal terminal; the first electrode of the driving transistor is connected to a first power supply voltage terminal;

[0016] The active region further comprises:

[0017] A plurality of third active area groups, each of which is located in each of the pixel circuit units in a one-to-one correspondence, the third active area group being located on one side of the first active area group along the second direction, the third active area group comprising a plurality of third active areas arranged at intervals, and different third active areas in the third active area group being used to form channel areas of the driving transistors corresponding to different pixel circuits in the pixel circuit unit;

[0018] The first conductive layer further comprises:

[0019] A plurality of third conductive portions, wherein the orthographic projections of the third conductive portions on the semiconductor substrate at least partially overlap with the third active region, and the third conductive portions are used to form the gate of the driving transistor.

[0020] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0021] A second conductive layer is provided on a side of the first conductive layer away from the semiconductor substrate, and the second conductive layer comprises:

[0022] a plurality of first connection portions, wherein the first connection portions connect a first electrode region of the first transistor and a second electrode region of the second transistor in the same pixel circuit;

[0023] A plurality of second connection portions, wherein the second connection portions connect the second electrode region of the first transistor and the second electrode region of the second transistor in the same pixel circuit.

[0024] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0025] A third conductive layer is provided on a side of the second conductive layer away from the semiconductor substrate, and the third conductive layer comprises:

[0026] A plurality of fifth connection portions, wherein the fifth connection portions extend along the second direction, and the fifth connection portions connect the gate of the driving transistor, the first electrode region of the first transistor, and the second electrode region of the second transistor in the same pixel circuit.

[0027] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0028] a plurality of first scan lines, wherein the first scan lines extend along the first direction and are connected to the gate of the second transistor;

[0029] a plurality of second scan lines, wherein the second scan lines extend along the first direction, the second scan lines are located on one side of the second scan lines along the second direction, and the second scan lines are connected to the gate of the first transistor;

[0030] The same first scanning line is distributed in two conductive layers, namely, the second conductive layer and the third conductive layer, and the same second scanning line is distributed in two conductive layers, namely, the second conductive layer and the third conductive layer.

[0031] In an exemplary embodiment of the present disclosure, the second conductive layer further includes:

[0032] a plurality of third connection portions, wherein the third connection portions extend along the first direction, and one end of the third connection portion is connected to the gates of the second transistors of the plurality of pixel circuits in the pixel circuit unit;

[0033] a plurality of fourth connection portions, wherein the fourth connection portions extend along the first direction, and one end of the fourth connection portion is connected to the gates of the first transistors of the plurality of pixel circuits in the pixel circuit unit;

[0034] The third conductive layer further comprises:

[0035] a plurality of sixth connection portions, wherein the sixth connection portions are connected to the third connection portion via holes in two adjacent pixel circuit units arranged along the first direction, the sixth connection portions and the third connection portions are connected to form the first scanning line, and an orthographic projection of the sixth connection portion on the semiconductor substrate at least partially overlaps with an orthographic projection of the fourth connection portion on the semiconductor substrate;

[0036] A plurality of seventh connection parts, wherein the seventh connection parts are connected to the fourth connection part via holes in two adjacent pixel circuit units arranged along the first direction, the seventh connection parts and the fourth connection parts are connected to form the second scanning line, and the orthographic projection of the seventh connection part on the semiconductor substrate at least partially overlaps with the orthographic projection of the third connection part on the semiconductor substrate.

[0037] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0038] a fourth conductive layer, disposed on a side of the third conductive layer away from the semiconductor substrate, the fourth conductive layer comprising a plurality of first power lines, the first power lines extending along the second direction, arranged at intervals along the first direction, and electrically connected to the first electrode region of the driving transistor;

[0039] The orthographic projection of the first power line on the semiconductor substrate is located on a side of the second active area group away from the first active area group.

[0040] In an exemplary embodiment of the present disclosure, the plurality of pixel circuit units include a plurality of first pixel circuit units, a plurality of second pixel circuit units, a plurality of third pixel circuit units, and a plurality of fourth pixel circuit units;

[0041] The first pixel circuit units and the second pixel circuit units are arranged at intervals along the first direction, and adjacent first pixel circuit units and second pixel circuit units are mirror-symmetrical;

[0042] The first pixel circuit units and the third pixel circuit units are arranged at intervals along the second direction, and adjacent first pixel circuit units and the third pixel circuit units are mirror-symmetrical;

[0043] The fourth pixel circuit unit and the third pixel circuit unit are arranged at intervals along the first direction, and at the same time, the fourth pixel circuit unit and the second pixel circuit unit are arranged at intervals along the second direction, and the adjacent fourth pixel circuit unit and the third pixel circuit unit are mirror-symmetrical, and at the same time, the adjacent fourth pixel circuit unit and the second pixel circuit unit are mirror-symmetrical.

[0044] In an exemplary embodiment of the present disclosure, one first pixel circuit unit, one second pixel circuit unit, one third pixel circuit unit and one fourth pixel circuit unit constitute a unit group, and a plurality of the unit groups are arranged in an array along the first direction and the second direction;

[0045] The first direction is a row direction, the second direction is a column direction, and the unit groups in two adjacent columns share the same first power line.

[0046] In an exemplary embodiment of the present disclosure, the third conductive layer further includes:

[0047] a plurality of eighth connection portions, wherein the eighth connection portions are connected to first electrode regions of driving transistors of a plurality of pixel circuits in the pixel circuit unit;

[0048] In the same pixel circuit unit, at least a portion of an orthographic projection of the eighth connection portion on the semiconductor substrate is located on a side of the third active area group away from the first active area group;

[0049] The first power line is connected to the eighth connection portion via hole.

[0050] In an exemplary embodiment of the present disclosure, the fourth conductive layer further includes:

[0051] A plurality of data lines are provided, wherein the data lines extend along the second direction and are arranged along the first direction, and the data lines are connected to the second connecting portion via holes.

[0052] In an exemplary embodiment of the present disclosure, the third conductive layer further includes:

[0053] A plurality of metal blocks, wherein the orthographic projections of the metal blocks on the semiconductor substrate at least partially overlap with the orthographic projections of the data lines on the semiconductor substrate, and the data lines are connected to the metal blocks via holes.

[0054] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a capacitor, wherein the capacitor is connected to a ground terminal and a gate of the driving transistor;

[0055] The display panel further includes:

[0056] A fifth conductive layer is provided on a side of the fourth conductive layer away from the semiconductor substrate, and the fifth conductive layer comprises:

[0057] a plurality of first conductive blocks, wherein the first conductive blocks are grounded, different first conductive blocks are used to form first plates of the capacitors in different pixel circuits, and an orthographic projection of the first conductive block on the semiconductor substrate at least partially overlaps with an orthographic projection of the first conductive portion, the second conductive portion, or the third conductive portion on the semiconductor substrate;

[0058] All of the first conductive blocks of the display panel are connected as one.

[0059] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0060] A sixth conductive layer is provided on a side of the fifth conductive layer away from the semiconductor substrate, and the sixth conductive layer comprises:

[0061] a plurality of second conductive blocks, wherein the orthographic projections of the second conductive blocks on the semiconductor substrate are located within the orthographic projections of the first conductive blocks on the semiconductor substrate, and different first conductive blocks are used to form the second plates of the capacitors in different pixel circuits;

[0062] a seventh conductive layer, disposed between the fourth conductive layer and the fifth conductive layer, wherein the orthographic projection of the seventh conductive layer on the semiconductor substrate does not overlap with the orthographic projection of the fifth conductive layer on the semiconductor substrate, and the seventh conductive layer comprises:

[0063] A plurality of twelfth connection portions, wherein the twelfth connection portions are electrically connected to the second electrode region of the driving transistor.

[0064] In an exemplary embodiment of the present disclosure, the display panel further includes an eighth conductive layer, which is disposed on a side of the sixth conductive layer away from the semiconductor substrate, and the eighth conductive layer includes:

[0065] A plurality of thirteenth connecting portions, wherein the thirteenth connecting portions are electrically connected to the gate of the driving transistor in the same pixel circuit and the second plate of the capacitor.

[0066] In an exemplary embodiment of the present disclosure, a single pixel circuit unit includes three pixel circuits, and the three pixel circuits correspond to a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit respectively;

[0067] The number of the first active areas in a single pixel circuit unit is three, the three first active areas are arranged at intervals along the first direction, and the three first active areas are used to form a channel area of ​​a first transistor of the first sub-pixel circuit, a channel area of ​​a first transistor of the second sub-pixel circuit, and a channel area of ​​a first transistor of the third sub-pixel circuit in sequence along a direction away from the second active area group;

[0068] The number of the second active areas in a single pixel circuit unit is three, the three second active areas are arranged at intervals along the first direction, and the three second active areas are used to form the channel area of ​​the second transistor of the first sub-pixel circuit, the channel area of ​​the second transistor of the second sub-pixel circuit, and the channel area of ​​the second transistor of the third sub-pixel circuit in sequence along the direction away from the first active area group.

[0069] In an exemplary embodiment of the present disclosure, the number of the third active areas in a single pixel circuit unit is three; among the three third active areas, two of the third active areas are arranged at intervals on one side of the second active area group in the second direction, and are used to form the channel region of the driving transistor of the third sub-pixel circuit and the channel region of the driving transistor of the first sub-pixel circuit in sequence along the direction away from the second active area group, and the other third active area is located on one side of the first active area group in the second direction, and is used to form the channel region of the driving transistor of the second sub-pixel circuit.

[0070] In an exemplary embodiment of the present disclosure, the semiconductor substrate further includes:

[0071] a first conductor region, located between the third active region group and the first active region group along the second direction, the first conductor region being used to form a first substrate electrode;

[0072] a second conductor region, located between the first conductor region and the first active region group along the second direction, the second conductor region being used to form a second substrate electrode;

[0073] The third conductive layer further comprises:

[0074] A sixteenth connection portion extending along the first direction, an orthographic projection of the sixteenth connection portion on the semiconductor substrate at least partially overlapping with the first conductor region, and the sixteenth connection portion being connected to a via hole of the first conductor region;

[0075] The seventeenth connection portion extends along the first direction, the orthographic projection of the seventeenth connection portion on the semiconductor substrate at least partially overlaps with the second conductor region, and the seventeenth connection portion is connected to the second conductor region via a via.

[0076] According to a second aspect of the present disclosure, a display device is provided, comprising the display panel described in the first aspect.

[0077] The display panel provided by the present disclosure includes a plurality of pixel circuit units, each of which includes a plurality of pixel circuits. The pixel circuit includes a first transistor and a second transistor, the first transistor is a type transistor, and the second transistor is a type transistor. The display panel also includes a semiconductor substrate, and the semiconductor substrate includes a first active area group and a second active area group. Different first active areas in the first active area group are used to form channel areas of first transistors in different pixel circuits, and different second active areas in the second active area group are used to form channel areas of second transistors. That is, the present disclosure places transistors of the same type in different pixel circuits in the same area, which helps to reduce the space occupied by pixel circuits and realize a high PPI design of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0079] Figure 1 is a schematic diagram of a circuit structure of a pixel circuit in an exemplary embodiment of the present disclosure;

[0080] Figure 2 is a structural layout of an active region of a semiconductor substrate in an exemplary embodiment of the present disclosure;

[0081] Figure 3 is a structural layout of an N-type substrate region of a semiconductor substrate in an exemplary embodiment of the present disclosure;

[0082] Figure 4 is a first conductive layer structure layout in an exemplary embodiment of the present disclosure;

[0083] Figure 5 It is a stacked layout of a semiconductor substrate and a first conductive layer in an exemplary embodiment of the present disclosure;

[0084] Figure 6 is a structural layout of the N ion implantation region in an exemplary embodiment of the present disclosure;

[0085] Figure 7 is a structural layout of a P ion implantation region in an exemplary embodiment of the present disclosure;

[0086] Figure 8 is a second conductive layer structure layout in an exemplary embodiment of the present disclosure;

[0087] Fig. 9 It is a superimposed layout of a semiconductor substrate, a first conductive layer, and a second conductive layer in an exemplary embodiment of the present disclosure;

[0088] Fig.10 is a third conductive layer structure layout in an exemplary embodiment of the present disclosure;

[0089] Fig.11It is a superposition pattern of a semiconductor substrate, a first conductive layer, a second conductive layer and a third conductive layer in an exemplary embodiment of the present disclosure;

[0090] Fig.12 is a twelfth conductive layer structure layout in an exemplary embodiment of the present disclosure;

[0091] Fig.13 It is a superposition pattern of a semiconductor substrate, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer in an exemplary embodiment of the present disclosure;

[0092] Fig.14 is a fifth conductive layer structure layout in an exemplary embodiment of the present disclosure;

[0093] Fig.15 It is a superposition pattern of a semiconductor substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer in an exemplary embodiment of the present disclosure;

[0094] Fig.16 It is a superimposed layout of the sixth conductive layer and the seventh conductive layer in the exemplary embodiment of the present disclosure;

[0095] Fig.17 is an eighth conductive layer structure layout in the exemplary embodiment of the present disclosure;

[0096] Fig.18 It is a superimposed layout of a semiconductor substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer and an eighth conductive layer in an exemplary embodiment of the present disclosure.

[0097] The main components in the figure are described as follows:

[0098] T1-first transistor; T2-second transistor; T3-driving transistor; Vdata-data signal terminal; Scan-gate driving signal terminal; GND-ground terminal; VDD-first power supply voltage terminal; C-capacitor; C1-first electrode plate; C2-second electrode plate; Vcom-second power supply terminal; 10-first pixel circuit unit; 20-second pixel circuit unit; 30-third pixel circuit unit; 40-fourth pixel circuit unit; 1-first sub-pixel circuit; 2-second sub-pixel circuit; 3-third sub-pixel circuit; 100-semiconductor substrate; 101-N-type substrate area; 110-first active area group; 111-first active area; 120-second active area group; 121-second active area; 130-third active area group; 131-third active area; 140-first conductor area; 150-second conductor area; 200-first conductive layer; 210-first conductive part; 220-second conductive part; 23 0-third conductive part; 300-second conductive layer; 310-first connecting part; 320-second connecting part; 330-third connecting part; 340-fourth connecting part; 350-fifteenth connecting part; 360-sixteenth connecting part; 370-seventeenth connecting part; 400-third conductive layer; 410-fifth connecting part; 420-sixth connecting part; 430-seventh connecting part; 440-eighth connecting part; 450-metal block; 460-ninth connecting part; 470-tenth connection part; 480-fourteenth connection part; GL1-first scan line; GL2-second scan line; 500-fourth conductive layer; VDD-first power line; DL-data line; 510-eleventh connection part; 600-fifth conductive layer; C1-first conductive block; 700-sixth conductive layer; C2-second conductive block; 800-seventh conductive layer; 810-twelfth connection part; 900-eighth conductive layer; 910-thirteenth connection part. DETAILED DESCRIPTION

[0099] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure.

[0100] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0101] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring the main technical ideas of the present disclosure.

[0102] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0103] The terms "a", "an", "the" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0104] In the related art, the display panel includes a plurality of scan lines and a plurality of data lines that intersect each other, and the scan lines and the data lines intersect to define a plurality of pixel areas. A plurality of pixel circuits are located in each pixel area in a one-to-one correspondence. In this arrangement, each pixel circuit occupies a large space and cannot achieve a higher-demand high PPI design.

[0105] like Figure 1 and Figure 2 As shown, in an embodiment of the present disclosure, a display panel is provided, including a plurality of pixel circuit units, the pixel circuit unit includes a plurality of pixel circuits, the pixel circuit includes a first transistor T1 and a second transistor T2, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor;

[0106] The display panel also includes:

[0107] The semiconductor substrate 100 includes active regions of various transistors, and the active regions include:

[0108] A plurality of first active area groups 110 are respectively located in each pixel circuit unit in a one-to-one correspondence, and the first active area group 110 includes a plurality of first active areas 111 arranged at intervals, and different first active areas 111 in the first active area group 110 are used to form channel regions of first transistors T1 of different pixel circuits in the corresponding pixel circuit unit;

[0109] A plurality of second active area groups 120 are respectively located in each pixel circuit unit in a one-to-one correspondence. In the same pixel circuit unit, the second active area group 120 is located on one side of the first active area group 110 along the first direction X. The second active area group 120 includes a plurality of second active areas 121 arranged at intervals. Different second active areas 121 in the second active area group 120 are used to form channel regions of second transistors T2 of different pixel circuits in the corresponding pixel circuit unit.

[0110] The display panel provided by the present disclosure includes a plurality of pixel circuit units, each of which includes a plurality of pixel circuits. The pixel circuit includes a first transistor T1 and a second transistor T2, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The display panel also includes a semiconductor substrate 100, and the semiconductor substrate 100 includes a first active area group 110 and a second active area group 120. Different first active areas 111 in the first active area group 110 are used to form the channel area of ​​the first transistor T1 in different pixel circuits, and different second active areas 121 in the second active area group 120 are used to form the channel area of ​​the second transistor T2. That is, the present disclosure places transistors of the same type in different pixel circuits in the same area, which helps to reduce the space occupied by the pixel circuit and realize the high PPI design of the display panel.

[0111] The components of the display panel provided in the embodiment of the present disclosure are described in detail below with reference to the accompanying drawings:

[0112] like Figure 1 As shown, the display panel provided by the present disclosure may be an OLED display panel. The display panel includes a plurality of pixel circuit units, each pixel circuit unit includes a plurality of pixel circuits, and the number of pixel circuits contained in a single pixel circuit unit may be two, three, four or more. Preferably, a single pixel circuit unit includes three pixel circuits.

[0113] Figure 1The present invention discloses a circuit structure schematic diagram of a pixel circuit in an exemplary embodiment. The pixel circuit includes a first transistor T1, a second transistor T2, a driving transistor T3 and a capacitor C. The first electrode of the first transistor T1 is connected to the second electrode of the second transistor T2, and is connected to the data signal terminal Vdata. The second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2, and is connected to the gate of the driving transistor T3. The gate of the first transistor T1 and the gate of the second transistor T2 are both connected to the gate drive signal terminal Scan. The gate of the first transistor T1 is connected to the gate drive signal terminal Scan-P of the P-type transistor, and the gate of the second transistor T2 is connected to the gate drive signal terminal Scan-N of the N-type transistor. The capacitor C connects the gate of the driving transistor T3 and the ground terminal GND. The first electrode of the driving transistor T3 is connected to the first power supply voltage terminal VDD. The pixel circuit can be connected to a light-emitting unit OLED, which can be connected between the second electrode of the driving transistor T3 and the second power supply voltage terminal VSS. The first transistor T1 can be a P-type transistor, and the second transistor T2 and the driving transistor T3 can be N-type transistors.

[0114] In addition, it should be noted that the type of transistor used in the embodiments of the present disclosure is not limited. It is only necessary to connect the electrodes of the selected type of transistors with reference to the electrodes of the corresponding transistors in the embodiments of the present disclosure, and to make the corresponding voltage terminals provide corresponding high voltages or low voltages. For example, for an N-type transistor, its input terminal is a drain and its output terminal is a source, and its control terminal is a gate; for a P-type transistor, its input terminal is a source and its output terminal is a drain, and its control terminal is a gate. For different types of transistors, the level of the control signal at its control terminal is also different. For example, for an N-type transistor, when the control signal is at a high level, the N-type transistor is in a conducting state; and when the control signal is at a low level, the N-type transistor is in a cut-off state. For a P-type transistor, when the control signal is at a low level, the P-type transistor is in a conducting state; and when the control signal is at a high level, the P-type transistor is in a cut-off state. In the present disclosure, each transistor can be manufactured using a CMOS process.

[0115] like Figure 2 As shown, the plurality of pixel circuit units include a plurality of first pixel circuit units 10, a plurality of second pixel circuit units 20, a plurality of third pixel circuit units 30 and a plurality of fourth pixel circuit units 40;

[0116] The first pixel circuit units 10 and the second pixel circuit units 20 are arranged at intervals along the first direction X, and the adjacent first pixel circuit units 10 and the second pixel circuit units 20 are mirror-symmetrical;

[0117] The first pixel circuit units 10 and the third pixel circuit units 30 are arranged at intervals along the second direction Y, and the adjacent first pixel circuit units 10 and the third pixel circuit units 30 are mirror-symmetrical;

[0118] The fourth pixel circuit unit 40 and the third pixel circuit unit 30 are arranged at intervals along the first direction X. At the same time, the fourth pixel circuit unit 40 and the second pixel circuit unit 20 are arranged at intervals along the second direction Y. The adjacent fourth pixel circuit units 40 and the third pixel circuit units 30 are mirror-symmetrical. At the same time, the adjacent fourth pixel circuit units 40 and the second pixel circuit units 20 are mirror-symmetrical.

[0119] That is, a first pixel circuit unit 10, a second pixel circuit unit 20, a third pixel circuit unit 30 and a fourth pixel circuit unit 40 form a unit group, and the first pixel circuit unit 10, the second pixel circuit unit 20, the third pixel circuit unit 30 and the fourth pixel circuit unit 40 in each unit group are arranged in a field shape. A plurality of unit groups are arranged in an array.

[0120] In an exemplary embodiment, the display panel further includes a first conductive layer 200 . Figure 2 FIG. 1 is a structural layout diagram of a display panel semiconductor substrate 100 in an exemplary embodiment. Figure 4 FIG. 2 is a structural diagram of the first conductive layer 200 in an exemplary embodiment. Figure 5 for Figure 4 The first conductive layer 200 and Figure 2 The semiconductor substrate 100 has an overlay structure layout.

[0121] like Figure 2 As shown, the semiconductor substrate 100 includes active areas of each transistor, and the active areas include a plurality of first active area groups 110 and a plurality of second active area groups 120. The plurality of first active area groups 110 are respectively located in each pixel circuit unit in a one-to-one correspondence. The plurality of second active area groups 120 are respectively located in each pixel circuit unit in a one-to-one correspondence. In the same pixel circuit unit, the second active area group 120 is located on one side of the first active area group 110 along the first direction X.

[0122] The first active area group 110 includes a plurality of first active areas 111 arranged at intervals. Different first active areas 111 in the first active area group 110 are used to form channel regions of first transistors T1 of different pixel circuits in corresponding pixel circuit units.

[0123] In some embodiments, the plurality of first active areas 111 in the first active area group 110 are arranged at intervals along a first direction X, and the first direction X may be a row direction. The number of first active areas 111 included in the first active area group 110 may be set according to the number of pixel circuits included in the pixel circuit unit and the number of first transistors T1 (P-type transistors) included in the pixel circuit. Figure 2 The pixel circuit shown includes a first transistor T1. When the pixel circuit unit includes three pixel circuits, the number of first active areas 111 included in the first active area group 110 is 3×1=3. The three pixel circuits may correspond to the first sub-pixel circuit 1, the second sub-pixel circuit 2 and the third sub-pixel circuit 3, respectively. Among them, the first sub-pixel circuit 1 may be driven to emit a first color light, the second sub-pixel circuit 2 may be driven to emit a second color light, and the third sub-pixel circuit 3 may be driven to emit a third color light. The first color light, the second color light and the second color light may correspond to red light, green light and blue light, respectively, and the colors corresponding to the three may be interchangeable. In one embodiment, the three first active areas 111 in the pixel circuit unit are used to form the channel area of ​​the first transistor T1 of the first sub-pixel circuit 1, the channel area of ​​the first transistor T1 of the second sub-pixel circuit 2 and the channel area of ​​the first transistor T1 of the third sub-pixel circuit 3 in sequence along the direction away from the second active area group 120. In the figure, reference numeral 111 -T1 -m indicates that the first active region 111 is used to form a channel region of a first transistor T1 of the m-th sub-pixel circuit, and m may be 1, 2 or 3.

[0124] In some embodiments, the plurality of first active regions 111 in the first pixel circuit unit 10 may extend along the second direction Y and be connected to the corresponding first active regions 111 in the third pixel circuit unit 30 as a whole.

[0125] In the present disclosure, each active region may form a doped region of the corresponding transistor in addition to forming a channel region of the corresponding transistor, wherein the channel region refers to the region of the active region of the transistor covered by the gate. The doped region refers to the first polar region and the second polar region of the transistor.

[0126] The second active area group 120 includes a plurality of second active areas 121 arranged at intervals. Different second active areas 121 in the second active area group 120 are used to form channel regions of second transistors T2 of different pixel circuits in corresponding pixel circuit units.

[0127] In some embodiments, the plurality of second active areas 121 in the second active area group 120 are arranged at intervals along the first direction X. The number of second active areas 121 included in the second active area group 120 can be set according to the number of pixel circuits included in the pixel circuit unit and the number of second transistors T2 (N-type transistors) included in the pixel circuit. Figure 2The pixel circuit shown includes a second transistor T2. When the pixel circuit unit includes three pixel circuits, the number of second active areas 121 included in the second active area group 120 is 3×1=3. As above, the three pixel circuits may correspond to the first sub-pixel circuit 1, the second sub-pixel circuit 2, and the third sub-pixel circuit 3, respectively. In one embodiment, the three second active areas 121 in the pixel circuit unit are used to form the channel area of ​​the second transistor T2 of the first sub-pixel circuit 1, the channel area of ​​the second transistor T2 of the second sub-pixel circuit 2, and the channel area of ​​the second transistor T2 of the third sub-pixel circuit 3, respectively, along the direction away from the first active area group 110. In the figure, the label 121-T2-m indicates that the second active area 121 is used to form the channel area of ​​the second transistor T2 of the mth sub-pixel circuit, and m can be 1, 2 or 3.

[0128] In some embodiments, the plurality of second active regions 121 in the first pixel circuit unit 10 may extend along the second direction Y and be connected to the corresponding second active regions 121 in the third pixel circuit unit 30 as a whole.

[0129] The active area also includes a plurality of third active area groups 130, which are respectively located in each pixel circuit unit in a one-to-one correspondence. The third active area group 130 includes a plurality of third active areas 131 arranged at intervals. Different third active areas 131 in the third active area group 130 are used to form channel regions of driving transistors T3 of different pixel circuits in the corresponding pixel circuit unit.

[0130] The number of the third active areas 131 included in the third active area group 130 can be set according to the number of pixel circuits included in the pixel circuit unit. Figure 2 As shown, when the pixel circuit unit includes three pixel circuits, the number of third active areas 131 included in the third active area group 130 is 3×1=3. Similarly, the three pixel circuits may correspond to the first sub-pixel circuit 1, the second sub-pixel circuit 2 and the third sub-pixel circuit 3 respectively.

[0131] In one embodiment, the three third active areas 131 in the pixel circuit unit are arranged in a roughly "L" shape. Specifically, among the three third active areas 131, two of the third active areas 131 are arranged at intervals on one side of the second active area group 120 in the second direction Y, and are used to form the channel region of the driving transistor T3 of the third sub-pixel circuit 3 and the channel region of the driving transistor T3 of the first sub-pixel circuit 1 in sequence along the direction away from the second active area group 120. Another third active area 131 is arranged on one side of the first active area group 110 in the second direction Y, and is used to form the channel region of the driving transistor T3 of the second sub-pixel circuit 2. In the figure, the label 131-T3-m indicates that the third active area 131 is used to form the channel region of the driving transistor T3 of the mth sub-pixel circuit, and m can be 1, 2 or 3.

[0132] In some embodiments, the third active area 131 located at one side of the first active area group 110 in the first pixel circuit unit 10 in the second direction Y may extend along the second direction Y and be connected to the corresponding third active area 131 in the third pixel circuit as a whole.

[0133] like Figure 3 As shown, in the present disclosure, the semiconductor substrate 100 may be a silicon-based semiconductor substrate 100. The substrate may include an N-type substrate region 101 and a P-type substrate region, an N-type transistor is formed in the P-type substrate region, and a P-type transistor is formed in the N-type substrate region 101. N-well implantation may be performed on the silicon-based semiconductor substrate 100 to form an N-well region, i.e., the N-type substrate region 101.

[0134] The first active area group 110 is located in the N-type substrate area 101, and the second active area group 120 and the third active area group 130 are located in the P-type substrate area. Each active area is used to form a channel area, a first polar area, and a second polar area of ​​each transistor. The first active area 111 includes a channel area, a first polar area, and a second polar area for forming a first transistor T1 (P-type transistor). The second active area 121 includes a channel area, a first polar area, and a second polar area for forming a second transistor T2 (N-type transistor). The third active area 131 includes a channel area, a first polar area, and a second polar area for forming a driving transistor T3 (N-type transistor).

[0135] like Figure 2 As shown, in some embodiments, the semiconductor substrate 100 further includes a plurality of first conductor regions 140 and a plurality of second conductor regions 150. The plurality of first conductor regions 140 are located in each pixel circuit unit in a one-to-one correspondence. The first conductor region 140 is located between the third active region group 130 and the first active region group 110 along the second direction Y. The first conductor region 140 in the first pixel circuit unit 10 extends along the first direction X and is connected to the first conductor region 140 in the second pixel circuit unit 20 as a whole. The first conductor region 140 is located in the P-type substrate region.

[0136] A plurality of second conductor regions 150 are located in each pixel circuit unit in a one-to-one correspondence. The second conductor region 150 is located between the first conductor region 140 and the first active region group 110 along the second direction Y. The second conductor region 150 in the first pixel circuit unit 10 extends along the first direction X and is connected to the second conductor region 150 in the second pixel circuit unit 20 as a whole. The second conductor region 150 is located in the N-type substrate region 101.

[0137] In the present disclosure, the first conductor region 140 and the second conductor region 150 are used to form a substrate electrode. The first conductor region 140 may be P-doped, and the second conductor region 150 may be N-doped.

[0138] like Figure 4 , Figure 5 As shown, the first conductive layer 200 is disposed on one side of the semiconductor substrate 100, and the first conductive layer 200 includes a plurality of first conductive portions 210 and a plurality of second conductive portions 220. The plurality of first conductive portions 210 are respectively located in each pixel circuit unit in a one-to-one correspondence. The orthographic projection of the first conductive portion 210 on the semiconductor substrate 100 at least partially overlaps with the plurality of first active areas 111 in the first active area group 110, and the first conductive portion 210 is used to form the gate of the first transistor T1 of different pixel circuits in the corresponding pixel circuit unit. The plurality of second conductive portions 220 are respectively located in each pixel circuit unit in a one-to-one correspondence, and the orthographic projection of the second conductive portion 220 on the semiconductor substrate 100 at least partially overlaps with the plurality of second active areas 121 in the second active area group 120, and the second conductive portion 220 is used to form the gate of the second transistor T2 of different pixel circuits in the corresponding pixel circuit unit.

[0139] In the present disclosure, the first conductive portion 210 is used to form the gate of the first transistor T1 included in different pixel circuits in the corresponding pixel circuit unit, and the second conductive portion 220 is used to form the gate of the second transistor T2 included in different pixel circuits in the corresponding pixel circuit unit. That is, the gates of the first transistor T1 of different pixel circuits in the same pixel circuit unit are shared, and the gates of the second transistor T2 of different pixel circuits in the same pixel circuit unit are shared. This helps to reduce the size of the pixel circuit and realize the high PPI design of the display panel.

[0140] In some embodiments, the first conductive portion 210 in the first pixel circuit unit 10 may extend along the first direction X to be connected to the corresponding first conductive portion 210 in the second pixel circuit unit 20. The second conductive portion 220 in the first pixel circuit unit 10 may extend along the first direction X to be connected to the corresponding second conductive portion 220 in the second pixel circuit unit 20 in the adjacent unit group.

[0141] In some embodiments, the first conductive layer 200 further includes a plurality of third conductive portions 230 , the orthographic projections of the third conductive portions 230 on the semiconductor substrate 100 at least partially overlap with the third active region 131 , and the third conductive portions 230 are used to form the gate of the driving transistor T3 .

[0142] In the present disclosure, the area of ​​the active region covered by the corresponding conductive portion forms the channel region of the corresponding transistor, and the area not covered by the corresponding conductive portion forms the first polar region and the second polar region of the transistor.

[0143] The transistors formed in the present disclosure can be prepared by using CMOS technology. Specifically, a P-type semiconductor substrate 100 can be provided first, and N-type ions can be implanted into selected areas of the P-type semiconductor substrate 100 to form an N-well area. In this way, the area where the N-type ions are not implanted is the P-type substrate area, and the area where the N-type ions are implanted is the N-type substrate area 101. Figure 3 shown.

[0144] like Figure 6 and Figure 7 As shown, a gate insulating layer and a first conductive layer 200 are then formed, and the gate insulating layer and the first conductive layer 200 cover the channel regions of each transistor and expose the first electrode region and the second electrode region of each transistor. It should be noted that the first conductor region 140 and the second conductor region 150 are not covered by the gate insulating layer and the first conductive layer 200. Then, P-type ion implantation is performed on each active region of the N-type substrate region 101, as shown in FIG. Figure 7 The middle gray covered area forms a P-type transistor, such as the first transistor T1. N-type particles are implanted into each active area of ​​the P-type substrate region, such as Figure 6 The midpoint filling area forms an N-type transistor, such as the second transistor T2 and the driving transistor T3. It should be noted that when performing P-type ion implantation, the first conductor region 140 can also be implanted with P-type particles to form a first substrate electrode. When performing N-type ion implantation, the second conductor region 150 can also be implanted with N-type ions to form a second substrate electrode.

[0145] like Figure 8 and Fig. 9 As shown, Figure 8 is the third conductive layer structure layout, Fig. 9 for Figure 5 Chinese version and Figure 8 Structural layout after superposition. In some embodiments of the present disclosure, the display panel further includes a second conductive layer 300, which is disposed on a side of the first conductive layer 200 away from the semiconductor substrate 100. The second conductive layer 300 includes a plurality of first connecting portions 310 and a plurality of second connecting portions 320. The first connecting portion 310 connects the first polar region of the first transistor T1 and the second polar region of the second transistor T2 in the same pixel circuit. The second connecting portion 320 connects the second polar region of the first transistor T1 and the second polar region of the second transistor T2 in the same pixel circuit.

[0146] like Figure 8As shown, in a single pixel circuit unit, the number of first connection parts 310 is three, and the three first connection parts 310 are respectively connected to the first electrode area of ​​the first transistor T1 and the second electrode area of ​​the second transistor T2 in the first sub-pixel circuit 1, the first electrode area of ​​the first transistor T1 and the second electrode area of ​​the second transistor T2 in the second sub-pixel circuit 2, and the first electrode area of ​​the first transistor T1 and the second electrode area of ​​the second transistor T2 in the third sub-pixel circuit 3. The number of second connection parts 320 is also three, and the three second connection parts 320 are respectively connected to the second electrode area of ​​the first transistor T1 and the first electrode area of ​​the second transistor T2 in the first sub-pixel circuit 1, the second electrode area of ​​the first transistor T1 and the first electrode area of ​​the second transistor T2 in the second sub-pixel circuit 2, and the second electrode area of ​​the first transistor T1 and the first electrode area of ​​the second transistor T2 in the third sub-pixel circuit 3.

[0147] Specifically, since the first active areas 111 and the second active areas 121 in the first pixel circuit unit 10 and the third pixel circuit unit 30 can be connected as one, the second polar region of each first transistor T1 in the first pixel circuit unit 10 and the first polar region of each first transistor T1 in the third pixel circuit unit 30 are shared, and the first polar region of each second transistor T2 in the first pixel circuit unit and the first polar region of each second transistor T2 in the third pixel circuit unit 30 are shared. Accordingly, the second connecting portions 320 of the first pixel circuit unit 10 and the third pixel circuit unit 30 can also be shared.

[0148] In some embodiments, the second conductive layer 300 further includes a plurality of third connecting portions 330 and a plurality of fourth connecting portions 340, wherein the third connecting portions 330 extend along the first direction X, and the third connecting portions 330 are connected to the gates of the second transistors T2 of the plurality of pixel circuits in the pixel circuit unit, and the fourth connecting portions 340 extend along the first direction X, and the fourth connecting portions 340 are connected to the gates of the first transistors T1 of the plurality of pixel circuits in the pixel circuit unit. Since the first conductive portions 210 in the adjacent first pixel circuit unit 10 and the second pixel circuit unit 20 can be connected as a whole, therefore, the fourth connecting portions 340 in the first pixel circuit unit 10 and the second pixel circuit unit 20 can also be connected as a whole.

[0149] The second conductive layer 300 further includes a fifteenth connecting portion 350 , which is connected to the gate of the driving transistor T3 in the second sub-pixel circuit 2 . The fifteenth connecting portion 350 can be used as a switching line to connect the gate of the driving transistor T3 in the second sub-pixel circuit 2 and the second electrode plate C2 of the capacitor C.

[0150] The second conductive layer 300 further includes a sixteenth connection portion 360 and a seventeenth connection portion 370. The sixteenth connection portion 360 extends along the first direction X, and the orthographic projection of the sixteenth connection portion 360 on the semiconductor substrate 100 at least partially overlaps with the first conductor region 140. The sixteenth connection portion 360 connects the first conductor region 140 and the first substrate voltage terminal, and the sixteenth connection portion 360 is connected to the first conductor region 140 via a hole. The seventeenth connection portion 370 extends along the first direction X, and the orthographic projection of the seventeenth connection portion 370 on the semiconductor substrate 100 at least partially overlaps with the second conductor region 150. The seventeenth connection portion 370 connects the second conductor region 150 and the second substrate voltage terminal, and the seventeenth connection portion 370 is connected to the second conductor region 150 via a hole.

[0151] like Fig.10 and Fig.11 As shown, Fig.10 is the third conductive layer structure layout, Fig.11 for Fig. 9 Chinese version and Fig.10 The structure layout after superposition. The display panel also includes a third conductive layer 400, which is arranged on the side of the second conductive layer 300 away from the semiconductor substrate 100, and the third conductive layer 400 includes a plurality of fifth connecting portions 410. The fifth connecting portion 410 extends along the second direction Y, and the fifth connecting portion 410 connects the gate of the driving transistor T3, the first electrode region of the first transistor T1, and the second electrode region of the second transistor T2 in the same pixel circuit. A single pixel circuit unit may include three fifth connecting portions 410, which are respectively connected to the first sub-pixel circuit 1, the second sub-pixel circuit 2, and the third sub-pixel circuit 3.

[0152] The third conductive layer 400 further includes a plurality of sixth connection portions 420 and a plurality of seventh connection portions 430. The sixth connection portion 420 is connected to the third connection portion 330 in two adjacent pixel circuit units arranged along the first direction X through a via hole, the sixth connection portion 420 and the third connection portion 330 are connected to form a first scan line GL1, and the orthographic projection of the sixth connection portion 420 on the semiconductor substrate 100 overlaps at least partially with the orthographic projection of the fourth connection portion 340 on the semiconductor substrate 100. This reduces the space occupied by the display panel wiring on the horizontal plane (the plane where the semiconductor substrate 100 is located), which helps to achieve a high PPI design of the display panel. The seventh connection portion 430 is connected to the fourth connection portion 340 in two adjacent pixel circuit units arranged along the first direction X through a via hole, the seventh connection portion 430 and the fourth connection portion 340 are connected to form a second scan line GL2, and the orthographic projection of the seventh connection portion 430 on the semiconductor substrate 100 overlaps at least partially with the orthographic projection of the third connection portion 330 on the semiconductor substrate 100.

[0153] In the present disclosure, the display panel includes a plurality of first scan lines GL1 and a plurality of second scan lines GL2. The first scan line GL1 extends along the first direction X, and the first scan line GL1 is connected to the gate of the second transistor T2; the second scan line GL2 extends along the first direction X, and the second scan line GL2 is located on one side of the second scan line GL2 along the second direction Y, and the second scan line GL2 is connected to the gate of the first transistor T1; the same first scan line GL1 is distributed in two conductive layers of the second conductive layer 300 and the third conductive layer 400, and the same second scan line GL2 is distributed in two conductive layers of the second conductive layer 300 and the third conductive layer 400. The same row of pixel circuit units can share the same first scan line GL1 or the same second scan line GL2. The scan lines of the present disclosure are distributed in two conductive layers, which helps to reduce the space occupied by the display panel wiring on the horizontal plane (the plane where the semiconductor substrate 100 is located), and realize the high PPI design of the display panel.

[0154] The third conductive layer 400 further includes a plurality of eighth connection portions 440, which are connected to the first electrode regions of the driving transistors T3 of the plurality of pixel circuits in the pixel circuit unit; in the same pixel circuit unit, at least a portion of the orthographic projection of the eighth connection portion 440 on the semiconductor substrate 100 is located on a side of the third active area group 130 away from the first active area group 110. In the same row of pixel circuit units, the eighth connection portions 440 in each pixel circuit unit can be connected as one.

[0155] The third conductive layer 400 further includes a ninth connecting portion 460 and a tenth connecting portion 470. The ninth connecting portion 460 is connected to the second electrode region of the driving transistor T3 of the second sub-pixel circuit 2. Specifically, the ninth connecting portion 460 may be connected through a metal wire via distributed in the second conductive layer 300, and then connected to the second electrode region of the driving transistor T3 in the second sub-pixel circuit 2. The ninth connecting portion 460 is generally in the shape of a long strip extending along the second direction Y.

[0156] The tenth connection portion 470 is connected to the second electrode region of the driving transistor T3 of the third sub-pixel circuit 3, and the shape of the tenth connection portion 470 is substantially a strip extending along the second direction Y. The ninth connection portion 460 and the tenth connection portion 470 can be used as a transfer line to connect the second electrode region of the driving transistor T3 in the corresponding sub-pixel circuit to the light-emitting unit.

[0157] The third conductive layer 400 further includes a fourteenth connection portion 480, which is connected to the first connection portion 310 connecting the first electrode region of the first transistor T1 and the second electrode region of the second transistor T2 in the first sub-pixel circuit 1 through a via hole, and the orthographic projection of the fourteenth connection portion 480 on the semiconductor substrate 100 is substantially L-shaped. The fourteenth connection portion 480 can serve as a transition line to electrically connect the gate of the driving transistor T3 in the first sub-pixel circuit 1, the first electrode region of the first transistor T1, the second electrode region of the second transistor T2, and the second electrode plate C2 of the capacitor C.

[0158] like Fig.12 , Fig.13 As shown, Fig.12 is the fourth conductive layer structure layout, Fig.13 for Fig.11 Chinese version and Fig.12 The structural layout after superposition. The display panel also includes a fourth conductive layer 500, which is arranged on the side of the third conductive layer 400 away from the semiconductor substrate 100. The fourth conductive layer 500 includes a plurality of first power lines VDD, the first power lines VDD extending along the second direction Y, arranged at intervals along the first direction X, and the first power lines VDD are electrically connected to the first pole region of the driving transistor T3. Specifically, the first power line VDD can be connected to the eighth connecting portion 440 via a via. Among them, the positive projection of the first power line VDD on the semiconductor substrate 100 is located on the side of the second active area group 120 away from the first active area group 110. Two adjacent column unit groups share the same first power line VDD. Specifically, in two adjacent column unit groups, the first pixel circuit unit 10 and the third pixel circuit unit 30 of one group share the same first power line VDD with the second pixel circuit unit 20 and the fourth pixel circuit unit 40 of the other group.

[0159] The fourth conductive layer 500 includes a plurality of data lines DL, which extend along the second direction Y and are arranged at intervals along the first direction X. The data lines DL are connected to the second connecting portion 320 via a via. Each pixel circuit in the same column of pixel circuit units may be correspondingly connected to the same data line DL. That is, in the same column of pixel circuit units, each first sub-pixel circuit 1 shares the same data line DL, each second sub-pixel circuit 2 shares the same data line DL, and each third sub-pixel circuit 3 shares the same data line DL. The orthographic projection of at least part of the data line DL on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the second conductive layer 300 on the semiconductor substrate 100. In the figure, DLm represents the data line DL corresponding to the mth sub-pixel circuit, and m can be 1, 2, or 3.

[0160] The third conductive layer 400 further includes a plurality of metal blocks 450. The orthographic projection of the metal block 450 on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the data line DL on the semiconductor substrate 100, and the data line DL is connected to the metal block 450 via a via hole. The same data line DL can be connected to a plurality of metal blocks 450 via holes to reduce the load of the data line DL and improve the performance of the display panel.

[0161] In some embodiments, the fourth conductive layer 500 further includes a plurality of eleventh connecting portions 510, and the eleventh connecting portion 510 is connected to the second electrode region of the driving transistor T3 in the third sub-pixel circuit 3. The eleventh connecting portion 510 is generally in the shape of a long strip extending along the second direction Y. The eleventh connecting portion 510 can be used as a transition line to connect the second electrode region of the driving transistor T3 in the third sub-pixel circuit 3 to the light-emitting unit corresponding to the sub-pixel circuit.

[0162] like Fig.16 , Fig.18 As shown, in some embodiments, the display panel further includes a fifth conductive layer 600 and a sixth conductive layer 700, and the fifth conductive layer 600 is disposed on a side of the fourth conductive layer 500 away from the semiconductor substrate 100. The fifth conductive layer 600 includes a plurality of first conductive blocks C1, the first conductive blocks C1 are grounded, and different first conductive blocks C1 are used to form the first electrode plate C1 of the capacitor C in different pixel circuits, and the orthographic projection of the first conductive block C1 on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the first conductive part 210, the second conductive part 220 or the third conductive part 230 on the semiconductor substrate 100; all the first conductive blocks C1 of the display panel are connected as a whole to reduce the number of connection holes and increase the electrode plate area of ​​the capacitor C. Fig.16 In FIG. 1 , C1-m represents the first plate C1 of the capacitor C in the m-th sub-pixel circuit, and m can be 1, 2, or 3.

[0163] In a single pixel circuit unit, the orthographic projection of the first plate C1 of the capacitor C in the first sub-pixel circuit 1 on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the second conductive portion 220 on the semiconductor substrate 100, the orthographic projection of the first plate C1 of the capacitor C in the second sub-pixel circuit 2 on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the gate of the driving transistor T3 in the second sub-pixel circuit 2 on the semiconductor substrate 100, and the orthographic projection of the first plate C1 of the capacitor C in the third sub-pixel circuit 3 on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the gate of the driving transistor T3 in the first sub-pixel circuit 1 on the semiconductor substrate 100.

[0164] The sixth conductive layer 700 is arranged on a side of the fifth conductive layer 600 away from the semiconductor substrate 100. The sixth conductive layer 700 includes a plurality of second conductive blocks C2. The orthographic projection of the second conductive block C2 on the semiconductor substrate 100 is located within the orthographic projection of the first conductive block C1 on the semiconductor substrate 100. Different first conductive blocks C1 are used to form the second plate C2 of the capacitor C in different pixel circuits.

[0165] like Fig.14 and Fig.15 As shown, Fig.14 is the structure layout of the seventh conductive layer 800, Fig.15 for Fig.13 Chinese version and Fig.14 The display panel further includes a seventh conductive layer 800, which is disposed between the fourth conductive layer 500 and the fifth conductive layer 600. The seventh conductive layer 800 includes a plurality of twelfth connecting portions 810, and the twelfth connecting portions 810 are electrically connected to the second electrode region of the driving transistor T3. Different sub-pixel circuits are connected using different twelfth connecting portions 810. Fig.14 In the figure, 810-m represents the twelfth connection portion 810 corresponding to the m-th sub-pixel circuit, and m is 1, 2, or 3. In the figure, the twelfth connection portion 810 corresponding to the first sub-pixel circuit 1 is connected to the eleventh connection portion 510 via a hole, the twelfth connection portion 810 corresponding to the second sub-pixel circuit 2 is connected to the ninth connection portion 460 via a hole, and the twelfth connection portion 810 corresponding to the third sub-pixel circuit 3 is connected to the tenth connection portion 470 via a hole.

[0166] like Fig.17 and Fig.18 As shown, Fig.17 is the structural layout of the eighth conductive layer 900, Fig.18 for Fig.15 , Fig.16 , Fig.17 The display panel further includes an eighth conductive layer 900, which is disposed on a side of the sixth conductive layer 700 away from the semiconductor substrate 100. The eighth conductive layer 900 includes a plurality of thirteenth connecting portions 910, and the thirteenth connecting portions 910 electrically connect the gate of the driving transistor T3 in the same pixel circuit and the second electrode plate C2 of the capacitor C. The orthographic projection of the thirteenth connecting portion 910 on the semiconductor substrate 100 is substantially L-shaped. Fig.17In the figure, 910-m represents the thirteenth connection portion 910 corresponding to the m-th sub-pixel circuit, and m is 1, 2, or 3. In the figure, the orthographic projection of the thirteenth connection portion 910 corresponding to the first sub-pixel circuit 1 on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the second plate C2 of the capacitor C of the first sub-pixel circuit 1 on the semiconductor substrate 100, and the thirteenth connection portion 910 of the first sub-pixel circuit 1 is connected to the fourteenth connection portion 480 via a hole. The orthographic projection of the thirteenth connection portion 910 corresponding to the second sub-pixel circuit 2 on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the second plate C2 of the capacitor C of the second sub-pixel circuit 2 on the semiconductor substrate 100, and the thirteenth connection portion 910 of the second sub-pixel circuit 2 is connected to the fifteenth connection portion 350 via a hole. The orthographic projection of the thirteenth connection portion 910 corresponding to the third sub-pixel circuit 3 on the semiconductor substrate 100 at least partially overlaps with the orthographic projection of the second plate C2 of the capacitor C of the third sub-pixel circuit 3 on the semiconductor substrate 100. The thirteenth connection portion 910 of the third sub-pixel circuit 3 is connected to the first connection portion 310 connecting the first electrode region of the first transistor T1 and the second electrode region of the second transistor T2 of the third sub-pixel circuit 3 via a via hole.

[0167] In some embodiments, the display panel of the present disclosure further includes a ninth conductive layer, which is disposed on a side of the eighth conductive layer 900 away from the semiconductor substrate 100, and the ninth conductive layer includes a plurality of conductive blocks, which are used to connect the twelfth connecting portion 810 and the corresponding light-emitting unit. The plurality of conductive blocks can be connected to the twelfth connecting portion 810 in a one-to-one corresponding via hole.

[0168] In the present disclosure, metal sheets may be provided at positions of via holes corresponding to each conductive layer to achieve multiple transfers of each conductive layer.

[0169] The present disclosure also provides a display device, including the above-mentioned display panel. The display device can be a display device such as a mobile phone, a tablet computer, or a television.

[0170] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc., which shall all be considered as part of the present disclosure.

[0171] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A display panel, characterized in that: The device comprises a plurality of pixel circuit units, wherein the pixel circuit unit comprises a plurality of pixel circuits, wherein the pixel circuit comprises a first transistor and a second transistor, wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor; The display panel further includes: A semiconductor substrate including an active region of each transistor, wherein the active region includes: A plurality of first active area groups, each of which is located in each of the pixel circuit units in a one-to-one correspondence, wherein the first active area group includes a plurality of first active areas arranged at intervals, and different first active areas in the first active area group are used to form channel areas of the first transistors corresponding to different pixel circuits in the pixel circuit unit; A plurality of second active area groups are respectively located in each of the pixel circuit units in a one-to-one correspondence. In the same pixel circuit unit, the second active area group is located on one side of the first active area group along the first direction. The second active area group includes a plurality of second active areas arranged at intervals. Different second active areas in the second active area group are used to form channel regions of the second transistors corresponding to different pixel circuits in the pixel circuit unit.

2. The display panel according to claim 1, characterized in that: The display panel further includes: A first conductive layer is provided on one side of the semiconductor substrate, and the first conductive layer comprises: a plurality of first conductive portions, wherein an orthographic projection of the first conductive portion on the semiconductor substrate at least partially overlaps with a plurality of the first active areas in the first active area group, and the first conductive portion is used to form a gate of the first transistor corresponding to different pixel circuits in the pixel circuit unit; A plurality of second conductive portions, wherein the orthographic projections of the second conductive portions on the semiconductor substrate at least partially overlap with the plurality of second active areas in the second active area group, and the second conductive portions are used to form gates of the second transistors corresponding to different pixel circuits in the pixel circuit unit.

3. The display panel according to claim 2, characterized in that: The pixel circuit further includes a driving transistor, wherein a first electrode of the first transistor is connected to a second electrode of the second transistor and is connected to a data signal terminal, and a second electrode of the first transistor is connected to a first electrode of the second transistor and is connected to a gate of the driving transistor; and both the gate of the first transistor and the gate of the second transistor are connected to a gate driving signal terminal; The first electrode of the driving transistor is connected to the first power supply voltage terminal; The active region further comprises: A plurality of third active area groups, each of which is located in each of the pixel circuit units in a one-to-one correspondence, the third active area group being located on one side of the first active area group along the second direction, the third active area group comprising a plurality of third active areas arranged at intervals, and different third active areas in the third active area group being used to form channel areas of the driving transistors corresponding to different pixel circuits in the pixel circuit unit; The first conductive layer further comprises: A plurality of third conductive portions, wherein the orthographic projections of the third conductive portions on the semiconductor substrate at least partially overlap with the third active region, and the third conductive portions are used to form the gate of the driving transistor.

4. The display panel according to claim 3, characterized in that: The display panel further includes: A second conductive layer is provided on a side of the first conductive layer away from the semiconductor substrate, and the second conductive layer comprises: a plurality of first connection portions, wherein the first connection portions connect a first electrode region of the first transistor and a second electrode region of the second transistor in the same pixel circuit; A plurality of second connection portions, wherein the second connection portions connect the second electrode region of the first transistor and the second electrode region of the second transistor in the same pixel circuit.

5. The display panel according to claim 4, characterized in that: The display panel also includes: A third conductive layer is provided on a side of the second conductive layer away from the semiconductor substrate, and the third conductive layer comprises: A plurality of fifth connection portions, wherein the fifth connection portions extend along the second direction, and the fifth connection portions connect the gate of the driving transistor, the first electrode region of the first transistor, and the second electrode region of the second transistor in the same pixel circuit.

6. The display panel according to claim 5, characterized in that: The display panel further includes: a plurality of first scan lines, wherein the first scan lines extend along the first direction and are connected to the gate of the second transistor; a plurality of second scan lines, wherein the second scan lines extend along the first direction, the second scan lines are located on one side of the second scan lines along the second direction, and the second scan lines are connected to the gate of the first transistor; The same first scanning line is distributed in two conductive layers, namely, the second conductive layer and the third conductive layer, and the same second scanning line is distributed in two conductive layers, namely, the second conductive layer and the third conductive layer.

7. The display panel according to claim 6, characterized in that: The second conductive layer further comprises: a plurality of third connection portions, wherein the third connection portions extend along the first direction, and one end of the third connection portion is connected to the gates of the second transistors of the plurality of pixel circuits in the pixel circuit unit; a plurality of fourth connection portions, wherein the fourth connection portions extend along the first direction, and one end of the fourth connection portion is connected to the gates of the first transistors of the plurality of pixel circuits in the pixel circuit unit; The third conductive layer further comprises: a plurality of sixth connection portions, wherein the sixth connection portions are connected to the third connection portion via holes in two adjacent pixel circuit units arranged along the first direction, the sixth connection portions and the third connection portions are connected to form the first scanning line, and an orthographic projection of the sixth connection portion on the semiconductor substrate at least partially overlaps with an orthographic projection of the fourth connection portion on the semiconductor substrate; A plurality of seventh connection parts, wherein the seventh connection parts are connected to the fourth connection part via holes in two adjacent pixel circuit units arranged along the first direction, the seventh connection parts and the fourth connection parts are connected to form the second scanning line, and the orthographic projection of the seventh connection part on the semiconductor substrate at least partially overlaps with the orthographic projection of the third connection part on the semiconductor substrate.

8. The display panel according to claim 5, characterized in that: The display panel further includes: a fourth conductive layer, disposed on a side of the third conductive layer away from the semiconductor substrate, the fourth conductive layer comprising a plurality of first power lines, the first power lines extending along the second direction, arranged at intervals along the first direction, and electrically connected to the first electrode region of the driving transistor; The orthographic projection of the first power line on the semiconductor substrate is located on a side of the second active area group away from the first active area group.

9. The display panel according to claim 8, characterized in that: The plurality of pixel circuit units include a plurality of first pixel circuit units, a plurality of second pixel circuit units, a plurality of third pixel circuit units and a plurality of fourth pixel circuit units; The first pixel circuit units and the second pixel circuit units are arranged at intervals along the first direction, and adjacent first pixel circuit units and second pixel circuit units are mirror-symmetrical; The first pixel circuit units and the third pixel circuit units are arranged at intervals along the second direction, and adjacent first pixel circuit units and the third pixel circuit units are mirror-symmetrical; The fourth pixel circuit unit and the third pixel circuit unit are arranged at intervals along the first direction, and at the same time, the fourth pixel circuit unit and the second pixel circuit unit are arranged at intervals along the second direction, and the adjacent fourth pixel circuit unit and the third pixel circuit unit are mirror-symmetrical, and at the same time, the adjacent fourth pixel circuit unit and the second pixel circuit unit are mirror-symmetrical.

10. The display panel according to claim 9, characterized in that: One first pixel circuit unit, one second pixel circuit unit, one third pixel circuit unit and one fourth pixel circuit unit form a unit group, and a plurality of the unit groups are arranged in an array along the first direction and the second direction; The first direction is a row direction, the second direction is a column direction, and the unit groups in two adjacent columns share the same first power line.

11. The display panel according to claim 8, characterized in that: The third conductive layer further comprises: a plurality of eighth connection portions, wherein the eighth connection portions are connected to first electrode regions of driving transistors of a plurality of pixel circuits in the pixel circuit unit; In the same pixel circuit unit, at least a portion of an orthographic projection of the eighth connection portion on the semiconductor substrate is located on a side of the third active area group away from the first active area group; The first power line is connected to the eighth connection portion via hole.

12. The display panel according to claim 8, characterized in that: The fourth conductive layer further comprises: A plurality of data lines are provided, wherein the data lines extend along the second direction and are arranged along the first direction, and the data lines are connected to the second connecting portion via holes.

13. The display panel according to claim 12, characterized in that: The third conductive layer further comprises: A plurality of metal blocks, wherein the orthographic projections of the metal blocks on the semiconductor substrate at least partially overlap with the orthographic projections of the data lines on the semiconductor substrate, and the data lines are connected to the metal blocks via holes.

14. The display panel according to claim 8, characterized in that: The pixel circuit further comprises a capacitor, wherein the capacitor is connected to a ground terminal and a gate of the driving transistor; The display panel further includes: A fifth conductive layer is provided on a side of the fourth conductive layer away from the semiconductor substrate, and the fifth conductive layer comprises: a plurality of first conductive blocks, wherein the first conductive blocks are grounded, different first conductive blocks are used to form first plates of the capacitors in different pixel circuits, and an orthographic projection of the first conductive block on the semiconductor substrate at least partially overlaps with an orthographic projection of the first conductive portion, the second conductive portion, or the third conductive portion on the semiconductor substrate; All of the first conductive blocks of the display panel are connected as one.

15. The display panel according to claim 14, characterized in that: The display panel further includes: A sixth conductive layer is provided on a side of the fifth conductive layer away from the semiconductor substrate, and the sixth conductive layer comprises: a plurality of second conductive blocks, wherein the orthographic projections of the second conductive blocks on the semiconductor substrate are located within the orthographic projections of the first conductive blocks on the semiconductor substrate, and different first conductive blocks are used to form the second plates of the capacitors in different pixel circuits; a seventh conductive layer, disposed between the fourth conductive layer and the fifth conductive layer, wherein the orthographic projection of the seventh conductive layer on the semiconductor substrate does not overlap with the orthographic projection of the fifth conductive layer on the semiconductor substrate, and the seventh conductive layer comprises: A plurality of twelfth connection portions, wherein the twelfth connection portions are electrically connected to the second electrode region of the driving transistor.

16. The display panel according to claim 15, characterized in that: The display panel further includes an eighth conductive layer, which is disposed on a side of the sixth conductive layer away from the semiconductor substrate, and the eighth conductive layer includes: A plurality of thirteenth connecting portions, wherein the thirteenth connecting portions are electrically connected to the gate of the driving transistor in the same pixel circuit and the second plate of the capacitor.

17. The display panel according to claim 3, characterized in that: A single pixel circuit unit includes three pixel circuits, and the three pixel circuits correspond to a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit respectively; The number of the first active areas in a single pixel circuit unit is three, the three first active areas are arranged at intervals along the first direction, and the three first active areas are used to form a channel area of ​​a first transistor of the first sub-pixel circuit, a channel area of ​​a first transistor of the second sub-pixel circuit, and a channel area of ​​a first transistor of the third sub-pixel circuit in sequence along a direction away from the second active area group; The number of the second active areas in a single pixel circuit unit is three, the three second active areas are arranged at intervals along the first direction, and the three second active areas are used to form the channel area of ​​the second transistor of the first sub-pixel circuit, the channel area of ​​the second transistor of the second sub-pixel circuit, and the channel area of ​​the second transistor of the third sub-pixel circuit in sequence along the direction away from the first active area group.

18. The display panel according to claim 17, characterized in that: The number of the third active areas in a single pixel circuit unit is three; among the three third active areas, two of the third active areas are arranged at intervals on one side of the second active area group in the second direction, and are used to form the channel region of the driving transistor of the third sub-pixel circuit and the channel region of the driving transistor of the first sub-pixel circuit in sequence along the direction away from the second active area group, and the other third active area is located on one side of the first active area group in the second direction, and is used to form the channel region of the driving transistor of the second sub-pixel circuit.

19. The display panel according to claim 5, characterized in that: The semiconductor substrate further comprises: a first conductor region, located between the third active region group and the first active region group along the second direction, the first conductor region being used to form a first substrate electrode; a second conductor region, located between the first conductor region and the first active region group along the second direction, the second conductor region being used to form a second substrate electrode; The third conductive layer further comprises: A sixteenth connection portion extending along the first direction, an orthographic projection of the sixteenth connection portion on the semiconductor substrate at least partially overlapping with the first conductor region, and the sixteenth connection portion being connected to a via hole of the first conductor region; The seventeenth connection portion extends along the first direction, the orthographic projection of the seventeenth connection portion on the semiconductor substrate at least partially overlaps with the second conductor region, and the seventeenth connection portion is connected to the second conductor region via a via.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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