A CMOS image chip, camera and debugging method thereof

Abstract

The present invention relates to a CMOS image chip, a camera, and a debugging method thereof. The CMOS image chip of the present invention includes a photosensitive area and a light-emitting area surrounding the photosensitive area. A plurality of light-emitting diodes are provided in the light-emitting area. Based on the principle of light reversibility, the projection pattern of the light-emitting diodes on the substrate to be inspected is used to determine the photosensitive effective area of ​​the substrate of the CMOS image chip. This avoids the problem of low debugging efficiency caused by signal delay in the camera image on a display, which is a problem in the prior art of using the camera image on a display as the debugging basis. The debugging efficiency of the camera is greatly improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a CMOS image chip, a camera, and a debugging method thereof. Background Art

[0002] Currently, most imaging chips used in industrial cameras are back-illuminated CMOS image sensors (CIS) chips. CIS chips have advantages such as small size and low power consumption and have a wide range of applications. The optical systems of traditional inspection equipment are relatively fixed. After debugging, in order to maintain camera stability, the camera and light source are generally placed in a fixed position and rarely move their position and distance. However, although there are theoretical calculation values ​​for reference during the camera debugging process, the image generated by the camera on the monitor must be used as the basis for debugging. In addition, since there is generally a signal delay during the transmission process of the camera imaging image, the debugging efficiency of the camera is relatively low. Especially for debugging experimental equipment, it is necessary to frequently switch camera types, replace lenses, and adjust the position of the camera and light source. Due to the low efficiency of the camera debugging process, the experimental efficiency is low. Summary of the Invention

[0003] The purpose of the present invention is to provide a CMOS image chip, a camera and a debugging method thereof, which can solve the problems in the prior art that the image imaged by the camera on the display is required as the basis for debugging, and there is a signal delay in the transmission process of the camera imaging image, resulting in low camera debugging efficiency.

[0004] In order to solve the above problems, the present invention provides a CMOS image chip, which includes: a photosensitive area and a light-emitting area surrounding the photosensitive area; the CMOS image chip includes: a circuit layer located in the photosensitive area and the light-emitting area; a plurality of photodiodes arranged on the circuit layer in the photosensitive area and electrically connected to the circuit layer; and a plurality of light-emitting diodes arranged on the circuit layer in the light-emitting area and electrically connected to the circuit layer.

[0005] Furthermore, a substrate is provided on the circuit layer located in the photosensitive area, and the plurality of photodiodes are provided on the substrate in the photosensitive area.

[0006] Furthermore, the substrate is also arranged on the circuit layer of the light-emitting area, and a first opening is provided on the substrate in the light-emitting area, and the light-emitting diode is located in the first opening.

[0007] Furthermore, the light emitting diode is a Micro LED or a Mini LED.

[0008] Furthermore, each of the light-emitting diodes includes: a substrate, a light-emitting layer arranged on the side of the substrate facing the circuit layer, and a P pole and an N pole spaced apart on the side of the light-emitting layer away from the substrate; wherein the circuit layer corresponding to the first opening has a first electrode and a second electrode electrically connected to the P pole and N pole respectively in a one-to-one correspondence.

[0009] Furthermore, each of the light-emitting diodes also has a bump metal disposed between the P pole and the first electrode and between the N pole and the second electrode.

[0010] Furthermore, a surface of the light-emitting layer of any one of the light-emitting diodes that is away from the circuit layer is flush with a surface of the substrate that is away from the circuit layer.

[0011] Furthermore, the CMOS image chip also includes: an anti-reflection layer, which is arranged on the side of the substrate away from the circuit layer; a second opening is provided between two adjacent photodiodes, and the anti-reflection layer is also filled in the second opening; and an encapsulation layer, which is filled in the first opening; wherein the surfaces of the encapsulation layer, the light-emitting diode and the anti-reflection layer on the side away from the circuit layer are flush.

[0012] Furthermore, the CMOS image chip also includes: a metal grid, which is arranged on a side of the anti-reflection layer away from the circuit layer and corresponding to the second opening; a first flat layer, which is arranged on a side of the anti-reflection layer, the light-emitting diode and the packaging layer away from the circuit layer; a color resist unit, which is arranged between adjacent metal grids on a side of the first flat layer away from the circuit layer; a second flat layer, which is arranged on a side of the color resist unit and the first flat layer away from the circuit layer; and a plurality of lenses, which are arranged on a side of the second flat layer away from the circuit layer and corresponding to the color resist unit and the light-emitting diode.

[0013] Furthermore, the length of the bottom edge of the first opening on the side close to the circuit layer is smaller than the length of the bottom edge on the side away from the circuit layer.

[0014] In order to solve the above problems, the present invention provides a camera, which includes the CMOS image chip and a lens described in the present invention; the camera includes one of an area array camera and a line array camera.

[0015] In order to solve the above problems, the present invention provides a debugging method for the camera described in the present invention, comprising the following steps: the display pattern of the light-emitting diode of the CMOS image chip is projected through the lens to form a projection pattern on the substrate to be inspected, the user observes the clarity of the projection pattern on the substrate to be inspected and adjusts the focal length of the lens, the user observes the clarity of multiple points of the projection pattern on the substrate to be inspected and adjusts the levelness of the camera.

[0016] Furthermore, when the camera is the line array camera, the following steps are also included: the user observes the position of the reflected light after the light emitted by the light emitting diode is reflected by the substrate to be inspected, determines the placement position and angle of the light source, and adjusts the bright and dark field imaging mode of the camera.

[0017] The advantages of the present invention are as follows: the CMOS image chip of the present invention includes a photosensitive area and a light-emitting area surrounding the photosensitive area; a plurality of light-emitting diodes are provided in the light-emitting area, and based on the principle of reversibility of light, the projection pattern of the light-emitting diodes on the substrate to be inspected is utilized to determine the photosensitive effective area of ​​the substrate of the CMOS image chip, thereby avoiding the problem in the prior art of using the image formed by the camera on the display as the basis for debugging, and the signal delay in the camera imaging image resulting in low debugging efficiency.

[0018] The display pattern of the light-emitting diode of the CMOS image chip of the present invention is projected through the lens onto the substrate to be inspected to form a projection pattern. The user observes the clarity of the projection pattern on the substrate to be inspected and adjusts the focal length of the lens, observes the clarity of multiple points of the projection pattern on the substrate to be inspected, and adjusts the levelness of the camera.

[0019] When the camera is a line array camera, the user can also observe the position of the reflected light after the light emitted by the light emitting diode is reflected by the substrate to be inspected, determine the placement position and angle of the light source, and adjust the bright and dark field imaging modes of the camera. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 1 is a planar schematic diagram of a CMOS image chip of the present invention;

[0022] Figure 2 yes Figure 1 AA cross-sectional diagram of ;

[0023] Figure 3 1 is a schematic structural diagram of a semi-finished product of a CMOS image chip according to the present invention;

[0024] Figure 4 This is a schematic structural diagram of a semi-finished product 2 of the CMOS image chip of the present invention;

[0025] Figure 5 1 is a schematic structural diagram of a third semi-finished product of the CMOS image chip of the present invention;

[0026] Figure 6 1 is a schematic structural diagram of a semi-finished product 4 of the CMOS image chip of the present invention;

[0027] Figure 7 1 is a schematic structural diagram of a semi-finished product 5 of the CMOS image chip of the present invention;

[0028] Figure 8 1 is a schematic structural diagram of a semi-finished product 6 of the CMOS image chip of the present invention;

[0029] Figure 9 1 is a schematic structural diagram of a semi-finished product 7 of a CMOS image chip of the present invention;

[0030] Figure 10 1 is a schematic structural diagram of a semi-finished product eight of the CMOS image chip of the present invention;

[0031] Figure 11 1 is a schematic structural diagram of a semi-finished product nine of the CMOS image chip of the present invention;

[0032] Figure 12 1 is a schematic diagram of light rays of the area array camera of Example 1;

[0033] Figure 13 Schematic diagram of light rays of the line array camera of Example 2.

[0034] Description of reference numerals:

[0035] 1000, camera; 2000, substrate to be inspected;

[0036] 3000, light source; 4000, projection pattern

[0037] 100, CMOS image chip; 200, lens;

[0038] 110, photosensitive area; 120, luminous area;

[0039] 1. Circuit layer; 2. Substrate;

[0040] 3. Photodiode; 4. Light-emitting diode;

[0041] 5. Anti-reflection layer; 6. Encapsulation layer;

[0042] 7. Metal grid; 8. First flat layer;

[0043] 9. Color resist unit; 10. Second flat layer;

[0044] 11. Lens;

[0045] 101. First electrode; 102. Second electrode;

[0046] 103, third electrode; 201, fourth electrode;

[0047] 202, second opening; 203, first opening;

[0048] 401, substrate; 402, light-emitting layer;

[0049] 403, P pole; 404, N pole;

[0050] 405, bump metal;

[0051] 901, red color resistance unit; 902, green color resistance unit;

[0052] 903. Blue color resistance unit. DETAILED DESCRIPTION

[0053] The following describes in detail preferred embodiments of the present invention in conjunction with the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, to illustrate that the present invention can be implemented, to make the technical content disclosed in the present invention clearer, and to make it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments described herein. The description of the embodiments below is not intended to limit the scope of the present invention.

[0054] The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate the present invention, and are not used to limit the scope of protection of the present invention.

[0055] In the accompanying drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for ease of understanding and description, the size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.

[0056] Example 1

[0057] like Figure 1As shown, this embodiment provides a CMOS image chip 100 , which includes a photosensitive area 110 and a light-emitting area 120 surrounding the photosensitive area 110 .

[0058] like Figure 2 As shown, the CMOS image chip 100 includes: a circuit layer 1, a substrate 2, multiple photodiodes 3, multiple light-emitting diodes 4, an anti-reflection layer 5, an encapsulation layer 6, a metal grid 7, a first planarization layer 8, a color resist unit 9, a second planarization layer 10 and a lens 11.

[0059] The circuit layer 1 is located in the photosensitive area 110 and the light-emitting area 120 .

[0060] The substrate 2 is disposed on the circuit layer 1 of the photosensitive area 110. In this embodiment, the substrate 2 is made of silicon.

[0061] The photodiode 3 is disposed on the substrate 2 in the photosensitive area 110 and is electrically connected to the circuit layer 1. In this embodiment, the circuit layer 1 has a plurality of third electrodes 103, and the substrate 2 has a plurality of fourth electrodes 201. The photodiode 3 is electrically connected to the fourth electrodes 201, and the third electrodes 103 and the fourth electrodes 201 are bonded in a one-to-one correspondence to achieve electrical connection between the photodiode 3 and the circuit layer 1. A second opening 202 is defined between two adjacent photodiodes 3.

[0062] The light-emitting diodes 4 are disposed on the circuit layer 1 in the light-emitting area 120 and are electrically connected to the circuit layer 1. In this embodiment, the light-emitting diodes 4 are micro-LEDs, with a size of less than 50 μm. In other embodiments, the light-emitting diodes 4 may also be mini-LEDs. In this embodiment, the light-emitting diodes 4 are arranged in a "U" shape surrounding the photosensitive area 110. In other embodiments, the light-emitting diodes 4 may also surround two sides of the photosensitive area 110 or be arranged at multiple corners of the photosensitive area 110. The spacing between the light-emitting diodes 4 can be adjusted according to actual needs and is not limited in this application. The CMOS image chip 100 of the present invention includes a photosensitive area 110 and a light-emitting area 120 surrounding the photosensitive area 110. Multiple light-emitting diodes 4 are disposed in the light-emitting area 120. Based on the principle of reversibility of light, the projection pattern of the light-emitting diodes 4 on the substrate to be inspected is used to determine the photosensitive effective area of ​​the substrate 2 of the CMOS image chip 100. This avoids the problem of conventional techniques that use the image captured by the camera on the display as the basis for debugging, which suffers from signal delays in the camera image and leads to low debugging efficiency.

[0063] In this embodiment, the substrate 2 is further disposed on the circuit layer 1 in the light-emitting region 120. A first opening 203 is defined on the substrate 2 in the light-emitting region 120, and the light-emitting diode 4 is located within the first opening 203. The substrate 2 prevents light emitted by the light-emitting diode 4 from irradiating the photodiode 3 in the photosensitive region 110, thereby preventing it from affecting the reliability of the photodiode 3. In other embodiments, the substrate 2 may not be disposed on the circuit layer 1 in the light-emitting region 120.

[0064] The length of the bottom edge of the first opening 203 on the side closest to the circuit layer 1 is shorter than the length of the bottom edge on the side farther from the circuit layer 1. That is, the first opening 203 is in an inverted trapezoidal shape. The sidewalls of the first opening 203 reflect light emitted by the LED 4, improving the collimation and light extraction efficiency of the light emitted by the LED 4.

[0065] Each of the light-emitting diodes 4 includes a substrate 401 , a light-emitting layer 402 , a P-pole 403 , an N-pole 404 and a metal bump 405 .

[0066] The light emitting layer 402 is disposed on a side of the substrate 401 facing the circuit layer 1 .

[0067] The P-pole 403 and the N-pole 404 are spaced apart on the side of the light emitting layer 402 away from the substrate 401. The circuit layer 1 corresponding to the first opening 203 has a first electrode 101 and a second electrode 102 electrically connected to the P-pole 403 and the N-pole 404 respectively.

[0068] The bump metal 405 is disposed between the P-pole 403 and the first electrode 101 and between the N-pole 404 and the second electrode 102 .

[0069] In this embodiment, by adjusting the height of the metal bump 405, the surface of the light-emitting layer 402 of any one of the light-emitting diodes 4, which is away from the circuit layer 1, is flush with the surface of the substrate 2, which is away from the circuit layer 1. This ensures that the debugging effect of the light-emitting diode 4 is consistent with the debugging effect of the photodiode 3 on the substrate 2, based on the principle of reversibility of light.

[0070] The anti-reflection layer 5 is disposed on a side of the substrate 2 away from the circuit layer 1. The anti-reflection layer 5 also fills the second opening 202. The anti-reflection layer 5 can reduce the reflectivity of the substrate 2 when exposed to external light, and can also reduce the occurrence of dark current on the sidewalls of the second opening 202.

[0071] The packaging layer 6 is filled in the first opening 203. The packaging layer 6 is used to prevent water and oxygen from corroding the light emitting diode 4, thereby increasing the service life of the light emitting diode 4.

[0072] The surfaces of the packaging layer 6, the light emitting diode 4, and the anti-reflection layer 5 away from the circuit layer 1 are flush. That is, the anti-reflection layer 5 does not cover the light emitting diode 4 and the packaging layer 6, thereby improving the light extraction efficiency of the light emitting diode 4.

[0073] The metal grid 7 is disposed on a side of the anti-reflection layer 5 away from the circuit layer 1 and is corresponding to the second opening 202. The metal grid 7 is mainly used to reduce optical crosstalk.

[0074] The first flat layer 8 is disposed on a side of the anti-reflection layer 5, the light emitting diode 4 and the packaging layer 6 away from the circuit layer 1. The first flat layer 8 is mainly used to provide a flat surface for the preparation of subsequent film layers.

[0075] The color resist unit 9 is disposed on a side of the first planar layer 8 between adjacent metal grids 7, away from the circuit layer 1. The color resist unit 9 is primarily used to filter external light that illuminates the photodiode 3. In this embodiment, the color resist unit 9 includes a red color resist unit 901, a green color resist unit 902, and a blue color resist unit 903.

[0076] The second flat layer 10 is disposed on the side of the color resist unit 9 and the first flat layer 8 away from the circuit layer 1. The second flat layer 10 is mainly used to provide a flat surface for the preparation of subsequent film layers.

[0077] A plurality of lenses 11 are disposed on a side of the second flat layer 10 away from the circuit layer 1, and are disposed corresponding to the color resist unit 9 and the light-emitting diode 4. The surface of the lens 11 away from the circuit layer 1 is convex, and the surface of the lens 11 close to the circuit layer 1 is flat.

[0078] like Figure 2-Figure 11 As shown, this embodiment also provides a method for preparing the CMOS image chip 100 of this embodiment, which includes the following steps.

[0079] like Figure 2 、 Figure 3 As shown, a plurality of photodiodes 3 are prepared on the substrate 2 in the photosensitive area 110, and then the substrate with the photodiodes 3 is placed on the circuit layer 1. Specifically, the fourth electrode 201 of the substrate 2 is bonded to the third electrode 103 on the circuit layer 1 to achieve electrical connection between the photodiodes 3 and the circuit layer 1, forming a semi-finished product 1.

[0080] like Figure 4 As shown, the substrate 2 is thinned to form a semi-finished product 2. Specifically, the thickness of the silicon substrate of the substrate 2 can be thinned, thereby reducing the thickness of the CMOS image chip 100.

[0081] like Figure 5 As shown, a second opening 202 is formed between two adjacent photodiodes 3 using a DTI (deep trench isolation) process to form a semi-finished product three.

[0082] like Figure 6 As shown, an anti-reflection layer 5 is coated on the substrate 2 and in the second opening 202 to form a semi-finished product 4.

[0083] like Figure 7 As shown, a metal grid 7 is provided at a position corresponding to the second opening 202 on a side of the anti-reflection layer 5 away from the circuit layer 1 to form a semi-finished product five.

[0084] like Figure 8 As shown, a first opening 203 is formed on the anti-reflection layer 5 and the substrate 2 to form a semi-finished product 6, so that the first electrode 101 and the second electrode 102 on the circuit layer 1 are exposed so as to be electrically connected to the light-emitting diode 4 later.

[0085] like Figure 9 As shown, the light emitting diode 4 is welded to the circuit layer 1 by mass transfer and laser welding to form a semi-finished product 7.

[0086] like Figure 10 As shown, a transparent material is filled into the first opening 203 of the substrate 2 by an inkjet printing process to form an encapsulation layer 6, and the encapsulation layer 6 is used to encapsulate the light-emitting diode 4 to form a semi-finished product 8.

[0087] like Figure 11 As shown, a first flat layer 8 is prepared on the side of the anti-reflection layer 5, the light-emitting diode 4 and the encapsulation layer 6 away from the circuit layer 1; a color resist unit 9 is prepared on the side of the first flat layer 8 between adjacent metal grids 7 away from the circuit layer 1 to form a semi-finished product nine.

[0088] like Figure 2 As shown, a second flat layer 10 is prepared on the side of the color resist unit 9 and the first flat layer 8 away from the circuit layer 1; a lens 11 is provided at a position corresponding to the color resist unit 9 and the light-emitting diode 4 on the side of the second flat layer 10 away from the circuit layer 1.

[0089] like Figure 12As shown, this embodiment further provides a camera 1000. The camera 1000 includes a CMOS image chip 100 and a lens 200. In this embodiment, the camera 1000 is an area array camera.

[0090] This embodiment also provides a method for debugging the camera described in this embodiment, comprising the following steps: the display pattern of the light-emitting diode 4 of the CMOS image chip 100 is projected onto the substrate 2000 to be inspected through the lens 200 to form a projection pattern 4000; a user observes the clarity of the projection pattern 4000 on the substrate 2000 to be inspected to adjust the focal length of the lens 200; the user observes the clarity of multiple points of the projection pattern 4000 on the substrate 2000 to adjust the level of the camera 1000. This can greatly improve the debugging efficiency of the camera 1000. Specifically, the user observes the clarity of the four corners of the projection pattern 4000 on the substrate 2000 to adjust the level of the camera 1000.

[0091] This embodiment is based on the principle of reversibility of light and uses the projection pattern 4000 of the light-emitting diode 4 on the substrate to be inspected 2000 to determine the photosensitivity effective area 5000 of the substrate of the CMOS image chip, thereby avoiding the problem of low debugging efficiency caused by signal delay in the camera imaging image as the basis for debugging in the prior art.

[0092] Example 2

[0093] like Figure 13 This embodiment includes most of the technical features of Example 1. The difference between this embodiment and Example 1 is that the camera 1000 in this embodiment is a line array camera. The camera debugging method described in this embodiment further includes the following steps: the user observes the position of the reflected light emitted by the light-emitting diode 4 after it is reflected by the substrate 2000 to be inspected, determines the placement and angle of the light source 3000, and adjusts the bright-field and dark-field imaging modes of the camera 1000.

[0094] The above is a detailed introduction to a CMOS image chip, camera, and debugging method thereof provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. At the same time, for those skilled in the art, based on the concept of the present application, there may be changes in the specific implementation methods and application scope. In summary, the contents of this specification should not be understood as limiting the present application.

Claims

1. A CMOS image chip, characterized in that: include: A photosensitive area and a light-emitting area surrounding the photosensitive area; The CMOS image chip includes: A circuit layer, located in the photosensitive area and the light-emitting area; a plurality of photodiodes disposed on the circuit layer of the photosensitive region and electrically connected to the circuit layer; and a plurality of light emitting diodes, disposed on the circuit layer of the light emitting area and electrically connected to the circuit layer; a plurality of lenses, disposed on a side of the plurality of photodiodes and the plurality of light-emitting diodes away from the circuit layer, and each of the lenses is disposed opposite to the corresponding photodiode or the corresponding light-emitting diode; a substrate, located on the circuit layer in the photosensitive area and the circuit layer in the light-emitting area; Wherein, the photodiode and the light-emitting diode share the circuit layer and the substrate; Wherein, a surface of the light-emitting layer of any one of the light-emitting diodes on a side away from the circuit layer is flush with a surface of the substrate on a side away from the circuit layer.

2. The CMOS image chip according to claim 1, characterized in that: The plurality of photodiodes are disposed on the substrate in the photosensitive area.

3. The CMOS image chip according to claim 2, characterized in that: A first opening is formed on the substrate in the light emitting area, and the light emitting diode is located in the first opening.

4. The CMOS image chip according to claim 1, characterized in that: The light emitting diode is a Micro LED or a Mini LED.

5. The CMOS image chip according to claim 3, characterized in that: Each of the light-emitting diodes comprises: a substrate, a light-emitting layer disposed on a side of the substrate facing the circuit layer, and a P pole and an N pole spaced apart and disposed on a side of the light-emitting layer away from the substrate; The circuit layer corresponding to the first opening has a first electrode and a second electrode electrically connected to the P pole and the N pole in a one-to-one correspondence.

6. The CMOS image chip according to claim 5, characterized in that: Each of the light emitting diodes further comprises a bump metal disposed between the P pole and the first electrode and between the N pole and the second electrode.

7. The CMOS image chip according to claim 5, characterized in that: The CMOS image chip further includes: an anti-reflection layer, disposed on a side of the substrate away from the circuit layer; a second opening is provided between two adjacent photodiodes, and the anti-reflection layer is further filled in the second opening; and an encapsulation layer, filling the first opening; The surfaces of the packaging layer, the light-emitting diode, and the anti-reflection layer on a side away from the circuit layer are flush.

8. The CMOS image chip according to claim 7, characterized in that: The CMOS image chip further includes: a metal grid, disposed on a side of the anti-reflection layer away from the circuit layer and corresponding to the second opening; a first flat layer, disposed on a side of the anti-reflection layer, the light-emitting diode, and the packaging layer away from the circuit layer; a color resist unit, disposed between adjacent metal grids on a side of the first flat layer away from the circuit layer; a second planar layer, disposed on a side of the color resist unit and the first planar layer away from the circuit layer; and A plurality of lenses are arranged on a side of the second flat layer away from the circuit layer and are arranged corresponding to the color resistance unit and the light emitting diode.

9. The CMOS image chip according to claim 3, characterized in that: The length of the bottom side of the first opening close to the circuit layer is smaller than the length of the bottom side of the first opening away from the circuit layer.

10. A camera, characterized in that: include: The CMOS image chip and lens according to any one of claims 1 to 9; The camera includes one of an area array camera and a line array camera.

11. A camera debugging method according to claim 10, characterized in that: The following steps are involved: The display pattern of the light-emitting diode of the CMOS image chip is projected through the lens onto the substrate to be inspected to form a projection pattern. The user observes the clarity of the projection pattern on the substrate to be inspected and adjusts the focal length of the lens. The user observes the clarity of multiple points of the projection pattern on the substrate to be inspected and adjusts the levelness of the camera.

12. The camera debugging method according to claim 11, characterized in that: When the camera is a linear array camera, the method further includes the following steps: The user observes the position of the reflected light after the light emitted by the light emitting diode is reflected by the substrate to be inspected, determines the placement position and angle of the light source, and adjusts the bright and dark field imaging modes of the camera.

Images