Semiconductor device and method of manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a first gate, a semiconductor layer, a first gate dielectric layer, a second gate dielectric layer, a source electrode, a drain electrode, and a piezoelectric device. The first gate is located above the substrate. The semiconductor layer overlaps the first gate in the normal direction of the top surface of the substrate. The first gate dielectric layer is located between the semiconductor layer and the first gate. The second gate dielectric layer is located above the semiconductor layer. The source electrode and the drain electrode are electrically connected to the semiconductor layer. The piezoelectric device is located above the second gate dielectric layer and includes a metal oxide electrode, a piezoelectric material, and a top electrode stacked on each other. The semiconductor layer is located between the metal oxide electrode and the first gate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and particularly to a semiconductor device including a piezoelectric device and a manufacturing method thereof. Background Art

[0002] At present, common thin-film transistors usually use amorphous silicon semiconductors as channels. Since amorphous silicon semiconductors have simple manufacturing processes and low costs, they are widely used in various thin-film transistors.

[0003] With the progress of display technology, the resolution of display panels has been increasing year by year. In order to reduce the size of thin-film transistors in pixel circuits, many manufacturers are committed to researching and developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, indium gallium zinc oxide (IGZO) has the advantages of small area and high electron mobility, and is therefore regarded as an important new semiconductor material. Summary of the Invention

[0004] The present invention provides a semiconductor device that changes the magnitude of the drain current in response to changes in the applied pressure.

[0005] The present invention provides a manufacturing method of a semiconductor device, which has the advantages of high manufacturing process yield and low production cost.

[0006] At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first gate, a semiconductor layer, a first gate dielectric layer, a second gate dielectric layer, a source electrode, a drain electrode, and a piezoelectric device. The first gate is located on the substrate. The semiconductor layer overlaps the first gate in the normal direction of the top surface of the substrate. The first gate dielectric layer is located between the semiconductor layer and the first gate. The second gate dielectric layer is located on the semiconductor layer. The source electrode and the drain electrode are electrically connected to the semiconductor layer. The piezoelectric device is located on the second gate dielectric layer and includes a metal oxide electrode, a piezoelectric material, and a top electrode stacked on each other. The semiconductor layer is located between the metal oxide electrode and the first gate.

[0007] At least one embodiment of the present invention provides a manufacturing method of a semiconductor device, including: forming a first gate on the substrate; forming a first gate dielectric layer on the first gate; forming a semiconductor layer on the first gate dielectric layer, where the first gate dielectric layer is located between the semiconductor layer and the first gate; forming a second gate dielectric layer on the semiconductor layer; forming a source electrode and a drain electrode, where the source electrode and the drain electrode are electrically connected to the semiconductor layer; forming a piezoelectric device on the second gate dielectric layer, where the piezoelectric device includes a metal oxide electrode, a piezoelectric material, and a top electrode stacked on each other, and the semiconductor layer is located between the metal oxide electrode and the first gate. Description of the Drawings

[0008] Figure 1 is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present invention;

[0009] Figures 2A to 2K is Figure 1 a cross-sectional schematic view of a manufacturing method of the semiconductor device;

[0010] Figure 3 is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present invention;

[0011] Figure 4 is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present invention;

[0012] Figure 5 is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present invention;

[0013] Figures 6A to 6I is Figure 5 a cross-sectional schematic view of a manufacturing method of the semiconductor device;

[0014] Figure 7 is a graph showing the change in the voltage of the second gate or metal oxide electrode and the change in the drain current of a semiconductor device according to an embodiment of the present invention;

[0015] Figure 8 is a waveform diagram of the time and the change in the drain current of a semiconductor device according to an embodiment of the present invention.

[0016] Symbol description

[0017] 10A, 10B, 10C, 10D: Semiconductor device

[0018] 100: Substrate

[0019] 110: First gate dielectric layer

[0020] 120: Second gate dielectric layer

[0021] 130: Interlayer dielectric layer

[0022] 210: First gate

[0023] 220’, 220: Semiconductor layer

[0024] 222: Source region

[0025] 224: Channel region

[0026] 226: Drain region

[0027] 232: Source

[0028] 234: Drain

[0029] 240: Second gate

[0030] 300, 300a: Piezoelectric device

[0031] 310’, 310”: Metal oxide material layer

[0032] 310, 310a: Metal oxide electrode

[0033] 320: Piezoelectric material

[0034] 330: Top electrode

[0035] ND: Normal direction

[0036] OP1: Opening

[0037] P: Doping process

[0038] TH1: First contact hole

[0039] TH2: Second contact hole Detailed implementation mode

[0040] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0041] Please refer to Figure 1 , the semiconductor device 10A includes a substrate 100, a first gate 210, a semiconductor layer 220, a first gate dielectric layer 110, a second gate dielectric layer 120, a source 232, a drain 234, and a piezoelectric device 300.

[0042] The material of the substrate 100 can be glass, quartz, organic polymer, or light-blocking / reflective material (e.g., conductive material, metal, wafer, ceramic, or other applicable materials) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short-circuit problems.

[0043] The first gate 210 is located above the substrate 100. The material of the first gate 210 is, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, the above alloys, the above metal oxides, the above metal nitrides, or a combination of the above or other conductive materials. In some embodiments, other conductive layers and insulating layers may also be included between the first gate 210 and the substrate 100.

[0044] The first gate dielectric layer 110 is located on the first gate 210 and covers the first gate 210. The first gate dielectric layer 110 includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or other suitable materials, or a combination of the above.

[0045] The semiconductor layer 220 is located on the first gate dielectric layer 110. The first gate dielectric layer 110 is located between the semiconductor layer 220 and the first gate 210. The semiconductor layer 220 overlaps the first gate 210 in the normal direction ND of the top surface of the substrate 100. The material of the semiconductor layer 220 includes, for example, a metal oxide, such as indium gallium zinc oxide (IGZO), indium tungsten zinc oxide (IWZO), or other suitable metal oxide semiconductor materials. In this embodiment, the semiconductor layer 220 includes a source region 222, a drain region 226, and a channel region 224 located between the source region 222 and the drain region 226. The source region 222 and the drain region 226 are, for example, hydrogen-doped regions. The channel region 224 overlaps the first gate 210 in the normal direction ND. In this embodiment, a part of the source region 222 and a part of the drain region 226 also overlap the first gate 210 in the normal direction ND.

[0046] The second gate dielectric layer 120 is located on the semiconductor layer 220 and covers the semiconductor layer 220. The second gate dielectric layer 120 includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or other suitable materials, or a combination of the above.

[0047] The second gate 240 is located on the second gate dielectric layer 120 and overlaps the channel region 224 of the semiconductor layer 240 in the normal direction ND. The material of the second gate 240 is, for example, a metal such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, etc., the above alloys, the above metal oxides, the above metal nitrides, or a combination of the above or other conductive materials. When the second gate 240 contains aluminum, the second gate 240 can act as a hydrogen barrier layer, thereby reducing the probability of hydrogen atoms diffusing into the channel region 224.

[0048] The interlayer dielectric layer 130 is located on the second gate dielectric layer 120. The interlayer dielectric layer 130 includes an opening that overlaps the channel region 224 of the semiconductor layer 220 and the second gate 240, and the second gate 240 is located at the bottom of the aforementioned opening. Two contact holes penetrate the interlayer dielectric layer 130 and the second gate dielectric layer 120 and extend to the source region 222 and the drain region 226 of the semiconductor layer 220.

[0049] The interlayer dielectric layer 130 includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or other suitable materials, or a combination of the above. In some embodiments, the interlayer dielectric layer 130 includes hydrogen. In some embodiments, during the manufacturing process of the semiconductor device 10A, the hydrogen in the interlayer dielectric layer 130 diffuses to the source region 222 and the drain region 226 of the semiconductor layer 220 and the metal oxide electrode 310 through a heat treatment manufacturing process, but the present invention is not limited thereto. In other embodiments, the hydrogen diffuses to the source region 222, the drain region 226, and the metal oxide electrode 310 through a hydrogen plasma manufacturing process or other doping manufacturing processes.

[0050] The source 232 and the drain 234 are filled into two contact holes penetrating through the interlayer dielectric layer 130 and the second gate dielectric layer 120 to electrically connect to the source region 222 and the drain region 226 of the semiconductor layer 220, respectively. The materials of the source 232 and the drain 234 are, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, the above alloys, the above metal oxides, the above metal nitrides, or a combination of the above or other conductive materials.

[0051] The piezoelectric device 300 is located on the second gate dielectric layer 120 and includes a metal oxide electrode 310, a piezoelectric material 320, and a top electrode 330 stacked on each other.

[0052] The metal oxide electrode 310 is filled into the opening of the interlayer dielectric layer 130 to electrically connect to the second gate 240. In this embodiment, the metal oxide electrode 310 directly contacts the second gate 240. In this embodiment, the width of the bottom of the opening of the interlayer dielectric layer 130 is equal to the width of the metal oxide electrode 310, that is to say, the metal oxide electrode 310 fills the entire bottom of the opening of the interlayer dielectric layer 130. In some embodiments, the metal oxide electrode 310 includes indium gallium zinc oxide treated with fluorine. The semiconductor layer 220 is located between the metal oxide electrode 310 and the first gate 210.

[0053] The piezoelectric material 320 is located on the metal oxide electrode 310. In some embodiments, the piezoelectric material 320 includes a polymer or a composite material of a polymer and a ceramic material. For example, the piezoelectric material 320 includes P(VDF-TrFE) or a composite material of P(VDF-TrFE) and lead zirconate titanate (PZT).

[0054] The top electrode 330 is located on the piezoelectric material 320. In some embodiments, both the top electrode 330 and the source electrode 232 are electrically connected to a reference voltage, such as a ground voltage. In some embodiments, the material of the top electrode 330 is, for example, a metal such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, an alloy thereof, a metal oxide thereof, a metal nitride thereof, or a combination of the foregoing or other conductive materials. In the present embodiment, the side edges of the top electrode 330 are aligned with the side edges of the piezoelectric material 320, but the present invention is not limited thereto. In other embodiments, the side edges of the top electrode 330 are not aligned with the side edges of the piezoelectric material 320.

[0055] Figures 2A to 2K is Figure 1 a cross-sectional schematic view of a method for manufacturing a semiconductor device.

[0056] Please refer to Figure 2A , a first gate 210 is formed on the substrate 100. Then, a first gate dielectric layer 110 is formed on the first gate 210.

[0057] Please refer to Figure 2B , a semiconductor layer 220' is formed on the first gate dielectric layer 110, wherein the first gate dielectric layer 110 is located between the semiconductor layer 220' and the first gate 210. Then, a second gate dielectric layer 120 is formed on the semiconductor layer 220'.

[0058] Please refer to Figure 2C , a second gate 240 is formed on the second gate dielectric layer 120. Then, using the second gate 240 as a mask, a doping process P is performed on the semiconductor layer 220' to form a semiconductor layer 220 including a source region 222, a drain region 226, and a channel region 224. In some embodiments, the doping process P is, for example, a hydrogen plasma process.

[0059] In the present embodiment, the second gate dielectric layer 120 covers the semiconductor layer 220', but the present invention is not limited thereto. In other embodiments, the second gate dielectric layer 120 is patterned to expose the semiconductor layer 220' that does not overlap with the second gate 240. In some embodiments, the doping process P is performed on the semiconductor layer 220' after patterning the second gate dielectric layer 120.

[0060] Please refer to Figure 2D , an interlayer dielectric layer 130 is formed on the second gate 240 and the second gate dielectric layer 120. The interlayer dielectric layer 130 covers the second gate 240.

[0061] Please refer to Figure 2E , a first contact hole TH1 and a second contact hole TH2 are formed through the interlayer dielectric layer 130 and the second gate dielectric layer 120.

[0062] Please refer to Figure 2F , to form the source electrode 232 and the drain electrode 234. The source electrode 232 and the drain electrode 234 belong to the same patterned conductive layer. The source electrode 232 and the drain electrode 234 are respectively filled into the first contact hole TH1 and the second contact hole TH2 to electrically connect the source region 222 and the drain region 226 of the semiconductor layer 220.

[0063] Please refer to Figure 2G , an opening OP1 is formed in the interlayer dielectric layer 130, and the opening 1 exposes at least a part of the top surface of the second gate 240. In this embodiment, the opening OP1 is formed in the interlayer dielectric layer 130 after the source electrode 232 and the drain electrode 234 are formed, thereby avoiding damaging the top surface of the second gate 240 during the etching process for forming the source electrode 232 and the drain electrode 234.

[0064] Please refer to Figures 2H to 2K and Figure 1 , a piezoelectric device 300 is formed on the second gate 240.

[0065] Please refer to Figure 2H , a metal oxide material layer 310” is formed in the opening OP1. In this embodiment, the metal oxide material layer 310” extends outside the opening OP1 and covers the interlayer dielectric layer 130, the source electrode 232 and the drain electrode 234.

[0066] Then please refer to Figure 2I , the metal oxide material layer 310” is fluorinated. For example, the metal oxide material layer 310” is treated with fluorine plasma to obtain a fluorinated metal oxide material layer 310’.

[0067] Then please refer to Figure 2J , the fluorinated metal oxide material layer 310’ is patterned to obtain the metal oxide electrode 310. In this embodiment, the fluorine content in the metal oxide electrode 310 is greater than the fluorine content in the semiconductor layer 220. In some embodiments, the metal oxide electrode 310 is not hydrogen-doped. Therefore, the hydrogen content in the metal oxide electrode 310 is less than the hydrogen content in the source region 222 and the drain region 226, but the present invention is not limited thereto. In other embodiments, a hydrogen doping process is performed before or after the fluorination process. Therefore, the hydrogen content in the metal oxide electrode 310 is greater than or equal to the hydrogen content in the source region 222 and the drain region 226.

[0068] Please refer to Figure 2K, a piezoelectric material 320 is formed on a metal oxide electrode 310. In this embodiment, since the surface of the metal oxide electrode 310 is fluorine-treated, the diffusion of fluorine during the thermal annealing crystallization process of the piezoelectric material will form carbon-fluorine bonds (C-F, C-F 2 ), carbon-fluorine-hydrogen bonds (C-FH) in the piezoelectric material, so the crystallinity of the piezoelectric material 320 can be improved.

[0069] Finally, please return to Figure 1 , and a top electrode 330 is formed on the piezoelectric material 320. Thus, the semiconductor device 10A is substantially completed.

[0070] Figure 3 is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 3 The embodiment of Figure 1 adopts the component numbers and partial contents of the embodiment of

[0071] Figure 3 , where the same or similar component numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiment, which will not be elaborated here. Figure 1 The main difference between the semiconductor device 10B of

[0072] Figure 4 and the semiconductor device 10A of Figure 4 is that: the width of the metal oxide electrode 310 of the semiconductor device 10B is greater than the width of the bottom of the opening OP1 of the interlayer dielectric layer 130. The metal oxide electrode 310 extends along the side surface of the opening OP1 to the top surface of the interlayer dielectric layer 130, for example. Figure 1 The embodiment of

[0073] Figure 4 adopts the component numbers and partial contents of the embodiment of Figure 1 The main difference between the semiconductor device 10C of

[0074] Figure 5 and the semiconductor device 10A ofFigure 5 The embodiments of Figure 1 adopt the component numbers and partial content of the embodiments of

[0075] Figure 5 The main difference between the semiconductor device 10D of Figure 1 and the semiconductor device 10A of Figure 1 is that the metal oxide electrode 310a of the piezoelectric device 300a of the semiconductor device 10D is directly formed on the second gate dielectric layer 120. In other words, the semiconductor device 10D does not include a second gate (such as Figure 1 the second gate 240 of

[0076] Figures 6A to 6I . In this embodiment, the metal oxide electrode 310a is, for example, a hydrogen-doped and fluorine-treated metal oxide (such as indium gallium zinc oxide or indium tungsten zinc oxide).

[0076] Figures 6A to 6I is Figure 5 a cross-sectional schematic diagram of a manufacturing method of a semiconductor device of

[0077] Figure 6A Continuing from Figure 2B the manufacturing process of Figure 6A , a metal oxide material layer 310” is formed on the second gate dielectric layer 120. The metal oxide material layer 310” overlaps the entire semiconductor layer 220’ in the normal direction ND of the top surface of the substrate 100.

[0078] Please refer to Figure 6B , and the metal oxide material layer 310” is fluorine-treated. For example, the metal oxide material layer 310” is treated with fluorine plasma to obtain a fluorine-treated metal oxide material layer 310’. Since the metal oxide material layer 310” covers the semiconductor layer 220’, the probability of fluorine element diffusing into the semiconductor layer 220’ can be reduced.

[0079] Next, please refer to Figure 6C , and the fluorine-treated metal oxide material layer 310’ is patterned to obtain the metal oxide electrode 310. The metal oxide electrode 310 is formed on the second gate dielectric layer 120.

[0080] Please refer to Figure 6D , using the metal oxide electrode 310 as a mask, a doping process P is performed on the semiconductor layer 220’ to form a semiconductor layer 220 including a source region 222, a drain region 226, and a channel region 224. In some embodiments, the doping process P is, for example, a hydrogen plasma process. In this embodiment, the metal oxide electrode 310 becomes a hydrogen-doped metal oxide electrode 310a after the doping process P.

[0081] In this embodiment, the fluorine content in the hydrogen-doped metal oxide electrode 310a is greater than the fluorine content in the semiconductor layer 220.

[0082] Please refer to Figure 6E , an interlayer dielectric layer 130 is formed over the metal oxide electrode 310a and the second gate dielectric layer 120. The interlayer dielectric layer 130 covers the metal oxide electrode 310a.

[0083] Please refer to Figure 6F , a first contact hole TH1 and a second contact hole TH2 are formed through the interlayer dielectric layer 130 and the second gate dielectric layer 120. The first contact hole TH1 and the second contact hole TH2 expose the source region 222 and the drain region 226 of the semiconductor layer 220.

[0084] Please refer to Figure 6G , a source electrode 232 and a drain electrode 234 are formed. The source electrode 232 and the drain electrode 234 belong to the same patterned conductive layer. The source electrode 232 and the drain electrode 234 are respectively filled into the first contact hole TH1 and the second contact hole TH2 to electrically connect the source region 222 and the drain region 226 of the semiconductor layer 220.

[0085] Please refer to Figure 6H , an opening OP1 is formed in the interlayer dielectric layer 130, and the opening OP1 exposes the metal oxide electrode 310a. In this embodiment, the opening OP1 is formed in the interlayer dielectric layer 130 after the source electrode 232 and the drain electrode 234 are formed, thereby avoiding damage to the metal oxide electrode 310a during the etching process for forming the source electrode 232 and the drain electrode 234. However, the present invention is not limited thereto. In other embodiments, the first contact hole TH1, the second contact hole TH2, and the opening OP1 are formed through the same etching process.

[0086] Please refer to Figure 6I , a piezoelectric material 320 is formed on the metal oxide electrode 310a. In this embodiment, since the surface of the metal oxide electrode 310a is fluorine-treated, the diffusion of fluorine during the thermal annealing crystallization process of the piezoelectric material will form carbon-fluorine bonds (C-F, C-F 2 ), carbon-fluorine-hydrogen bonds (C-FH) in the piezoelectric material, so that the crystallinity of the piezoelectric material 320 can be improved.

[0087] Finally, please refer back to Figure 5 , a top electrode 330 is formed on the piezoelectric material 320. Thus, the semiconductor device 10D is substantially completed.

[0088] Figure 7It is a graph showing the change in the voltage of the second gate or metal oxide electrode and the change in the drain current of a semiconductor device according to an embodiment of the present invention. Figure 8 It is a waveform diagram showing the time and the change in the drain current of a semiconductor device according to an embodiment of the present invention.

[0089] Please refer to Figure 7 , the horizontal axis is the voltage V of the second gate or metal oxide electrode TG , and the vertical axis is the drain current (I D ).

[0090] When no additional pressure is applied to the piezoelectric device, the voltage-current curve of the semiconductor device conforms to Figure 7 the solid line in; when additional pressure is applied to the piezoelectric device, the voltage-current curve of the semiconductor device conforms to Figure 7 the dashed line in. When the voltage of the first gate is fixed and the semiconductor device is in the subthreshold region, after applying additional pressure to the piezoelectric device, the drain current will decrease from I 1 to I 2 , and there is a current change ΔI between I 1 and I 2 . By measuring the current change ΔI, the additional pressure applied to the piezoelectric device by the outside world can be known.

[0091] In this embodiment, since after applying additional pressure to the piezoelectric device, a positive voltage appears on the side of the piezoelectric material close to the metal oxide electrode, and a negative voltage appears on the side of the piezoelectric material close to the top electrode, therefore Figure 7 the dashed line in is shifted to the right compared to the solid line, that is, the drain current after applying pressure decreases. The positive and negative voltages generated when applying additional pressure are related to the polarization direction of the piezoelectric material. Therefore, in other embodiments, after applying additional pressure to the piezoelectric device, a negative voltage appears on the side of the piezoelectric material close to the metal oxide electrode, and a positive voltage appears on the side of the piezoelectric material close to the top electrode. At this time, the dashed line will shift to the left compared to the solid line, that is, the drain current after applying pressure increases.

[0092] In summary, the semiconductor device of the present invention will change the magnitude of the drain current in response to the change in the applied pressure. In addition, the semiconductor device of the present invention has the advantages of high manufacturing process yield and low production cost.

Claims

1. A semiconductor device, comprising: a substrate; a first gate located above the substrate; a semiconductor layer overlapping the first gate in the normal direction of the top surface of the substrate; a first gate dielectric layer located between the semiconductor layer and the first gate; a second gate dielectric layer located above the semiconductor layer; a source electrode and a drain electrode electrically connected to the semiconductor layer; a piezoelectric device located above the second gate dielectric layer and including a metal oxide electrode, a piezoelectric material, and a top electrode stacked on each other, wherein the metal oxide electrode of the piezoelectric device includes fluorine-treated indium gallium zinc oxide, the fluorine content in the metal oxide electrode is greater than the fluorine content in the semiconductor layer, the piezoelectric material is located between the metal oxide electrode and the top electrode, the metal oxide electrode is located between the piezoelectric material and the second gate dielectric layer, and wherein the semiconductor layer is located between the metal oxide electrode and the first gate; and an interlayer dielectric layer located on the second gate dielectric layer, wherein the interlayer dielectric layer includes hydrogen element and contacts the metal oxide electrode.

2. The semiconductor device according to claim 1, wherein the material of the semiconductor layer includes indium gallium zinc oxide.

3. The semiconductor device according to claim 1, wherein the semiconductor layer includes a hydrogen-doped source region, a hydrogen-doped drain region, and a channel region located between the source region and the drain region, and the metal oxide electrode is hydrogen-doped.

4. The semiconductor device according to claim 1, further comprising: a second gate overlapping the semiconductor layer in the normal direction, and the metal oxide electrode directly contacts the second gate.

5. The semiconductor device according to claim 1, wherein the interlayer dielectric layer includes an opening overlapping the semiconductor layer, and the metal oxide electrode fills the opening.

6. The semiconductor device according to claim 5, wherein the width of the metal oxide electrode is less than, greater than, or equal to the width of the bottom of the opening of the interlayer dielectric layer.

7. A method of manufacturing a semiconductor device, comprising: forming a first gate above a substrate; forming a first gate dielectric layer above the first gate; forming a semiconductor layer above the first gate dielectric layer, wherein the first gate dielectric layer is located between the semiconductor layer and the first gate; forming a second gate dielectric layer above the semiconductor layer; forming an interlayer dielectric layer on the second gate dielectric layer; forming a source electrode and a drain electrode on the interlayer dielectric layer, wherein the source electrode and the drain electrode are electrically connected to the semiconductor layer; and forming a piezoelectric device above the second gate dielectric layer, wherein the piezoelectric device includes a metal oxide electrode, a piezoelectric material, and a top electrode stacked on each other, wherein the metal oxide electrode of the piezoelectric device includes fluorine-treated indium gallium zinc oxide, the fluorine content in the metal oxide electrode is greater than the fluorine content in the semiconductor layer, the piezoelectric material is located between the metal oxide electrode and the top electrode, the metal oxide electrode is located between the piezoelectric material and the second gate dielectric layer, and wherein the semiconductor layer is located between the metal oxide electrode and the first gate, and wherein the interlayer dielectric layer includes hydrogen element and contacts the metal oxide electrode.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the method of forming the piezoelectric device comprises: forming the metal oxide electrode over the second gate dielectric layer; forming the piezoelectric material over the metal oxide electrode; and forming the top electrode over the piezoelectric material.

9. The method of manufacturing a semiconductor device according to claim 8, further comprises: after forming the metal oxide electrode, using the metal oxide electrode as a mask to perform a doping process on the semiconductor layer.

10. The method of manufacturing a semiconductor device according to claim 7, further comprises: forming a second gate over the second gate dielectric layer; and forming the piezoelectric device over the second gate.

11. The method of manufacturing a semiconductor device according to claim 10, further comprises: before forming the piezoelectric device, using the second gate as a mask to perform a doping process on the semiconductor layer.

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