Laminate and method for manufacturing an elastic wave device

Abstract

A laminate includes a wiring substrate and a plurality of device chips joined to the wiring substrate by a conductive material, the plurality of device chips including at least a first device chip and a second device chip adjacent to the first device chip, a separation region provided between the first device chip and the second device chip, and a first resin layer, a first metal layer, an intermediate separation region, a second metal layer, and a second resin layer in the separation region in a direction from the first device chip to the second device chip. A coefficient of thermal expansion of the wiring substrate is the same as a coefficient of thermal expansion in a first direction of the device chip having the largest coefficient of thermal expansion, and a direction having the largest coefficient of thermal expansion of the wiring substrate is parallel to the first direction.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a laminate and an elastic wave device. Background Technology

[0002] Japanese Patent Document 1 (JP2020-184703) illustrates an elastic wave device. Patent Document 1 describes that when a substrate using a connection layer such as bumps is mounted on a composite substrate formed by bonding substrates having different coefficients of thermal expansion, thermal stress is generated on the connection layer due to thermal strain in the composite substrate. The coefficient of thermal expansion of the device chip after dicing is also discussed in Patent Document 1.

[0003] The manufacture of elastic wave devices requires high production volumes. However, in the technology exemplified in Patent Document 1, the process of mounting the device chips after dicing to a substrate using flip-chip bonding technology is relatively complex, necessitating further increases in production volume. Summary of the Invention

[0004] In view of the above-mentioned problems, the present disclosure aims to provide a method for manufacturing a laminate and an elastic wave device that can improve production output.

[0005] This disclosure discloses a multilayer assembly comprising a wiring substrate and a plurality of device chips bonded to the wiring substrate by means of a conductive material. The plurality of device chips includes at least a first device chip and a second device chip adjacent to the first device chip. A separation region is provided between the first device chip and the second device chip. In the separation region, the multilayer assembly has a first resin layer, a first metal layer, an intermediate separation region, a second metal layer, and a second resin layer in the direction from the first device chip to the second device chip. The coefficient of thermal expansion of the wiring substrate is the same as the coefficient of thermal expansion of the device chip in a first direction with the largest coefficient of thermal expansion. The direction in which the wiring substrate has the largest coefficient of thermal expansion is parallel to the first direction.

[0006] In one embodiment of this disclosure, the coefficient of thermal expansion of the wiring substrate is the same as that of the device chip in a second direction orthogonal to the first direction.

[0007] In one embodiment of this disclosure, the wiring substrate has a first thermal expansion adjustment portion with a coefficient of thermal expansion smaller than that of the substrate of the wiring substrate along a direction parallel to the first direction, and a second thermal expansion adjustment portion with a coefficient of thermal expansion smaller than that of the substrate of the wiring substrate along a direction parallel to the second direction, wherein the density of the second thermal expansion adjustment portion is greater than that of the first thermal expansion adjustment portion.

[0008] In one embodiment of this disclosure, the first thermal expansion adjustment portion and the second thermal expansion adjustment portion are prepreg fibers.

[0009] In one embodiment of this disclosure, the wiring substrate has a third thermal expansion adjustment portion with a coefficient of thermal expansion greater than that of the substrate of the wiring substrate along a direction parallel to the first direction, and a fourth thermal expansion adjustment portion with a coefficient of thermal expansion greater than that of the substrate of the wiring substrate along a direction parallel to the second direction, wherein the density of the third thermal expansion adjustment portion is greater than that of the fourth thermal expansion adjustment portion.

[0010] In one embodiment of this disclosure, the third thermal expansion adjustment part and the fourth thermal expansion adjustment part are made of glass or copper.

[0011] In one embodiment of this disclosure, the device chip comprises lithium tantalate.

[0012] In one embodiment of this disclosure, the laminate further includes an upper resin layer formed on the upper surface of the device chip, wherein the first resin layer and the second resin layer are thinner than the upper resin layer.

[0013] In one embodiment of this disclosure, the upper resin layer has at least one hole, and the hole is filled with metal.

[0014] In one embodiment of this disclosure, the wiring substrate includes a plurality of unit wiring substrates, each of the unit wiring substrates being bonded to at least two of the device chip.

[0015] In one embodiment of this disclosure, the intermediate separation region is a gap.

[0016] In one embodiment of this disclosure, the laminate further includes a resin layer covering the side and top surface of the device chip and embedded in a notch in the wiring substrate located directly below the separation region. The resin layer includes a first resin layer and a second resin layer.

[0017] This disclosure describes a method for manufacturing an elastic wave device, comprising:

[0018] Step 1: Form multiple functional units on the piezoelectric wafer;

[0019] Step 2: Fabricate a wiring substrate with the same coefficient of thermal expansion as the first direction in which the coefficient of thermal expansion is largest in the piezoelectric wafer;

[0020] Step 3: Align the direction in which the wiring substrate has the maximum coefficient of thermal expansion with the first direction, and attach the piezoelectric wafer to the wiring substrate;

[0021] Step 4: Cut the piezoelectric wafer into multiple device chips, while at least not completely cutting off the wiring substrate;

[0022] Step 5: Forming a resin layer on the side and top surface of the device chip; and

[0023] Step 6: A metal layer is formed between the side and the top surface of the device chip, separated by the resin layer.

[0024] One form of this disclosure also includes:

[0025] Step 7: Cut the wiring substrate and perform a single-chip dicing process to form an elastic wave device having at least two adjacent device chips. The elastic wave device has the resin layer, the metal layer, an intermediate separation region, the metal layer, and the resin layer in the separation region between the device chips, along the direction from one device chip to the other device chip.

[0026] In one embodiment of this disclosure, a first cutting blade is used in step 4, and a second cutting blade, which is finer than the first cutting blade, is used in step 7.

[0027] In one embodiment of this disclosure, the coefficient of thermal expansion of the wiring substrate is the same as that of the piezoelectric wafer in a second direction orthogonal to the first direction.

[0028] In one embodiment of this disclosure, a first thermal expansion adjustment portion with a smaller coefficient of thermal expansion than the thermal expansion coefficient of the substrate of the wiring substrate is provided along a direction parallel to the first direction, and a second thermal expansion adjustment portion with a smaller coefficient of thermal expansion than the thermal expansion coefficient of the substrate of the wiring substrate is provided along a direction parallel to the second direction, wherein the density of the second thermal expansion adjustment portion is greater than the density of the first thermal expansion adjustment portion.

[0029] In one embodiment of this disclosure, the first thermal expansion adjustment portion and the second thermal expansion adjustment portion are prepreg fibers.

[0030] The beneficial effects of the present invention are that, according to this disclosure, a method for manufacturing a laminated body and an elastic wave device that increases production capacity can be provided. Attached Figure Description

[0031] Figure 1 This is a cross-sectional view of the laminate being manufactured in the first embodiment.

[0032] Figure 2 This is a plan view of the wiring substrate.

[0033] Figure 3 It is a plan view of the laminate.

[0034] Figure 4 This is a schematic diagram of cutting a piezoelectric wafer.

[0035] Figure 5 This is a schematic diagram of the formation of the resin layer.

[0036] Figure 6 This is a schematic diagram of the formation of the metal layer.

[0037] Figure 7 This is a schematic diagram of cutting the wiring board.

[0038] Figure 8 This is a plan view of the laminate being manufactured in the second embodiment.

[0039] Figure 9 This is a schematic diagram of the elastic wave device.

[0040] Figure 10 This is a schematic diagram of another type of elastic wave device.

[0041] Figure 11 This is a schematic diagram of a variation of a laminated body. Detailed Implementation

[0042] The specific embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the same or equivalent parts in each figure are labeled with the same reference numerals. The descriptions of the same or equivalent parts will be appropriately simplified or omitted.

[0043] (First Embodiment)

[0044] Figure 1 This is a cross-sectional view of the laminate in the manufacturing process of the first embodiment. The laminate includes a wiring substrate 2. According to one example, the wiring substrate 2 is, for example, a printed circuit board (PCB) or a high-temperature co-fired ceramic (HTCC) substrate. In other examples, any substrate including a substrate and wiring electrodes having penetrations through the substrate may be used as the wiring substrate 2. Figure 1 In one example, the wiring substrate 2 includes a substrate 2a, and an upper electrode 2b and a lower electrode 2c formed on opposite surfaces of the substrate 2a in a z-direction perpendicular to the x and y directions. The lower electrode 2c is electrically connected to the upper electrode 2b via through-hole wiring or the like. Passive components such as capacitors and inductors can be disposed inside the wiring substrate 2. According to one example, the wiring substrate 2 is a substrate in which unit wiring substrates are arranged in an array in a two-dimensional direction. In this case, the wiring substrate 2 may have multiple such unit wiring substrates.

[0045] The wiring substrate 2 is, for example, a sapphire substrate, alumina substrate, spinel substrate, quartz substrate, crystal substrate, or silicon substrate. In other examples, other substrates may also be used.

[0046] The stacked body further includes a piezoelectric wafer 3 on which multiple unit functional elements are formed. According to one example, the piezoelectric wafer 3 is made of lithium tantalate, or a material containing lithium tantalate. According to other examples, the piezoelectric wafer 3 is formed from a piezoelectric single crystal such as lithium tantalate, lithium niobate, or quartz. According to other examples, the piezoelectric wafer 3 is formed from piezoelectric ceramic. According to still other examples, the piezoelectric wafer 3 is a substrate formed by bonding a piezoelectric substrate and a support substrate. The main surface of the piezoelectric wafer 3, for example, is provided with an interdigital transducer (IDT) and a reflector. The main surface is provided with a wiring pattern formed of a suitable metal or alloy such as silver, aluminum, copper, titanium, or palladium.

[0047] like Figure 1 As shown, the piezoelectric wafer 3 is bonded to the wiring substrate 2 by a conductive material 4, which is, for example, a bump formed of gold, conductive adhesive or solder.

[0048] Figure 2 This is a plan view of the wiring substrate 2. The upper electrode 2b is omitted for simplicity. The wiring substrate 2 has a first thermal expansion adjustment portion 2d along a direction slightly parallel to the first direction (x-direction), whose coefficient of thermal expansion is smaller than that of the substrate 2a of the wiring substrate 2. According to one example, the first thermal expansion adjustment portion 2d is completely embedded inside the substrate 2a. According to other examples, the first thermal expansion adjustment portion 2d can be embedded in the substrate 2a while being exposed on either the upper or lower surface of the substrate 2a. In this example, the first thermal expansion adjustment portions 2d are arranged in groups of three, with five groups arranged at approximately equal intervals.

[0049] The wiring substrate 2 has a second thermal expansion adjustment portion 2e with a smaller coefficient of thermal expansion than that of the substrate 2a along a direction slightly parallel to the second direction (y-direction). According to one example, the second thermal expansion adjustment portion 2e is completely embedded within the substrate 2a. According to other examples, the second thermal expansion adjustment portion 2e can be embedded within the substrate 2a while also being exposed on either the upper or lower surface of the substrate 2a. In this example, the second thermal expansion adjustment portions 2e are arranged in groups of five, with approximately equal spacing between the five groups.

[0050] The density of the second thermal expansion adjustment portion 2e is greater than the density of the first thermal expansion adjustment portion 2d. In other words, the density of the second thermal expansion adjustment portion 2e per unit length along the first direction is greater than the density of the first thermal expansion adjustment portion 2d per unit length along the second direction. In this example, the number of second thermal expansion adjustment portions 2e is greater than the number of first thermal expansion adjustment portions 2d. The wiring substrate 2 has the largest coefficient of thermal expansion along the first direction and the smallest coefficient of thermal expansion along the second direction.

[0051] The materials of the first thermal expansion adjusting portion 2d and the second thermal expansion adjusting portion 2e are not limited to materials with a coefficient of thermal expansion smaller than that of the substrate 2a. For example, the first thermal expansion adjusting portion 2d and the second thermal expansion adjusting portion 2e can be prepreg fibers. For instance, glass fiber can be used as the material for the first thermal expansion adjusting portion 2d and the second thermal expansion adjusting portion 2e.

[0052] Figure 3 yes Figure 1 A planar view of the laminate. For example, using lithium tantalate as the material of the piezoelectric wafer 3, its coefficient of thermal expansion varies with direction. In other words, the coefficient of thermal expansion of the piezoelectric wafer 3 is anisotropic. For example, the coefficient of thermal expansion of the piezoelectric wafer 3 along the first direction (x-direction) is 16.1 ppm / K, and the coefficient of thermal expansion along the second direction (y-direction) is 4.1 ppm / K. In this example, the piezoelectric wafer 3 has the largest coefficient of thermal expansion along the first direction. According to other examples, the coefficient of thermal expansion of the piezoelectric wafer 3 along the first direction (x-direction) is 13 ppm / K, and the coefficient of thermal expansion along the second direction (y-direction) is 3 ppm / K.

[0053] According to one example, the wiring substrate 2 is fabricated to have the same anisotropy as the piezoelectric wafer 3 in terms of its coefficient of thermal expansion. In this example, the wiring substrate 2 has the largest coefficient of thermal expansion along the first direction, and the piezoelectric wafer 3 and the plurality of device chips described later also have the largest coefficient of thermal expansion along the first direction. In other words, the direction in which the wiring substrate 2 has the largest coefficient of thermal expansion is slightly parallel to the first direction. Furthermore, in a second direction (y-direction) orthogonal to the first direction, the coefficient of thermal expansion of the wiring substrate 2 is the same as that of the piezoelectric wafer 3 (and the plurality of device chips described later).

[0054] Therefore, by providing the first thermal expansion adjustment part 2d and the second thermal expansion adjustment part 2e on the wiring substrate 2 to adjust the thermal expansion coefficient of the wiring substrate 2, the thermal expansion coefficient of the wiring substrate 2 can be made approximately the same as that of the piezoelectric wafer 3. This prevents or suppresses significant distortion of the laminate even after heat treatment such as reflow soldering.

[0055] In the example described, although the coefficient of thermal expansion of the piezoelectric wafer 3 is anisotropic, a piezoelectric wafer with a non-anisotropic coefficient of thermal expansion can also be used. Even in this case, by providing a thermal expansion adjustment section on the wiring substrate 2, the coefficient of thermal expansion of the wiring substrate 2 can be made approximately the same as that of the piezoelectric wafer 3, thereby preventing or suppressing significant distortion of the laminate.

[0056] The following describes a method for manufacturing an elastic surface wave device including the fabrication of the aforementioned laminate. First, in step 1, a plurality of unit functional elements are formed on the piezoelectric wafer 3. These unit functional elements are, for example, elastic surface wave devices such as bandpass filters, dual filters, and duplexers.

[0057] Next, step 2 is performed. In this second step, the wiring substrate 2 is fabricated. The wiring substrate 2, for example, has the same coefficient of thermal expansion as the first direction in which the coefficient of thermal expansion is largest in the piezoelectric wafer 3. According to one example, as previously described, the coefficient of thermal expansion of the wiring substrate 2 is made approximately the same as that of the piezoelectric wafer 3 by providing the first thermal expansion adjustment portion 2d and the second thermal expansion adjustment portion 2e.

[0058] Next, step 3 is performed. In this third step, the direction of the maximum thermal expansion coefficient in the wiring substrate 2 is aligned with the first direction, and the piezoelectric wafer 3 is bonded to the wiring substrate 2. In this example, as... Figure 1 As shown, the piezoelectric wafer 3 and the wiring substrate 2 are electrically connected and bonded together by the conductive material 4.

[0059] At this point, based on one of the examples, such as Figure 3 As shown, the piezoelectric wafer 3 and the wiring substrate 2 are bonded together such that in the second direction (y direction) orthogonal to the first direction (x direction), the coefficient of thermal expansion of the wiring substrate 2 is the same as that of the piezoelectric wafer 3.

[0060] Next, step 4 is performed. In this fourth step, the piezoelectric wafer 3 is diced into individual functional units. Figure 4 In the process, the piezoelectric wafer 3 is diced using a first cutting blade C1 to form multiple device chips. This dicing process creates multiple device chips arranged in an array in a two-dimensional direction. Figure 4 Examples of the device chips are first device chip 3a, second device chip 3b, first device chip 3c, second device chip 3d, and first device chip 3e. Furthermore, a separation region R1 is provided between two of the device chips. Figure 4Example: A separation region R1 is provided between the first device chip 3a and its adjacent second device chip 3b. Also, the separation region R1 is provided between the first device chip 3c and its adjacent second device chip 3d. According to one example, a notch 2u can be cut into a portion of the wiring substrate 2 using the first cutting blade C1 while the piezoelectric wafer 3 is being cut. However, the wiring substrate 2 is not completely cut in the fourth step. Forming the notch 2u in the wiring substrate 2 can increase the sealing performance of the resin to the wiring substrate 2 and improve reliability. If improved sealing performance is not required, the notch 2u can be omitted. Furthermore, the wiring substrate 2 can also employ an ultra-thin chip-scale packaging (CSP).

[0061] Next, step 5 is performed. In step 5, a resin layer 5 is formed on the side surface and the top surface of the device chip. For example... Figure 5 The resin layer 5 is formed in step 5, as shown. According to one example, a resin sheet is placed across multiple device chips after slicing. According to one example, the resin sheet is obtained by pressing liquid epoxy resin into a sheet shape. According to other examples, the resin sheet can be a synthetic resin such as polyimide, which is different from epoxy resin. A protective film made of polyethylene terephthalate (PET) can be provided on the upper surface of the resin sheet, or a base film made of polyester fiber can be provided on the lower surface of the resin sheet.

[0062] The resin sheet is temporarily fixed to the plurality of device chips by placing it on them. Then, using an upper roller heated to at least the softening temperature of the resin sheet, the resin sheet is formed on the upper surface of the plurality of device chips and fills the space between the sides of the plurality of device chips and the upper surface of the wiring substrate 2. This method is called hot rolling. Other methods besides hot rolling can also be used as long as lamination is achieved.

[0063] Next, to fully harden the resin sheet, for example, pressure is applied to the resin sheet towards the wiring substrate 2 using a hot press equipped with an upper mold and a lower mold heated to the resin's curing temperature. This allows the resin to harden while suppressing the expansion of air in the space S1 below the device chip. Figure 5As shown, upper resin layers 5A, 5B, 5C, 5D, and 5E are formed on the upper surfaces of the first device chip 3a, the second device chip 3b, the first device chip 3c, the second device chip 3d, and the first device chip 3e, respectively. Furthermore, first resin layers 5a, 5b, 5c, 5d, and 5e are formed on the side surfaces of the first device chip 3a, the second device chip 3b, the first device chip 3c, the second device chip 3d, and the first device chip 3e, respectively. According to one example, the first resin layers 5a, 5c, 5e and the second resin layers 5b, 5d are thinner than the upper resin layers 5A, 5B, 5C, 5D, and 5E. Figure 5 As shown, for example, the thickness z1 of the upper resin layer 5A is greater than the thickness z2 of the first resin layer 5a. Furthermore, the notch 2u is filled by the embedded resin layer 5x.

[0064] According to the example, the resin sheet is temporarily heated to a softening temperature, then pressure is applied to deform it, causing the resin sheet to adhere tightly to the outer surface of the device chip and the upper surface of the wiring substrate 2. The shape is then fixed by heating to a curing temperature, thus forming the resin layer 5. The resin layer 5, for example, makes the space S1 below the device chip a sealed space and strengthens the adhesion of the device chip to the plurality of wiring substrates 2. Figure 5 In one example, the space S1 is a sealed space surrounded by the main surface of the device chip, the upper surface of the wiring substrate 2, and the resin layer 5. In one example, the resin layer 5 is a thermosetting resin. Therefore, while forming the space S1 between the resin layer 5, the wiring substrate 2, and the plurality of device chips, the plurality of device chips are sealed. The resin layer 5 can also be replaced by any insulator, metal, or a resin layer and a metal layer.

[0065] According to one example, after step 5 and before step 6, a step of grinding the resin layer 5 is also included. In the step of grinding the resin layer 5, grinding may continue until the cut piezoelectric wafer 3 is exposed. This grinding step may also be omitted.

[0066] Next, step 6 is performed. In step 6, a metal layer 6 is formed between the side surface and the top surface of the device chip, separated by the resin layer 5. Figure 6 The example shows the metal layer 6 formed in step 6. According to one example, the metal layer 6 is formed using an electroless electroplating method. Figure 6As shown, a portion of the metal layer 6 is formed on the upper resin layers 5A, 5B, 5C, 5D, and 5E, respectively. Furthermore, another portion of the metal layer 6 forms a first metal layer 6a in contact with the first resin layer 5a, a second metal layer 6b in contact with the second resin layer 5b, a first metal layer 6c in contact with the first resin layer 5c, and a second metal layer 6d in contact with the second resin layer 5d. Additionally, another portion of the metal layer 6 is formed on the embedded resin layer 5x.

[0067] like Figure 6 The stack shown, in the separation region R1 between the two device chips, along the direction from one device chip to the other, includes the resin layer 5, the metal layer 6, an intermediate separation region, the metal layer 6, and the resin layer 5. More specifically, the stack... Figure 6 Of the two separation regions R1, the left separation region R1, along the direction from the first device chip 3a to the second device chip 3b, has a first resin layer 5a, a first metal layer 6a, the intermediate separation region, a second metal layer 6b, and a second resin layer 5b. Of the two separation regions R1, the right separation region R1, along the direction from the first device chip 3c to the second device chip 3d, has a first resin layer 5c, a first metal layer 6c, the intermediate separation region, a second metal layer 6d, and a second resin layer 5d. According to one example, the intermediate separation region is a void.

[0068] Proceed to step 7. In step 7, at least two adjacent device chips from a plurality of device chips are individually cut by slicing the wiring substrate 2 to form an elastic wave device. For example... Figure 7 As shown, the wiring substrate 2 is cut in step 7. Figure 7 In one example, the wiring substrate 2 is completely cut off. By cutting the wiring substrate 2, a unit wiring substrate is separated from multiple unit wiring substrates. One unit wiring substrate is connected to at least two of the device chips. According to one example, in step 7, the wiring substrate 2 is completely cut off using a second cutting blade C2. For example, the width x2 of the second cutting blade C2 is thinner than the width x1 of the first cutting blade C1 used in step 4. Because of the use of the thinner second cutting blade C2, the resin layer 5 and the metal layer 6 on the sides of the device chip can be preserved.

[0069] In the example described, although cutting blades are used in steps 4 and 7, at least one of these steps can be replaced by laser cutting instead of a cutting blade. According to other examples, ultrasonic cutting or laser stealth cutting may also be used.

[0070] According to one example, once step 7 is completed, an elastic wave device having the first device chip 3a and the second device chip 3b can be provided. The elastic wave device has a first resin layer 5a, a first metal layer 6a, the intermediate separation region, a second metal layer 6b, and a second resin layer 5b in the separation region R1 between the first device chip 3a and the second device chip 3b, along the direction from the first device chip 3a to the second device chip 3b. Therefore, the isolation between the first device chip 3a and the second device chip 3b can be improved. By improving isolation, for example, the propagation of unnecessary signals between different frequency bands can be suppressed. According to one example, the first device chip 3a or the second device chip 3b is a transmitting or receiving SAW filter using an elastic wave element. The transmitting or receiving SAW filter is a trapezoidal filter formed by multiple series resonators and multiple parallel resonators. According to another example, the first device chip 3a or the second device chip 3b is a filter using a thin-film acoustic resonator. According to yet another example, the first device chip 3a or the second device chip 3b can be any type of elastic wave element.

[0071] Assuming the resin layer on the side of the device chip is relatively thick, the spacing between the first and second device chips must be increased to reliably form the metal layer on the resin layer. In contrast, according to the example above, the first resin layer 5a and the second resin layer 5b are thinner than the upper resin layers 5A and 5B. As resin layers located on the side of the device chip, the thinner first resin layer 5a and the second resin layer 5b can shorten the distance between the first device chip 3a and the second device chip 3b, and allow the metal layer to be formed in the separation region R1. Therefore, the manufacturing method of the laminate and elastic wave device of the first embodiment is suitable for miniaturization and can improve isolation.

[0072] The elastic wave device having the first device chip 3c and the second device chip 3d also has the same attack effect as the elastic wave device having the first device chip 3a and the second device chip 3b.

[0073] Here, we describe the case where one elastic wave device has two device chips. However, the unit wiring substrate cut from step 7 can also accommodate more than three device chips.

[0074] In this way, the piezoelectric wafer 3 and the wiring substrate 2 are bonded together by wafer-level bonding to form the stack, which can, for example, improve the efficiency of the manufacturing process, suppress process variation, and increase yield.

[0075] (Second Embodiment)

[0076] The manufacturing method of the laminate and the elastic wave device in the second embodiment is similar to that in the first embodiment, so only the parts that are different from the first embodiment will be described. Figure 8 This is a plan view of the laminate of the second embodiment. The wiring substrate 2' has a third thermal expansion adjustment portion 2f along a direction slightly parallel to the first direction (x-direction), whose coefficient of thermal expansion is greater than that of the substrate 2a of the wiring substrate 2'. In this example, the third thermal expansion adjustment portions 2f are arranged in groups of five, with approximately equal spacing between the five groups.

[0077] Furthermore, the wiring substrate 2' has a fourth thermal expansion adjustment portion 2g along a direction slightly parallel to the second direction (y-direction), whose coefficient of thermal expansion is greater than that of the substrate 2a of the wiring substrate 2'. In this example, the fourth thermal expansion adjustment portions 2g are arranged in groups of three, with five groups spaced at approximately the same interval. Therefore, the density of the third thermal expansion adjustment portion 2f is greater than the density of the fourth thermal expansion adjustment portion 2g.

[0078] In the example, the number of third thermal expansion adjustment parts 2f is greater than the number of fourth thermal expansion adjustment parts 2g. The wiring substrate 2' has the largest coefficient of thermal expansion along the first direction and the smallest coefficient of thermal expansion along the second direction.

[0079] The materials of the third thermal expansion adjusting part 2f and the fourth thermal expansion adjusting part 2g are not limited to materials with a thermal expansion coefficient greater than that of the material of the substrate 2a. The third thermal expansion adjusting part 2f and the fourth thermal expansion adjusting part 2g are, for example, glass or copper.

[0080] The wiring substrate 2' has the largest coefficient of thermal expansion in the first direction (x direction) and the smallest coefficient of thermal expansion in the second direction (y direction). Therefore, the piezoelectric wafer, which has the largest coefficient of thermal expansion in the first direction and the smallest coefficient of thermal expansion in the second direction, combined with the wiring substrate 2' to form a multilayer, can prevent or suppress significant distortion even after heat treatment such as reflow soldering.

[0081] In the first and second embodiments, a wiring substrate with anisotropy that is substantially the same as the aforementioned anisotropy is fabricated for a piezoelectric wafer with an anisotropic coefficient of thermal expansion. According to other examples, the coefficient of thermal expansion of the wiring substrate may, for example, be adjusted by the thermal expansion adjustment unit to be the same as the maximum coefficient of thermal expansion of the piezoelectric wafer. In this case, for example, the coefficient of thermal expansion of the wiring substrate is isotropic.

[0082] Furthermore, a thermal expansion adjustment part with a smaller coefficient of thermal expansion than the substrate and a thermal expansion adjustment part with a larger coefficient of thermal expansion than the substrate can be provided on a wiring substrate to make the thermal expansion coefficient of the wiring substrate close to that of the piezoelectric wafer.

[0083] Figure 9 This is a schematic diagram of the main surface 50 of the device chip in the first and second embodiments. The main surface 50 is provided with an interdigital transducer (IDT) 52a and a pair of reflectors 52b. The IDT 52a and the reflectors 52b can excite elastic surface waves. The IDT 52a and the reflectors 52b are formed, for example, of an alloy of aluminum and copper, titanium, palladium, silver, or alloys thereof, or are multilayer metal structures composed of multiple stacked metal layers. The IDT 52a has a pair of comb-shaped electrodes 52c. The comb-shaped electrodes 52c are opposite each other. The comb-shaped electrodes 52c have multiple electrode fingers 52d and a busbar 52e. The busbar 52e connects the electrode fingers 52d.

[0084] Figure 10 These are schematic diagrams of the device chip in the first and second embodiments. In the example, the device chip is a thin-film acoustic resonator. Figure 10 The chip in the device is a semiconductor such as silicon, or an insulating substrate such as sapphire, alumina, spinel, or glass. A piezoelectric film 62 is provided on the chip substrate 60. The material of the piezoelectric film 62 is, for example, aluminum nitride. A lower electrode 64 and an upper electrode 66 sandwich the piezoelectric film 62 therein. The lower electrode 64 and the upper electrode 66 are made of metals such as ruthenium. A gap 68 is formed between the lower electrode 64 and the chip substrate 60. The lower electrode 64 and the upper electrode 66 excite elastic waves in a thickness-longitudinal vibration mode within the piezoelectric film 62.

[0085] Figure 11This is a schematic diagram of a multilayer structure that improves heat dissipation, representing a variation of the first and second embodiments. The upper resin layer 5A has two holes 5A', and the upper resin layer 5B has two holes 5B'. The holes 5A' and 5B' can be formed by, for example, laser processing of the resin layer 5. The holes 5A' are filled with metal 7A, and the holes 5B' are filled with metal 7B. According to one example, the metals 7A and 7B, and the metal layer 6 are simultaneously formed using an electroless nickel plating method. The metal 7A improves the heat dissipation of the first device chip 3a. The metal 7B improves the heat dissipation of the second device chip 3b. Any number of metals can be formed on one device chip.

[0086] While at least one embodiment has been described above, it should be understood that various changes, modifications, or improvements will readily occur to those skilled in the art. These changes, modifications, or improvements are also part of this disclosure and fall within the scope of this invention.

[0087] It should be understood that the embodiments of the methods or apparatus described herein are not limited to the architecture and arrangement of the constituent components described above or illustrated in the accompanying drawings. The methods and apparatus can be installed or performed in other embodiments.

[0088] The embodiments described are for illustrative purposes only and are not intended to be limiting.

[0089] The descriptions and terms used in this disclosure are for illustrative purposes only and are not intended to be limiting. The use of "including," "possessing," "having," "comprise," and variations thereof here means to include the items listed below, their equivalents, and additional items.

[0090] The word “or”, or any word used in a description, may be interpreted as one, more than one, or all of the descriptive words.

[0091] The references to front, back, left, right, top, bottom, upper, lower, and horizontal and vertical are for ease of description and are not intended to limit the position and spatial configuration of any component in this invention. Therefore, the above description and drawings are merely exemplary.

Claims

1. A laminate, characterized in that: The multilayer assembly includes a wiring substrate and a plurality of device chips bonded to the wiring substrate by means of a conductive material. The plurality of device chips includes at least a first device chip and a second device chip adjacent to the first device chip. A separation region is provided between the first device chip and the second device chip. In the separation region, the multilayer assembly has a first resin layer, a first metal layer, an intermediate separation region, a second metal layer, and a second resin layer in the direction from the first device chip to the second device chip. The coefficient of thermal expansion of the wiring substrate is the same as the coefficient of thermal expansion of the device chip in a first direction where the coefficient of thermal expansion is greatest. The direction of the wiring substrate with the greatest coefficient of thermal expansion is parallel to the first direction. In a second direction orthogonal to the first direction, the coefficient of thermal expansion of the wiring substrate is the same as the coefficient of thermal expansion of the device chip. The thermal expansion coefficients are the same. Specifically, the wiring substrate has a first thermal expansion adjustment portion with a smaller thermal expansion coefficient than the substrate material along a direction parallel to the first direction, and a second thermal expansion adjustment portion with a smaller thermal expansion coefficient than the substrate material along a direction parallel to the second direction. The density of the second thermal expansion adjustment portion is greater than the density of the first thermal expansion adjustment portion. Alternatively, the wiring substrate has a third thermal expansion adjustment portion with a larger thermal expansion coefficient than the substrate material along a direction parallel to the first direction, and a fourth thermal expansion adjustment portion with a larger thermal expansion coefficient than the substrate material along a direction parallel to the second direction. The density of the third thermal expansion adjustment portion is greater than the density of the fourth thermal expansion adjustment portion.

2. The laminate according to claim 1, characterized in that: The first thermal expansion adjustment part and the second thermal expansion adjustment part are prepreg fibers.

3. The laminate according to claim 1, characterized in that: The third and fourth thermal expansion adjustment parts are made of glass or copper.

4. The laminate according to any one of claims 1 to 3, characterized in that: The device chip contains lithium tantalate.

5. The laminate according to claim 1, characterized in that: The stack further includes an upper resin layer formed on the upper surface of the device chip, wherein the first resin layer and the second resin layer are thinner than the upper resin layer.

6. The laminate according to claim 5, characterized in that: The upper resin layer has at least one hole, and the hole is filled with metal.

7. The laminate according to claim 1, characterized in that: The wiring substrate includes a plurality of unit wiring substrates, each of which is bonded to at least two of the device chips.

8. The laminate according to claim 1, characterized in that: The intermediate separation region is a gap.

9. The laminate according to claim 1, characterized in that: The stack further includes a resin layer covering the side and top surface of the device chip and embedded in a notch in the wiring substrate located directly below the separation region. The resin layer includes a first resin layer and a second resin layer.

10. A method for manufacturing an elastic wave device, characterized in that... Include: Step 1: Form multiple functional units on the piezoelectric wafer; Step 2: Fabricate a wiring substrate with the same coefficient of thermal expansion as the first direction in which the coefficient of thermal expansion is largest in the piezoelectric wafer; Step 3: Align the direction in which the wiring substrate has the maximum coefficient of thermal expansion with the first direction, and attach the piezoelectric wafer to the wiring substrate; Step 4: Cut the piezoelectric wafer into multiple device chips, while at least not completely cutting off the wiring substrate; Step 5: Forming a resin layer on the side and top surface of the device chip; and Step 6: A metal layer is formed between the side surface and the top surface of the device chip, separated by the resin layer; In the second direction orthogonal to the first direction, the thermal expansion coefficient of the wiring substrate is the same as that of the piezoelectric wafer. A first thermal expansion adjustment portion with a thermal expansion coefficient smaller than that of the substrate is provided in the direction parallel to the first direction of the wiring substrate, and a second thermal expansion adjustment portion with a thermal expansion coefficient smaller than that of the substrate is provided in the direction parallel to the second direction. The density of the second thermal expansion adjustment portion is greater than that of the first thermal expansion adjustment portion.

11. The method for manufacturing the elastic wave device according to claim 10, characterized in that... Also includes: Step 7: Cut the wiring substrate and perform a single-chip dicing process to form an elastic wave device having at least two adjacent device chips. The elastic wave device has the resin layer, the metal layer, an intermediate separation region, the metal layer, and the resin layer in the separation region between the device chips, along the direction from one device chip to the other device chip.

12. The method for manufacturing the elastic wave device according to claim 11, characterized in that: The first cutting blade is used in step 4, and a second cutting blade that is finer than the first cutting blade is used in step 7.

13. The method for manufacturing the elastic wave device according to claim 10, characterized in that: The first thermal expansion adjustment part and the second thermal expansion adjustment part are prepreg fibers.

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