A high-order FIR digital filter based on reduced calculation

Abstract

The present invention proposes a high-order FIR digital filter based on reduced calculation. The filter taps are n single-bit binary random coefficients. During each sampling period, the filter inputs a sampling point and calculates the product of the n sampling points and the previous n-1 sampling points, which are composed of n sampling points and n binary random coefficients. The multiplication result of the sampling point and the binary random coefficient is specified: if the coefficient is 1, the multiplication result is the value of the original sampling point; otherwise, the multiplication result is the inverse of the sampling point. Based on this reduced calculation, the present invention designs a high-order FIR digital filter based on a data broadcast structure. The sampling point and the binary random coefficient are combined into n items. The partial sum of the combined items is a finite number of items. A lookup table with a small depth is used to compress the large number of repeated additions required to calculate the partial sum at each addition node. Each addition node of the filter obtains the corresponding partial sum by matching the address of each table entry in the lookup table, which greatly reduces the use of adders.

Description

Technical Field

[0001] The invention relates to the technical field of time domain capture, and mainly relates to a high-order FIR digital filter based on reduced calculation. Background Art

[0002] Currently, FIR digital filters are widely used in fields such as signal processing. Their design requires both amplitude and phase characteristics. As systems increasingly demand higher speed and real-time performance, research on high-performance filters has important theoretical and engineering value.

[0003] The time domain expression of the FIR digital filter is:

[0004]

[0005] h(n) is the filter coefficient, x(ni) is the input sampling point, y(n) is the product of the multiplication and accumulation of the input sampling point and the filter coefficient, and N is the filter order. An FIR digital filter consists of a finite number of sampling points. The convolution operation in the left-hand equation is simplified to the product of the multiplication and accumulation of N sampling points and N coefficients in each sampling period in the right-hand equation.

[0006] In fact, the larger the FIR order, the longer the coefficient length corresponding to h(n), and the higher the hardware complexity of the final implementation. Currently, there are mainly the following types of FPGA implementations of high-order FIR digital filters: FIR digital filters based on MAC structure, FIR digital filters based on distributed algorithms, and FIR digital filters based on FFT. The limitations of FPGA implementations of these three types of FIR digital filters are analyzed below:

[0007] First, for the FIR digital filter based on the distributed algorithm, the input N-bit data is disassembled into N-bit binary, and a depth of 2 is established based on all the multiplication results of N filter coefficients and N-bit binary numbers. N Although this method saves multiplier resource consumption and can be optimized by splitting the lookup table to reduce the lookup table resource consumption and increasing the number of lookup tables to increase the calculation speed, for high-order FIR digital filters, the lookup table resource consumption is still huge.

[0008] Second, for FIR digital filters based on FFTs, the convolution operation between the filter input sampling points and the coefficients is transformed into a frequency-domain multiplication operation through FFT. Finally, the multiplication result is restored to a time-domain sequence through IFFT. Although this reduces FPGA resource usage, system performance is severely limited by data operation latency.

[0009] Third, for FIR digital filters based on multiplier structures, especially high-order FIR digital filters based on data broadcasting, input data is first broadcast to each multiplier and then sent to each adding node for delayed accumulation, effectively ensuring real-time and efficient data processing. FPGAs offer a clear advantage in processing speed. However, for high-order FIR digital filters, ensuring real-time processing speed and efficiency requires a significant number of adders in hardware implementation. Therefore, compressing adders is necessary to conserve hardware resources for implementing high-order FIR digital filters. Summary of the Invention

[0010] The present invention proposes a high-order FIR digital filter based on reduction calculation, characterized in that the high-order FIR digital filter includes a combination module, a lookup table, a broadcast module, a Gate node, a Pipeline module, a hard-wired module, an addition node and a cache module;

[0011] The combination module performs multiple combinations of sampling points;

[0012] The lookup table stores the partial sums formed by reducing the multiple combination sampling points and the corresponding addresses in order of addresses from small to large, and the addresses are binary numbers after the multiple combinations.

[0013] The broadcast module is used to transmit the portion in the lookup table and the address to the corresponding Gate node;

[0014] The Gate node saves the partial sum and adds a flag bit to the partial sum;

[0015] The Pipeline module is connected to the Gate node, and synchronizes and outputs the data output by the Gate node within a cycle;

[0016] The hard-wired module is connected to the Pipeline module, and simultaneously outputs the partial sum or the inverse of the partial sum to the addition node according to the flag bit for the time-sharing input value of each addition node;

[0017] The adding node adopts a time-division multiplexing strategy to accumulate the input data from the hard-wired module and the input data from the cache module, and stores the accumulated result in the cache module;

[0018] The cache module is arranged between each addition node, and the cache module caches data of a preset period and then inputs the data into the adjacent addition node.

[0019] Furthermore, the combination module first performs n combinations on the new sampling points in the current sampling period and the n sampling points in the previous n-1 sampling periods, a total of n combinations; the binary random coefficients of the filter with an original length of m also need to be combined in n terms, and the partial sum formed by the reduced calculation of the sampling points and the binary random coefficients after the n combinations is calculated.

[0020] Furthermore, the address of the lookup table is composed of 2 n-bit binary numbers with the highest bit of the address being 0. n-1 All possible sortings are listed; each of the addresses corresponds to a partial sum formed by the reduced calculation of the n-bit binary number and the current n sampling points.

[0021] Furthermore, the number of the Gate nodes is m / n, and the Gate nodes are provided with node addresses, and the node addresses are determined by the binary random coefficients corresponding to the locations thereof after being combined by n items;

[0022] Assume that the system operating frequency is k times the sampling frequency, if k>2 n-1 , the broadcast module every 1 / 2 n-1 Each Gate node compares its n-bit node address with the currently broadcast n-bit lookup table address in cycles; otherwise, if k<2 n-1 The broadcast module compares the n-bit node address with the current broadcast 2-bit node address every 1 / k cycles. n-1 / k n-bit lookup table addresses are compared;

[0023] If the n-bit Gate node address is equal to the currently broadcast n-bit lookup table address, this Gate node saves the partial sum corresponding to the lookup table address and adds a flag bit 0 to the highest bit when outputting; if the n-bit Gate node address is the opposite of the currently broadcast n-bit lookup table address, this Gate node saves the partial sum corresponding to the lookup table address and adds a flag bit 1 to the highest bit when outputting.

[0024] Furthermore, the hard-wired module includes a shift register group, an inverting unit, and a two-to-one multiplexer: the shift register group is used to input values ​​from each node of the pipeline module; the inverting unit is used to generate the inverse of the input partial sum; the partial sum data output by the shift register group is directly input to the two-to-one multiplexer and then input to the two-to-one multiplexer after passing through the inverting unit;

[0025] The flag bit output by the shift register group serves as a flag signal of a two-to-one multiplexer. If the flag signal is 0, the two-to-one multiplexer outputs a partial sum that enters the addition node; if the flag signal is 1, the opposite of the two-to-one multiplexer outputs a partial sum that enters the addition node.

[0026] Furthermore, the cache module is set between two adding nodes and is composed of a shift register group of n+1 stages from C1 to Cn+1, and one sampling cycle is divided into k system working cycles;

[0027] During the 1st to k-1th system working cycles, Cn+1 receives the result of the previous adder through the last register in this stage in each system working cycle, and shifts it upward within the stage. When it reaches the kth system working cycle, it is shifted into Cn as a whole, and the data input during the kth system working cycle directly enters the last register of Cn;

[0028] After one sampling cycle, C2~Cn move data to the next level register. C1 outputs the result to the adder through the first register of this level in each system working cycle and shifts it upward within the level.

[0029] The beneficial effects of the present invention are:

[0030] The present invention implements a high-order FIR digital filter based on reduced computation. This filter combines sampling points with binary random coefficients into n combinations. By utilizing the fact that the partial sums of these combinations are finite, a lookup table with a relatively low depth is used to compress the numerous repeated additions required to calculate the partial sums at each adding node. Each adding node in the filter obtains the corresponding partial sum by matching the addresses of the lookup table entries, significantly reducing the number of adders used. The advantage of saving adders achieved by the present invention is more significant for higher-order FIR digital filters. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 1 is an overall structural diagram of a high-order FIR digital filter based on reduced calculation provided by an embodiment of the present invention;

[0032] Figure 2 This is a structural diagram of a hard-wired module within a high-order FIR digital filter based on protocol calculation provided by an embodiment of the present invention.

[0033] Figure 3 This is a diagram of the input and output structure of a single addition node within a high-order FIR digital filter based on reduced calculation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The technical solutions of the present invention are described in more detail below with reference to the accompanying drawings. The present invention includes but is not limited to the following embodiments.

[0035] The purpose of the present invention is to provide a high-order FIR digital filter based on reduced calculation, which includes a combination module, a lookup table, a broadcast module, a Gate node, a pipeline module, a hard-wired module, an addition node and a cache module.

[0036] The combined module sets the sampling point X under the new sampling period i+n and the sampling point X of the previous n-1 sampling periods i+n-1 ,...,X i+2 ,X i+1 Perform n combinations, which is equivalent to a shift register group of length n. The sampling point X in the new sampling period i+n Entering from the bottom side of the shift register group, the sampling points of the corresponding first n-1 cycles slide upward by 1 length, and X0 slides upward out of this shift register group; and for the binary random coefficients of the filter, the original filter binary coefficients of length m are grouped in order from left to right to perform n combination operations.

[0037] The lookup table converts the sampling point X under the new sampling period into i+n and the sampling point X of the previous n-1 sampling periods i+n-1 ,...,X i+2 ,X i+1 After performing n combinations and calculating the 2 n Possible partial sums.

[0038] To further compress resources, address 0 and address 2 n-1 The sum of the parts corresponding to -1 is the opposite number relationship, address 1 and address 2 n-1 The partial sum corresponding to -2 is also the opposite number relationship, so the lookup table entries that need to be established are only the partial sums whose highest bit of the address is 0, and the number of corresponding lookup table entries can be obtained by 2 n Reduced to 2 n-1 .

[0039] Build depth 2 n-1 Lookup table: where 2 is an n-bit binary number with the highest address bit being 0. n-1 The possible sortings are fully enumerated, and each entry address corresponds to the partial sum formed by the reduced calculation of the n-bit binary number and the current n sampling points.

[0040] Specifically, based on the reduced computational characteristics, if the binary coefficient is 0000, the partial sum accumulated after multiplying it with the sample point ABCD is Y1 = -(ABCD); if the binary coefficient is 1111, the partial sum accumulated after multiplying it with the sample point ABCD is Y2 = ABCD. It can be seen that Y1 and Y2 are inverse numbers. Therefore, if the current cycle broadcast address is 0000 and the gate node address is 1111, the gate node stores the partial sum corresponding to address 0000 and outputs a flag bit in the highest bit, indicating that the partial sum that this gate node actually needs to pass on is the inverse of the currently stored partial sum. In summary, only the partial sum corresponding to the 0xxx address needs to be established.

[0041] When broadcasting, the broadcast module matches the address corresponding to the table entry with the address of each addition node of the Gate node. If the match is successful, the corresponding Gate node addition node obtains the corresponding partial sum.

[0042] The number of gate nodes is m / n, and the node address of each gate node is determined by the binary random coefficient corresponding to its location after n combinations.

[0043] Specifically, assuming that the system operating frequency is k times the sampling frequency, if k>2 n-1 , the broadcast module every 1 / 2 n-1 Each Gate node compares its n-bit node address with the currently broadcast n-bit lookup table address in cycles; otherwise, if k<2 n-1 The broadcast module compares the n-bit node address with the current broadcast 2-bit node address every 1 / k cycles. n-1 / k n-bit lookup table addresses are compared;

[0044] If they are equal, this Gate node saves the partial sum corresponding to the lookup table address and adds a flag bit 0 to the highest bit when outputting; if this n-bit Gate node address is the opposite of the currently broadcast n-bit lookup table address, this Gate node saves the partial sum corresponding to the lookup table address and adds a flag bit 1 to the highest bit when outputting.

[0045] At this point, 2 n-1 The partial sums are fully enumerated by lookup table and broadcast to the addition nodes. There must be a large number of duplicates in the partial sums received between the addition nodes. n-1 The lookup table compresses a large number of repeated additions after each addition node performs n combinations with the binary random coefficients.

[0046] The number of nodes in the Pipeline module is the same as the number of Gate nodes, which is m / n and corresponds one to one. Due to the time difference of the output of each Gate node, the Pipeline module is used to synchronize the output value of each Gate node to the hardwired module.

[0047] The hardwired module includes a shift register group, an inverting unit, and a binary multiplexer. If the system operating frequency is k times the sampling frequency, a time-division multiplexing strategy is adopted for the addition nodes: m / n nodes from the pipeline module are divided into k groups, and the outputs of (m / n) / k nodes from the pipeline module are calculated in 1 / k system operating cycles. Therefore, the total number of addition nodes consumed is only (m / n) / k.

[0048] The shift register group is a first-in, first-out memory used to obtain the output values ​​of the Pipeline module from the input end according to the time-sharing calculation order of the addition node; the flag data at the output end is directly connected to the two-to-one multiplexer, and the partial sum is input into the two-to-one multiplexer and the inversion unit respectively.

[0049] The negation unit is used to generate the inverse of the input partial sum, and the inverse is input into the two-to-one multiplexer.

[0050] The flag bit output by the shift register group serves as the flag signal of the two-to-one multiplexer. If the flag signal is 0, the output of the two-to-one multiplexer is partially summed and enters the addition node; if the flag signal is 1, the inverse of the output of the two-to-one multiplexer is partially summed and enters the addition node.

[0051] Thus, through the above device, the length of the original filter is changed from m to (m / n) / k, and the number of addition nodes of the corresponding filter is (m / n) / k.

[0052] The cache module is arranged between each adding node and realizes the series connection of each adding node. The cache module caches the data of n sampling cycles and then inputs the data into the next adding node.

[0053] Specifically, since the sampled data and the filter's binary random coefficients are combined into n combinations, the original filter's one-sample-cycle delay between adder nodes needs to be converted to a delay of n sample cycles according to register retiming principles. Therefore, n register levels, C1 through Cn, are required. Furthermore, because the adder nodes are time-shared for k system operating cycles, an additional register level, Cn+1, is required. Thus, C1 through Cn-1 each constitute a one-sample-cycle delay, while Cn and Cn+1 constitute a one-sample-cycle delay.

[0054] If we divide a sampling period into k system operating cycles, the number of shift registers in each stage corresponds to a single system operating cycle. Thus, during the 1st to k-1th system operating cycles, C2-Cn maintain their positions, and during the kth system operating cycle, they shift to the next stage register as a whole, simultaneously receiving the data from the previous stage as a whole.

[0055] For Cn+1, during the 1st to k-1th system working cycles, Cn+1 receives the result of the previous adder through the last register in this stage in each system working cycle, and shifts it upward within the stage. When it reaches the kth system working cycle, it is moved into Cn as a whole, and the data input during the kth system working cycle directly enters the last register of Cn.

[0056] After one sampling cycle, C2~Cn move data to the next level register. C1 outputs the result to the adder through the first register of this level in each system working cycle and shifts it upward within the level.

[0057] It is worth noting that since Cn+1 requires a system working cycle to write the result of the previous stage into the last register in this stage, in the kth cycle, Cn+1 only writes k-1 numbers. Then, in the kth cycle, Cn+1 is shifted as a whole to Cn.

[0058] In one embodiment, the original FIR digital filter has a length of 4096, the system operating frequency is 96 MHz, and a 16-bit sampled data input is used at each 12 MHz sampling frequency. The requirement is to calculate the cumulative multiplication results of 4096 16-bit sample points and 4096 1-bit binary random coefficients at each 12 MHz sampling frequency. The binary random coefficients correspond to the coefficients of the FIR filter and are either 0 or 1. The input sample points correspond to the data input to the FIR filter. The multiplication result of a sample point and a 1-bit binary coefficient is specified as follows: if the coefficient is 1, the multiplication result is the value of the sample point; otherwise, the multiplication result is the inverse of the value of the sample point.

[0059] Before combining, the FIR filter based on the data broadcast structure receives new sample data during each sampling cycle and broadcasts it to 4096 adding nodes. The value received by each adding node is determined by the single-bit binary random coefficient of 0 or 1 at its corresponding position as the value of the current sampling point or the value of the current sampling point after taking its inverse. In this case, the number of adders required in each sampling cycle is 4096, which consumes too much adder resources.

[0060] Therefore, in the current embodiment, the sampling points and the binary random coefficients of the filter are firstly selected to perform four combination operations: the sampling points X under the new sampling period i+4 The sampling point X of the first three sampling cycles i+3 ,X i+2 ,X i+1 This operation is equivalent to a shift register group of length 4. The sampling point X in the new sampling period is i+4 Entering from the bottom of the shift register group, the sampling points corresponding to the first three cycles slide upward by one length, and X0 slides upward out of this shift register group. At the same time, the filter binary coefficients of length 4096 are grouped from left to right and subjected to four combination operations. After these four combination operations, the filter length is reduced from the original 4096 to 1024.

[0061] Secondly, the rule that the possible outcomes of the four sampling point combinations and the four-bit binary random number in each sampling period are reduced to a maximum of 16 possible results, thus the partial sums calculated between each adding node inevitably contain a large number of duplicate entries. To further conserve adder resources, only the table entries corresponding to the partial sums from "address 0000" to "address 0111" need to be established. The partial sums corresponding to "address 1000" to "address 1111" can be directly obtained by negating the partial sums of the corresponding addresses. In summary, the 24 adders consumed by each entry in the depth-8 lookup table further reduce the repeated additions of the four combinations of binary random coefficients by each adding node, allowing each adding node in the filter to obtain the corresponding partial sum by matching the addresses of the lookup table entries.

[0062] As attached Figure 1 As shown, in view of the 8-fold relationship between the sampling frequency 12MHz and the system operating frequency 96MHz, the partial sum in the compressed lookup table entry can generate a partial sum within 8 working cycles and be broadcast to 1024 Gate nodes in a time-sharing manner in the order of "address 0000" to "address 0111". The broadcast content is divided into two parts: one part is a 4-bit broadcast coefficient, corresponding to the address corresponding to each table entry in the lookup table; the other part is an 18-bit partial sum corresponding to the address of each table entry in the lookup table. Specifically, when each table entry in the lookup table broadcasts the address and the corresponding partial sum periodically, each Gate node compares its 4-bit address with the 4-bit broadcast coefficient in each cycle. If they are equal, this Gate node outputs the corresponding partial sum and adds a flag bit 0 to the highest bit when outputting, which is used to mark that the received weighted sum can be sent to the addition node for direct accumulation later; otherwise If the 4-bit local coefficient is equal to the bitwise inversion of the 4-bit broadcast coefficient, then this Gate node outputs the corresponding partial sum and adds a flag bit 1 to the highest bit during output to indicate that the received weighted sum needs to be inverted before being sent to the addition node for accumulation. The data format output by each Gate node is: {1-bit flag, 18-bit partial sum}. Given that the partial sums output by all Gate nodes have a time difference, in order to ensure that all addition nodes can simultaneously receive the corresponding partial sums and flag signals, when all Gate nodes receive the flag signal and the corresponding partial sum and output them, a Pipeline module is added between the Gate node and the addition node level for first-level caching to synchronize the output signals of all Gate nodes. The number of nodes in the Pipeline module is the same as the number of Gate nodes, both 1024, and they correspond one to one.

[0063] As attached Figure 2As shown, the hardwired module includes a shift register group, an inverting unit, and a two-to-one multiplexer. Because the system's operating frequency of 96MHz is eight times the sampling frequency of 12MHz, one sampling cycle is divided into eight system operating cycles. A time-sharing multiplexing strategy is implemented for the addition nodes: 128 addition nodes calculate the outputs of 1024 nodes from the pipeline module in eight cycles. The shift register group contains eight registers. Values ​​from each node in the pipeline module enter the shift register group from the right in the order of the calculation cycles, with values ​​entering in adjacent cycles shifted to the left. The inverting unit is used to generate the inverse of the input partial sum: the flag bit output by the shift register group serves as the flag signal for the two-to-one multiplexer. If the flag signal is 0, the output partial sum of the two-to-one multiplexer enters the addition node; if the flag signal is 1, the inverse of the output partial sum of the two-to-one multiplexer enters the addition node.

[0064] As attached Figure 3 As shown, the cache module is set between each adding node and realizes the series connection of each adding node. The cache module caches the data of 4 cycles and then inputs it into the next adding node.

[0065] Specifically, since the sampled data and the filter's binary random coefficients are combined into four combinations, the one-sample-cycle delay between the original filter's adder nodes needs to be changed to a four-sample-cycle delay according to register retiming principles. Therefore, four register levels, C1, C2, C3, and C4, are required. Furthermore, because the adder nodes are time-shared for eight cycles, an additional register level, C5, is required. Thus, C1, C2, and C3 each constitute a one-sample-cycle delay, while C4 and C5 constitute a one-sample-cycle delay.

[0066] If we divide one sampling period into eight system operating cycles, the number of shift registers in each stage corresponds to a single system operating cycle. Thus, during the first to seventh system operating cycles, C2, C3, and C4 remain constant. By the eighth system operating cycle, the entire registers are shifted to the next stage, simultaneously receiving the entire data from the previous stage.

[0067] For C5, during the 1st to 7th system working cycles, C5 receives the result of the previous adder through the last register in this stage in each system working cycle, shifts it upward within the stage, and is moved into C4 as a whole in the 8th system working cycle.

[0068] For C1, each system working cycle outputs the result to the adder through the first register of this stage and shifts it upward within the stage.

[0069] It is worth noting that since C5 needs a system working cycle to write the result of the previous stage into the last register in this stage, in the 8th cycle, only 7 numbers are written into C5. Then, when C5 is shifted to C4 as a whole in the 8th cycle,

[0070] The present invention is not limited to the above-mentioned specific embodiments. A person skilled in the art can implement the present invention in a variety of other specific embodiments based on the embodiments and the contents disclosed in the drawings. Therefore, any design that adopts the design structure and ideas of the present invention and makes some simple transformations or changes falls within the scope of protection of the present invention.

Claims

1. A high-order FIR digital filter based on reduced calculation, characterized in that: The high-order FIR digital filter includes a combination module, a lookup table, a broadcast module, a Gate node, a Pipeline module, a hard-wired module, an addition node and a cache module; The combination module performs multiple combinations of sampling points; The lookup table stores the partial sums formed by reducing the multiple combination sampling points and the corresponding addresses in order of addresses from small to large, wherein the addresses are binary numbers after the multiple combinations; The broadcast module is used to transmit the portion in the lookup table and the address to the corresponding Gate node; The Gate node saves the partial sum and adds a flag bit to the partial sum; The Pipeline module is connected to the Gate node, and synchronizes and outputs the data output by the Gate node within a cycle; The hard-wired module is connected to the Pipeline module, and simultaneously outputs the partial sum or the inverse of the partial sum to the addition node according to the flag bit for the time-sharing input value of each addition node; The adding node adopts a time-division multiplexing strategy to accumulate the input data from the hard-wired module and the input data from the cache module, and stores the accumulated result in the cache module; The cache module is arranged between each addition node, and the cache module caches data of a preset period and then inputs the data into the adjacent addition node.

2. The high-order FIR digital filter according to claim 1, wherein The combination module first performs n-item combinations on the new sampling points in the current sampling period and the n-1 sampling periods before it; the binary random coefficients of the filter with an original length of m also need to be combined in n items, and the partial sum formed by the reduced calculation of the sampling points and the binary random coefficients after the n-item combination is calculated.

3. The high-order FIR digital filter according to claim 2, characterized in that The address of the lookup table is composed of n-bit binary numbers with the highest bit of the address being 0. n-1 All possible sortings are listed; each of the addresses corresponds to a partial sum formed by the reduced calculation of the n-bit binary number and the current n sampling points.

4. The high-order FIR digital filter according to claim 3, characterized in that: The number of the Gate nodes is m / n, and the Gate nodes are provided with node addresses, which are determined by the binary random coefficients corresponding to the locations thereof after n combinations; Assume that the system operating frequency is k times the sampling frequency, if k>2 n-1 , the broadcast module every 1 / 2 n-1 In each cycle, each Gate node compares its n-bit node address with the currently broadcast n-bit lookup table address; otherwise, if k<2 n-1 The broadcast module compares the n-bit node address with the current broadcast 2-bit node address every 1 / k cycles. n-1 / k n-bit lookup table addresses are compared; If the n-bit Gate node address is equal to the currently broadcast n-bit lookup table address, this Gate node saves the partial sum corresponding to the lookup table address and adds a flag bit 0 to the highest bit when outputting; if the n-bit Gate node address is the opposite of the currently broadcast n-bit lookup table address, this Gate node saves the partial sum corresponding to the lookup table address and adds a flag bit 1 to the highest bit when outputting.

5. The high-order FIR digital filter according to claim 4, characterized in that: The hard-wired module includes a shift register group, an inverting unit, and a two-to-one multiplexer: the shift register group is used to input values ​​from each node of the pipeline module; the inverting unit is used to generate the inverse of the input partial sum; the partial sum data output by the shift register group is directly input to the two-to-one multiplexer and then input to the two-to-one multiplexer after passing through the inverting unit; The flag bit output by the shift register group serves as a flag signal of a two-to-one multiplexer. If the flag signal is 0, the two-to-one multiplexer outputs a partial sum that enters the addition node; if the flag signal is 1, the opposite of the two-to-one multiplexer outputs a partial sum that enters the addition node.

6. The high-order FIR digital filter according to claim 4, characterized in that: The cache module is set between two adding nodes and is composed of n+1 shift register groups from C1 to Cn+1. One sampling cycle is divided into k system working cycles. During the 1st to k-1th system working cycles, Cn+1 receives the result of the previous adder through the last register in this stage in each system working cycle, and shifts it upward within the stage. When it reaches the kth system working cycle, it is shifted into Cn as a whole, and the data input during the kth system working cycle directly enters the last register of Cn; After one sampling cycle, C2~Cn move data to the next level register. C1 outputs the result to the adder through the first register of this level in each system working cycle and shifts it upward within the level.

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