signal processing circuitry

Abstract

The present application provides a signal processing circuit, which includes an input buffer circuit and a DC detection circuit. The input buffer circuit is coupled to a pin. The pin is used to receive an input signal. The DC detection circuit is coupled to the pin and the input buffer circuit. The DC detection circuit is used to detect the input signal to generate a mode signal, and to bias the input buffer circuit according to the mode signal.

Description

Technical Field

[0001] The embodiments described in this invention relate to a signal processing technique, and more particularly to a signal processing circuit that can maintain a high dynamic range. Background Technology

[0002] In some signal processing techniques, an AC-coupled capacitor is placed between the input terminal and the signal processing circuit (e.g., audio processing circuit). This AC-coupled capacitor filters out the direct current (DC) component of the input signal received at the input terminal, thereby giving the signal a better low-frequency response. However, this reduces the dynamic range of the signal path. Summary of the Invention

[0003] Some embodiments of the present invention relate to a signal processing circuit. The signal processing circuit includes an input buffer circuit and a DC detection circuit. The input buffer circuit is coupled to a pin. The pin is used to receive an input signal. The DC detection circuit is coupled to the pin and the input buffer circuit. The DC detection circuit is used to detect the input signal to generate a mode signal, and biases the input buffer circuit according to the mode signal.

[0004] In summary, in the signal processing circuit of this invention, the DC detection circuit can detect the DC voltage of the input signal to bias the input buffer circuit. In this way, the input buffer circuit can maintain a high dynamic range. Attached Figure Description

[0005] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:

[0006] Figure 1 This is a schematic diagram of a signal processing system according to some embodiments of the present invention;

[0007] Figure 2 This is a schematic diagram of a signal processing system according to some embodiments of the present invention;

[0008] Figure 3 This is a functional block diagram of a signal processing circuit according to some embodiments of the present invention;

[0009] Figure 4 As shown in some embodiments of the present invention Figure 3 A flowchart illustrating the operation of the signal processing circuit;

[0010] Figure 5 As shown in some embodiments of the present invention Figure 3 The circuit diagram of the signal processing circuit;

[0011] Figure 6 A circuit diagram illustrating a DC voltage generating circuit according to some embodiments of the present invention;

[0012] Figure 7 As shown in some embodiments of the present invention Figure 5 The equivalent circuit diagram of the signal processing circuit in the first mode;

[0013] Figure 8 As shown in some embodiments of the present invention Figure 5 The equivalent circuit diagram of the signal processing circuit in the second mode; and

[0014] Figure 9 As shown in some embodiments of the present invention Figure 5 The equivalent circuit diagram of the signal processing circuit in the third mode. Detailed Implementation

[0015] In this specification, the term "coupled" may also refer to "electrical coupling," and the term "connected" may also refer to "electrical connection." "Coupled" and "connected" may also refer to two or more components cooperating or interacting with each other.

[0016] refer to Figure 1 . Figure 1 This is a schematic diagram of a signal processing system 100 according to some embodiments of the present invention. The signal processing system 100 includes a signal processing circuit 110 and a signal processing circuit 120. The signal processing circuit 110 or the signal processing circuit 120 may be implemented by an integrated circuit (IC).

[0017] by Figure 1 For example, the signal processing circuit 110 includes a pin P_MIC, an input buffer circuit 111, and a DC detection circuit 112. In some embodiments, the microphone MIC is coupled to the pin P_MIC. The pin P_MIC is used to receive the audio input signal from the microphone MIC. For example, the pin P_MIC is coupled to a resistor R0 and the microphone MIC at node N1. The resistor R0 is used to receive the bias signal MIC_BIAS. The input buffer circuit 111 is coupled to the pin P_MIC and is used to receive the input signal VIN1 (which may be the aforementioned audio input signal from the microphone MIC). The DC detection circuit 112 is coupled to the pin P_MIC and the input buffer circuit 111 and is used to detect the DC voltage of the input signal VIN1 to bias the input buffer circuit 111 according to the detection result.

[0018] Similarly, the signal processing circuit 120 includes a pin P_LINE, an input buffer circuit 121, and a DC detection circuit 122. In some embodiments, other integrated circuits or other electronic devices are coupled to the pin P_LINE. The pin P_LINE is used to receive an audio source input signal from the other integrated circuit or other electronic device. The input buffer circuit 121 is coupled to the pin P_LINE and is used to receive an input signal VIN2 (which may be the aforementioned audio source input signal from the other integrated circuit or other electronic device). The DC detection circuit 122 is coupled to the pin P_LINE and the input buffer circuit 121, and is used to detect the DC voltage of the input signal VIN2 to bias the input buffer circuit 121 according to the detection result.

[0019] It should be noted that the above and following paragraphs are illustrated using "audio source signal" as the input signal, but the present invention is not limited thereto. In some other embodiments, the input signal is not "audio source signal".

[0020] refer to Figure 2 . Figure 2 This is a schematic diagram of a signal processing system 200 according to some embodiments of the present invention. Figure 2 Signal processing system 200 and Figure 1 The main difference between the signal processing systems 100 is that... Figure 2 In the signal processing system 200, an AC-coupled capacitor C1 is coupled between pin P_MIC and node N1, and an AC-coupled capacitor C2 is coupled between pin P_LINE and other integrated circuits or other electronic devices. AC-coupled capacitor C1 is used to filter out the DC component of the signal from node N1 (i.e., input signal VIN1). Similarly, AC-coupled capacitor C2 is used to filter out the DC component of the signal from other integrated circuits or other electronic devices (i.e., input signal VIN2). In some embodiments, AC-coupled capacitors C1-C2 are disposed on a printed circuit board. Figure 2 Other operating modes of the signal processing system 200 in the system are similar to Figure 1 The signal processing system is similar to that in the 100, and will not be described in detail here.

[0021] because Figure 1 The signal processing system 100 does not have AC coupling capacitors C1 and C2, therefore compared to Figure 2 Signal processing system 200, Figure 1 The signal processing system 100 can achieve the effect of small area and low cost.

[0022] In some related technologies, AC coupling capacitors are used to filter out the DC component of the input signal in order to achieve better low-frequency response. However, this reduces the dynamic range of the signal path.

[0023] Compared to the aforementioned related technologies, in this invention, regardless of whether an AC coupling capacitor is provided ( Figure 1 The signal processing system 100 does not have an AC coupling capacitor. Figure 2 The signal processing system 200 is equipped with an AC coupling capacitor, and the DC detection circuit 112 (or DC detection circuit 122) can detect the DC component of the input signal VIN1 (or input signal VIN2), and bias the input buffer circuit 111 (or input buffer circuit 121) according to the detection result. In this way, regardless of whether the AC coupling capacitor is provided, the input buffer circuit 111 (or input buffer circuit 121) can be biased by a relatively appropriate DC common-mode voltage, so that the signal still maintains a high dynamic range.

[0024] refer to Figure 3 . Figure 3 This is a functional block diagram of a signal processing circuit 300 according to some embodiments of the present invention. In some embodiments, the signal processing circuit 300 is used to implement... Figure 1 (or Figure 2 The signal processing circuit 110 or signal processing circuit 120 in the signal processing circuit.

[0025] by Figure 3 For example, the signal processing circuit 300 includes an input buffer circuit 131 and a DC detection circuit 132. The DC detection circuit 132 includes a DC voltage generation circuit 1321 and a mode selection circuit 1322. The DC voltage generation circuit 1321 is coupled to a pin PIN to receive the input signal VIN. The pin PIN can be... Figure 1 (or Figure 2 The input signal VIN can be either pin P_MIC or pin P_LINE. Figure 1 (or Figure 2 The input signal is either VIN1 or VIN2. The DC voltage generation circuit 1321 is used to track the input signal VIN and generate a DC voltage V. MIC_IN The mode selection circuit 1322 is coupled to the DC voltage generation circuit 1321 and the input buffer circuit 131. The mode selection circuit 1322 is used to receive the threshold voltage value V. TH And the DC voltage V MIC_IN With threshold voltage value V TH The comparison is performed to generate a mode signal MODE, based on which the input buffer circuit 131 can apply an appropriate bias voltage according to the mode signal MODE.

[0026] refer to Figure 4 .Figure 4 This is illustrated in some embodiments according to the present invention. Figure 3 The flowchart of the operation method of the signal processing circuit 400.

[0027] In operation S402, it is determined whether the pin of the signal processing circuit 300 is coupled to... Figure 2 The AC coupling capacitor C1 or AC coupling capacitor C2 in the circuit. If not coupled to an AC coupling capacitor (such as...) Figure 1 As shown in the example), the process enters operation S404. If coupled to an AC coupling capacitor (such as...), the process continues. Figure 2 (As shown in the example), the process then proceeds to operation S410.

[0028] In operation S404, the DC voltage V detected by the DC voltage generation circuit 1321 is determined. MIC_IN Is it greater than the threshold voltage value V? TH If the DC voltage V MIC_IN Not greater than (e.g., less than or equal to) the threshold voltage value V TH The process proceeds to operation S406. If the DC voltage V MIC_IN Greater than the threshold voltage value V TH Then the process enters operation S408.

[0029] In operation S406, the input buffer circuit 131 uses a voltage divider signal V. CM’ (For example Figure 5 (As shown). For example, the voltage divider signal V CM It can be generated by another operational amplifier and input to the input buffer circuit 131 (e.g. Figure 5 The common-mode voltage conversion circuit 1311 shown is illustrated.

[0030] In operation S408, the input buffer circuit 131 uses a DC voltage V. MIC_IN For example, DC voltage V MIC_IN can be Figure 5 The DC voltage generated by the Unity Gain Buffer (also known as a single-gain buffer circuit) 13212 in the Unity DC voltage generation circuit 1321 is input to the input buffer circuit 131 (e.g., ...). Figure 5 The common-mode voltage conversion circuit 1311 and the inverter circuit 1312 are shown.

[0031] In operation S410, the input buffer circuit 131 uses a preset voltage V. CM For example, the preset voltage V CM It can be generated by another voltage source and input to the input buffer circuit 131 (e.g. Figure 5 The common-mode voltage conversion circuit 1311 and the inverter circuit 1312 are shown.

[0032] refer to Figure 5 . Figure 5 This is illustrated in some embodiments according to the present invention. Figure 3 The circuit diagram of the signal processing circuit 300. (Compared to...) Figure 3 resemblance, Figure 5 The signal processing circuit 300 includes an input buffer circuit 131 and a DC detection circuit 132. The DC detection circuit 132 includes a DC voltage generation circuit 1321 and a mode selection circuit 1322.

[0033] The input buffer circuit 131 includes a common-mode voltage conversion circuit 1311 and an inverting circuit 1312. The DC voltage generation circuit 1321 includes a low-pass filter circuit 13211 and a single-gain buffer circuit 13212. The mode selection circuit 1322 includes a comparator circuit 13221 and a debounce circuit 13222.

[0034] The common-mode voltage converter circuit 1311 is controlled by control signals LINE_IN, MIC_IN, and AC_IN, and is based on the input signal VIN and the DC voltage V. MIC_IN Preset voltage V CM Voltage divider signal V CM’ And the input signal VIN generates the output signal V OP .by Figure 5 For example, the common-mode voltage conversion circuit 1311 includes an amplifier AM1, switches M1 to M4, and resistors R1 to R5. In some embodiments, resistor R3 can be implemented using a variable resistor. The resistance value of resistor R5 is as follows (1):

[0035] N×r...formula (1)

[0036] Where r is the resistance value of resistor R4, and N is a positive integer (for example, it can be achieved by the ratio of the two resistors).

[0037] Amplifier AM1 includes a negative input terminal, a positive input terminal, and an output terminal. Switch M1 is used to receive DC voltage V. MIC_IN It is controlled by the control signal MIC_IN. Resistor R1 is coupled between switch M1 and the negative input terminal of amplifier AM1. Switch M2 is used to receive the preset voltage VCM and is controlled by the control signal LINE_IN or the control signal AC_IN. Resistor R2 is coupled between switch M2 and the negative input terminal of amplifier AM1. Resistor R3 is coupled between the output terminal of amplifier AM1 and the negative input terminal of amplifier AM1. Resistor R4 is coupled between the pin and the positive input terminal of amplifier AM1. Switch M3 is used to receive the preset voltage VCM. CM voltage divider signal V CM’It is also controlled by the LINE_IN control signal. In this configuration, the voltage divider signal V... CM’ The preset voltage V can be set to (N+1) times. CM Resistor R5 is coupled between switch M3 and the positive input terminal of amplifier AM1. Switch M4 is used to receive the preset voltage V. CM It is also controlled by the control signal AC_IN.

[0038] The inverter circuit 1312 is controlled by the control signals LINE_IN and MIC_IN, and is based on the output signal V. OP Generate an inverted output signal V ON Output signal V OP and the inverted output signal V ON It can be passed to the next stage of processing circuitry, and the next stage of processing circuitry can process the output signal V. ON and the inverted output signal V OP Perform a fully differential processing procedure. Figure 5 For example, the inverting circuit 1312 includes amplifier AM2, switches M5-M6, and resistors R6-R7. Amplifier AM2 includes a negative input terminal, a positive input terminal, and an output terminal. Resistor R6 is coupled between the output terminal of amplifier AM1 and the negative input terminal of amplifier AM2. Resistor R7 is coupled between the output terminal of amplifier AM2 and the negative input terminal of amplifier AM2. Switch M5 is used to receive DC voltage V. MIC_IN It is controlled by the control signal MIC_IN. Switch M5 is coupled to the positive input terminal of amplifier AM2. Switch M6 is used to receive the preset voltage VCM and is controlled by the control signal LINE_IN or the control signal AC_IN. Switch M6 is coupled to the positive input terminal of amplifier AM2.

[0039] The low-pass filter circuit 13211 generates a filtered signal FS based on the input signal VIN. Figure 5 For example, the low-pass filter circuit 13211 is a first-order low-pass filter circuit. The low-pass filter circuit 13211 includes switches S1 to S2 and a capacitor C. S1 ~C S2 The first terminal of switch S1 is coupled to pin PIN. The second terminal of switch S1 is coupled to the first terminal of switch S2. The second terminal of switch S2 is coupled to the positive input of the single-gain buffer circuit 13212. Switch S1 is controlled by clock signal CK. Switch S2 is controlled by inverted clock signal CK'. Capacitor CS1 is coupled between the first terminal of switch S2 and ground GND. Capacitor CS2 is coupled between the second terminal of switch S2 and ground GND. In this configuration, switches S1, S2, and capacitor CS1... S1 This forms an equivalent resistance, which is related to the capacitance C. S2A resistor-capacitor circuit is formed, and this resistor-capacitor circuit corresponds to a time constant.

[0040] like Figure 5 As shown, the frequency of the clock signal CK in time interval T1 is greater than the frequency of the clock signal CK in time interval T2, and time interval T1 precedes time interval T2. In other words, the resistance value of the equivalent resistor is smaller in time interval T1, and larger in time interval T2. Therefore, the clock signal CK in time interval T1 can quickly charge the filtered signal FS to a certain level. Then, the clock signal CK in time interval T2 can effectively filter out high-frequency components.

[0041] The output of the single-gain buffer circuit 13212 is coupled to its negative input. The single-gain buffer circuit 13212 generates a DC voltage V based on the filtered signal FS. MIC_IN Since the gain of the single-gain buffer circuit 13212 is approximately equal to 1, the voltage value of the filtered signal FS is essentially equal to the DC voltage V. MIC_IN The voltage value. As mentioned before, the DC voltage V MIC_IN It can be generated by a single-gain buffer circuit 13212 and input from the single-gain buffer circuit 13212 to the common-mode voltage conversion circuit 1311 and the inverting circuit 1312.

[0042] The positive input terminal of comparator circuit 13221 is coupled to the output terminal of single-gain buffer circuit 13212 to receive DC voltage V. MIC_IN The negative input of comparator circuit 13221 is used to receive the threshold voltage value V. TH Therefore, the comparator circuit 13221 can convert the DC voltage V MIC_IN It is compared with the threshold voltage value VTH to generate a comparison signal CS.

[0043] The debounce circuit 13222 includes at least one flip-flop (FF) and an AND gate. The debounce circuit 13222 is used to perform a debounce procedure on the comparator signal CS to generate a mode signal MODE. The purpose of the debounce procedure is to prevent drastic changes in the mode signal MODE. For example, Figure 5 The debounce circuit 13222 includes three flip-flops FF, but the invention is not limited to this number. These flip-flops FF receive a comparison signal CS and are controlled by a clock signal CK. The AND gate receives the output signals of the flip-flops FF and the comparison signal CS, and performs an AND operation on these two signals to generate a mode signal MODE. Since the input of any flip-flop FF only transmits a signal to its output when enabled by the received clock signal CK, multiple flip-flops FF connected in series can effectively prevent drastic changes in the mode signal MODE.

[0044] Reference Figure 6 . Figure 6 is a circuit diagram of the direct current voltage generation circuit 1321A according to some embodiments of the present application. Figure 6 The main difference between the direct current voltage generation circuit 1321A of Figure 5 and the direct current voltage generation circuit 1321 of Figure 6 The direct current voltage generation circuit 1321A of includes a plurality of first order low pass filter circuits 13211. Therefore, the direct current voltage generation circuit 1321A can filter out high frequency components more effectively.

[0045] Reference Figure 5 If the pin PIN of the signal processing circuit 300 is the pin P LINE in Figure 1 , the pin PIN of the signal processing circuit 300 is used to receive the input signal VIN2. The direct current voltage generation circuit 1321 can track the input signal VIN2 and generate the direct current voltage V MIC_IN , and the comparison circuit 13221 can compare the direct current voltage V MIC_IN with the threshold voltage value V TH . Since the input signal VIN2 from the pin P LINE in Figure 1 is usually an alternating current voltage AC biased at 0 volts, the direct current voltage V MIC_IN is not greater than (equal to or less than) the pre-set threshold voltage value V TH . In this case, the comparison signal CS has a logic value of 0. Since the comparison signal CS has a logic value of 0, the mode signal MODE has a logic value of 0. In some embodiments, when the mode signal MODE has a logic value of 0, the control signal MIC IN has a logic value of 0 and the control signal LINE IN has a logic value of 1 (hereinafter referred to as the first mode). For example, the input buffer circuit 131 can use the mode signal MODE as the control signal MIC IN. In addition, an inverter can be provided in the input buffer circuit 131, and the inverter can receive the mode signal MODE and perform an inversion process on the mode signal MODE to generate the control signal LINE IN. In this case, Figure 5 the signal processing circuit 300 of Figure 7 is equivalent to Figure 7 is a circuit diagram of the signal processing circuit 300 of Figure 5 in the first mode according to some embodiments of the present application. Figure 7 Only the input buffer circuit 131 of Figure 3 is shown and the direct current detection circuit 132 of Figure 3 is omitted. For example, the divided voltage signal V CM’ is input to the input buffer circuit 131 (as shown in Figure 7 ).Figure 4 (S406 in the operation). In some embodiments, when the mode signal MODE has a logic value of 0, the power supply to the DC voltage generation circuit 1321 can be turned off.

[0046] Refer again Figure 5 If the pin of the signal processing circuit 300 is... Figure 1 Pin P_MIC in the signal processing circuit 300 is used to receive the input signal VIN1. The DC voltage generation circuit 1321 tracks the input signal VIN1 and generates a DC voltage V. MIC_IN The comparator circuit 13221 can convert the DC voltage V MIC_IN With threshold voltage value V TH Comparison. Due to the source Figure 1 The input signal VIN1 of the middle pin P_MIC is typically an AC voltage with a bias voltage BIAS (e.g., but not limited to 2.8 volts), therefore the DC voltage V... MIC_IN This will be greater than the pre-designed threshold voltage value VTH. In this case, the comparison signal CS has a logic value of 1. Since the comparison signal CS has a logic value of 1, the mode signal MODE also has a logic value of 1 (hereinafter referred to as the second mode). In some embodiments, when the mode signal MODE has a logic value of 1, the control signal MIC_IN has a logic value of 1 and the control signal LINE_IN / AC_IN has a logic value of 0. Accordingly, Figure 5 The signal processing circuit 300 is equivalent to Figure 8 . Figure 8 This is illustrated in some embodiments according to the present invention. Figure 5 The equivalent circuit diagram of the signal processing circuit 300 in the second mode. Figure 8 For example, DC voltage V MIC_IN The input is fed to the input buffer circuit 131 (e.g.) Figure 4 Operation S408 in the middle.

[0047] Refer again Figure 5 If the pin of the signal processing circuit 300 is... Figure 2 The pin P_MIC or pin P_LINE (i.e., with AC coupling capacitor C1 or AC coupling capacitor C2) of the signal processing circuit 300 is used to receive the input signal VIN1 or input signal VIN2 through the AC coupling capacitor. The input signal VIN1 or input signal VIN2 through the AC coupling capacitor is typically an AC voltage AC. In this case, the DC detection circuit 132 can be disabled and the control signal AC_IN has a logic value of 1. Accordingly, Figure 5 The signal processing circuit 300 is equivalent to Figure 9 . Figure 9is shown according to some embodiments of the present application Figure 5 The equivalent circuit diagram of the signal processing circuit 300 in the third mode is shown in FIG. 13B. In the third mode, the DC detection circuit 132 is disabled. Figure 9 For example, the preset voltage V CM is input to the input buffer circuit 131 (as shown in operation S410 in FIG. 4). In some embodiments, the DC detection circuit 132 can be disabled by turning off the power supply thereof. Figure 4

[0048] In summary, in the signal processing circuit of the present application, the DC detection circuit can detect the DC voltage of the input signal to bias the input buffer circuit. In this way, the input buffer circuit can maintain a higher dynamic range.

[0049] The above discloses various functional elements and modules. For those skilled in the art, the functional modules can be implemented by a circuit (whether a special-purpose circuit, or a general-purpose circuit operating under the control of one or more processors and coded instructions), which generally includes transistors or other circuit elements for performing the functions described herein and for controlling the operation of the electrical circuit.

[0050] Although the present application has been disclosed with reference to the embodiments above, this is not intended to limit the present application, and various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the present application, and the scope of protection of the present application should be defined by the claims.

[0051] Legend of reference numerals:

[0052] 100, 200: signal processing system

[0053] 110, 120, 300: signal processing circuit

[0054] 111, 121, 131: input buffer circuit

[0055] 112, 122, 132: DC detection circuit

[0056] 1311: common-mode voltage conversion circuit

[0057] 1312: inverter circuit

[0058] 1321, 1321A: DC voltage generation circuit

[0059] 13211: low-pass filter circuit

[0060] 13212: single-gain buffer circuit

[0061] 1322: mode selection circuit ​

[0062] 13221: comparison circuit

[0063] 13222: bounce removal circuit

[0064] 400: operation method

[0065] P_MIC, P_LINE, PIN: pin

[0066] R0, R1, R2, R3, R4, R5, R6, R7: resistance

[0067] N1: node

[0068] MIC: microphone

[0069] MIC_BIAS: bias signal

[0070] VIN1, VIN2, VIN: input signal

[0071] C1, C2: AC coupling capacitor

[0072] V MIC_IN : DC voltage

[0073] V TH : threshold voltage value

[0074] MODE: mode signal

[0075] V CM : preset voltage

[0076] V CM’ : divided voltage signal

[0077] S402, S404, S406, S408, S410: operation

[0078] S1, S2, M1, M2, M3, M4, M5, M6: switch

[0079] C S1 , C S2 : capacitor

[0080] CK: clock signal

[0081] CK': inverted clock signal

[0082] GND: ground

[0083] FS: filter signal

[0084] CS: comparison signal

[0085] FF: flip-flop

[0086] AND: AND gate

[0087] LINE IN, MIC IN, AC IN: control signals

[0088] V OP : output signal

[0089] V ON : inverted output signal

[0090] AM1, AM2: amplifier

[0091] T1, T2: time interval

[0092] AC: alternating voltage

[0093] BIAS: bias voltage

Claims

1. A signal processing circuit, comprising: An input buffer circuit coupled to a pin, wherein said pin is used to receive an input signal; as well as A DC detection circuit is coupled to the pin and the input buffer circuit, wherein the DC detection circuit is used to detect the input signal to generate a mode signal, and bias the input buffer circuit according to the mode signal. The DC detection circuit includes: A DC voltage generating circuit, coupled to the pin and used to generate a DC voltage according to the input signal; and A mode selection circuit is coupled to the DC voltage generation circuit and generates the mode signal based on the DC voltage and a preset threshold voltage value.

2. The signal processing circuit of claim 1, wherein, The DC voltage generating circuit includes: a low-pass filter circuit coupled to the pin and used to generate a filtered signal based on the input signal; and A single-gain buffer circuit is coupled to the low-pass filter circuit and is used to generate the DC voltage based on the filtered signal. The mode selection circuit includes: A comparator circuit, coupled to the single-gain buffer circuit and used to compare the DC voltage with the threshold voltage value to generate a comparison signal; and A debounce circuit is used to perform a debounce procedure on the comparison signal to generate the mode signal.

3. The signal processing circuit according to claim 2, characterized in that, The input buffer circuit includes: A common-mode voltage converter circuit, controlled by a first control signal, a second control signal, and a third control signal, and generating an output signal based on the DC voltage, a preset voltage, and an input signal; and An inverting circuit, controlled by the first control signal and the second control signal, generates an inverted output signal based on the output signal. The output signal and the inverted output signal are used to enable the next-level processing circuit to execute a fully differential processing program. Wherein, if the DC voltage is equal to or less than the threshold voltage value, the comparison signal, the mode signal, and the second control signal have a first logic value and the first control signal has a second logic value, wherein, if the DC voltage is greater than the threshold voltage value, the comparison signal, the mode signal, and the second control signal have the second logic value and the first control signal has the first logic value.

4. The signal processing circuit according to claim 3, characterized in that, The common-mode voltage conversion circuit includes: a first amplifier, including a first input terminal, a second input terminal and a first output terminal; A first switch is used to receive the DC voltage and is controlled by the second control signal; A first resistor is coupled between the first switch and the first input terminal; A second switch is used to receive the preset voltage and is controlled by the first control signal or the third control signal; A second resistor is coupled between the second switch and the first input terminal; A third resistor is coupled between the first output terminal and the first input terminal; A fourth resistor is coupled between the pin and the second input terminal; A third switch is used to receive a voltage divider signal related to the preset voltage and is controlled by the first control signal; A fifth resistor is coupled between the third switch and the second input terminal; and A fourth switch is used to receive the preset voltage and is coupled to the second input terminal and controlled by the third control signal.

5. The signal processing circuit according to claim 4, characterized in that, The inverting circuit includes: A second amplifier includes a third input terminal, a fourth input terminal, and a second output terminal; A sixth resistor is coupled between the first output terminal and the third input terminal; A seventh resistor is coupled between the second output terminal and the third input terminal; A fifth switch, for receiving the DC voltage and coupled to the fourth input terminal and controlled by the second control signal; and A sixth switch is used to receive the preset voltage and is coupled to the fourth input terminal and controlled by the first control signal or the third control signal.

6. The signal processing circuit according to claim 4, characterized in that, If the pin is coupled to an AC coupling capacitor, the DC detection circuit is deenabled and the third control signal has the second logic value.

7. The signal processing circuit according to claim 2, characterized in that, The low-pass filter circuit includes at least one first-order low-pass filter circuit, and at least one of the first-order low-pass filter circuits includes: A first switch, controlled by a clock signal; A second switch includes a first terminal and a second terminal, the first terminal being coupled to the first switch and the second terminal being coupled to the single-gain buffer circuit, wherein the second switch is controlled by an inverted clock signal. A first capacitor is coupled between the first terminal and a ground terminal; and A second capacitor is coupled between the second terminal and the ground terminal. The clock signal corresponds to a first time interval and a second time interval, the first time interval precedes the second time interval, and the signal frequency of the first time interval is greater than the signal frequency of the second time interval.

8. The signal processing circuit according to claim 2, characterized in that, The low-pass filter circuit includes multiple first-order low-pass filter circuits.

9. The signal processing circuit according to claim 1, characterized in that, The input signal is an audio source input signal, wherein the audio source input signal comes from a microphone, an integrated circuit, or an electronic device coupled to the signal processing circuit.

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