Semiconductor device, reception device, and transmission device

Abstract

A semiconductor device, a receiving device, and a transmitting device are provided. A semiconductor device (111) includes a semiconductor chip (10A) and a package (20). The semiconductor chip (10A) has a signal processing circuit (11), a plurality of pads, and a first resistor (16) formed on a semiconductor substrate. On the semiconductor chip (10A), a first pad (14) and a second pad (15) of the plurality of pads are not short-circuited to each other. A signal input terminal of the signal processing circuit (11) is connected to the second pad (15). The first resistor (16) is provided between a reference potential supply terminal that supplies a power supply potential and the first pad (14). An arbitrary terminal (21) of a plurality of terminals of the package (20) is connected to the first pad (14) through a first bonding wire (31) and is connected to the second pad (15) through a second bonding wire (32).

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, a receiving device, and a transmitting device. BACKGROUND

[0002] A semiconductor device generally mounts a semiconductor chip having a signal processing circuit composed of a plurality of elements such as transistors and a plurality of pads in a package having a plurality of terminals for inputting or outputting signals to or from the outside, and connects the pads of the semiconductor chip and the terminals of the package to each other with fine bonding wires composed of gold or copper.

[0003] A bonding wire has a parasitic inductance. For example, as a typical example of a bonding wire, in a case where a wire length is 1 mm and a wire diameter is 0.015 mm, the parasitic inductance of the bonding wire is about 0.92 nH. In a case where a frequency of a signal is 10 GHz, an absolute value of impedance of the bonding wire is 57.8 Ω (= 2π x 10 GHz x 0.92 nH). Further, a characteristic impedance of a signal transmission path connected to the terminal of the package is, for example, 50 Ω.

[0004] As shown in this example, the absolute value of the impedance of the bonding wire (57.8 Ω) is in a size that cannot be ignored with respect to the characteristic impedance of the signal transmission path (50 Ω), and this becomes a factor of degradation of signal processing performance of the signal processing circuit on the semiconductor chip. The higher the frequency of a signal processed by the signal processing circuit, the more the performance of the signal processing is easily affected by the parasitic inductance of the bonding wire.

[0005] Several techniques for coping with the problem of the parasitic inductance of the bonding wire are known (Patent Documents 1 to 3, Non-Patent Document 1). In addition, a package in which the pads of the semiconductor chip and the terminals are electrically connected to each other without using a bonding wire is also known (for example, WCSP (Wafer Level Chip Size Package)).

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2010 / 0253435

[0007] [Patent Document 2] U.S. Patent No. 8427799

[0008] [Patent Document 3] U.S. Patent Application Publication No. 2001 / 0015490

[0009] [Non-Patent Literature 1] "what-when-how, In Depth Tutorials and Information, Circuit Design (GPS) Part 9", [online], [retrieved on February 13, 2020], Internet <URL: http: / / what-when-how.com / gps-galileo-dual-rf-front-end-receiver-and-design-fabrication-and-test / circuit-design-gps-part-9 / > SUMMARY

[0010] However, in the related art, the influence of the parasitic inductance of the bonding wire in high-speed signal transmission cannot be sufficiently reduced. In addition, the packaging cost of the semiconductor chip that can be mounted without using the bonding wire is high, and a highly skilled mounting technique is required.

[0011] The present application was made to solve the above problems, and has an object to provide a semiconductor device capable of reducing the influence of the parasitic inductance of the bonding wire.

[0012] The semiconductor device of the present application, (1) has a signal processing circuit, a plurality of pads, and a first resistor, a first pad and a second pad among the plurality of pads are not short-circuited to each other, and the first resistor is provided between the first pad and a reference potential supply terminal, (1) a semiconductor device including: a semiconductor chip having a second pad connected to a signal input terminal or a signal output terminal of a signal processing circuit; and (2) a package on which the semiconductor chip is mounted, and the package has a plurality of terminals for inputting or outputting a signal to or from the outside. A specific terminal among the plurality of terminals of the package is connected to the first pad through a first bonding wire, and is connected to the second pad through a second bonding wire. The semiconductor chip preferably has a second resistor provided between the second pad and the reference potential supply terminal. In addition, the semiconductor chip preferably has a third resistor provided between the first pad and the second pad.

[0013] (1) A semiconductor device having: (1) a semiconductor chip having a signal processing circuit, a plurality of pads, and a first resistor, a first pad and a second pad of the plurality of pads not being short-circuited to each other, the first resistor being provided between the first pad and a reference potential supply terminal, the second pad being connected to a signal input terminal or a signal output terminal of the signal processing circuit; and (2) a package mounting the semiconductor chip, having a plurality of terminals inputting or outputting signals to or from the outside. Any specific terminal of the plurality of terminals of the package is connected to the first pad through a first bonding wire and to the second pad through a second bonding wire. The reception device of the present application is provided with the semiconductor device and a fourth resistor provided between the specific terminal of the package and the reference potential supply terminal.

[0014] A semiconductor device having: (1) a semiconductor chip having a signal processing circuit and a plurality of pads, a first pad and a second pad of the plurality of pads not being short-circuited to each other, the second pad being connected to a signal output terminal of the signal processing circuit; and (2) a package mounting the semiconductor chip, having a plurality of terminals inputting or outputting signals to or from the outside. Any specific terminal of the plurality of terminals of the package is connected to the first pad through a first bonding wire and to the second pad through a second bonding wire. The transmission device of the present application is provided with the semiconductor device and a fifth resistor provided between the specific terminal of the package and the reference potential supply terminal.

[0015] In the semiconductor device of the present application, it is preferable that the semiconductor chip have an electrostatic discharge (ESD) protection element connected to the first pad.

[0016] According to the present application, it is possible to reduce the influence of the parasitic inductance of the bonding wire. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a diagram showing the structure of a semiconductor device 211 of a first comparative example.

[0018] Figure 2 is a diagram showing the structure of a semiconductor device 212 of the first comparative example.

[0019] Figure 3 is a diagram showing the structure of a semiconductor device 221 of a second comparative example.

[0020] Figure 4 is a diagram showing the structure of a semiconductor device 222 of the second comparative example.

[0021] Figure 5 is a diagram showing the structure of a semiconductor device 111 of a first embodiment.

[0022] Figure 6 is a diagram showing the structure of a semiconductor device 112 of the first embodiment.

[0023] Figure 7 is a diagram showing an equivalent circuit.

[0024] Figure 8 is a diagram showing a structure of the semiconductor device 121 according to the second embodiment.

[0025] Figure 9 is a diagram showing a structure of the semiconductor device 122 according to the second embodiment.

[0026] Figure 10 is a diagram showing a structure of the semiconductor device 131 according to the third embodiment.

[0027] Figure 11 is a diagram showing a structure of the semiconductor device 132 according to the third embodiment.

[0028] Figure 12 is a diagram showing a structure of the semiconductor device 141 according to the fourth embodiment.

[0029] Figure 13 is a diagram showing a structure of the semiconductor device 142 according to the fourth embodiment.

[0030] Figure 14 is a diagram showing a structure of the reception device 1 provided with the semiconductor device 151 according to the fifth embodiment and the fourth resistor 40.

[0031] Figure 15 is a diagram showing a structure of the transmission device 2 provided with the semiconductor device 152 according to the fifth embodiment and the fifth resistor 80.

[0032] Figure 16 is a diagram showing a transceiving system provided with the reception device 1 and the transmission device 2. DETAILED DESCRIPTION

[0033] Hereinafter, modes for carrying out the present application will be explained in detail with reference to the drawings. In addition, in the explanation of the drawings, the same reference numerals are attached to the same elements, and the repeated explanation will be omitted. The present application is not limited to these examples, and is indicated by the claims, and includes all modifications within the meaning and the scope equivalent to the claims.

[0034] Hereinafter, after the structure of the comparative examples is explained, the structure of the embodiments is explained. In addition, in each comparative example and each embodiment, two modes are explained. One mode has a feature on the signal input side of the semiconductor chip, and the other mode has a feature on the signal output side of the semiconductor chip.

[0035] (First Comparative Example)

[0036] Figure 1Fig. 1 is a diagram showing the structure of a semiconductor device 211 of a first comparative example. The semiconductor device 211 is provided with a semiconductor chip 10X and a package 20, and receives a signal transmitted in a signal transmission path 3.

[0037] The semiconductor chip 10X has a signal processing circuit 11, ESD protection elements 12, 13, a plurality of pads, and a resistor 16, which are formed in or on a semiconductor substrate. The signal processing circuit 11 is composed of a plurality of elements such as transistors. The kind of the signal processing circuit 11 is arbitrary. The signal processing circuit 11 is, for example, a logic circuit, a high-frequency differential amplifier, a low-noise amplifier, or the like. A signal input terminal of the signal processing circuit 11 is connected to any one of the plurality of pads 14.

[0038] The ESD protection elements 12, 13 are provided for protecting the signal processing circuit 11 from a surge voltage such as static electricity intruding from the outside or preventing a malfunction of the signal processing circuit 11, and are, for example, diodes. One ESD protection element 12 is provided between a reference potential supply terminal for supplying a power supply potential and the pad 14. The other ESD protection element 13 is provided between a reference potential supply terminal for supplying a ground potential and the pad 14. The resistor 16 is provided between the reference potential supply terminal for supplying the power supply potential and the pad 14.

[0039] The package 20 mounts the semiconductor chip 10X, and has a plurality of terminals for inputting or outputting a signal to or from the outside. Any one of the plurality of terminals 21 is connected to the pad 14 through a bonding wire 31. In addition, the terminal 21 is connected to the signal transmission path 3. Various types of packages are known, and the type of the package 20 can be arbitrary as long as the package is one in which connection between a pad of a semiconductor chip and a terminal is made by a bonding wire.

[0040] A signal transmitted through the signal transmission path 3 and reaching the terminal 21 of the package 20 is input to the signal input terminal of the signal processing circuit 11 via the terminal 21, the bonding wire 31, and the pad 14. The resistor 16 has a resistance value of the same order as the characteristic impedance of the signal transmission path 3. Even in the case where a surge voltage such as static electricity is input to the terminal 21, the signal processing circuit 11 is protected from the surge voltage by the ESD protection elements 12, 13, and a malfunction of the signal processing circuit 11 is prevented.

[0041] As described above, as an example, the frequency of the signal is 10 GHz, the absolute value of the impedance of the bonding wire is 57.8 Ω, the characteristic impedance of the signal transmission path 3 is 50 Ω, and the resistance value of the resistor 16 is 50 Ω. The absolute value of the impedance of the bonding wire 31 is a size that cannot be ignored with respect to the characteristic impedance of the signal transmission path 3, and becomes a factor of deterioration of the performance of the signal processing of the signal processing circuit 11. The higher the frequency of the signal processed by the signal processing circuit 11, the more the performance of the signal processing is likely to be affected by the parasitic inductance of the bonding wire 31.

[0042] Figure 2 Fig. 12 is a diagram showing the structure of a semiconductor device 212 of a first comparative example. The semiconductor device 212 has a semiconductor chip 50X and a package 60, and transmits a signal to a signal transmission path 4.

[0043] The semiconductor chip 50X has a signal processing circuit 51, ESD protection elements 52, 53, a plurality of pads, and a resistor 56, which are formed in or on a semiconductor substrate. The signal processing circuit 51 is constituted by a plurality of elements such as transistors. The kind of the signal processing circuit 51 is arbitrary. The signal processing circuit 51 is, for example, a logic circuit, a high-frequency differential amplifier, a low-noise amplifier, or the like. A signal output terminal of the signal processing circuit 51 is connected to any one of the plurality of pads 54.

[0044] The ESD protection elements 52, 53 are provided for protecting the signal processing circuit 51 from a surge voltage such as static electricity intruding from the outside or preventing a malfunction of the signal processing circuit 51, and are, for example, diodes. One ESD protection element 52 is provided between a reference potential supply terminal for supplying a power supply potential and the pad 54. The other ESD protection element 53 is provided between a reference potential supply terminal for supplying a ground potential and the pad 54. The resistor 56 is provided between the reference potential supply terminal for supplying the power supply potential and the pad 54.

[0045] The package 60 mounts the semiconductor chip 50X, and has a plurality of terminals for inputting or outputting a signal to or from the outside. Any one of the plurality of terminals 61 is connected to the pad 54 through a bonding wire 71. The terminal 61 is connected to the signal transmission path 4. Various kinds of packages are known, but the kind of the package 60 can be arbitrary as long as the kind is one in which connection between a pad of a semiconductor chip and a terminal is made through a bonding wire.

[0046] The signal output from the signal output terminal of the signal processing circuit 51 is transmitted to the signal transmission path 4 via the pad 54, the bonding line 71, and the terminal 61. The resistor 56 has a resistance value that is the same as the characteristic impedance of the signal transmission path 4. Even if surge voltages such as electrostatic discharge are input to the terminal 61, the signal processing circuit 51 can be protected and malfunctions can be prevented by providing ESD protection elements 52 and 53.

[0047] Semiconductor device 212 also suffers from the same problem as semiconductor device 211. Specifically, the absolute value of the impedance of the junction line 71 is a significant amount that cannot be ignored relative to the characteristic impedance of the signal transmission path 4, thus contributing to the degradation of the signal processing performance of the signal processing circuit 51. The higher the frequency of the signal processed by the signal processing circuit 51, the more susceptible its performance is to the parasitic inductance of the junction line 71.

[0048] (Comparative Example 2)

[0049] Figure 3 This is a diagram illustrating the structure of the semiconductor device 221 of the second comparative example. The semiconductor device 221 includes a semiconductor chip 10Y and a package 20, and receives signals transmitted in the signal transmission path 3. The structure is compared to that of the semiconductor device 211 of the first comparative example. Figure 1 Compared to the second comparative example, the semiconductor device 221 has a different structure. Figure 3 The difference is that the signal input terminal of the signal processing circuit 11 is connected to two pads 14 and 15. On the semiconductor chip 10Y, pads 14 and 15 are short-circuited to each other. Terminal 21 of package 20 is connected to pad 14 via bonding wire 31 and to pad 15 via bonding wire 32.

[0050] Figure 4 This is a diagram showing the structure of the semiconductor device 222 of the second comparative example. The semiconductor device 222 has a semiconductor chip 50Y and a package 60, and transmits signals to the signal transmission path 4. The structure is compared with that of the semiconductor device 212 of the first comparative example. Figure 2 Compared to the second comparative example, the structure of the semiconductor device 222 ( Figure 4 The difference lies in that the signal output terminal of the signal processing circuit 51 is connected to two pads 54 and 55. On the semiconductor chip 50Y, pads 54 and 55 are short-circuited to each other. Terminal 61 of package 60 is connected to pad 54 via bonding wire 71 and to pad 55 via bonding wire 72.

[0051] In the second comparative example, a signal input terminal or a signal output terminal of the signal processing circuit is connected to two pads on the semiconductor chip, and the two pads are connected to one terminal of the package. That is, the signal input terminal or the signal output terminal of the signal processing circuit is connected to one terminal of the package through two bonding wires arranged side by side. Thus, in the second comparative example, the influence of the parasitic inductance of the bonding wires can be reduced as compared with the first comparative example. However, the reduction of the influence of the parasitic inductance of the bonding wires is not sufficient.

[0052] (First Embodiment)

[0053] Figure 5 is a diagram showing the structure of a semiconductor device 111 of the first embodiment. The semiconductor device 111 has a semiconductor chip 10A and a package 20, which receives a signal transmitted in a signal transmission path 3.

[0054] The semiconductor chip (10A) has a signal processing circuit 11, ESD protection elements 12, 13, a plurality of pads, and a first resistor 16, which are formed in or on a semiconductor substrate. On the semiconductor chip 10A, a first pad 14 and a second pad 15 of the plurality of pads are not short-circuited to each other. A signal input terminal of the signal processing circuit 11 is connected to the second pad 15. The ESD protection element 12 is provided between a reference potential supply terminal for supplying a power supply potential and the first pad 14. The ESD protection element 13 is provided between a reference potential supply terminal for supplying a ground potential and the first pad 14. The first resistor 16 is provided between the reference potential supply terminal for supplying the power supply potential and the first pad 14.

[0055] The package 20 mounts the semiconductor chip 10A and has a plurality of terminals for inputting or outputting a signal to or from the outside. A certain terminal 21 of the plurality of terminals is connected to the first pad 14 through a first bonding wire 31 and is connected to the second pad 15 through a second bonding wire 32. In addition, the terminal 21 is connected to the signal transmission path 3.

[0056] The signal transmitted in the signal transmission path 3 and reaching the terminal 21 of the package 20 is input to the signal input terminal of the signal processing circuit 11 through the terminal 21, the second bonding wire 32, and the second pad 15. The input impedance of the signal processing circuit 11 is generally much larger than the characteristic impedance of the system (for example, 50 Ω). Therefore, the signal reaching the terminal 21 is directly transmitted to the signal input terminal of the signal processing circuit 11. The first resistor 16 is connected to the signal transmission path 3 via the first pad 14, the first bonding wire 31, and the terminal 21, and has a resistance value of the same order as the characteristic impedance of the signal transmission path 3. Even in the case where a surge voltage such as static electricity is input to the terminal 21, the signal processing circuit 11 can be protected from malfunction by providing the ESD protection elements 12 and 13. Note that the ESD protection elements 12 and 13 can not be provided.

[0057] Figure 6 is a diagram showing the structure of a semiconductor device 112 according to a first embodiment. The semiconductor device 112 has a semiconductor chip 50A and a package 60, and transmits a signal to a signal transmission path 4.

[0058] The semiconductor chip 50A has a signal processing circuit 51, ESD protection elements 52 and 53, a plurality of pads, and a first resistor 56, which are formed in or on a semiconductor substrate. Among the plurality of pads on the semiconductor chip 50A, a first pad 54 and a second pad 55 are not short-circuited to each other. A signal output terminal of the signal processing circuit 51 is connected to the second pad 55. The ESD protection element 52 is provided between a reference potential supply terminal for supplying a power supply potential and the first pad 54. The ESD protection element 53 is provided between a reference potential supply terminal for supplying a ground potential and the first pad 54. The first resistor 56 is provided between the reference potential supply terminal for supplying the power supply potential and the first pad 54.

[0059] The package 60 mounts the semiconductor chip 50A, and has a plurality of terminals for inputting or outputting a signal to or from the outside. Any one of the plurality of terminals 61 is connected to the first pad 54 through a first bonding wire 71, and is connected to the second pad 55 through a second bonding wire 72. Further, the terminal 61 is connected to the signal transmission path 4.

[0060] A signal output from the signal output terminal of the signal processing circuit 51 is sent to the signal transmission path 4 via the second pad 55, the second bonding wire 72, and the terminal 61. The first resistor 56 has a resistance value of the same order as the characteristic impedance of the signal transmission path 4. Even in the case where a surge voltage such as static electricity is input to the terminal 61, the signal processing circuit 51 can be protected from malfunction by providing the ESD protection elements 52 and 53. Note that the ESD protection elements 52 and 53 can not be provided.

[0061] In the first embodiment (1), on the semiconductor chip, a signal input terminal or a signal output terminal of the signal processing circuit is connected to the second pad, the first resistor is connected to the first pad, and the first pad and the second pad are not short-circuited to each other. One terminal of the package is connected to the first pad through the first bonding wire, and is connected to the second pad through the second bonding wire. Figure 5 , Figure 6 ) In this case, a circuit portion including the first bonding wire, the second bonding wire, the first pad, the second pad, the first resistor, and the ESD protection element is represented by an equivalent circuit shown in Fig. 1. A synthetic impedance Z of this equivalent circuit is represented by the following (1). L is an inductance value of the bonding wire, C is a capacitance value between the pad or the like and the ground potential, R is a resistance value of the first resistor, and s is an s space operator in Laplace transformation.

[0062] Figure 7 In this case, a circuit portion including the first bonding wire, the second bonding wire, the first pad, the second pad, the first resistor, and the ESD protection element is represented by an equivalent circuit shown in Fig. 1. A synthetic impedance Z of this equivalent circuit is represented by the following (1). L is an inductance value of the bonding wire, C is a capacitance value between the pad or the like and the ground potential, R is a resistance value of the first resistor, and s is an s space operator in Laplace transformation.

[0063] Math. 1

[0064]

[0065] In this (1), if s is replaced with jω and expressed with an angular frequency ω, the synthetic impedance Z is represented by the following (2). j is an imaginary unit.

[0066] Math. 2

[0067]

[0068] The absolute value of the synthetic impedance Z is represented by the following (3).

[0069] Math. 3

[0070]

[0071] The value of ωRC is sufficiently small compared with 1, so the (3) can be approximated by the following (4).

[0072] Math. 4

[0073]

[0074] From this (4), if L = R 2 C, the synthetic impedance Z is equal to R. Or, if L is made to be a value close to R 2 C, the synthetic impedance Z becomes a value close to R. Each value of L, R, and C can be appropriately set. For example, when L = InH and R = 50Ω, C = 400fF, or C is made to be a value close to 400fF. Thereby, the influence of the parasitic inductance of the bonding wire can be reduced. ​

[0075] (Second Embodiment)

[0076] Figure 8 is a view showing the structure of a semiconductor device 121 according to the second embodiment. The semiconductor device 121 includes a semiconductor chip 10B and a package 20, and receives a signal transmitted in a signal transmission path 3. The semiconductor chip 10B according to the second embodiment is different from the semiconductor chip 10A according to the first embodiment in that it further includes a second resistor 17. The second resistor 17 is provided between a reference potential supply terminal that supplies a power supply potential and a second pad 15.

[0077] Figure 9 is a view showing the structure of a semiconductor device 122 according to the second embodiment. The semiconductor device 122 includes a semiconductor chip 50B and a package 60, and transmits a signal to a signal transmission path 4. The semiconductor chip 50B according to the second embodiment is different from the semiconductor chip 50A according to the first embodiment in that it further includes a second resistor 57. The second resistor 57 is provided between a reference potential supply terminal that supplies a power supply potential and a second pad 55.

[0078] In the structure of the second embodiment, Figure 8 , Figure 9 ), when the resistance value of the first resistor is Rl, the resistance value of the second resistor is R2, and the characteristic impedance of the signal transmission path is Z0, the influence of the parasitic inductance of the bonding wire can be reduced by making the following (5) hold (or approximately hold). In the second embodiment, since both Rl and R2 can be made larger than Z0, C can be made smaller compared to the first embodiment Figure 5 , Figure 6 ), and even if L is a relatively large value, it is easy to make the above (4) hold (or approximately hold). In the embodiment of Figure 8 , the left side of (5) is the parallel combination of the resistance value R between the input terminal 21 and the reference potential supply terminal that supplies a power supply potential. In the embodiment of Figure 9 , the left side of (5) is the parallel combination of the resistance value R between the output terminal 61 and the reference potential supply terminal that supplies a power supply potential. In order to make (5) approximately hold, for example, R x 90% < Z0 < R x 110% can be satisfied, and this principle can also be applied to other embodiments.

[0079] Equation (5)

[0080]

[0081] (Third Embodiment)

[0082] Figure 10is a view showing the structure of the semiconductor device 131 of the third embodiment. The semiconductor device 131 has the semiconductor chip IOC and the package 20, and receives a signal transmitted in the signal transmission path 3. The semiconductor chip IOC of the third embodiment differs from the semiconductor chip 10A of the first embodiment in that it further has a third resistor 18. The third resistor 18 is provided between the first pad 14 and the second pad 15.

[0083] Figure 11 is a view showing the structure of the semiconductor device 132 of the third embodiment. The semiconductor device 132 has the semiconductor chip 50C and the package 60, and transmits a signal to the signal transmission path 4. The semiconductor chip 50C of the third embodiment differs from the semiconductor chip 50A of the first embodiment in that it further has a third resistor 58. The third resistor 58 is provided between the first pad 54 and the second pad 55.

[0084] In the structure of the third embodiment, Figure 10 , Figure 11 In the structure of the third embodiment, in addition to the first resistor provided between the reference potential supply terminal for supplying a power supply potential and the first pad, a third resistor is provided between the first pad and the second pad. Even in a case where the frequency characteristic becomes too steep due to the influence of the parasitic inductance of the bonding wire, by providing the third resistor, it is possible to adjust the frequency characteristic.

[0085] In the structure of the third embodiment, Figure 10 , Figure 11 In the structure of the third embodiment, if the resistance value of the third resistor is R3, the resultant impedance Z is represented by the following (6).

[0086] Mathematical expression (6)

[0087]

[0088] Expressing this (6) by an angular frequency ω, and assuming that the value of ωL / R3 is sufficiently small compared with 1, and the value of ωRC is sufficiently small compared with 1, the (6) can be approximated by the following (7).

[0089] Mathematical expression (7)

[0090]

[0091] The absolute value of the resultant impedance Z is represented by the following (8).

[0092] Mathematical expression (8)

[0093]

[0094] On the other hand, if the above-described equation (4) in the first embodiment is modified, it becomes the following equation (9).

[0095] Equation (9)

[0096]

[0097] Comparing equation (8) and equation (9), they differ in the presence or absence of a factor represented by the following equation (10). Since the value of this equation (10) is less than 1, in the third embodiment, as compared with the first embodiment, it is possible to easily reduce the influence of the parasitic impedance of the bonding wire.

[0098] Equation (10)

[0099]

[0100] (Fourth Embodiment)

[0101] Figure 12 is a view showing the structure of a semiconductor device 141 of the fourth embodiment. The semiconductor device 141 has a semiconductor chip 10D and a package 20, and receives a signal transmitted in a signal transmission path 3. As compared with the semiconductor chip 10B of the second embodiment, the semiconductor chip 10D of the fourth embodiment is different in that it further has a third resistor 18. The third resistor 18 is provided between the first pad 14 and the second pad 15.

[0102] Figure 13 is a view showing the structure of a semiconductor device 142 of the fourth embodiment. The semiconductor device 142 has a semiconductor chip 50D and a package 60, and transmits a signal to a signal transmission path 4. As compared with the semiconductor chip 50B of the second embodiment, the semiconductor chip 50D of the fourth embodiment is different in that it further has a third resistor 58. The third resistor 58 is provided between the first pad 54 and the second pad 55.

[0103] In the structure of the fourth embodiment ( Figure 12 , Figure 13 ), the effects of the respective structures of the second embodiment ( Figure 8 , Figure 9 ) and the third embodiment ( Figure 10 , Figure 11 ) can be obtained.

[0104] (Fifth Embodiment)

[0105] Figure 14is a diagram showing the structure of the receiving device 1 provided with the semiconductor device 151 of the fifth embodiment and the fourth resistor 40. The semiconductor device 151 is provided with the semiconductor chip 10E and the package 20, and receives a signal transmitted in the signal transmission path 3. The semiconductor chip 10E of the fifth embodiment differs from the semiconductor chip 10A of the first embodiment in that it does not have the first resistor 16. The receiving device 1 is provided with the fourth resistor 40 disposed between the reference potential supply terminal that supplies the power supply potential and the terminal 21, in place of the first resistor 16 in the semiconductor chip.

[0106] Figure 15 is a diagram showing the structure of the transmitting device 2 provided with the semiconductor device 152 of the fifth embodiment and the fifth resistor 80. The semiconductor device 152 is provided with the semiconductor chip 50E and the package 60, and transmits a signal to the signal transmission path 4. The semiconductor chip 50E of the fifth embodiment differs from the semiconductor chip 50A of the first embodiment in that it does not have the first resistor 56. The transmitting device 2 is provided with the fifth resistor 80 disposed between the reference potential supply terminal that supplies the power supply potential and the terminal 61, in place of the first resistor 56 in the semiconductor chip.

[0107] In the structure of the fifth embodiment Figure 14 , Figure 15 , the effects of the structure of the first embodiment Figure 5 , Figure 6 can be obtained. In addition, since the resistor 40, 80 as the termination resistor is disposed outside the semiconductor chip, it can be applied to LVDS (Low voltage differential signaling), and a resistor 40, 80 having a suitable resistance value can be selected for use.

[0108] Figure 16 A transceiving system provided with the receiving device 1 and the transmitting device 2 is shown.

[0109] The receiving device 1 is the semiconductor device 141 shown in Figure 12 , and the transmitting device 2 is the semiconductor device 142 shown in Figure 13 .

[0110] (Receiving device)

[0111] The semiconductor chip 10D, which constitutes a main part of the reception device 1, has a semiconductor substrate S1 as a semiconductor chip main body. The surface of the semiconductor substrate S1 made of Si or the like is covered with an insulating layer I1 made of SiO2or the like. A plurality of pads of electric conductivity, a power supply line Vcc1 (reference potential supply terminal), and a ground line GND1 are arranged on the insulating layer I1 of the semiconductor substrate S1. A first ESD protection element 12 (diode), a second ESD protection element 13 (diode), a first resistor 16, a second resistor 17, and a third resistor 18 are formed in the semiconductor substrate S1. These respective resistors can also be formed on the insulating layer I1.

[0112] The cathode of the first ESD protection element 12 (diode) is connected to the pad T13, and the anode is connected to the pad 14. The cathode of the second ESD protection element 13 (diode) is connected to the pad 14, and the anode is connected to the pad 14. This pair of diodes constitutes clamp diodes. The clamp diodes are a pair of ESD protection devices, and are a pair of ESD protection diodes. The number of diodes can also be two or more.

[0113] The first potential (V1) for the power supply line Vcc1 is supplied to the terminal S16, the second potential (V2) for ESD is supplied to the terminal S17, the third potential (V3) for ESD is supplied to the terminal S18, and the fourth potential (V4) for the ground line GND1 is supplied to the terminal S19. The relationship of these potentials satisfies, for example, V1 > V2 > V3 > V4, and the amplitude center potential of the input signal input to the input terminal 21 can be set between the second potential (V2) and the third potential (V3).

[0114] The package 20 has a substrate 20S of insulating property and an insulating layer 20P made of a resin material or the like. A die pad DP1 is arranged on the substrate 20S, and the semiconductor chip 10D is attached to the die pad DP1. The semiconductor chip 10D is covered with the insulating layer 20P. A plurality of terminals are arranged on the substrate 20S. The output terminal S11 and the terminal S14 or the like are arranged on the output side (right side) of the substrate 20S. The input terminal 21 or the like is arranged on the input side (left side) of the substrate 20S. The connection method of the pads and the terminals has various types, and therefore terminals not used in this example are also shown in the drawing.

[0115] The conductive pad Tll on the output side of the semiconductor chip 10D constituting the receiving device 1 is connected to the output-side terminal Sll via the wire Wll. The conductive pad T12 connected to the power supply line Vcc1 on the semiconductor chip 10D is connected to the terminal S16 via the wire W12. The conductive pad T13 on the input side of the semiconductor chip 10D is connected to the terminal S17 via the wire W13. The conductive pad 14 on the input side of the semiconductor chip 10D is connected to the terminal 21 via the wire 31. The conductive pad T14 on the input side of the semiconductor chip 10D is connected to the terminal S18 via the wire W14. The conductive pad 15 on the input side of the semiconductor chip 10D is connected to the terminal 21 via the wire 32. The conductive pad T15 connected to the ground line GND1 on the semiconductor chip 10D is connected to the terminal S19 via the wire W15.

[0116] (transmitting device)

[0117] The semiconductor chip 50D constituting the main part of the transmitting device 2 has a semiconductor substrate S2 as a semiconductor chip main body, and the surface of the semiconductor substrate S2 made of Si or the like is covered with an insulating layer I2 made of SiO2 or the like. On the insulating layer I2 of the semiconductor substrate S2, a plurality of conductive pads, a power supply line Vcc2 (reference potential supply terminal), and a ground line GND2 are arranged. Inside the semiconductor substrate S2, a first ESD protection element 52 (diode), a second ESD protection element 53 (diode), a first resistor 56, a second resistor 57, and a third resistor 58 are formed. These respective resistors can also be formed on the insulating layer I2.

[0118] The cathode of the first ESD protection element 52 (diode) is connected to the pad T23, and the anode is connected to the pad 54. The cathode of the second ESD protection element 53 (diode) is connected to the pad 54, and the anode is connected to the pad T24. This pair of diodes constitutes clamp diodes. The clamp diodes are a pair of ESD protection devices, and are a pair of ESD protection diodes. The number of diodes can also be two or more.

[0119] The first potential (Vl) for the power supply line Vcc2 is supplied to the terminal S26, the second potential (V2) for ESD is supplied to the terminal S27, the third potential (V3) for ESD is supplied to the terminal S28, and the fourth potential (V4) for the ground line GND2 is supplied to the terminal S29. The relationship of these potentials satisfies, for example, Vl > V2 > V3 > V4, and the amplitude center potential of the output signal output from the output terminal 61 can be set to between the second potential (V2) and the third potential (V3).

[0120] The package 60 has a substrate 60S having insulating properties and an insulating layer 60P made of a resin material or the like. A die pad DP2 is arranged on the substrate 60S, and the semiconductor chip 50D is attached to the die pad DP2. The semiconductor chip 50D is covered with the insulating layer 60P. A plurality of terminals are arranged on the substrate 60S. An output terminal 61 or the like is arranged on the output side (right side) of the substrate 60S. An input terminal S21, a terminal S24, or the like is arranged on the input side (left side) of the substrate 60S. There are various types of connection methods of pads and terminals, and therefore a terminal not used in this example is also shown in the drawing.

[0121] The conductive pad T21 on the input side of the semiconductor chip 50D constituting the transmission device 2 is connected to the input-side terminal S21 via a wire W21. The conductive pad T22 connected to the power supply line Vcc2 on the semiconductor chip 50D is connected to the terminal S26 via a wire W22. The conductive pad T23 on the output side of the semiconductor chip 50D is connected to the terminal S27 via a wire W23. The conductive pad 54 on the output side of the semiconductor chip 50D is connected to the terminal 61 via a wire 71. The conductive pad T24 on the output side of the semiconductor chip 50D is connected to the terminal S28 via a wire W24. The conductive pad 55 on the output side of the semiconductor chip 50D is connected to the terminal 61 via a wire 72. The conductive pad T25 connected to the ground line GND2 on the semiconductor chip 50D is connected to the terminal S29 via a wire W25.

[0122] The terminal 61 of the transmission device 2 is connected to the terminal 21 of the reception device 1 via a signal transmission path LINE. The signal transmission path LINE is the above-described signal transmission paths 3, 4.

[0123] In addition, in the Figure 16 , the resistors corresponding to these drawings can be omitted in the above-described manner Figure 5 , the manner of Figure 6 , the manner of Figure 8 , the manner of Figure 9 , the manner of Figure 10 , the manner of Figure 11 In addition, in the Figure 16 , the resistors corresponding to these drawings can be added in the above-described manner Figure 14 , the manner of Figure 15

[0124] ​As described above, the semiconductor device as the above-described receiving device 1 includes: a package 20 including a first terminal 21; a semiconductor chip 10D mounted on the package 20, having a first pad 14 and a second pad 15, a pair of ESD protection elements 12, 13 connected to the first pad 14, a signal processing circuit 11 connected to the second pad 15; a first wire 31 connecting the first terminal 21 and the first pad 14; a second wire 32 connecting the first terminal 21 and the second pad 15; and a first resistor (16 or 40) directly or indirectly connected between a connection point between the pair of ESD protection elements 12, 13 and a reference potential supply terminal Vccl.

[0125] An example of the signal processing circuit 11 is an amplifier, and a signal output from the signal processing circuit 11 is output to the outside of the receiving device 1 through a pad Tl l, a wire Wl l, and a terminal Sll.

[0126] The semiconductor device as the above-described transmitting device 2 includes: a package 60 including a first terminal 61; a semiconductor chip 50D mounted on the package, having a first pad 54 and a second pad 55, a pair of ESD protection elements 52, 53 connected to the first pad 54, a signal processing circuit 51 connected to the second pad 55; a first wire (71) connecting the first terminal 61 and the first pad 54; a second wire 72 connecting the first terminal 61 and the second pad 55; and a first resistor (56 or 80) directly or indirectly connected between a connection point between the pair of ESD protection elements 52, 53 and a reference potential supply terminal Vcc2.

[0127] An example of the signal processing circuit 51 is an amplifier, and a signal input to the transmitting device 2 from the outside via a terminal S21 is input to the signal processing circuit 51 via a wire W21 and a pad T21.

[0128] Figure 5 、 Figure 6 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 16 The semiconductor chip illustrated in FIGS. 1 to 5 includes a first resistor (16 or 56).

[0129] Figure 8 、 Figure 9 、 Figure 12 、 Figure 13 and Figure 16 The semiconductor chip illustrated in FIGS. 1 to 5 further includes a second resistor (17 or 57) connected between the second pad (15 or 55) and the reference potential supply terminal (Vccl or Vcc2).

[0130] Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 16 The semiconductor chip shown also includes a third resistor (18 or 58) disposed between the first pad (14 or 54) and the second pad (15 or 55).

[0131] exist Figure 14 and Figure 15 The external fourth or fifth resistor (40 or 80: the first resistor) shown is located outside the semiconductor chip. In this case, the connection point between the ESD protection elements is indirectly connected to the reference potential supply terminal (power supply potential) via the first bonding line (31 or 71) and the external resistor (40 or 80). Additionally, in this description, unless otherwise specified, the connection of circuit elements implies a direct electrical connection; however, other circuit elements may be interposed between the circuit elements if the effect remains substantially unchanged.

[0132] exist Figure 5 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 In a semiconductor device, when the second pad 15 is connected to the signal input terminal of the signal processing circuit 11, the semiconductor device constitutes a receiving device. Furthermore, in Figure 6 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 16 In the semiconductor device, when the second pad 55 is connected to the signal output terminal of the signal processing circuit 51, the semiconductor device constitutes a transmitting device. Furthermore, even when the semiconductor device does not have ESD protection components, the influence of parasitic inductance of the bonding wires can be reduced, improving signal processing performance. However, when the semiconductor device has ESD protection components, malfunctions can be suppressed, thereby improving signal processing performance.

Claims

1. A semiconductor device, comprising: a semiconductor chip having a signal processing circuit, a plurality of pads, a first pad and a second pad of the plurality of pads not short-circuited to each other, and a first resistor provided between the first pad and a reference potential supply terminal, the second pad connected to a signal input terminal or a signal output terminal of the signal processing circuit; and a package mounting the semiconductor chip, having a plurality of terminals inputting or outputting signals to or from an outside, any specific terminal of the plurality of terminals of the package connected to the first pad by a first bonding wire and connected to the second pad by a second bonding wire.

2. The semiconductor device according to claim 1, wherein The semiconductor chip has a second resistor provided between the second pad and the reference potential supply terminal.

3. The semiconductor device according to claim 1, wherein The semiconductor chip has a third resistor provided between the first pad and the second pad.

4. The semiconductor device according to any one of Claims 1 to 3, wherein The semiconductor chip has an electrostatic discharge protection element, i.e., an ESD protection element, connected to the first pad.

5. A receiving device, comprising: a semiconductor device having a semiconductor chip and a package, the semiconductor chip having a signal processing circuit and a plurality of pads, a first pad and a second pad of the plurality of pads not short-circuited to each other, the second pad connected to a signal input terminal of the signal processing circuit, the package mounting the semiconductor chip and having a plurality of terminals inputting or outputting signals to or from an outside, any specific terminal of the plurality of terminals of the package connected to the first pad by a first bonding wire and connected to the second pad by a second bonding wire; and a fourth resistor provided between the specific terminal of the package and a reference potential supply terminal.

6. A transmitting device, comprising: a semiconductor device having a semiconductor chip and a package, the semiconductor chip having a signal processing circuit and a plurality of pads, a first pad and a second pad of the plurality of pads not short-circuited to each other, the second pad connected to a signal output terminal of the signal processing circuit, the package mounting the semiconductor chip and having a plurality of terminals inputting or outputting signals to or from an outside, any specific terminal of the plurality of terminals of the package connected to the first pad by a first bonding wire and connected to the second pad by a second bonding wire; and a fifth resistor provided between the specific terminal of the package and a reference potential supply terminal.

7. A semiconductor device having: a package having a first terminal; a semiconductor chip mounted on the package, the semiconductor chip comprising: a first pad and a second pad; a pair of electrostatic discharge protection elements, i.e., ESD protection elements, connected to the first pad; and a signal processing circuit connected to the second pad; a first bonding wire connected between the first terminal and the first pad; a second bonding wire connected between the first terminal and the second pad; and a first resistor directly or indirectly connected between a connection point between the pair of ESD protection elements and a reference potential supply terminal.

8. The semiconductor device according to claim 7, wherein The semiconductor chip includes the first resistor.

9. The semiconductor device according to claim 8, wherein The semiconductor chip further includes a second resistor connected between the second pad and the reference potential supply terminal.

10. The semiconductor device according to claim 9, wherein The semiconductor chip further includes a third resistor provided between the first pad and the second pad.

11. The semiconductor device according to claim 7, wherein The first resistor is provided outside the semiconductor chip.

12. The semiconductor device according to any one of Claims 7 to 11, wherein The signal processing circuit is an amplifier.

13. A receiving device comprising the semiconductor device according to any one of claims 7 to 11, wherein the second pad is connected to a signal input terminal of the signal processing circuit.

14. A transmitting device comprising the semiconductor device according to any one of claims 7 to 11, wherein the second pad is connected to a signal output terminal of the signal processing circuit.

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