Display substrate and display device

Abstract

The present application provides a display substrate and a display device. The display substrate includes a touch area and a wiring area. The touch area includes a plurality of first electrodes and a second electrode arranged in an array. The wiring area includes a first trace, a second trace, and a shielding line arranged in sequence along a first direction. The first trace connects the first electrode, and the second trace connects the second electrode. The shielding line is used to shield the first trace and the second trace from interference from external signals. The shielding line includes a first line segment and a second line segment arranged and spaced apart along a second direction. In this way, by separating the shielding line into the first line segment and the second line segment, the interference of the shielding line on the second trace is reduced, thereby improving the touch yield of the display substrate.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a display substrate and a display device. Background Art

[0002] A touchscreen display is an input device that significantly improves the human-computer interface, offering advantages such as intuitiveness, simplicity, and speed. Touchscreens have been widely used in many electronic products, such as mobile phones, PDAs, multimedia, and public information query systems. Touchscreens can operate in a low-power mode (Doze mode or sleep mode) and a normal active mode (normal active mode). In low-power mode, the touchscreen detects whether a finger is on the screen by testing the Raw value of the touchscreen. The low-power mode does not require reporting of information such as the exact finger coordinates. Once a finger is detected in low-power mode, the touchscreen automatically switches to normal active mode. Summary of the Invention

[0003] In view of this, the present application provides a display substrate and a display device.

[0004] The display substrate of an embodiment of the present application includes a touch area and a wiring area, the touch area includes a plurality of first electrodes and a second electrode arranged in an array, the wiring area includes a first trace, a second trace and a shielding line arranged along a first direction, the first trace is connected to the first electrode, the second trace is connected to the second electrode, the shielding line is used to shield the first trace and the second trace from interference of external signals, and the shielding line includes a first line segment and a second line segment arranged and spaced apart from each other along a second direction.

[0005] In some embodiments, the wiring area further includes a switching element, the switching element is formed in a gap between the first line segment and the second line segment, and a source and a drain of the switching element are respectively connected to the first line segment and the second line segment.

[0006] In some embodiments, the wiring area further includes a control line, which is arranged on a side of the shielding line away from the first routing line or the second routing line, and the control line is connected to a gate of the switching element.

[0007] In some embodiments, the wiring area includes a base substrate, an active layer, a gate layer, a first source-drain layer, a second source-drain layer, an inorganic layer, and a second touch metal layer stacked in sequence, the active layer, the gate layer, the first source-drain layer, the second source-drain layer, and the second touch metal layer are connected, the shielding line is formed in the second touch metal layer, the active layer, the gate layer, the first source-drain layer, and the second source-drain layer form the switching element, and the control line is formed in the gate layer.

[0008] In some embodiments, the shielding line also includes a third line segment, which is formed at the interval between the first line segment and the second line segment. The third line segment is not located on the same layer as the first line segment and the second line segment, and partially overlaps with the first line segment and the second line segment along a third direction.

[0009] In some embodiments, the wiring area includes a base substrate, an insulating layer, an interlayer dielectric layer, a first flat layer, a second flat layer, an inorganic layer, a first touch metal layer, an organic layer, and a second touch metal layer stacked in sequence, the first line segment and the second line segment are formed in the second touch metal layer, and the third line segment is formed in the first touch metal layer.

[0010] In some embodiments, a via hole is formed in the organic layer, and the via hole is located where the third line segment overlaps with the first line segment or the second line segment along the third direction.

[0011] In some embodiments, the second trace includes a welding portion located at a location overlapping with the third line segment along the third direction.

[0012] In some embodiments, the first trace or the second trace is at least partially parallel to the shielding line.

[0013] In some embodiments, the shielding wire is provided with a plurality of first open slots facing the first routing line or the second routing line, and the plurality of first open slots are arrayed along the length direction of the shielding wire.

[0014] In some embodiments, the first routing line or the second routing line is provided with a plurality of second opening slots facing the shielding wire, and the plurality of second opening slots are arrayed along the length direction of the first routing line or the second routing line.

[0015] In some embodiments, the first opening slot and the second opening slot are staggered.

[0016] In some embodiments, the first trace or the second trace and the shielding line are located in different layers.

[0017] The display device provided in the embodiment of the present application includes the display substrate.

[0018] In the display substrate and display device provided in the embodiments of the present application, by dividing the shielding line into a first line segment and a second line segment, the antenna effect of the shielding line can be effectively reduced, and the parasitic capacitance generated by the shielding line and the first line or the second line can be effectively reduced, thereby reducing the interference of the shielding line itself on the first line or the second line, and improving the touch yield of the display substrate under low power consumption.

[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0021] Figure 1 It is a schematic plan view of a display substrate according to certain embodiments of the present application.

[0022] Figure 2 It is a schematic plan view of a display substrate according to certain embodiments of the present application.

[0023] Figure 3 yes Figure 1 Partial schematic diagram of point III in the middle.

[0024] Figure 4 It is a schematic plan view of a display substrate according to certain embodiments of the present application.

[0025] Figure 5 yes Figure 4 Local schematic diagram of point V in the middle.

[0026] Figure 6 yes Figure 5 Schematic diagram of the cross section at point VI.

[0027] Figure 7 It is a schematic plan view of a display substrate according to certain embodiments of the present application.

[0028] Figure 8 yes Figure 7 Partial schematic diagram of position VIII in the figure.

[0029] Figure 9 yes Figure 8 Schematic diagram of the cross section at point IX.

[0030] Figure 10 It is a cross-sectional schematic diagram of the display area of ​​certain embodiments of the present application.

[0031] Figure 11 4 is a schematic cross-sectional view of a touch layer in a display area of ​​certain embodiments of the present application.

[0032] Figure 12-16 It is a partial schematic diagram of the second routing line and the shielding line in the wiring area of ​​certain embodiments of the present application.

[0033] Description of main component symbols:

[0034] Display substrate 100, touch area 10, first electrode 11, second electrode 12, wiring area 20, first trace 21, second trace 22, second opening 221, shielding line 23, first line segment 231, second line segment 232, third line segment 233, first opening 234, ground line GND, switching element TFT, control line SW, bonding area 30, touch chip 31, bonding pin PIN;

[0035] Base substrate BS, active layer POLY, insulating layer GI, interlayer dielectric layer ILD, gate layer GATE1, first source and drain layer SD1, first planar layer PLN1, second source and drain layer SD2, second planar layer PLN2, inorganic layer CVD, first touch metal layer TMA, touch insulating layer TLD, second touch metal layer TMB, protective layer VOC;

[0036] First direction x, second direction y, third direction z. DETAILED DESCRIPTION

[0037] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be understood as limiting the present application.

[0038] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0039] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0040] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0041] Typically, for a 16x36-channel touch screen, during low-power mode testing, the signal transmission lines T0-T15 simultaneously generate waveforms, while the signal receiving lines R0-R35 simultaneously receive signals. After processing, the received signals correspond to data C36-C01. Since the signal receiving line R35 is located near the Guard line, the Guard line primarily functions to shield against external signal interference and protect both the transmitted and received signals. However, there is a certain amount of parasitic capacitance between the signal receiving line R35 and the Guard line. Under process fluctuations, a significant proportion of this capacitance may exceed specifications, which can easily reduce the product's touch screen yield. Furthermore, since the Guard line is typically long, it exhibits a strong antenna effect.

[0042] In view of this, please combine Figure 1-3 , an embodiment of the present application provides a display substrate 100, the display substrate 100 includes a touch area 10 and a wiring area 20, the touch area 10 includes a plurality of first electrodes 11 and second electrodes 12 arranged in an array, the wiring area 20 includes a first trace 21, a second trace 22 and a shielding line 23, the first trace 21, the second trace 22 and the shielding line 23 are arranged in sequence along the first direction x, or the shielding line 23, the first trace 21 and the second trace are arranged in sequence along the first direction x, the first trace 21 is connected to the first electrode 11, the second trace 22 is connected to the second electrode 12, the shielding line 23 is used to shield the first trace 21 and the second trace 22 from interference from external signals, and the shielding line 23 includes a first line segment 231 and a second line segment 232 arranged and spaced along the second direction y.

[0043] The embodiment of the present application also provides a display device. The display substrate 100 provided in the embodiment of the present application can be applied to the display device of the embodiment of the present application. That is, the display device of the embodiment of the present application can realize a touch function through the display substrate 100 of the embodiment of the present application.

[0044] In the display substrate 100 and the display device provided in the embodiment of the present application, by dividing the shielding line 23 into a first line segment 231 and a second line segment 232, the antenna effect of the shielding line 23 can be effectively reduced, and the parasitic capacitance generated by the shielding line 23 and the first wiring 21 or the second wiring 22 can be effectively reduced, thereby reducing the interference of the shielding line 23 itself on the first wiring 21 or the second wiring 22, and improving the touch yield of the display substrate 100 under low power consumption.

[0045] See also Figures 1 to 12 , the following is an explanation in combination with the specific structure of the display substrate 100 and the display device.

[0046] In some embodiments, the display device may be a touch-enabled display device such as a smart phone, a tablet computer, a smart bracelet, a virtual reality device, a personal data terminal, a laptop computer, etc., but is not limited thereto. Figure 1 In the embodiment shown, the display device is a smart phone.

[0047] The display substrate 100 may be an OLED display substrate 100, which can implement both touch and display functions. The display device includes a low-power mode and a normal activation mode. In the low-power mode, background CPU and network activities of the application are delayed, and the display substrate 100 does not display images, thereby reducing the power consumption of the display device.

[0048] The low power consumption mode and the normal activation mode can be switched according to the touch function. For example, when the display substrate 100 is in the normal activation mode, if the display substrate 100 does not receive a touch input within a predetermined time, the display substrate 100 can automatically switch from the normal activation mode to the low power consumption mode. When the display substrate 100 is in the low power consumption mode, if the display substrate 100 receives a touch input, the display substrate 100 can automatically switch from the low power consumption mode to the normal activation mode.

[0049] The display substrate 100 can be divided into a touch area 10 , a wiring area 20 and a binding area 30 . The wiring area 20 is located between the touch area 10 and the binding area 30 .

[0050] The touch area 10 includes a plurality of first electrodes 11 and second electrodes 12. The plurality of first electrodes 11 extend along a second direction y and are arranged along a first direction x. The second electrodes 12 extend along the first direction x and are arranged along a second direction y. The first direction x intersects the second direction y, and the second direction y can be perpendicular to the first direction x. For example, the first direction x can be horizontal and the second direction y can be vertical, or the first direction x can be vertical and the second direction y can be horizontal.

[0051] In this embodiment, an example in which the plurality of first electrodes 11 form M first electrode columns and the plurality of second electrodes 12 form N second electrode rows may be used for description.

[0052] When the display substrate 100 enters the low power mode, if the user performs an action input such as clicking or sliding on the touch area 10 of the display substrate 100, the original values ​​of the first electrode 11 and the second electrode 12 at the click or slide location will be changed, thereby automatically switching to the normal activation mode.

[0053] The wiring area 20 includes a first routing line 21, a second routing line 22, a shielding line 23, and a grounding line GND. The first routing line 21, the second routing line 22, the shielding line 23, and the grounding line GND are arranged sequentially along a first direction x. Alternatively, the grounding line GND, the shielding line 23, the first routing line 21, and the second routing line 22 are arranged sequentially along the first direction x. The first direction x is parallel to the horizontal direction. That is, the first routing line 21, the second routing line 22, the shielding line 23, and the grounding line GND are arranged sequentially along the horizontal direction. Alternatively, the grounding line GND, the shielding line 23, the first routing line 21, and the second routing line 22 are arranged sequentially along the horizontal direction.

[0054] In this embodiment, the first trace 21 , the second trace 22 , the shielding line 23 and the ground line GND are arranged in sequence along the first direction x. That is, the shielding line 23 is located on the side of the second trace 22 away from the first trace 21 .

[0055] The first routing line 21 may include one group or two groups. The number of groups of the first routing line 21 is related to the number of first electrodes 11 in each column of the first electrode column. When the number of first electrodes 11 in each column of the first electrode column is less than a preset number, the first routing line 21 may be one group. When the number of first electrodes 11 in each column of the first electrode column is greater than the preset number, the first routing line 21 may be two groups.

[0056] In this embodiment, there may be two groups of first traces 21, each group of first traces 21 including multiple traces. The number of first traces 21 in each group is equal to the number of first electrode columns. Each first trace 21 in one group extends from the wiring area 20 to the bottom of the touch area 10 and connects to one column of first electrode columns. Each first trace 21 in the other group extends from the wiring area 20 to the top of the touch area 10 and connects to one column of first electrode columns. Each first trace 21 is used to send a touch signal to the first electrode 11.

[0057] Multiple second traces 22 are arranged sequentially along the first direction x in the wiring area 20. The number of second traces 22 is the same as the number of second electrodes 12. Each second trace 22 corresponds to a row of second electrodes and extends across the touch control area 10. Each second trace 22 is connected to a row of second electrodes. The second traces 22 are configured to receive sensing signals from the first electrodes 11. In low-power mode, the display device processes the sensing signals received by the second traces 22 to obtain capacitance data of the first electrodes 11, thereby automatically switching to normal activation mode based on changes in the capacitance data.

[0058] The shielding line 23 is used to shield the first and second traces 21 and 22 from interference from external electric fields. The shielding line 23 includes a first segment 231 and a second segment 232 arranged and spaced apart along the second direction y. The second segment 232 extends from the wiring area 20 and surrounds the touch area 10. It is understood that parasitic capacitance is generated between the shielding line 23 and the first or second trace 21 or 22 adjacent to the shielding line 23, thereby reducing the signal received by the second trace 22. For example, if the second trace 22 includes traces R0-R35, which are arranged sequentially, and the second trace R35 is located near the shielding line 23, the shielding line 23 itself is likely to affect the sensing signal of the second trace R35, resulting in a decrease in the capacitance value data generated by the sensing signal of the second trace R35, which can easily affect the touch control yield of the sensing substrate. Therefore, by separating the shielding line 23 into a first line segment 231 and a second line segment 232, the influence of the shielding line 23 on the second routing line R35 can be reduced, so that in the low power consumption mode, the capacitance data generated by the sensing signal of the second routing line R35 adjacent to the shielding line 23 is improved, thereby improving the touch yield of the display substrate 100 in the low power consumption mode.

[0059] The binding area 30 may include a touch chip 31 . The touch chip 31 may be connected to the first trace 21 , the second trace 22 , the shielding wire 23 and the ground wire GND through pins.

[0060] Please combine Figure 4-Figure 6In some embodiments, the wiring area 20 further includes a switching element TFT. The switching element TFT is formed in the interval between the first line segment 231 and the second line segment 232. The source and drain of the switching element TFT are respectively connected to the first line segment 231 and the second line segment 232. The switching element TFT is used to control the connection between the first line segment 231 and the second line segment 232.

[0061] It should be noted that, in the embodiments of the present application, the switching element TFT can be a thin film transistor or a field effect transistor or other switching devices with the same characteristics. The source and drain of the switching element TFT used here can be symmetrical in structure, so its source and drain can be structurally indistinguishable. In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. The switching element TFT of this embodiment is described using a P-type transistor as an example. That is, in the embodiments of the present application, when the gate of the switching element TFT receives a low-level signal, the source and drain of the switching element TFT are turned on, and the first line segment 231 and the second line segment 232 are turned on. In this way, the shielding line 23 can effectively shield the interference of the external electric field on the first routing line 21 and the second routing line 22. When the gate of the switching element TFT receives a high-level signal, the switching element TFT is turned off, and the first line segment 231 is disconnected from the second line segment 232, which can reduce the antenna effect of the shielding line 23. At the same time, the capacitance data generated by the second routing line 22 adjacent to the shielding line 23 will be significantly improved, thereby reducing the impact of the shielding line 23 on the second routing line R35 in the low-power mode, improving the touch yield of the display substrate 100 in the low-power mode, and ensuring that the display substrate 100 can normally switch to the normal activation mode.

[0062] It can be understood that based on the description and teaching of the implementation of P-type transistors in this disclosure, ordinary technicians in this field can easily think of the implementation of the embodiments of this disclosure using N-type transistors without making any creative work. Therefore, these implementations are also within the scope of protection of this disclosure.

[0063] In this way, the connection between the first connecting segment and the second line segment 232 can be controlled by turning off the switching element TFT, which can ensure that the display substrate 100 is in the normal activation mode and avoid external signals from interfering with the first wiring 21 and the second wiring 22. At the same time, the interference of the shielding line 23 itself to the second wiring 22 in the low power consumption mode of the display substrate 100 is reduced, thereby effectively improving the touch yield of the display substrate 100 in the low power consumption mode.

[0064] In some embodiments, the wiring area 20 further includes a control line SW. The control line SW is arranged on a side of the shielding line 23 away from the second wiring 22 . The control line SW is connected to the gate of the switching element TFT.

[0065] Specifically, the control line SW is located on the side of the ground line GND in the wiring area 20 that is away from the shielding line 23. The control line SW is connected to the gate of the switching element TFT and is used to provide a control signal to the gate of the switching element TFT, thereby controlling the switching element TFT to turn on or off. When the control signal is high, the switching element TFT is turned off, the first line segment 231 and the second line segment 232 are disconnected, and the antenna effect of the shielding line 23 is reduced. This improves the touch yield of the display substrate 100 while reducing power consumption. When the control signal is low, the switching element TFT is turned on, and the first line segment 231 and the second line segment 232 are connected. The shielding line 23 acts as a shield against external electric fields, preventing external electric fields from interfering with the first and second lines 21 and 22.

[0066] Please further combine Figure 5 and Figure 6 In some embodiments, the wiring area 20 includes a base substrate BS and a switching element TFT formed on the base substrate BS, and the switching element TFT includes an active layer POLY, an insulating layer GI, a gate layer GATE1, an interlayer dielectric layer ILD, a first source and drain layer SD1, a first planar layer PLN1, a second source and drain layer SD2, a second planar layer PLN2, an inorganic layer CVD, and a second touch metal layer TMB.

[0067] The first source-drain layer SD1 is electrically connected to the active layer POLY through the interlayer dielectric layer ILD and the insulating layer GI. The second source-drain layer SD2 is electrically connected to the first source-drain layer SD1 through the first planar layer PLN1. The second touch metal layer TMB is connected to the second source-drain layer SD2 through the second planar layer PLN2 and the inorganic layer CVD, thereby forming a switching element TFT. The control line SW is formed on the gate layer GATE1. It should be noted that the above is only an exemplary description of the switching element TFT. The structure of the switching element TFT is not limited to this and can be set according to actual needs.

[0068] Specifically, the substrate BS can be a flexible substrate. The active layer POLY can form the source region and the drain region of the switching element TFT, and form a channel region located between the source region and the drain region. For example, the material of the active layer POLY may include polycrystalline silicon or an oxide semiconductor (for example, indium gallium zinc oxide). The material of the gate layer GATE1 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti). The material of the first source and drain layer SD1 and the second source and drain layer SD2 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0069] In this embodiment, the first line segment 231 and the second line segment 232 of the shielding line 23 can be arranged in the same layer and both form the second touch metal layer TMB, wherein the first line segment 231 can be connected to the second touch metal layer TMB connected to the drain region, and the second line segment 232 is connected to the second touch metal layer TMB connected to the source region.

[0070] It should be noted that the same layer may refer to: a film layer for forming a specific pattern is formed using the same film-forming process, and then the film layer is patterned using the same mask through a single patterning process to form a layer structure. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are made of the same material and are formed through the same patterning process. In this way, by arranging the first line segment 231 and the second line segment 232 in the same layer, the production efficiency of the display substrate 100 can be improved.

[0071] Please further combine Figure 6 or Figure 9 In some embodiments, the bonding area 30 includes a base substrate BS and a bonding pin PIN formed on the base substrate BS. The bonding pin PIN includes an insulating layer GI, a gate layer GATE1, a first source / drain electrode layer SD1, a second source / drain electrode layer SD2, and a second touch metal layer TMB, which are sequentially formed on the base substrate BS. The gate layer GATE1, the first source / drain electrode layer SD1, the second source / drain electrode layer SD2, and the second touch metal layer TMB are sequentially connected. The first line segment 231 is connected to the second touch metal layer TMB of the bonding pin PIN.

[0072] Please combine Figure 7 、 Figure 8 and Figure 9 In some embodiments, the shielding line 23 also includes a third line segment 233, which is formed at the interval between the first line segment 231 and the second line segment 232. The third line segment 233 is not located on the same layer as the first line segment 231 and the second line segment 232, and partially overlaps with the first line segment 231 and the second line segment 232 along the third direction z.

[0073] In this embodiment, the first line segment 231 and the second line segment 232 may be located in the same layer, and the third line segment 233 and the first line segment 231 may be located in a different layer.

[0074] Specifically, the wiring area 20 may include a base substrate BS, an insulating layer GI, an interlayer dielectric layer ILD, a first planar layer PLN1, a second planar layer PLN2, an inorganic CVD layer, a first touch metal layer TMA, a touch insulating layer TLD, and a second touch metal layer TMB, which are stacked in sequence. The first line segment 231 and the second line segment 232 are formed in the second touch metal layer TMB, and the third line segment 233 is formed in the first touch metal layer TMA.

[0075] Of course, it is understandable that in some other embodiments, the first line segment 231 and the second line segment 232 are formed in the first touch metal layer TMA, and the third line segment 233 is formed in the second touch metal layer TMB.

[0076] Additionally, it should be noted that the first line segment 231 and the second line segment 232 may also be located in different layers. For example, the first line segment 231 and the third line segment 233 may be located in the first metal touch layer TMA, and the second line segment 232 may be located in the second metal touch layer TMB. Alternatively, the second line segment 232 and the third line segment 233 may be located in the first metal touch layer TMA, and the first line segment 231 may be located in the second metal touch layer TMB. In other words, in the application, at least two of the first line segment 231, the second line segment 232, and the third line segment 233 may be located in different layers.

[0077] In some embodiments, a via hole is formed in the touch insulating layer TLD, and the via hole is located at a position where the third line segment 233 overlaps with the first line segment 231 or the second line segment 232 along the third direction z.

[0078] It should be noted that the third direction z is the film layer stacking direction, that is, the via hole is located in the touch insulation layer TLD in the overlapping area between the third line segment 233 and the first line segment 231 or the second line segment 232 along the film layer direction.

[0079] For example, please combine Figure 8 and Figure 9In some examples, a via hole can be formed in the touch insulation layer TLD at the overlapping position of the third line segment 233 and the first line segment 231, and the second touch metal layer TMB portion of the first line segment 231 extends from the via hole to the first touch metal layer TMA, so that the first line segment 231 and the third line segment 233 are connected.

[0080] In some embodiments, the second line segment 232 includes a welding portion located at a location overlapping the third line segment 233 along the third direction z. The welding portion dissolves when heated by the laser and partially extends through the via to the first touch metal layer TMA, thereby connecting the second line segment 232 and the third line segment 233.

[0081] In this way, by setting a via hole at the overlapping position of the touch insulation layer TLD and the third line segment 233 and the first line segment 231 or the second line segment 232 along the third direction z, the first line segment 231, the second line segment 232 and the third line segment 233 can be connected by laser heating the second line segment 232 at the via hole of the touch insulation layer TLD as needed, thereby improving the shielding effect of the shielding line 23 against the external electric field.

[0082] Please combine Figure 10 In some embodiments, the touch control area 10 includes a substrate 111 and a sub-pixel 112 formed on the substrate 111. The sub-pixel 112 includes a driving transistor 121 and a storage capacitor 122. The driving transistor 121 includes a first active layer 1211 located on the substrate 111, a first gate 1213 located on a side of the first active layer 1211 away from the substrate 111, a first insulating layer 1214 located on a side of the first gate 1213 away from the substrate 111, a second insulating layer 1215 located on a side of the first insulating layer 1214 away from the substrate 111, and a source 1216 and a drain 1217 located on a side of the second insulating layer 1215 away from the substrate 111 and electrically connected to the first active layer 1211. In some embodiments, the driving transistor 121 further includes a gate dielectric layer 1212 located on a side of the first active layer 1212 away from the substrate 111, and the first gate 1213 is located on a side of the gate dielectric layer 1212 away from the substrate 111. For example, the source electrode 1216 and the drain electrode 1217 are electrically connected to the first active layer 1211 through via holes penetrating the second insulating layer 1215 , the first insulating layer 1214 , and the gate dielectric layer 1212 , respectively.

[0083] The storage capacitor 122 includes a first electrode plate 1221 located on the same layer as the first gate 1213, and a second electrode plate 1222 located between the first insulating layer 1214 and the second insulating layer 1215. It should be understood that the storage capacitor 122 also includes a first insulating layer 1214 located between the first electrode plate 1221 and the second electrode plate 1222.

[0084] The sub-pixel 112 also includes a light-emitting diode 123, such as an OLED. The light-emitting diode 123 includes a first electrode 1231 (e.g., an anode), a functional layer 1232 located on the side of the first electrode 1231 away from the substrate 111, and a second electrode 1233 (e.g., a cathode) located on the side of the functional layer 1232 away from the substrate 111. For example, the first electrode 1231 of the light-emitting diode 123 is electrically connected to the drain 1217 of the driving transistor 121. Here, the functional layer 1232 includes at least a light-emitting layer, such as an organic light-emitting layer. In some embodiments, the functional layer 1232 may also include one or more layers of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.

[0085] In some embodiments, see Figure 10 , the sub-pixel 112 may further include a buffer layer 124 located between the base substrate 111 and the first active layer 1211, a planarization layer 125 covering the source electrode 1216 and the drain electrode 1217, a pixel definition layer 126 for defining the plurality of sub-pixels 112, a support layer 127, and an encapsulation layer 128. For example, the first electrode 1231 of the light-emitting diode 123 may be electrically connected to the drain electrode 1217 of the driving transistor 121 through a via hole penetrating the planarization layer 125. For example, the pixel definition layer 126 has a plurality of openings corresponding to the plurality of sub-pixels 112, and the light-emitting diodes 123 of the plurality of sub-pixels 112 are located in the plurality of openings. For example, the encapsulation layer 128 may include a thin film encapsulation layer. In some embodiments, the encapsulation layer 128 may include a first inorganic layer 1281, a second inorganic layer 1282, and an organic layer 1283 located between the first inorganic layer 1281 and the second inorganic layer 1282.

[0086] As some implementations, one or more layers of the second insulating layer 1215, the first insulating layer 1214, the gate dielectric layer 1212, the buffer layer 124, the planarization layer 125, the pixel defining layer 126, and the support layer 127 may include organic insulating materials such as polyimide, resin materials, etc., or inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0087] Please combine Figure 6 、 Figure 9 and Figure 10 The gate dielectric layer 1212 is located on the same layer as the insulating layer GI, the active layer POLY is located on the same layer as the first active layer 1211, the gate layer GATE1 is located on the same layer as the first gate electrode 1213, the interlayer dielectric layer ILD is located on the same layer as the first insulating layer 1214, and the source electrode 1216 and the drain electrode 1217 are located on the same layer as the first source-drain electrode layer SD1. The first planarizing layer PLN1 is located on the same layer as the second insulating layer 1215, and the second planarizing layer PLN2 is located on the same layer as the planarization layer 125.

[0088] Please combine Figure 11 In some embodiments, the touch area 10 further includes a touch layer 129, on which the first electrode 11 and the second electrode 12 are formed. The first electrode 11 and the second electrode 12 include a buffer layer, a first touch metal layer TMA, an insulating touch layer TLD, a second touch metal layer TMB, and a protective layer VOC, which are stacked in sequence. The second touch metal layer TMB is at least partially connected to the first touch metal layer TMA through the insulating touch layer TLD.

[0089] Please combine Figure 12 In some embodiments, the first trace 21 or the second trace 22 is at least partially parallel to the shielding line 23 .

[0090] It should be noted that in this embodiment, the first routing line 21 or the second routing line 22 can be the first routing line 21 or the second routing line 22 closest to the shielding line 23, that is, the first routing line 21 or the second routing line 22 adjacent to the shielding line 23 is at least partially parallel to the shielding line 23.

[0091] This is beneficial for optimizing the space of the wiring area 20 and reducing the parasitic capacitance between the shielding line 23 and the first wiring 21 or the second wiring 22, thereby reducing the interference of the shielding line 23 itself on the first wiring 21 or the second wiring 22, and improving the touch yield of the display substrate 100.

[0092] Please combine Figure 13 In some embodiments, the shielding wire 23 is provided with a plurality of first opening slots 234 facing the first wiring 21 or the second wiring 22 , and the plurality of first opening slots 234 are arrayed along the length direction of the shielding wire 23 .

[0093] It is understandable that the magnitude of the parasitic capacitance generated between the shielding wire 23 and the first or second wiring 21, 22 is proportional to the spacing between the shielding wire 23 and the first or second wiring 21, 22. Therefore, by providing the shielding wire 23 with multiple first openings 234 facing the first or second wiring 21, 22, the average spacing between the shielding wire 23 and the second wiring 22 can be increased, thereby reducing the parasitic capacitance generated between the shielding wire 23 and the second wiring 22. This can reduce the impact of the shielding wire 23 on the second wiring 22, thereby improving the touch yield of the display substrate 100.

[0094] Please combine Figure 14 In some embodiments, the first trace 21 or the second trace 22 is provided with a plurality of second opening slots 221 facing the shielding line 23 , and the plurality of second opening slots 221 are arrayed along the length direction of the first trace 21 or the second trace 22 .

[0095] In this way, the average spacing between the shielding line 23 and the first wiring 21 or the second wiring 22 can be increased, the parasitic capacitance generated by the shielding line 23 and the first wiring 21 or the second wiring 22 can be reduced, and the influence of the shielding line 23 itself on the first wiring 21 or the second wiring 22 can be reduced, thereby improving the touch yield of the display substrate 100.

[0096] Please combine Figure 15 In some embodiments, the first opening slot 234 and the second opening slot 221 are staggered.

[0097] In this way, the average spacing between the shielding line 23 and the first wiring 21 or the second wiring 22 can be further increased, thereby further reducing the parasitic capacitance generated by the shielding line 23 and the first wiring 21 or the second wiring 22, reducing the impact of the shielding line 23 itself on the first wiring 21 or the second wiring 22, and further improving the touch yield of the display substrate 100.

[0098] Please combine Figure 6 In some embodiments, the first trace 21 or the second trace 22 and the shielding trace 23 are located on the same layer. For example, the second trace 22 and the shielding trace 23 are both located on the first touch metal layer TMA, or both located on the second touch metal layer TMB.

[0099] In some embodiments, the first trace 21 or the second trace 22 and the shielding line 23 are located in different layers.

[0100] Specifically, the first trace 21 or the second trace 22 and the shielding trace 23 being located on different layers can mean that the entire first trace 21 and the shielding trace 23 are completely located on different layers, or that the entire first trace 21 or the second trace 22 and the shielding trace 23 are completely located on different layers. For example, when the first trace 21 is adjacent to the shielding trace 23, the first trace 21 can be located on the first touch metal layer TMA and the shielding trace 23 is located on the second touch metal layer TMB, or the shielding trace 23 can be located on the first touch metal layer TMA and the first trace 21 is located on the second touch metal layer TMB. For another example, when the second trace 22 is adjacent to the shielding trace 23, the second trace 22 can be located on the first touch metal layer TMA and the shielding trace 23 is located on the second touch metal layer TMB, or for another example, the shielding trace 23 can be located on the first touch metal layer TMA and the second trace 22 is located on the second touch metal layer TMB.

[0101] The first trace 21 or the second trace 22 and the shielding line 23 are located in different layers. Alternatively, the areas directly facing the first trace 21 and the shielding line 23 are located in different layers, or the areas directly facing the second trace 22 and the shielding line 23 are located in different layers. Figure 16, the first line segment 231 of the shielding line 23 is located in the first touch metal layer TMA, the line segment of the first routing line 21 or the second routing line 22 that is opposite to the first line segment 231 is located in the second touch metal layer TMB, the second line segment 232 of the shielding line 23 is located in the second touch metal layer TMB, and the line segment of the first routing line 21 or the second routing line 22 that is opposite to the second line segment 232 is located in the first touch metal layer TMA, or, the first line segment 231 of the shielding line 23 is located in the second touch metal layer TMB, and the line segment of the first routing line 21 or the second routing line 22 that is opposite to the first line segment 231 is located in the first touch metal layer TMA, the second line segment 232 of the shielding line 23 is located in the first touch metal layer TMA, and the line segment of the first routing line 21 or the second routing line 22 that is opposite to the second line segment 232 is located in the second touch metal layer TMB

[0102] In this way, by designing the first routing line 21 or the second routing line 22 and the shielding line 23 in a layered and staggered manner, the parasitic capacitance generated by the first routing line 21 or the second routing line 22 and the shielding line 23 is reduced, so that the impact of the shielding line 23 on the first routing line 21 or the second routing line 22 is reduced, thereby improving the touch yield of the display substrate 100.

[0103] Throughout this specification, reference to terms such as "one embodiment," "certain embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0104] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that: The display substrate includes a touch area and a wiring area, the touch area includes a plurality of first electrodes and a second electrode arranged in an array, the wiring area includes a first trace, a second trace, and a shielding line arranged along a first direction, the first trace connecting the first electrode, the second trace connecting the second electrode, the shielding line is used to shield the first trace and the second trace from interference by external signals, and the shielding line includes a first line segment and a second line segment arranged and spaced apart along a second direction; The wiring area further includes a switching element formed in a gap between the first line segment and the second line segment, wherein a source and a drain of the switching element are connected to the first line segment and the second line segment, respectively.

2. The display substrate according to claim 1, wherein: The wiring area further includes a control line, which is arranged on a side of the shielding line away from the first routing line or the second routing line, and is connected to a gate of the switching element.

3. The display substrate according to claim 2, wherein: The wiring area includes a base substrate, an active layer, a gate layer, a first source-drain layer, a second source-drain layer, an inorganic layer, and a second touch metal layer stacked in sequence. The active layer, the gate layer, the first source-drain layer, the second source-drain layer, and the second touch metal layer are connected. The shielding line is formed in the second touch metal layer. The active layer, the gate layer, the first source-drain layer, and the second source-drain layer form the switching element. The control line is formed in the gate layer.

4. The display substrate according to claim 1, wherein The shielding line also includes a third line segment, which is formed at the interval between the first line segment and the second line segment. The third line segment is not located in the same layer as the first line segment and the second line segment, and partially overlaps with the first line segment and the second line segment along a third direction.

5. The display substrate according to claim 4, wherein: The wiring area includes a base substrate, an insulating layer, an interlayer dielectric layer, a first flat layer, a second flat layer, an inorganic layer, a first touch metal layer, an organic layer, and a second touch metal layer stacked in sequence. The first line segment and the second line segment are formed in the second touch metal layer, and the third line segment is formed in the first touch metal layer.

6. The display substrate according to claim 5, wherein: A via is formed in the organic layer, and the via is located at a position where the third line segment overlaps with the first line segment or the second line segment along the third direction.

7. The display substrate according to claim 6, wherein: The second trace includes a welding portion located at a position overlapping with the third line segment along the third direction.

8. The display substrate according to claim 1, wherein: The second wiring or the first wiring is at least partially parallel to the shielding wire.

9. The display substrate according to claim 8, wherein: The shielding wire is provided with a plurality of first opening slots facing the first routing line or the second routing line, and the plurality of first opening slots are arranged in an array along the length direction of the shielding wire; and / or The first routing line or the second routing line is provided with a plurality of second opening slots facing the shielding line, and the plurality of second opening slots are arrayed along the length direction of the first routing line or the second routing line.

10. The display substrate according to claim 9, wherein: The first opening slot and the second opening slot are staggered.

11. The display substrate according to claim 1, wherein The first wiring or the second wiring and the shielding line are located in different layers.

12. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 11.

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