Timing correction device and method for extended data output mode

Abstract

The present application discloses a timing correction device suitable for an extended data output mode of a flash memory. The timing correction device includes a data comparison buffer, a timing control buffer, and a read delay time controller. The data comparison buffer stores first test data. The timing control buffer stores a read delay time of a data read instruction. When in the extended data output mode, the read delay time controller instructs the flash memory controller to read the second test data of the flash memory according to the data read instruction and the read delay time, and the read delay time controller verifies whether the first test data and the second test data are the same. When the verification result is not the same, the stored read delay time is updated, and the test data is read and verified repeatedly until the verification result is the same.

Description

Technical Field

[0001] The invention relates to a timing correction device, and in particular to a timing correction device capable of automatically correcting a read delay time in an extended data output mode of a flash memory. Background Art

[0002] In flash memory, if the user needs to speed up the data reading speed in the extended data output (EDO) mode, the user currently needs to set the timing parameters in the extended data output mode from the software, that is, set the delay time for reading data, and test the set delay time to confirm that the data can be read correctly before confirming that the extended data output mode can operate correctly. However, the user may not know how to set and convert the relevant timing parameters, and even if the user knows how to set and convert the relevant timing parameters, the user's time cost will be increased through user setting and conversion. Summary of the invention

[0003] It can be understood from the above description that the technical problem to be solved is to provide a timing correction device without requiring the user to set the timing parameters in the extended data output mode from the software.

[0004] In order to solve the above-mentioned conventional problems, an embodiment of the present invention provides a timing correction device, which is suitable for the extended data output mode of the flash memory, and the timing correction device includes a data comparison register, a timing control register and a read delay time controller. The data comparison register stores the first test data. The timing control register stores the read delay time of the data read instruction of the extended data output mode of the flash memory.

[0005] When the read delay time controller is in the extended data output mode, the read delay time controller instructs the flash memory controller to read the second test data of the flash memory according to the data read instruction and the read delay time, and the read delay time controller verifies whether the first test data is the same as the second test data. When the first test data is different from the second test data, the timing control register updates the stored read delay time, and the read delay time controller instructs the flash memory controller to repeatedly read the second test data according to the updated read delay time, and the read delay time controller repeatedly verifies whether the first test data is the same as the second test data, until the first test data is the same as the second test data.

[0006] According to an embodiment of the present invention, the timing control buffer includes a D flip-flop.

[0007] According to an embodiment of the present invention, the data read command of the timing control register is a read ID (identification) command.

[0008] According to an embodiment of the present invention, the read delay time controller is implemented by a hardware control circuit.

[0009] According to an embodiment of the present invention, the read latency controller is implemented through a microcontroller and firmware of a flash memory controller.

[0010] According to an embodiment of the present invention, when the first test data is different from the second test data, the read delay time controller updates the read delay time by increasing or decreasing the unit time.

[0011] According to an embodiment of the present invention, the data comparison register further stores third and fourth test data, and the third, first and fourth test data are located at three consecutive addresses of the flash memory. When the first test data is different from the second test data, the read delay time controller updates the read delay time in a binary search manner.

[0012] Based on the above purpose, the present invention also provides a flash memory control chip, comprising the above timing correction device, a flash memory controller, a direct memory access controller and a first in first out (FIFO) buffer. When the flash memory controller is in an extended data output mode, according to a data read instruction and a read delay time, the second test data of the flash memory is read, and the timing correction device verifies whether the first test data and the second test data are the same.

[0013] The DMA controller stores the first test data in the data comparison register and reads the second test data from the flash memory in the extended data output mode. The FIFO buffer transmits the first test data and the second test data in the extended data output mode.

[0014] Based on the above purpose, the present invention also provides a timing correction method, which is applicable to the extended data output mode of the flash memory, and at least includes the following steps: storing the read delay time of the data read instruction in the timing control register, and storing the first test data in the data comparison register.

[0015] In the extended data output mode, the flash memory controller is instructed to read the second test data of the flash memory according to the read delay time.

[0016] Verify whether the first test data and the second test data are consistent, and when the first test data and the second test data are inconsistent, update the read delay time, repeatedly read the second test data, and repeat the verification until the first test data is consistent with the second test data.

[0017] According to an embodiment of the present invention, the step of updating the read delay time includes updating the read delay time by increasing or decreasing the unit time.

[0018] As described above, the timing correction device and method of the embodiments of the present invention have the advantage of automatically finding the read delay time of read data in the extended data output mode by means of hardware (or hardware in combination with firmware), thereby eliminating the need for the user to manually test the read delay time in the extended data output mode, thereby improving usage efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0020] Figure 1 Schematic diagram of a timing correction device in an extended data output mode according to an embodiment of the present invention.

[0021] Figure 2 FIG. 4 is a schematic diagram of a timing correction device in an extended data output mode according to another embodiment of the present invention.

[0022] Figure 3 FIG. 4 is a waveform diagram of a delay time test of an extended data output mode according to an embodiment of the present invention.

[0023] Figure 4 FIG. 4 is a schematic diagram of a flash memory control chip including a timing correction device according to an embodiment of the present invention.

[0024] Figure 5 4 is a flow chart of a timing correction method for an extended data output mode according to an embodiment of the present invention.

[0025] The symbols indicated in the figure are explained as follows:

[0026] 10: Timing correction device

[0027] 20: Flash memory control chip

[0028] 100: Data comparison buffer

[0029] 200: Timing control register

[0030] 210: D flip-flop

[0031] 300: Read delay time controller

[0032] 301, 401: Trigger signal

[0033] 310: Control circuit

[0034] 400: Flash memory controller

[0035] 410: Microcontroller

[0036] 420: Firmware

[0037] 500: Direct Memory Access Controller

[0038] 600: First-in-first-out buffer

[0039] 700: Flash memory

[0040] DT: Read delay time

[0041] HCLK: clock signal

[0042] RE: Read enable signal

[0043] S1~S4: Steps DETAILED DESCRIPTION

[0044] In view of the above technical problems to be overcome, the present invention develops a timing correction device and method for an extended data output mode, which automatically tests the read delay time in the extended data output mode to improve the use efficiency.

[0045] For a more clear description of the embodiments of the present invention, please refer to Figure 1 , Figure 1 As shown in the figure, the embodiment of the present invention provides a timing correction device 10 for the extended data output mode of a flash memory, comprising a data comparison register 100, a timing control register 200 and a read delay time controller 300.

[0046] Extended data output (EDO) mode overview:

[0047] When the memory is in the general data output mode, the memory must first spend time to transmit the signal to a memory address (address) where the data is to be read. At this time, the logic circuit of the memory must be charged and discharged once. Therefore, to read the data of a memory address, a charge and discharge action is required, which makes the efficiency of data reading unable to be improved. However, when reading the data of a certain memory address, there is a considerable chance that the data at a nearby location will be read during the next read action.

[0048] In the extended data output mode, each memory read does not force the memory logic circuit to charge and discharge and update, but remembers the memory address of the previous read action to read the data of the nearby memory address, thus speeding up the memory read cycle and achieving the effect of accelerating data reading. However, in the extended data output mode, the delay time needs to be read correctly to ensure that the read data is correct, but as described in the previous technology, users may not know how to set and convert the relevant timing parameters.

[0049] The data comparison buffer 100 is used to store data in the flash memory 700. When the flash memory enters the extended data output mode, the data stored in the data comparison buffer 100 is used as comparison data for verifying the read delay time. The data comparison buffer 100 can first store a fixed length of data in the flash memory 700. For example, each time data is read and written in the general data output mode, the last 32 bits of data read and written are additionally stored in the data comparison buffer 100. When the flash memory 700 switches to the extended data output mode, the 32 bits of data are used as the first test data for verification; for another example, the data comparison buffer 100 can store the identification data obtained according to the identification read instruction as the first test data for verification.

[0050] The timing control buffer 200 is used to store the read delay time of the data read instruction of the flash memory 700 in the extended data output mode, and the data read instruction includes the above-mentioned read delay time, so the timing control buffer 200 can also store the entire data read instruction. The following table 1 exemplarily illustrates the instruction data stored in the timing control buffer 200.

[0051] Table 1:

[0052]

[0053] The instruction data stored in bits 31 to 0 in Table 1 represent the following information:

[0054] EDOEN (extended data output mode enable): stored in bit 31, indicating whether the command data to enable the extended data output mode is received;

[0055] Reserved: Stored in bits 30 to 28 and bit 23 as a spare address;

[0056] EDOD (extended data output mode delay time): stored in bits 27 to 24, indicating the read delay time in the extended data output mode. When the flash memory 700 is in the extended data output mode, the data in the flash memory 700 is read according to the read delay time corresponding to the command data stored in bits 27 to 24;

[0057] CALESH (CLE / ALE setup / hold time): Stored in bits 22 to 16, represents the setup and hold time of the command latch enable (CLE) and address latch enable (ALE);

[0058] HIWID (read / write enable signal high pulse width, HIWID): stored in bits 15 to 8, representing the pulse width of the read / write enable signal at the high level;

[0059] LOWID (read / write enable signal low pulse width, LOWID): stored in bits 7 to 0, represents the pulse width of the read / write enable signal at the low level.

[0060] When the read delay time controller 300 receives the trigger signal 301 to switch to the extended data output mode, it can send an indication signal to the flash memory controller. The flash memory controller then controls the data read instruction and the read delay time stored in the buffer 200 according to the timing, and reads the second test data in the flash memory 700. The read delay time controller 300 verifies the first test data and the second test data.

[0061] When the first test data is different from the second test data, it indicates that the setting value of the read delay time is incorrect, and the read delay time controller 300 returns a signal corresponding to the verification result to the timing control register 200 to update the stored read delay time. The read delay time controller 300 instructs the flash memory controller to repeatedly read the second test data according to the updated read delay time, and the read delay time controller 300 repeatedly verifies the first test data and the second test data until the first test data is the same as the second test data.

[0062] According to an embodiment of the present invention, the timing control buffer 200 storing the first test data may be implemented by a flip-flop, for example, a D flip-flop 210 , but not limited thereto.

[0063] According to an embodiment of the present invention, the data read instruction stored in the timing control buffer 200, in addition to the data read instruction including the read delay time, also includes the above-mentioned Table 1, with spare addresses reserved for storing other read instructions, forming a complete identification read instruction (read ID command).

[0064] According to the embodiment of the present invention, the read delay time controller 300 may be implemented by a hardware circuit, such as a control circuit 310 , but is not limited thereto.

[0065] See also Figure 2 , Figure 2 This is a schematic diagram of a timing correction device for an extended data output mode according to another embodiment of the present invention. As shown in the figure, Figure 2 Examples and Figure 1 The embodiment of the present invention is different in that the read delay time controller 300 can be used as follows Figure 1 In the embodiment, a dedicated hardware circuit is designed to send an indication signal to the flash memory controller 400 to implement data reading, and the hardware circuit then performs a verification operation. Alternatively, the microcontroller 410 (MCU) and firmware 420 in the flash memory controller 400 can be used to implement the operation. When the flash memory controller 400 receives the trigger signal 401, the microcontroller 410 in the flash memory controller 400 executes the firmware 420 to automatically obtain the read delay time.

[0066] Next Read Figure 3 , Figure 3 The waveform diagram of the delay time test of the extended data output mode according to an embodiment of the present invention. As shown in the figure, the clock signal HCLK represents the data reading cycle, for example, it can be 200MHz, that is, the clock cycle is 5 nanoseconds. When the read enable (RE) changes from a high level to a low level, it means that a read instruction is received to read data. The time when the read enable signal is at a low level is the row address select pre-charge time (t RP ), which represents the time it takes for the memory to finish reading the current address and start reading the next row.

[0067] The data signal is a time point (read enable access time, t) after the read enable signal changes from a high level to a low level and then changes back to a high level. REA ) starts to read the data, and t REA The time must be greater than t RP .

[0068] Similarly, the sampling signal also starts sampling at a certain time point after a read enable signal changes from a high level to a low level and then changes back to a high level to perform data reading. However, the sampling time point is different from a t RP The time difference between the end time points is the read delay time DT mentioned in the embodiment of the present invention. When the flash memory is in the extended data output mode, the read delay time needs to be tested multiple times. If the corresponding correct read delay time is not tested, the data cannot be read correctly.

[0069] According to an embodiment of the present invention, after verifying the first test data and the second test data, if the data of the two are different, the read delay time controller 300 will return a signal corresponding to the verification result to the timing control buffer 200. At this time, the timing control buffer 200 can update the read delay time by increasing or decreasing the unit time, for example, the data read cycle time (t RC ) is 30 nanoseconds, and 1 nanosecond can be used as a unit. After each verification, the preset read delay time is increased or decreased by 1 nanosecond until the read first test data is the same as the second test data.

[0070] According to an embodiment of the present invention, the timing control register 200 can also update the read delay time by a binary search method. In this embodiment, in addition to storing the first test data, the data comparison register 100 also stores the third and fourth test data (the third, first and fourth test data are designed to be different from each other), wherein the address of the first test data in the flash memory is located between the addresses of the third and fourth test data in the flash memory. In other words, corresponding to the specific three consecutive addresses, the flash memory stores the third, first and fourth test data in sequence. Assuming that the data acquisition cycle is 30 nanoseconds, the correct read delay time is 8 nanoseconds, the initial read delay time is 1 nanosecond, and the timing control register 200 compares that the first test data is equal to the third test data, it means that the read delay time is not large enough, so the read delay time can be updated to 15 nanoseconds. Then, the timing control register 200 compares that the first test data is equal to the fourth test data, which means that the read delay time is too large, so the read delay time can be updated to 8 nanoseconds. Afterwards, the timing control register 200 compares and finds that the first test data is equal to the second test data, and thus determines that the correct read delay time is 8 nanoseconds.

[0071] See also Figure 4 , Figure 4 Schematic diagram of a flash memory control chip including a timing correction device according to an embodiment of the present invention. As shown in the figure, the timing correction device 10 of the above embodiment can be integrated into the flash memory control chip 20. In order to reduce the computational burden when verifying the read delay time, in addition to the flash memory controller 400 for verification, a direct memory access (DMA) controller 500 and a first-in-first-out buffer 600 can also be used. In the extended data output mode, in order not to increase the computational burden of the central processing unit, the first test data is stored in the data comparison register and the second test data of the flash memory is read through the direct memory access controller 500, and the first-in-first-out buffer 600 is used to further improve the transmission speed.

[0072] See also Figure 5 , Figure 5 The timing correction method in the extended data output mode is illustrated in the flowchart of the embodiment of the present invention. As shown in the figure, the timing correction method in the extended data output mode is described by the following steps (S1-S4):

[0073] In step S1, when the flash memory 700 has not entered the extended data output mode, the read delay time in the data read instruction is first stored in the timing control buffer 200 of the timing correction device 10, and the data in the flash memory 700 is stored in the data comparison buffer 100 of the timing correction device 10 as the first test data, which can be used when the flash memory 700 enters the extended data output mode.

[0074] In step S2 , after receiving the trigger signal, the read delay time controller 300 instructs the flash memory controller to read the test data in the flash memory 700 according to the read delay time stored in the timing control buffer 200 .

[0075] In step S3, the read delay time controller 300 verifies whether the first test data stored in the data comparison buffer 100 is the same as the second test data currently read from the flash memory 700. If the data of the two are the same, it means that the set read delay time is correct, and then the timing correction process ends.

[0076] In step S4, if the data of the two are different, it means that the set read delay time is incorrect. At this time, the signal of the verification result will be transmitted to the timing control register 200, and the timing control register 200 will update the read delay time in a unit time increment or decrement manner (or update the read delay time in a binary search manner. If a binary search is used, the data comparison register 100 must store data of three consecutive addresses of the flash memory as the third, first and fourth test data for verification), and repeat the verification action of the above step S3 with the updated read delay time.

[0077] According to the above, the present invention can automatically find out the read delay time of reading data in the extended data output mode, thereby eliminating the need for the user to manually test the read delay time in the data output mode, thereby improving usage efficiency.

[0078] The present invention is disclosed herein only by preferred embodiments, but any person skilled in the art should understand that the above embodiments are only used to describe the present invention and are not used to limit the scope of the patent rights claimed by the present invention. Any changes or substitutions that are equal or equivalent to the above embodiments should be interpreted as being included in the spirit or scope of the present invention. Therefore, the protection scope of the present invention should be based on what is defined in the claims.

Claims

1. A timing correction device, suitable for an extended data output mode of a flash memory, characterized in that: The timing correction device comprises: A data comparison buffer storing a first test data; a timing control register storing a read delay time of a data read instruction of the extended data output mode of the flash memory; as well as a read delay time controller, in the extended data output mode, the read delay time controller instructs a flash memory controller to read a second test data of the flash memory according to the data read instruction and the read delay time, and the read delay time controller verifies whether the first test data and the second test data are the same; When the first test data is different from the second test data, the timing control buffer updates the stored read delay time, and the read delay time controller instructs the flash memory controller to repeatedly read the second test data according to the updated read delay time, and the read delay time controller repeatedly verifies whether the first test data is the same as the second test data until the first test data is the same as the second test data.

2. The timing correction device according to claim 1, characterized in that: The timing control buffer includes a D flip-flop.

3. The timing correction device according to claim 1, characterized in that: The data read instruction of the timing control register is an identification read instruction.

4. The timing correction device according to claim 1, wherein: The read delay time controller is a hardware control circuit.

5. The timing correction device according to claim 1, characterized in that: The read delay time controller is a microcontroller and a firmware of the flash memory controller.

6. The timing correction device according to claim 1, characterized in that: When the first test data is different from the second test data, the read delay time controller updates the read delay time by incrementing or decrementing a unit time.

7. The timing correction device according to claim 1, characterized in that: The data comparison register further stores a third test data and a fourth test data, wherein the third test data, the first test data and the fourth test data are located at three consecutive addresses of the flash memory, and when the first test data is different from the second test data, the read delay time controller updates the read delay time in a binary search manner.

8. A flash memory control chip, characterized in that: The flash memory control chip comprises: The timing correction device according to any one of claims 1 to 7; a flash memory controller, in the extended data output mode, reading the second test data of the flash memory according to the data read instruction and the read delay time; a direct memory access controller, which stores the first test data in the data comparison register and reads the second test data from the flash memory via the direct memory access controller in the extended data output mode; as well as A first-in-first-out buffer is used to transmit the first test data and the second test data in the extended data output mode.

9. A timing correction method, applicable to an extended data output mode of a flash memory, characterized in that: The timing correction method at least comprises the following steps: storing a read delay time of a data read instruction in a timing control register, and storing a first test data in a data comparison register; In an extended data output mode, instructing a flash memory controller to read a second test data of the flash memory according to the read delay time; Verifying whether the first test data and the second test data are consistent; as well as When the first test data and the second test data are inconsistent, the read delay time is updated, the second test data is repeatedly read, and verification is repeated until the first test data and the second test data are consistent.

10. The timing correction method according to claim 9, characterized in that: The step of updating the read delay time comprises: The read delay time is updated by incrementing or decrementing a unit time.

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