A data processing circuit, method, and semiconductor memory

Abstract

Embodiments of the present disclosure provide a data processing circuit, a method, and a semiconductor memory. The data processing circuit includes a receiving module, a first power supply module, and a processing module. Among them, the receiving module is configured to receive a data signal and determine a first node signal according to the data signal; the first power supply module is configured to receive an enable signal and control the processing module to be in a working state when the enable signal is in an effective state; the processing module is configured to output a target data signal according to the first node signal when it is in the working state. The data processing circuit has a small leakage current generated in the standby mode, which is beneficial to saving circuit power consumption.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit technologies, and particularly to a data processing circuit, a method, and a semiconductor memory. Background Art

[0002] Semiconductor memories are very important components in digital integrated circuits, and they play a crucial role in constructing application systems of microprocessors. In recent years, people have increasingly embedded various semiconductor memories inside processors to make the processors have higher integration and faster working speeds. However, in related technologies, taking a data receiver as an example, the leakage current of the data receiver in the standby state is relatively large, and this leakage current may also cause excessive power consumption of the circuit. Summary of the Invention

[0003] Embodiments of the present disclosure provide a data processing circuit, a method, and a semiconductor memory:

[0004] In a first aspect, embodiments of the present disclosure provide a data processing circuit, including a receiving module, a first power supply module, and a processing module, where

[0005] the receiving module is configured to receive a data signal and determine a first node signal according to the data signal;

[0006] the first power supply module is configured to receive an enable signal and control the processing module to be in a working state when the enable signal is in an effective state;

[0007] the processing module is configured to output a target data signal according to the first node signal when being in the working state.

[0008] In some embodiments, the data processing circuit further includes a latching module; where

[0009] the latching module is configured to receive a first sampling signal and a second sampling signal, and perform a latching process on the first sampling signal and the second sampling signal to generate the enable signal;

[0010] wherein the second sampling signal is delayed by a preset clock cycle compared with the first sampling signal, and the enable signal is valid within the preset clock cycle.

[0011] In some embodiments, the data processing circuit further includes a first sampling module and a second sampling module; where

[0012] the first sampling module is configured to receive a first enable signal and a clock signal, and perform a sampling process on the first enable signal according to the clock signal to generate the first sampling signal;

[0013] The second sampling module is configured to receive a second enable signal and the clock signal, and sample the second enable signal according to the clock signal to generate a second sampling signal.

[0014] In some embodiments, both the first enable signal and the second enable signal are command signals;

[0015] The first sampling module includes N first flip - flops. The clock terminals of the first flip - flops are all configured to receive the clock signal. The output terminal of the i - th first flip - flop is connected to the input terminal of the (i + 1)-th first flip - flop. The input terminal of the first first flip - flop is configured to receive the first enable signal, and the output terminal of the N - th first flip - flop is configured to output the first sampling signal; where i is an integer greater than 0 and less than N, and N is an integer greater than 0;

[0016] The second sampling module includes M second flip - flops. The clock terminals of the second flip - flops are all configured to receive the clock signal. The output terminal of the j - th second flip - flop is connected to the input terminal of the (j + 1)-th second flip - flop. The input terminal of the first second flip - flop is configured to receive the second enable signal, and the output terminal of the M - th second flip - flop is configured to output the second sampling signal; where j is an integer greater than 0 and less than M, and M is an integer greater than 0.

[0017] In some embodiments, the first enable signal includes a command signal, and the second enable signal includes the first sampling signal;

[0018] The first sampling module includes N first flip - flops. The clock terminals of the first flip - flops are all configured to receive the clock signal. The output terminal of the i - th first flip - flop is connected to the input terminal of the (i + 1)-th first flip - flop. The input terminal of the first first flip - flop is configured to receive the command signal, and the output terminal of the N - th first flip - flop is configured to output the first sampling signal; where i is an integer greater than 0 and less than N, and N is an integer greater than 0;

[0019] The second sampling module includes M second flip - flops. The clock terminals of the second flip - flops are all configured to receive the clock signal. The output terminal of the j - th second flip - flop is connected to the input terminal of the (j + 1)-th second flip - flop. The input terminal of the first second flip - flop is connected to the output terminal of the N - th first flip - flop and is configured to receive the first sampling signal, and the output terminal of the M - th second flip - flop is configured to output the second sampling signal; where j is an integer greater than 0 and less than M, and M is an integer greater than 0.

[0020] In some embodiments, the latching module includes a latch. A first input terminal of the latch is connected to an output terminal of the Nth first flip-flop and is configured to receive the first sampling signal. A second input terminal of the latch is connected to an output terminal of the Mth second flip-flop and is configured to receive the second sampling signal. An output terminal of the latch is configured to output the enable signal.

[0021] In some embodiments, the first power supply module includes a first switch unit. A control terminal of the first switch unit is configured to receive the enable signal. A first terminal of the first switch unit is connected to the processing module. A second terminal of the first switch unit is connected to a power supply terminal.

[0022] The first power supply module is configured to control the first switch unit to be in a conducting state when the enable signal is in an effective state, so that the processing module is in the working state; and to control the first switch unit to be in an off state when the enable signal is in a non-effective state, so that the processing module is in a non-working state.

[0023] In some embodiments, the receiving module includes a second power supply module, a first control module, and a second control module. Among them,

[0024] The second power supply module is configured to receive a clock signal and control a connection state between the power supply terminal and the first control module and the second control module according to the clock signal.

[0025] The first control module is configured to receive a first data signal, control the first data signal according to the connection state between the power supply terminal and the first control module, and generate a first sub-node signal.

[0026] The second control module is configured to receive a second data signal, control the second data signal according to the connection state between the power supply terminal and the second control module, and generate a second sub-node signal.

[0027] In some embodiments, the second power supply module includes a second switch unit. A control terminal of the second switch unit is configured to receive the clock signal. A first terminal of the second switch unit is respectively connected to the first control module and the second control module. A second terminal of the second switch unit is connected to the power supply terminal. Among them,

[0028] The second power supply module is configured to control the second switch unit to be in the on state when the clock signal is in the first level state, so that the power supply terminal is connected to the first control module and the power supply terminal is connected to the second control module; and, when the clock signal is in the second level state, control the second switch unit to be in the off state, so that the power supply terminal is not connected to the first control module and the power supply terminal is not connected to the second control module.

[0029] In some embodiments, the first control module includes a third switch unit and a fourth switch unit, and the second control module includes a fifth switch unit and a sixth switch unit; wherein,

[0030] The control terminal of the third switch unit is configured to receive the first data signal, the second terminal of the third switch unit is connected to the first terminal of the second switch unit, the control terminal of the fourth switch unit is configured to receive the clock signal, and the second terminal of the fourth switch unit is grounded; the first terminal of the third switch unit is connected to the first terminal of the fourth switch unit for outputting the first sub-node signal;

[0031] The control terminal of the fifth switch unit is configured to receive the second data signal, the second terminal of the fifth switch unit is connected to the first terminal of the second switch unit, the control terminal of the sixth switch unit is configured to receive the clock signal, and the second terminal of the sixth switch unit is grounded; the first terminal of the fifth switch unit is connected to the first terminal of the sixth switch unit for outputting the second sub-node signal.

[0032] In some embodiments, the first control module is configured to control the fourth switch unit to be in the off state when the clock signal is in the first level state, and control the fourth switch unit to be in the on state when the clock signal is in the second level state;

[0033] The second control module is configured to control the sixth switch unit to be in the off state when the clock signal is in the first level state, and control the sixth switch unit to be in the on state when the clock signal is in the second level state.

[0034] In some embodiments, the processing module includes a differential module and a cross-coupling module, wherein;

[0035] The differential module is configured to receive the first sub-node signal and the second sub-node signal, and perform differential processing on the first sub-node signal and the second sub-node signal to generate a third sub-node signal and a fourth sub-node signal;

[0036] The cross-coupling module is used to amplify the third sub-node signal and the fourth sub-node signal to generate a first output signal and a second output signal; wherein, the target data signal is composed of the first output signal and the second output signal.

[0037] In some embodiments, the differential module includes a seventh switch unit and an eighth switch unit; wherein,

[0038] The control end of the seventh switch unit is connected to the first end of the third switch unit and the first end of the fourth switch unit for receiving the first sub-node signal. The first end of the seventh switch unit is connected to the cross-coupling module for outputting the third sub-node signal, and the second end of the seventh switch unit is grounded;

[0039] The control end of the eighth switch unit is connected to the first end of the fifth switch unit and the first end of the sixth switch unit for receiving the second sub-node signal. The first end of the eighth switch unit is connected to the cross-coupling module for outputting the fourth sub-node signal, and the second end of the eighth switch unit is grounded.

[0040] In some embodiments, the cross-coupling module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; wherein,

[0041] The source electrodes of the first PMOS transistor and the second PMOS transistor are connected and connected to the first end of the first switch unit;

[0042] The drain electrodes of the first PMOS transistor and the first NMOS transistor are connected for outputting the first output signal;

[0043] The drain electrodes of the second PMOS transistor and the second NMOS transistor are connected for outputting the second output signal;

[0044] The gate electrodes of the first PMOS transistor and the first NMOS transistor are connected for receiving the second output signal;

[0045] The gate electrodes of the second PMOS transistor and the second NMOS transistor are connected for receiving the first output signal;

[0046] The source electrode of the first NMOS transistor is connected to the first end of the seventh switch unit for receiving the third sub-node signal;

[0047] The source electrode of the second NMOS transistor is connected to the first end of the eighth switch unit for receiving the fourth sub-node signal.

[0048] In some embodiments, when the enable signal is in an active state and the clock signal is in a first level state:

[0049] If the level state of the first data signal is greater than the level state of the second data signal, the first output signal is a first value and the second output signal is a second value;

[0050] If the level state of the first data signal is less than the level state of the second data signal, the first output signal is the second value and the second output signal is the first value.

[0051] In some embodiments, the data processing circuit further includes a pre-charge module; wherein,

[0052] The pre-charge module is configured to pre-charge the initial data signal output by the processing module;

[0053] The processing module is further configured to, when in a working state, amplify the signal according to the first node signal and the initial data signal, and output the target data signal.

[0054] In some embodiments, the data processing circuit further includes a compensation module; wherein,

[0055] The compensation module is configured to receive a compensation signal and determine a target compensation signal according to the compensation signal, wherein the target compensation signal is used to reduce the current mismatch of the processing module;

[0056] The processing module is specifically configured to, when in a working state, output the target data signal according to the target compensation signal and the first node signal.

[0057] In a second aspect, an embodiment of the present disclosure provides a data processing method, which is applied to a data processing circuit. The data processing circuit includes a receiving module, a first power supply module, and a processing module. The method includes:

[0058] Receiving a data signal through the receiving module and determining a first node signal according to the data signal;

[0059] Receiving an enable signal through the first power supply module and controlling the processing module to be in a working state when the enable signal is in an active state;

[0060] Outputting a target data signal through the processing module when in a working state according to the first node signal.

[0061] In a third aspect, an embodiment of the present disclosure provides a semiconductor memory, including the data processing circuit according to any one of the first aspect.

[0062] Embodiments of the present disclosure provide a data processing circuit, a method, and a semiconductor memory. The data processing circuit includes a receiving module, a first power supply module, and a processing module. Among them, the receiving module is configured to receive a data signal and determine a first node signal according to the data signal; the first power supply module is configured to receive an enable signal and control the processing module to be in a working state when the enable signal is in an effective state; the processing module is configured to output a target data signal according to the first node signal when it is in a working state. In this way, the first power supply module controls the working state of the processing module through the enable signal, so that the processing module is in a working state only when the enable signal is in an effective state, and when the enable signal is in a non-effective state, that is, when entering the standby mode, the processing module is in a non-working state, thereby effectively reducing the leakage current of the data processing circuit in the standby mode and saving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 Schematic diagram of the composition structure of a data processing circuit provided by an embodiment of the present disclosure Figure 1 ;

[0064] Figure 2 Schematic diagram of the composition structure of a data processing circuit provided by an embodiment of the present disclosure Figure 2 ;

[0065] Figure 3 Schematic diagram of the composition structure of an SR latch provided by an embodiment of the present disclosure;

[0066] Figure 4 Schematic diagram of a signal timing provided by an embodiment of the present disclosure Figure 1 ;

[0067] Figure 5 Partial structure schematic diagram of a data processing circuit provided by an embodiment of the present disclosure Figure 1 ;

[0068] Figure 6 Partial structure schematic diagram of a data processing circuit provided by an embodiment of the present disclosure Figure 2 ;

[0069] Figure 7 Specific structure schematic diagram of a data processing circuit provided by an embodiment of the present disclosure Figure 1 ;

[0070] Figure 8 Schematic diagram of a signal timing provided by an embodiment of the present disclosure Figure 2 ;

[0071] Figure 9 Specific structure schematic diagram of a data processing circuit provided by an embodiment of the present disclosure Figure 2 ;

[0072] Figure 10 Schematic flowchart of a data processing method provided by an embodiment of the present disclosure;

[0073] Figure 11 Schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0074] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related disclosure, rather than limiting the disclosure. Additionally, it should be noted that for the sake of description, only the parts related to the relevant disclosure are shown in the drawings.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0076] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0077] It should be noted that the terms "first / second / third" related to the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0078] In data processing circuits such as a data receiver, the leakage current of the data processing circuit in the standby mode is very large, especially when low-threshold voltage devices are used for speed, this kind of leakage is particularly obvious, which will lead to excessive power consumption of the circuit and may damage the circuit. Therefore, how to effectively reduce the power consumption of the memory has become the key to designing the memory.

[0079] An embodiment of the present disclosure provides a data processing circuit, including a receiving module, a first power supply module, and a processing module. Among them, the receiving module is configured to receive a data signal and determine a first node signal according to the data signal; the first power supply module is configured to receive an enable signal and control the processing module to be in an operating state when the enable signal is in an effective state; the processing module is configured to output a target data signal according to the first node signal when it is in an operating state. In this way, the first power supply module controls the operating state of the processing module through the enable signal, so that the processing module is only in an operating state when the enable signal is in an effective state, and when the enable signal is in an ineffective state and enters the standby mode, the processing module is in a non-operating state, thereby effectively reducing the leakage current of the data processing circuit in the standby mode and saving power consumption.

[0080] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0081] In an embodiment of the present disclosure, refer to Figure 1 , which shows a schematic structural composition of a data processing circuit 10 provided by an embodiment of the present disclosure Figure 1 . As Figure 1 shown, the data processing circuit 10 may include a receiving module 11, a first power supply module 12, and a processing module 13. Among them,

[0082] The receiving module 11 is configured to receive a data signal and determine a first node signal according to the data signal;

[0083] The first power supply module 12 is configured to receive an enable signal and control the processing module 13 to be in an operating state when the enable signal is in an effective state;

[0084] The processing module 13 is configured to output a target data signal according to the first node signal when it is in an operating state.

[0085] It should be noted that the data processing circuit 10 provided by the embodiment of the present disclosure can be used as a part of a read circuit, an amplification circuit, a comparator, a data receiver, or a Decision Feedback Equalizer (DFE) circuit in a memory, etc., and can implement functions such as data reading, data amplification, or data comparison.

[0086] It should also be noted that the receiving module 11 is mainly used to receive a data signal, and the data signal represents a signal to be processed by the data processing circuit 10. In the embodiment of the present disclosure, the connection between the receiving module 11 and the processing module 13 is marked as the first node, then the receiving module 11 can determine the first node signal at the first node according to the data signal.

[0087] The first power supply module 12 is mainly used to implement the state control of the processing module 13, and control the processing module 13 to be in the working state or the non-working state based on the enable signal. Specifically, the first power supply module 12 first receives the enable signal. When the enable signal is in the valid state, it controls the processing module 13 to be in the working state. At this time, the processing module 13 will output the target data signal according to the first node signal; when the enable signal is in the non-valid state, the first power supply module 12 controls the processing module 13 to be in the non-working state. At this time, the processing module 13 does not work and no leakage current will be generated.

[0088] In this way, by controlling the state of the processing module 13 through the first power supply module 12, the processing module 13 is only in the working state when the enable signal is in the valid state, so that the leakage current generated by the processing module 13 can be reduced, and the power consumption of the data processing circuit 10 in the standby state can be saved.

[0089] For the generation of the enable signal, refer to Figure 2 , which shows the schematic composition structure of a data processing circuit 10 provided by an embodiment of the present disclosure Figure 2 . As Figure 2 shown, in some embodiments, the data processing circuit 10 may further include a latch module 14; wherein,

[0090] The latch module 14 is used to receive the first sampling signal and the second sampling signal, and perform latch processing on the first sampling signal and the second sampling signal to generate an enable signal;

[0091] wherein, the second sampling signal is delayed by a preset clock period compared with the first sampling signal, and the enable signal is valid within the preset clock period.

[0092] It should be noted that the latch module 14 is connected to the first power supply module 12 and is used to provide an enable signal for the first power supply module 12. Specifically, the latch module 14 receives the first sampling signal and the second sampling signal, generates an enable signal after latch processing, and sends the enable signal to the first power supply module 12. Here, the second sampling signal is delayed by a preset clock period compared with the first sampling signal, and within the preset clock period, the enable signal is in the valid state.

[0093] It should also be noted that in the embodiment of the present disclosure, the latch module 14 may be specifically implemented by a Set-Reset (SR) latch. The SR latch is a bistable flip-flop. If there is no external trigger signal acting on it, it will remain in its original state unchanged. Under the action of an external trigger signal, the output state may change, that is, the output state of the SR latch is directly controlled by the input signal.

[0094] Exemplarily, refer to Figure 3, which shows a schematic structural diagram of an SR latch provided by an embodiment of the present disclosure. As Figure 3 shown, the SR latch is composed of two NOR gates. Among them, the two input terminals of the first NOR gate NOR_1 respectively receive the first sampling signal and the output signal Q' of the second NOR gate NOR_2, and the output signal of the first NOR gate NOR_1 is Q; the two input terminals of the second NOR gate NOR_2 respectively receive the second sampling signal and the output signal Q of the first NOR gate NOR_1. In the embodiment of the present disclosure, the enable signal can be the output signal Q of the first NOR gate NOR_1, or can also be the output signal Q' of the second NOR gate NOR_2, which is specifically determined in combination with the actual circuit structure.

[0095] Exemplarily, referring to Figure 4 , which shows a schematic signal timing diagram provided by an embodiment of the present disclosure. As Figure 4 shown, the second sampling signal is delayed by a preset clock period T compared to the first sampling signal, and the enable signal can be Q or Q'. If the enable signal is a high-level effective signal, then Q is determined as the enable signal. At this time, the output terminal of the first NOR gate NOR_1 is connected to the first power supply module 12; if the enable signal is a low-level effective signal, then Q' is determined as the enable signal. At this time, the output terminal of the second NOR gate NOR_2 is connected to the first power supply module 12.

[0096] In this way, since the enable signal is only valid within the preset clock period, that is, within the preset clock period, the processing module 13 is in the working state, and outside the preset clock period, the processing module 13 is in the non-working state, thereby reducing the generation of leakage current.

[0097] Furthermore, as Figure 2 shown, in some embodiments, the data processing circuit 10 may further include a first sampling module 15 and a second sampling module 16; among them,

[0098] The first sampling module 15 is configured to receive the first enable signal and the clock signal, and sample the first enable signal according to the clock signal to generate a first sampling signal;

[0099] The second sampling module 16 is configured to receive the second enable signal and the clock signal, and sample the second enable signal according to the clock signal to generate a second sampling signal.

[0100] It should be noted that the first sampling signal can be obtained by the first sampling module 15 sampling the first enable signal, and the second sampling signal can be obtained by the second sampling module 16 sampling the second enable signal. Among them, both the first sampling module 15 and the second sampling module 16 can be composed of several flip-flops.

[0101] It should also be noted that the enabling signal can be generated based on a command signal, and the command signal is a signal related to the operations performed by the data processing circuit 10. For example, when the data processing circuit 10 serves as part of a data receiving circuit in a memory, the command signal can be a read signal.

[0102] Exemplarily, the first enabling signal and the second enabling signal can both be command signals. In the first sampling module 15 and the second sampling module 16, the command signals are respectively sampled and delayed to different extents through different numbers of flip-flops to obtain the first sampling signal and the second sampling signal.

[0103] See Figure 5 , which shows a schematic diagram of a partial circuit structure of a data processing circuit 10 provided by an embodiment of the present disclosure. As Figure 5 shown, in a specific embodiment, the first sampling module 15 includes N first flip-flops 151. The clock terminals of the first flip-flops 151 are all used to receive a clock signal. The output terminal of the i-th first flip-flop 151 is connected to the input terminal of the (i + 1)-th first flip-flop 151, and the input terminal of the first first flip-flop 151 is used to receive the first enabling signal, and the output terminal of the N-th first flip-flop 151 is used to output the first sampling signal; where i is an integer greater than 0 and less than N, and N is an integer greater than 0;

[0104] The second sampling module 16 includes M second flip-flops 161. The clock terminals of the second flip-flops 161 are all used to receive a clock signal. The output terminal of the j-th second flip-flop 161 is connected to the input terminal of the (j + 1)-th second flip-flop 161, and the input terminal of the first second flip-flop 161 is used to receive the second enabling signal, and the output terminal of the M-th second flip-flop 161 is used to output the second sampling signal; where j is an integer greater than 0 and less than M, and M is an integer greater than 0.

[0105] It should be noted that, as Figure 5 shown, both the first sampling module 15 and the second sampling module 16 can include several flip-flops. For the sake of easy distinction, the flip-flops included in the first sampling module 15 are denoted as the first flip-flops 151, and the flip-flops included in the second sampling module 16 are denoted as the second flip-flops 161. Among them, the first flip-flops 151 and the second flip-flops 161 can be of the same type of flip-flop. For example, the first flip-flops 151 and the second flip-flops 161 can both be data flip-flops (Data Flip-Flop flip-flops, D flip-flops, or CMOS flip-flops).

[0106] As Figure 5 shown, each of the first flip-flops 151 and the second flip-flops 161 includes an input terminal ( Figure 5 shown as D inFigure 5 as shown in Q, and the clock terminal ( Figure 5 as shown); among them, the clock terminals of the first flip-flop 151 and the second flip-flop 161 are both used to receive the clock signal. In the first sampling module 15, N first flip-flops 151 are connected in series. The input terminal of the first first flip-flop 151 is used to receive the first enable signal, the output terminal of the Nth first flip-flop 151 is used to output the first sampling signal, and the input terminals of the second to the Nth first flip-flops 151 are all connected to the output terminal of the previous first flip-flop 151. In this way, each first flip-flop 151 samples the signal received at its input terminal based on the clock signal, delays and latches the signal until the Nth first flip-flop 151 outputs the first sampling signal.

[0107] In the second sampling module 16, M second flip-flops 161 are connected in series. The input terminal of the first second flip-flop 161 is used to receive the second enable signal, the output terminal of the Mth second flip-flop 161 is used to output the second sampling signal, and the input terminals of the second to the Mth second flip-flops 161 are all connected to the output terminal of the previous second flip-flop 161. Among them, N and M can be the same or different. In this way, each second flip-flop 161 samples the signal received at its input terminal based on the clock signal, delays and latches the signal until the Mth second flip-flop 161 outputs the second sampling signal.

[0108] Among them, as described above, the first enable signal and the second enable signal can both be command signals, and the number of the first flip-flop 151 and the second flip-flop 161 can be set in combination with a preset clock cycle, so that the second sampling signal is delayed by the preset clock cycle compared with the first sampling signal.

[0109] Further, in some embodiments, the first enable signal includes a command signal, and the second enable signal includes the first sampling signal. At this time, referring to Figure 6 which shows a partial circuit structure schematic diagram of a data processing circuit 10 provided by an embodiment of the present disclosure Figure 2 as Figure 6 shown, the first sampling module 15 includes N first flip-flops 151. The clock terminals of the first flip-flops 151 are all used to receive the clock signal. The output terminal of the ith first flip-flop 151 is connected to the input terminal of the (i + 1)th first flip-flop 151, and the input terminal of the first first flip-flop 151 is used to receive the command signal, and the output terminal of the Nth first flip-flop 151 is used to output the first sampling signal; where i is an integer greater than 0 and less than N, and N is an integer greater than 0;

[0110] The second sampling module 16 includes M second flip-flops 161. The clock terminals of the second flip-flops 161 are all used to receive a clock signal. The output terminal of the j-th second flip-flop 161 is connected to the input terminal of the (j + 1)-th second flip-flop 161, and the input terminal of the first second flip-flop 161 is connected to the output terminal of the N-th first flip-flop 161 for receiving a first sampling signal. The output terminal of the M-th second flip-flop 161 is used to output a second sampling signal. Wherein, j is an integer greater than 0 and less than M, and M is an integer greater than 0.

[0111] It should be noted that, as Figure 6 shown, the difference from Figure 5 is that Figure 6 the output terminal of the N-th first flip-flop 151 in

[0112] is not only connected to the latching module 14, but also connected to the input terminal of the first second flip-flop 161. That is, in the embodiments of the present disclosure, the first sampling module 15 and the second sampling module 16 can be connected in series. At this time, the first enable signal can be a command signal, and the second enable signal can be a first sampling signal. That is to say, the second sampling signal can be obtained by sampling and delaying the first sampling signal. Figure 5 or Figure 6 shown, the latching module 14 may include a latch. The first input terminal of the latch is connected to the output terminal of the N-th first flip-flop 151 for receiving a first sampling signal. The second input terminal of the latch is connected to the output terminal of the M-th second flip-flop 161 for receiving a second sampling signal. The output terminal of the latch is used to output an enable signal.

[0113] It should be noted that in Figure 5 or Figure 6 in the latching module 14, the first input terminal of the latch, which is an input terminal of the first NOR gate NOR_1, is connected to the output terminal of the N-th first flip-flop 151 for receiving a first sampling signal. The second input terminal of the latch, which is an input terminal of the second NOR gate NOR_2, is connected to the output terminal of the M-th second flip-flop 161 for receiving a second sampling signal. The output terminal of the latch is used to output an enable signal Q or Q'.

[0114] Furthermore, for the first power supply module 12, referring to Figure 7 , it shows a specific structural schematic diagram of a data processing circuit 10 provided by the embodiments of the present disclosure Figure 1 . As Figure 7 shown, in some embodiments, the first power supply module 12 includes a first switch unit P1. The control terminal of the first switch unit P1 is used to receive an enable signal. The first terminal of the first switch unit P1 is connected to the processing module 13. The second terminal of the first switch unit P1 is connected to a power supply terminal;

[0115] The first power supply module 12 is configured to control the first switching unit P1 to be in a conducting state when the enable signal is in an active state, so that the processing module 13 is in an operating state; and to control the first switching unit P1 to be in a disconnected state when the enable signal is in an inactive state, so that the processing module 13 is in a non-operating state.

[0116] It should be noted that, as Figure 7 shown, the state control of the processing module 13 by the first power supply module 12 can be implemented through the first switching unit P1. Among them, the first switching unit P1 can be a diode, a triode, a P-channel metal oxide semiconductor field effect transistor (P-type channel Metal Oxide Semiconductor, PMOS transistor), or an N-channel metal oxide semiconductor field effect transistor (N-type channel Metal Oxide Semiconductor, NMOS transistor), etc., which are devices with switching control functions. Here, taking the first switching unit P1 as a PMOS transistor as an example, the specific implementation of the embodiments of the present disclosure will be described in detail.

[0117] Among them, the control terminal of the first switching unit P1 is the gate, the first terminal of the first switching unit P1 can be the drain, and the second terminal of the first switching unit P1 can be the source. Since the PMOS transistor has the characteristic of conducting at a low level and disconnecting at a high level, for the first switching unit P1, the active state of the enable signal is a low level state. That is, in this case, the enable signal is Figure 4 Q' in. In this way, when the enable signal is in a low level state, the first switching unit P1 conducts, and the processing module 13 is in an operating state; when the enable signal is in a high level state, the first switching unit P1 disconnects, and the processing module 13 is in a non-operating state. Thus, the processing module 13 only operates during the effective period of the enable signal, avoiding the generation of leakage current in the processing module 13 during the non-operating period and saving the power consumption of the circuit.

[0118] Furthermore, for the receiving module 11, referring to Figure 7 , in some embodiments, the receiving module 11 includes a second power supply module 111, a first control module 112, and a second control module 113; among them,

[0119] The second power supply module 111 is configured to receive a clock signal and control the connection state between the power supply terminal and the first control module 112 and the second control module 113 according to the clock signal;

[0120] The first control module 112 is configured to receive a first data signal, control the first data signal according to the connection state between the power supply terminal and the first control module 112, and generate a first sub-node signal;

[0121] The second control module 113 is configured to receive the second data signal, control the second data signal according to the connection state between the power supply end and the second control module 113 , and generate a second sub-node signal.

[0122] It should be noted that the receiving module 11 not only receives data signals, but also receives clock signals, and the clock signals are used to control the charging state and discharging state of the first node. Figure 7 As shown, the second power supply module 111 controls the connection state between the power supply terminal and the first control module 112, and the connection state between the power supply terminal and the second control module 113 according to the received clock signal. Here, the connection state may include connecting the first control module 112 and the second control module 113 to the power supply terminal or disconnecting the first control module 112 and the second control module 113 from the power supply terminal.

[0123] It should also be noted that in the embodiments of the present disclosure, the data signal may include a first data signal and a second data signal. The first control module 112 receives the first data signal, and the second control module 113 receives the second data signal. Since both the first control module 112 and the second control module 113 are connected to the processing module 13, the first node specifically includes two nodes. The connection between the first control module 112 and the processing module 13 is denoted as the first child node stg1n, and the connection between the second control module 113 and the processing module 13 is denoted as the second child node stg1p.

[0124] The first control module 112 generates a first sub-node signal at the first sub-node stg1n according to the first data signal and the connection status between the first control module 112 and the power supply terminal; similarly, the second control module 113 generates a second sub-node signal at the second sub-node stg1p according to the second data signal and the connection status between the second control module 113 and the power supply terminal.

[0125] Furthermore, for the control of the connection status between the power supply terminal and the first control module 112 and the second control module 113, as shown in FIG. Figure 7 As shown, in some embodiments, the second power supply module 111 includes a second switch unit P2, the control end of the second switch unit P2 is used to receive the clock signal, the first end of the second switch unit P2 is connected to the first control module 112 and the second control module 113 respectively, and the second end of the second switch unit P2 is connected to the power end; wherein,

[0126] The second power supply module 111 is configured to control the second switch unit P2 to be in a conducting state when the clock signal is in the first level state, so that the power supply terminal is connected to the first control module 112 and the power supply terminal is connected to the second control module 113; and, when the clock signal is in the second level state, control the second switch unit P2 to be in an off state, so that the power supply terminal is not connected to the first control module 112 and the power supply terminal is not connected to the second control module 113.

[0127] It should be noted that the second power supply module 111 can be implemented through the second switch unit P2. Among them, the second switch unit P2 can be a device with a switching control function such as a diode, a triode, or a field effect transistor. Here, taking the second switch unit P2 as a PMOS transistor as an example, the specific implementation of the embodiments of the present disclosure will be described in detail.

[0128] It should also be noted that the control terminal of the second switch unit P2, that is, the gate, is used to receive the clock signal. Corresponding to different level states of the clock signal, the second switch unit P2 can be turned on or off. The second terminal of the second switch unit P2 can be the source electrode and is connected to the power supply terminal. The first terminal of the second switch unit P2 can be the drain electrode and is respectively connected to the first control module 112 and the second control module 113; when the clock signal is in the first level state, the second switch unit P2 is turned on, so that the first control module 112 and the second control module 113 can be connected to the power supply terminal; since the second switch unit P2 is a PMOS transistor, the first level state represents a low level state. When the clock signal is in the second level state, the second switch unit P2 is turned off, and the first control module 112 and the second control module 113 are not connected to the power supply terminal; since the second switch unit P2 is a PMOS transistor, the second level state represents a high level state.

[0129] Furthermore, for the first control module 112 and the second control module 113, see Figure 7 , in some embodiments, the first control module 112 includes a third switch unit P3 and a fourth switch unit N4, and the second control module 113 includes a fifth switch unit P5 and a sixth switch unit N6; among them,

[0130] The control terminal of the third switch unit P3 is used to receive the first data signal. The second terminal of the third switch unit P3 is connected to the first terminal of the second switch unit P2. The control terminal of the fourth switch unit N4 is used to receive the clock signal. The second terminal of the fourth switch unit N4 is grounded; the first terminal of the third switch unit P3 is connected to the first terminal of the fourth switch unit N4 for outputting a first sub-node signal;

[0131] The control terminal of the fifth switching unit P5 is used to receive the second data signal. The second terminal of the fifth switching unit P5 is connected to the first terminal of the second switching unit P2. The control terminal of the sixth switching unit N6 is used to receive the clock signal, and the second terminal of the sixth switching unit N6 is grounded. The first terminal of the fifth switching unit P5 is connected to the first terminal of the sixth switching unit N6 and is used to output the second sub-node signal.

[0132] It should be noted that taking the third switching unit P3 and the fifth switching unit P5 as PMOS transistors, and the fourth switching unit N4 and the sixth switching unit N6 as NMOS transistors as an example, in the first control module 112 and the second control module 113, the control terminals of the third switching unit P3, the fourth switching unit N4, the fifth switching unit N5, and the sixth switching unit N6 all represent the gates, the first terminals all represent the drains, and the second terminals all represent the sources.

[0133] In the first control module 112, the gate of the third switching unit P3 receives the first data signal, the gate of the fourth switching unit N4 receives the clock signal, the first terminals of the third switching unit P3 and the fourth switching unit N4 are connected to the first sub-node stg1n, and the first sub-node signal is output at the first sub-node stg1n.

[0134] In the second control module 113, the gate of the fifth switching unit P5 receives the second data signal, the gate of the sixth switching unit N6 receives the clock signal, the first terminals of the fifth switching unit P5 and the sixth switching unit N6 are connected to the second sub-node stg1p, and the second sub-node signal is output at the second sub-node stg1p.

[0135] Furthermore, in some embodiments, the first control module 112 is configured to control the fourth switching unit N4 to be in an off state when the clock signal is in the first level state, and to control the fourth switching unit N4 to be in an on state when the clock signal is in the second level state;

[0136] The second control module 113 is configured to control the sixth switching unit N6 to be in an off state when the clock signal is in the first level state, and to control the sixth switching unit N6 to be in an on state when the clock signal is in the second level state.

[0137] It should be noted that the fourth switching unit N4 and the sixth switching unit N6 can both be NMOS transistors. In this case, the first level state represents the low level state, and the second level state represents the high level state; that is, when the clock signal is in the first level state, the gates of the fourth switching unit N4 and the sixth switching unit N6 receive the low-level clock signal and are in the off state, and when the clock signal is in the second level state, the gates of the fourth switching unit N4 and the sixth switching unit N6 receive the high-level clock signal and are in the on state.

[0138] It should also be noted that in the receiving module 11, if the clock signal is in the low level state, the second switching unit P2 is in the conducting state. At this time, the first end of the second switching unit P2 is clamped to the power supply voltage (equivalent to the high level state), the first control module 112 is in the connected state with the power supply terminal, and the second control module 113 is also in the connected state with the power supply terminal, that is: the first ends of the third switching unit P3 and the fifth switching unit P5 are connected to the power supply terminal through the second switching unit P2 and are both pulled up to the power supply voltage. At the same time, the fourth switching unit N4 and the sixth switching unit N6 are both in the off state.

[0139] In the case where the clock signal is in the low level state, for the first control module 112, if the first data signal is a data signal in the high level state, the third switching unit P3 is not conducting (or the conduction degree is very low). Since both the third switching unit P3 and the fourth switching unit N4 are not conducting, the first sub-node signal is neither the power supply voltage (high level state) nor the ground voltage (low level state); if the first data signal is a data signal in the low level state, the third switching unit P3 conducts, and the first end of the third switching unit P3 is clamped to the power supply voltage, so that the first sub-node signal is in the high level state. For the second control module 113, if the second data signal is a data signal in the high level state, the fifth switching unit P5 is not conducting (or the conduction degree is very low). Since both the fifth switching unit P5 and the sixth switching unit N6 are not conducting, the second sub-node signal is neither the power supply voltage (high level state) nor the ground voltage (low level state); if the second data signal is a data signal in the low level state, the fifth switching unit P5 conducts, and the first end of the fifth switching unit P5 is clamped to the power supply voltage, so that the second sub-node signal is in the high level state. At this time, the first sub-node stg1n and / or the second sub-node stg1p is in the charging state, that is, charged until the node level gradually becomes the power supply voltage.

[0140] When the clock signal is at a high level, since the second switching unit P2 is in an open state, both the first control module 112 and the second control module 113 are in a non-connected state with the power supply terminal. At this time, regardless of the level state of the first data signal and the second data signal, the third switching unit P3 and the fifth switching unit P5 are not conducting. Therefore, neither the first sub-node signal nor the second sub-node signal is at a high level state. At the same time, the fourth switching unit N4 and the sixth switching unit N6 are both in a conducting state. Since the second ends of the fourth switching unit N4 and the sixth switching unit N6 are both grounded, the first ends of the fourth switching unit N4 and the sixth switching unit N6 are both clamped to the ground voltage (equivalent to a low level state), and both the first sub-node signal and the second sub-node signal are in a low level state. At this time, both the first sub-node stg1n and the second sub-node stg1p are in a discharging state, that is, discharging until the node level gradually becomes the ground voltage.

[0141] It should also be noted that in practical applications, the first data signal and the second data signal are usually a pair of differential signals, and they generally do not both be at a high level state or both be at a low level state at the same time, but are in a relatively high and low level state. The first control module 112 obtains the first sub-node signal according to the first data signal, and the second control module 113 obtains the second sub-node signal according to the second data signal. The first sub-node signal and the second sub-node signal can also be regarded as a pair of differential signals.

[0142] For the processing module 13, refer to Figure 7 , in some embodiments, the processing module 13 includes a differential module 131 and a cross-coupling module 132, where;

[0143] The differential module 131 is configured to receive the first sub-node signal and the second sub-node signal, and perform differential processing on the first sub-node signal and the second sub-node signal to generate a third sub-node signal and a fourth sub-node signal;

[0144] The cross-coupling module 132 is configured to perform amplification processing on the third sub-node signal and the fourth sub-node signal to generate a first output signal and a second output signal; wherein, the target data signal is composed of the first output signal and the second output signal.

[0145] It should be noted that when the enable signal is in an active state, the processing module 13 is in a working state. The processing module 13 includes a differential module 131 and a cross-coupling module 132. Among them, the differential module 131 receives a first sub-node signal and a second sub-node signal respectively. After being processed by the differential module 131, a third sub-node signal and a fourth sub-node signal are obtained and sent to the cross-coupling module 132. The cross-coupling module 132 amplifies the third sub-node signal and the fourth sub-node signal to generate a target data signal, and the target data signal specifically includes a first output signal and a second output signal.

[0146] In the embodiments of the present disclosure, as Figure 7 shown, the differential module 131 is also used to discharge the leakage currents IL1 and IL2 generated by the cross-coupling module 132.

[0147] Furthermore, for the differential module 131, referring to Figure 7 , in some embodiments, the differential module 131 includes a seventh switch unit N7 and an eighth switch unit N8; among them,

[0148] The control end of the seventh switch unit N7 is connected to the first end of the third switch unit P3 and the first end of the fourth switch unit N4, and is used to receive the first sub-node signal. The first end of the seventh switch unit N7 is connected to the cross-coupling module 132 and is used to output the third sub-node signal. The second end of the seventh switch unit N7 is grounded;

[0149] The control end of the eighth switch unit N8 is connected to the first end of the fifth switch unit P5 and the first end of the sixth switch unit N6, and is used to receive the second sub-node signal. The first end of the eighth switch unit N8 is connected to the cross-coupling module 132 and is used to output the fourth sub-node signal. The second end of the eighth switch unit N8 is grounded.

[0150] It should be noted that taking the seventh switch unit N7 and the eighth switch unit N8 as NMOS transistors as an example, the control ends of the seventh switch unit N7 and the eighth switch unit N8 are both gates, the first ends of the seventh switch unit N7 and the eighth switch unit N8 can both be drains, and the second ends of the seventh switch unit N7 and the eighth switch unit N8 can both be sources.

[0151] Among them, the gate of the seventh switch unit N7, the first end of the third switch unit P3, and the first end of the fourth switch unit N4 are connected to the first sub-node stg1n, and the first end of the seventh switch unit N7 and the cross-coupling module 132 are connected to the third sub-node stg-2n; the gate of the eighth switch unit N8, the first end of the fifth switch unit P5, and the first end of the sixth switch unit N6 are connected to the second sub-node stg1p, and the eighth switch unit N8 and the cross-coupling module 132 are connected to the fourth sub-node stg2p.

[0152] It should also be noted that the gate of the seventh switching unit N7 receives the first sub-node signal, and the gate of the eighth switching unit N8 receives the second sub-node signal. The first sub-node signal and the third sub-node signal can be regarded as a pair of differential signals. The NMOS transistor conducts when a high-level signal is received at the gate. Since the second ends of both the seventh switching unit N7 and the eighth switching unit N8 are grounded, when the seventh switching unit N7 conducts, the level at the first end of the seventh switching unit N7 can be pulled down to the ground voltage. Similarly, when the eighth switching unit N8 conducts, the level at the first end of the eighth switching unit N8 can be pulled down to the ground voltage. At this time, for the seventh switching unit N7 and the eighth switching unit N8, the switching unit with a higher gate signal level can pull its first end to the ground voltage faster, and send the third sub-node signal and the fourth sub-node signal corresponding to the first end to the cross-coupling module 132. At the same time, the seventh switching unit N7 and the eighth switching unit N8 discharge the leakage currents IL1 and IL2 generated by the cross-coupling module 132 to the ground.

[0153] Furthermore, for the cross-coupling module 132, refer to Figure 7 , in some embodiments, the cross-coupling module 132 includes a first PMOS transistor P01, a second PMOS transistor P02, a first NMOS transistor N01, and a second NMOS transistor N02; where

[0154] The source of the first PMOS transistor P01 and the source of the second PMOS transistor P02 are connected and connected to the first end of the first switching unit P1;

[0155] The drain of the first PMOS transistor P01 and the drain of the first NMOS transistor N01 are connected to output a first output signal;

[0156] The drain of the second PMOS transistor P02 and the drain of the second NMOS transistor N02 are connected to output a second output signal;

[0157] The gate of the first PMOS transistor P01 and the gate of the first NMOS transistor N01 are connected to receive the second output signal;

[0158] The gate of the second PMOS transistor P02 and the gate of the second NMOS transistor N02 are connected to receive the first output signal;

[0159] The source of the first NMOS transistor N01 is connected to the first end of the seventh switching unit N7 to receive the third sub-node signal;

[0160] The source of the second NMOS transistor N02 is connected to the first end of the eighth switching unit N8 to receive the fourth sub-node signal.

[0161] It should be noted that the cross-coupling module 132 is composed of a pair of NMOS transistors and a pair of PMOS transistors. Here, the first ends of the first NMOS transistor N01, the second NMOS transistor N02, the first PMOS transistor P01, and the second PMOS transistor P02 all represent the source electrodes, and the second ends of the first NMOS transistor N01, the second NMOS transistor N02, the first PMOS transistor P01, and the second PMOS transistor P02 all represent the drain electrodes.

[0162] It should also be noted that in some embodiments, the data processing circuit 10 may further include a pre-charge module; wherein,

[0163] The pre-charge module is used to pre-charge the initial data signal output by the processing module 13;

[0164] The processing module 13 is further used to, when in the working state, amplify the signal according to the first node signal and the initial data signal, and output a target data signal.

[0165] It should be noted that the processing module 13 is used to amplify the slight difference between signals and finally output a pair of inverted output signals, and this pair of inverted output signals is the target data signal. Before amplifying the signal, it is also necessary to pre-charge the output signal of the processing module 13 (at this time, the data signal has not been processed yet, and the output signal of the processing module 13 at this time is called the initial data signal); this can be done through a pre-charge module (not shown in the figure), and the initial data signal at the output end of the processing module 13 is pre-charged to a preset voltage value, for example, pre-charged to VDD / 2.

[0166] It should also be noted that the initial data signal includes a first initial data signal and a second initial data signal. After pre-charging, the gate signals of the second PMOS transistor P02 and the second NMOS transistor N02 are both the first initial data signal, and the gate signals of the first PMOS transistor P01 and the first NMOS transistor M01 are both the second initial data signal. The voltages of the first initial data signal and the second initial data signal can both be VDD / 2 (VDD represents the power supply voltage). The sources of the first PMOS transistor P01 and the second PMOS transistor P02 are connected and connected to the drain of the first switching unit P1, that is, the sources of the first PMOS transistor P01 and the second PMOS transistor P02 are both connected to the power supply terminal. The source of the first NMOS transistor N01 is connected to the first end of the seventh switching unit N7 at the third sub-node stg2n, and the source of the second NMOS transistor N02 is connected to the first end of the eighth switching unit N8 at the fourth sub-node stg2p. When the processing module 13 is in the working state, the gate of the seventh switching unit N7 receives a first sub-node signal generated by being controlled by the first data signal, and the gate of the eighth switching unit N8 receives a second sub-node signal generated by being controlled by the second data signal. Since the first sub-node signal and the second sub-node signal are a pair of differential signals and there is a potential difference between them, the conduction speeds of the seventh switching unit N7 and the eighth switching unit N8 are different.

[0167] Exemplarily, since pre-charging has been performed, the gate signals of the first NMOS transistor N01, the second NMOS transistor N02, the first PMOS transistor P01, and the second PMOS transistor P02 are all VDD / 2. Then, all four transistors are in a very low conduction state. If the level state of the first data signal is lower than that of the second data signal, the level state of the first sub-node signal is higher than that of the second sub-node signal. Then, the seventh switching unit N7 will conduct faster than the eighth switching unit N8, thereby pulling down the third sub-node signal to a low level state faster until it reaches the ground voltage. As a result, the drain of the first NMOS transistor NO1 is pulled down faster until it reaches the ground voltage. The gate signal of the second PMOS transistor P02 is the drain signal of the first NMOS transistor NO1, that is, the gate signal of the second PMOS transistor is closer to the ground voltage. Compared with VDD / 2 after pre-charging, it can increase the conduction degree of the second PMOS transistor P02. At the same time, the source of the second PMOS transistor P02 is connected to the power supply terminal, so the drain of the second PMOS transistor P02 will also be closer to the power supply voltage to a greater extent; the drain signal of the second PMOS transistor P02 is the gate signal of the first NMOS transistor N01, that is, the gate signal of the first NMOS transistor N01 is closer to the power supply voltage. Compared with VDD / 2 after pre-charging, it can increase the conduction degree of the first NMOS transistor N01, making the drain of the first NMOS transistor N01 closer to the ground voltage to a greater extent. In this way, through the coupling and amplification of the cross-coupling module 132, finally, a stable low-level first output signal and a stable high-level second output signal can be obtained, realizing the amplified output of the differential signal.

[0168] It should also be noted that when the data processing circuit 10 is used as a data reading circuit, the first data signal can represent the signal to be read, the second data signal can represent the reference signal, and the level state of the reference signal can always be VDD / 2. If the first data signal is in a low level state, that is, the level state of the first data signal is lower than that of the second data signal, the first sub-node signal is higher than the second sub-node signal, and finally the first output signal is in a low level state, while the second data signal is in a high level state; if the first data signal is in a high level state, that is, the level state of the first data signal is higher than that of the second data signal, the first sub-node signal is lower than the second sub-node signal, and finally the first output signal is in a high level state, while the second data signal is in a low level state. Thus, the difference between the differential signals is further amplified and output, that is, "a relatively high level state is output as a high level, and a relatively low level state is output as a low level".

[0169] Exemplarily, refer to Figure 8 , which shows a signal timing diagram provided by an embodiment of the present disclosure Figure 2 . In Figure 8The timing diagrams of the clock signal, read command signal, read-out data DQ, and enable signal are respectively shown.

[0170] It should be noted that Figure 8 the shown signal timing diagram corresponds to the command signal being the read command signal, and the circuit for generating the enable signal is Figure 6 . As Figure 8 shown, within the preset clock cycle T, the processing module 13 only operates, and is in a non-operating state at other times. Among them, DQ is equivalent to the first data signal, and finally it can be amplified into the first output signal for output.

[0171] Combined with the foregoing analysis, in some embodiments, when the enable signal is in an effective state and the clock signal is in the first level state:

[0172] If the level state of the first data signal is greater than the level state of the second data signal, the first output data is the first value, and the second output data is the second value;

[0173] If the level state of the first data signal is less than the level state of the second data signal, the first output data is the second value, and the second output data is the first value.

[0174] It should be noted that the first value can be 1, and the second value can be 0. That is to say, when the enable signal is in an effective state, the processing module 13 is in an operating state, used to amplify and output the data signal and discharge the leakage current generated by the processing module 13. At the same time, when the clock signal is in the first level state, the receiving module 11 is in a receiving state, charges the first sub-node stg1n and the second sub-node stg1p to obtain the first sub-node signal and the second sub-node signal respectively, and is processed and output by the processing module 13.

[0175] When the level state of the first data signal is greater than the level state of the second data signal, the first output signal is 1 and the second output signal is 0. In this way, if the data processing circuit 10 is a data reading circuit, the first data signal in the high level state is successfully read out and output. If the data processing circuit 10 is a comparator, the first output signal corresponds to the first data signal, and the second output signal corresponds to the second data signal, then the small difference between the first data signal and the second data signal is significantly amplified, that is, "the higher is higher, the lower is lower". The same is true when the level state of the first data signal is less than the level state of the second data signal.

[0176] In some embodiments, as Figure 9 shown, the data processing circuit 10 may further include a compensation module 17; among them,

[0177] A compensation module 17 for receiving a compensation signal and determining a target compensation signal according to the compensation signal, where the target compensation signal is used to reduce the current mismatch of the processing module 13;

[0178] The processing module 13 is specifically configured to output a target data signal according to the target compensation signal and the first node signal when in a working state.

[0179] It should be noted that during the preparation process of the circuit, circuit mismatch is inevitable. In Figure 9 , the mismatch between the seventh switch unit N7 and the eighth switch unit N8 will cause a difference in their current discharge capabilities, resulting in current mismatch, which may cause deviation or even inaccurate output of the target data signal output by the cross-coupling module 132. Therefore, an embodiment of the present disclosure can also add a compensation module 17 to the data processing circuit 10. As Figure 9 shown, the initial compensation signal may include a first initial compensation signal os<0> and a second initial compensation signal os<1>, the target compensation signal may include a first target compensation signal and a second target compensation signal, and the compensation module 17 may include four NMOS transistors: N21, N21t, N22, and N22t. The first ends of the four NMOS transistors may be the drains, and the second ends may be the sources.

[0180] Specifically, the gate of N21 is connected to the first sub-node stg1n, the first end of N21 is connected to the third sub-node stg2n, the second end of N21 is connected to the first end of N21t, the gate of N21t receives the first output compensation signal os<0>, and the second end of N21t is grounded. The gate of N22 is connected to the second sub-node stg1p, the first end of N22 is connected to the fourth sub-node stg2p, the second end of N22 is connected to the first end of N22t, the gate of N22t receives the second compensation signal os<1>, and the second end of N22t is grounded.

[0181] Among them, N21 and N21t are mainly used to compensate for the current mismatch of the seventh switch unit N7, and N22 and N22t are mainly used to compensate for the current mismatch of the eighth switch unit N8. In this way, in the compensation module 17, N21t receives the first initial compensation signal, N21 receives the first node signal, the first end of N21t is connected to the second end of N21, and finally the first target compensation signal is output at the first end of N21 to compensate for the output of the first end of the seventh switch unit N7, making the third sub-node signal more accurate. N22t receives the second initial compensation signal, N22 receives the second node signal, the first end of N22t is connected to the second end of N22, and finally the second target compensation signal is output at the first end of N22 to compensate for the output of the first end of the eighth switch unit N8, making the fourth sub-node signal more accurate.

[0182] Thus, after being compensated by the compensation module 17, the seventh switch unit N7 and the eighth switch unit N8 have the same circuit discharging ability and can process signals with the same driving ability. In this way, when the processing module 13 is in the working state, it can accurately output the target data signal by combining the target compensation signal and the first node signal.

[0183] An embodiment of the present disclosure provides a data processing circuit, which includes a receiving module, a first power supply module, and a processing module. Among them, the receiving module is used to receive a data signal and determine a first node signal according to the data signal; the first power supply module is used to receive an enabling signal and control the processing module to be in the working state when the enabling signal is in the effective state; the processing module is used to output a target data signal according to the first node signal when it is in the working state. In this way, the first power supply module controls the working state of the processing module through the enabling signal, so that the processing module is in the working state only when the enabling signal is in the effective state, and when the enabling signal is in the non-effective state, that is, when entering the standby mode, the processing module is in the non-working state, thereby effectively reducing the leakage current of the data processing circuit in the standby mode and saving power consumption.

[0184] In another embodiment of the present disclosure, based on the data processing circuit 10 described in any one of the foregoing embodiments, refer to Figure 10 , which shows a schematic flowchart of a data processing method provided by an embodiment of the present disclosure. As Figure 10 shown, the method may include:

[0185] S201. Receive a data signal through the receiving module and determine a first node signal according to the data signal.

[0186] S202. Receive an enabling signal through the first power supply module and control the processing module to be in the working state when the enabling signal is in the effective state.

[0187] S203. Output a target data signal according to the first node signal through the processing module when it is in the working state.

[0188] In some embodiments, the data processing circuit further includes a latching module; the method may further include:

[0189] Receive a first sampling signal and a second sampling signal through the latching module, and perform latching processing on the first sampling signal and the second sampling signal to generate an enabling signal;

[0190] wherein, the second sampling signal is delayed by a preset clock cycle compared with the first sampling signal, and the enabling signal is valid within the preset clock cycle.

[0191] In some embodiments, the data processing circuit further includes a first sampling module and a second sampling module; the method may further include:

[0192] The first sampling module receives a first enable signal and a clock signal, and samples the first enable signal according to the clock signal to generate a first sampling signal;

[0193] The second sampling module receives a second enable signal and a clock signal, and samples the second enable signal according to the clock signal to generate a second sampling signal.

[0194] In some embodiments, the first enable signal includes a command signal, and the second enable signal includes the first sampling signal.

[0195] In some embodiments, the first power supply module includes a first switch unit. The first power supply module receives an enable signal, and when the enable signal is in an active state, controls the processing module to be in a working state, including:

[0196] Receiving the enable signal through the control terminal of the first switch unit. When the enable signal is in an active state, the first switch unit is in a conducting state, so that the processing module is in a working state; and when the enable signal is in a non-active state, the first switch unit is in an off state, so that the processing module is in a non-working state.

[0197] In some embodiments, the receiving module includes a second power supply module, a first control module, and a second control module; the receiving module receives a data signal, and determines a first node signal according to the data signal, including:

[0198] Receiving a clock signal through the second power supply module, and controlling the connection state between the power supply terminal and the first control module and the second control module according to the clock signal;

[0199] Receiving a first data signal through the first control module, and controlling the first data signal according to the connection state between the power supply terminal and the first control module to generate a first sub-node signal;

[0200] Receiving a second data signal through the second control module, and controlling the second data signal according to the connection state between the power supply terminal and the second control module to generate a second sub-node signal.

[0201] In some embodiments, the second power supply module includes a second switch unit. The second power supply module receives a clock signal, and controls the connection state between the power supply terminal and the first control module and the second control module according to the clock signal, including:

[0202] Receiving a clock signal through the control terminal of the second switch unit. When the clock signal is in the first level state, the second switch unit is in the conducting state, such that the power supply terminal is connected to both the first control module and the second control module; and when the clock signal is in the second level state, the second switch unit is in the non-conducting state, such that the power supply terminal is not connected to both the first control module and the second control module.

[0203] In some embodiments, the first control module includes a third switch unit and a fourth switch unit, and the second control module includes a fifth switch unit and a sixth switch unit; the method may further include:

[0204] Receiving a first data signal through the control terminal of the third switch unit and receiving a clock signal through the control terminal of the fourth switch unit; outputting a first sub-node signal through the first terminal of the third switch unit and the first terminal of the fourth switch unit;

[0205] Receiving a second data signal through the control terminal of the fifth switch unit and receiving a clock signal through the control terminal of the sixth switch unit; outputting a second sub-node signal through the first terminal of the fifth switch unit and the first terminal of the sixth switch unit.

[0206] In some embodiments, the method may further include:

[0207] When the clock signal is in the first level state, controlling the fourth switch unit to be in the non-conducting state through the first control module, and when the clock signal is in the second level state, controlling the fourth switch unit to be in the conducting state through the first control module;

[0208] When the clock signal is in the first level state, controlling the sixth switch unit to be in the non-conducting state through the second control module, and when the clock signal is in the second level state, controlling the sixth switch unit to be in the conducting state through the second control module.

[0209] In some embodiments, the processing module includes a differential module and a cross-coupling module. Outputting a target data signal according to the first node signal includes:

[0210] Receiving the first sub-node signal and the second sub-node signal through the differential module and performing differential processing on the first sub-node signal and the second sub-node signal to generate a third sub-node signal and a fourth sub-node signal;

[0211] Performing amplification processing on the third sub-node signal and the fourth sub-node signal through the cross-coupling module to generate a first output signal and a second output signal; wherein, the target data signal is composed of the first output signal and the second output signal.

[0212] In some embodiments, the differential module includes a seventh switching unit and an eighth switching unit; receiving a first sub-node signal through the differential module and generating a third sub-node signal includes:

[0213] Receiving the first sub-node signal through the control terminal of the seventh switching unit and outputting the third sub-node signal through the first terminal of the seventh switching unit;

[0214] Receiving a second sub-node signal through the differential module and generating a fourth sub-node signal includes:

[0215] Receiving the second sub-node signal through the control terminal of the eighth switching unit and outputting the fourth sub-node signal through the first terminal of the eighth switching unit.

[0216] In some embodiments, the cross-coupling module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; amplifying the third sub-node signal and the fourth sub-node signal through the cross-coupling module to generate a first output signal and a second output signal includes:

[0217] Receiving the third sub-node signal through the source of the first NMOS transistor and the first terminal of the seventh switching unit;

[0218] Receiving the fourth sub-node signal through the source of the second NMOS transistor and the first terminal of the eighth switching unit, and outputting the first output signal through the drain of the first PMOS transistor and the drain of the first NMOS transistor;

[0219] Outputting the second output signal through the drain of the second PMOS transistor and the drain of the second NMOS transistor;

[0220] Receiving the second output signal through the gates of the first PMOS transistor and the first NMOS transistor;

[0221] Receiving the first output signal through the gates of the second PMOS transistor and the second NMOS transistor.

[0222] In some embodiments, when the enable signal is in an active state and the clock signal is in a first level state:

[0223] If the level state of the first data signal is greater than the level state of the second data signal, the first output data is a first value and the second output data is a second value;

[0224] If the level state of the first data signal is less than the level state of the second data signal, the first output data is a second value and the second output data is a first value.

[0225] In some embodiments, the data processing circuit may further include a pre-charge module; the method may further include:

[0226] Precharge the initial data signal output by the processing module through a precharge module;

[0227] Correspondingly, when the processing module is in the working state, output a target data signal according to the first node signal, including:

[0228] When the processing module is in the working state, amplify the signal according to the first node signal and the initial data signal, and output a target data signal.

[0229] In some embodiments, the data processing circuit may further include a compensation module; the method may further include:

[0230] Receive a compensation signal through the compensation module, and determine a target compensation signal according to the compensation signal, where the target compensation signal is used to reduce the current mismatch of the processing module;

[0231] Correspondingly, when the processing module is in the working state, output a target data signal according to the first node signal, including:

[0232] When the processing module is in the working state, output a target data signal according to the target compensation signal and the first node signal.

[0233] For details not disclosed in the embodiments of the present disclosure, please refer to the description of the foregoing embodiments for understanding.

[0234] The embodiments of the present disclosure provide a data processing method, which is applied to the foregoing data processing circuit. When performing data processing, control the working state of the processing module through the first power supply module and the enable signal, so that the processing module is in the working state only when the enable signal is in the effective state, and when the enable signal is in the non-effective state and enters the standby mode, the processing module is in the non-working state, thereby effectively reducing the leakage current of the data processing circuit in the standby mode and saving power consumption.

[0235] In another embodiment of the present disclosure, refer to Figure 11 , which shows a schematic structural diagram of a semiconductor memory 100 provided by the embodiments of the present disclosure. As Figure 11 shown, the semiconductor memory 100 may include the data processing circuit 10 described in any one of the foregoing embodiments.

[0236] For the semiconductor memory 100, since it includes the data processing circuit 10 in the foregoing embodiments, the leakage current can be effectively reduced and the power consumption can be saved.

[0237] The above is only a preferred embodiment of the present disclosure, and is not intended to limit the protection scope of the present disclosure.

[0238] It should be noted that in this disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising that element.

[0239] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the superiority or inferiority of the embodiments.

[0240] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0241] The above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A data processing circuit, characterized in that, It includes a receiving module, a first power module, and a processing module. Among them, the receiving module is used to receive a data signal and determine a first node signal according to the data signal; the first power module is used to receive an enable signal and control the processing module to be in a working state when the enable signal is in an effective state; the processing module is used to output a target data signal according to the first node signal when it is in a working state; the data processing circuit further includes a latching module; among them, the latching module is used to receive a first sampling signal and a second sampling signal, and perform latching processing on the first sampling signal and the second sampling signal to generate the enable signal; wherein, the second sampling signal is delayed by a preset clock cycle compared with the first sampling signal, and the enable signal is effective within the preset clock cycle; the data processing circuit further includes a first sampling module and a second sampling module; among them, the first sampling module is used to receive a first enable signal and a clock signal, and perform sampling processing on the first enable signal according to the clock signal to generate the first sampling signal; the second sampling module is used to receive a second enable signal and the clock signal, and perform sampling processing on the second enable signal according to the clock signal to generate a second sampling signal.

2. The data processing circuit according to claim 1, wherein Both the first enable signal and the second enable signal are command signals; the first sampling module includes N first flip-flops. The clock terminals of the first flip-flops are all used to receive the clock signal. The output terminal of the i-th first flip-flop is connected to the input terminal of the (i + 1)-th first flip-flop. The input terminal of the first first flip-flop is used to receive the first enable signal, and the output terminal of the N-th first flip-flop is used to output the first sampling signal; wherein, i is an integer greater than 0 and less than N, and N is an integer greater than 0; the second sampling module includes M second flip-flops. The clock terminals of the second flip-flops are all used to receive the clock signal. The output terminal of the j-th second flip-flop is connected to the input terminal of the (j + 1)-th second flip-flop. The input terminal of the first second flip-flop is used to receive the second enable signal, and the output terminal of the M-th second flip-flop is used to output the second sampling signal; wherein, j is an integer greater than 0 and less than M, and M is an integer greater than 0.

3. The data processing circuit according to claim 1, wherein The first enable signal includes a command signal, and the second enable signal includes the first sampling signal; the first sampling module includes N first flip-flops. The clock terminals of the first flip-flops are all used to receive the clock signal. The output terminal of the i-th first flip-flop is connected to the input terminal of the (i + 1)-th first flip-flop. The input terminal of the first first flip-flop is used to receive the command signal, and the output terminal of the N-th first flip-flop is used to output the first sampling signal; wherein, i is an integer greater than 0 and less than N, and N is an integer greater than 0; The second sampling module includes M second flip - flops. The clock terminals of the second flip - flops are all used to receive the clock signal. The output terminal of the j - th second flip - flop is connected to the input terminal of the (j + 1) - th second flip - flop, and the input terminal of the first second flip - flop is connected to the output terminal of the N - th first flip - flop for receiving the first sampling signal. The output terminal of the M - th second flip - flop is used to output the second sampling signal; where j is an integer greater than 0 and less than M, and M is an integer greater than 0.

4. The data processing circuit according to claim 2 or 3, wherein The latching module includes a latch. The first input terminal of the latch is connected to the output terminal of the N - th first flip - flop for receiving the first sampling signal; the second input terminal of the latch is connected to the output terminal of the M - th second flip - flop for receiving the second sampling signal; the output terminal of the latch is used to output the enable signal.

5. The data processing circuit according to claim 1, wherein The first power supply module includes a first switch unit. The control terminal of the first switch unit is used to receive the enable signal. The first terminal of the first switch unit is connected to the processing module, and the second terminal of the first switch unit is connected to the power supply terminal; The first power supply module is used to control the first switch unit to be in the on state when the enable signal is in the valid state, so that the processing module is in the working state; and to control the first switch unit to be in the off state when the enable signal is in the non - valid state, so that the processing module is in the non - working state.

6. The data processing circuit according to claim 5, wherein The receiving module includes a second power supply module, a first control module, and a second control module; where The second power supply module is used to receive the clock signal and control the connection state between the power supply terminal and the first control module and the second control module according to the clock signal; The first control module is used to receive the first data signal, control the first data signal according to the connection state between the power supply terminal and the first control module, and generate a first sub - node signal; The second control module is used to receive the second data signal, control the second data signal according to the connection state between the power supply terminal and the second control module, and generate a second sub - node signal.

7. The data processing circuit according to claim 6, wherein The second power supply module includes a second switch unit. The control terminal of the second switch unit is used to receive the clock signal. The first terminal of the second switch unit is respectively connected to the first control module and the second control module, and the second terminal of the second switch unit is connected to the power supply terminal; where The second power supply module is used to control the second switch unit to be in the on state when the clock signal is in the first level state, so that the power supply terminal is connected to the first control module and the power supply terminal is connected to the second control module; and to control the second switch unit to be in the off state when the clock signal is in the second level state, so that the power supply terminal is not connected to the first control module and the power supply terminal is not connected to the second control module.

8. The data processing circuit according to claim 7, wherein The first control module includes a third switch unit and a fourth switch unit, and the second control module includes a fifth switch unit and a sixth switch unit; wherein, The control terminal of the third switch unit is used to receive the first data signal, the second terminal of the third switch unit is connected to the first terminal of the second switch unit, the control terminal of the fourth switch unit is used to receive the clock signal, and the second terminal of the fourth switch unit is grounded; the first terminal of the third switch unit is connected to the first terminal of the fourth switch unit for outputting the first sub-node signal; The control terminal of the fifth switch unit is used to receive the second data signal, the second terminal of the fifth switch unit is connected to the first terminal of the second switch unit, the control terminal of the sixth switch unit is used to receive the clock signal, and the second terminal of the sixth switch unit is grounded; the first terminal of the fifth switch unit is connected to the first terminal of the sixth switch unit for outputting the second sub-node signal.

9. The data processing circuit according to claim 8, wherein The first control module is configured to control the fourth switch unit to be in an off state when the clock signal is in a first level state, and control the fourth switch unit to be in an on state when the clock signal is in a second level state; The second control module is configured to control the sixth switch unit to be in an off state when the clock signal is in a first level state, and control the sixth switch unit to be in an on state when the clock signal is in a second level state.

10. The data processing circuit according to claim 8, wherein The processing module includes a differential module and a cross-coupling module, wherein; The differential module is configured to receive the first sub-node signal and the second sub-node signal, and perform differential processing on the first sub-node signal and the second sub-node signal to generate a third sub-node signal and a fourth sub-node signal; The cross-coupling module is configured to perform amplification processing on the third sub-node signal and the fourth sub-node signal to generate a first output signal and a second output signal; wherein, the target data signal is composed of the first output signal and the second output signal.

11. The data processing circuit according to claim 10, wherein The differential module includes a seventh switch unit and an eighth switch unit; wherein, The control terminal of the seventh switch unit is connected to the first terminal of the third switch unit and the first terminal of the fourth switch unit for receiving the first sub-node signal, the first terminal of the seventh switch unit is connected to the cross-coupling module for outputting the third sub-node signal, and the second terminal of the seventh switch unit is grounded; The control terminal of the eighth switch unit is connected to the first terminal of the fifth switch unit and the first terminal of the sixth switch unit for receiving the second sub-node signal, the first terminal of the eighth switch unit is connected to the cross-coupling module for outputting the fourth sub-node signal, and the second terminal of the eighth switch unit is grounded.

12. The data processing circuit according to claim 11, wherein The cross-coupling module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; wherein, The source of the first PMOS transistor and the source of the second PMOS transistor are connected and connected to the first end of the first switching unit; The drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to output the first output signal; The drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to output the second output signal; The gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to receive the second output signal; The gate of the second PMOS transistor and the gate of the second NMOS transistor are connected to receive the first output signal; The source of the first NMOS transistor is connected to the first end of the seventh switching unit to receive the third sub-node signal; The source of the second NMOS transistor is connected to the first end of the eighth switching unit to receive the fourth sub-node signal.

13. The data processing circuit according to claim 10, wherein When the enable signal is in an active state and the clock signal is in a first level state: If the level state of the first data signal is greater than the level state of the second data signal, the first output signal is a first value and the second output signal is a second value; If the level state of the first data signal is less than the level state of the second data signal, the first output signal is a second value and the second output signal is a first value.

14. The data processing circuit according to claim 1, wherein The data processing circuit further includes a pre-charge module; wherein, The pre-charge module is used to pre-charge the initial data signal output by the processing module; The processing module is further used to, when in a working state, amplify the signal according to the first node signal and the initial data signal and output the target data signal.

15. The data processing circuit according to claim 1, characterized in that, The data processing circuit further includes a compensation module; wherein, The compensation module is used to receive a compensation signal and determine a target compensation signal according to the compensation signal, wherein the target compensation signal is used to reduce the current mismatch of the processing module; The processing module is specifically used to, when in a working state, output the target data signal according to the target compensation signal and the first node signal.

16. A data processing circuit, characterized in that, It includes a receiving module, a first power supply module and a processing module, wherein, The receiving module is used to receive a data signal and determine a first node signal according to the data signal; The first power supply module is used to receive an enable signal and control the processing module to be in a working state when the enable signal is in an active state; The processing module is used to, when in a working state, output a target data signal according to the first node signal; The first power supply module includes a first switching unit, the control end of the first switching unit is used to receive the enable signal, the first end of the first switching unit is connected to the processing module, and the second end of the first switching unit is connected to the power supply terminal; The first power supply module is configured to control the first switch unit to be in a conducting state when the enable signal is in an active state, so that the processing module is in the working state; and to control the first switch unit to be in an off state when the enable signal is in an inactive state, so that the processing module is in a non-working state; The receiving module includes a second power supply module, a first control module, and a second control module; wherein, The second power supply module is configured to receive a clock signal and control the connection state between the power supply terminal and the first control module and the second control module according to the clock signal; The first control module is configured to receive a first data signal, control the first data signal according to the connection state between the power supply terminal and the first control module, and generate a first sub-node signal; The second control module is configured to receive a second data signal, control the second data signal according to the connection state between the power supply terminal and the second control module, and generate a second sub-node signal.

17. A data processing method, characterized in that, Applied to the data processing circuit according to any one of claims 1-16, the method includes: Receiving a data signal through the receiving module and determining a first node signal according to the data signal; Receiving an enable signal through the first power supply module and controlling the processing module to be in a working state when the enable signal is in an active state; Outputting a target data signal according to the first node signal through the processing module when it is in a working state.

18. A semiconductor memory, characterized in that, The semiconductor memory includes the data processing circuit according to any one of claims 1 to 16.

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