Methods of forming conductive vias and associated devices and systems

Abstract

This application relates to methods of forming conductive vias and associated devices and systems. Methods of fabricating semiconductor devices and associated systems and devices are disclosed herein. In some embodiments, a method of fabricating a semiconductor device includes forming an opening in insulating material at least partially over a conductive feature. The method can further include forming a ring of non-conductive material extending at least partially around sidewalls of the insulating material defining the opening. The method can further include removing a portion of the ring to form an opening over the conductive feature, and then depositing a conductive material into the opening in the ring to form a conductive via electrically coupled to the conductive feature.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices and methods for manufacturing semiconductor devices, and more specifically, to methods for forming conductive vias in semiconductor devices. Background Technology

[0002] Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of memory cells. Various types of memory devices exist, such as non-volatile memory devices (e.g., NAND flash memory devices) and volatile memory devices (e.g., dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), etc.).

[0003] Improving memory devices typically involves increasing memory cell density, increasing read / write speeds or otherwise reducing operating latency, improving reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs. One way to reduce manufacturing costs is to improve manufacturing processes to increase the margin of success in manufacturing devices. Manufacturers can increase manufacturing margins by implementing processes such as increasing the consistency or tolerance of manufacturing steps (e.g., material removal or deposition) or increasing manufacturing scale. Summary of the Invention

[0004] In one aspect, this application relates to a method of manufacturing a semiconductor device, the method comprising: removing a portion of an insulating material to define an opening at least partially over a conductive feature, wherein the insulating material includes sidewalls that at least partially define the opening; forming a non-conductive material layer that at least partially covers the sidewalls; removing a portion of the non-conductive material layer to form the opening over the conductive feature; and depositing a conductive material into the opening in the non-conductive material layer to form a conductive via electrically coupled to the conductive feature.

[0005] In another aspect, this application relates to a method of manufacturing a semiconductor device, the method comprising: removing a portion of an insulating material to define an opening at least partially over a first conductive feature and a second conductive feature, wherein the insulating material includes sidewalls that at least partially define the opening; forming a non-conductive material layer that at least partially covers the sidewalls; removing a first portion of the non-conductive material layer to form a first opening over the first conductive feature; removing a second portion of the non-conductive material layer to form a second opening over the second conductive feature; depositing a conductive material into the first opening to form a first conductive via electrically coupled to the first conductive feature; and depositing a conductive material into the second opening to form a second conductive via electrically coupled to the second conductive feature.

[0006] In another aspect, this application relates to a semiconductor device comprising: a first layer including conductive features; and a second layer above the first layer, wherein the second layer includes: a via of conductive material electrically connected to the conductive features; a non-conductive material layer including a first portion extending away from the via and a second portion extending away from the via, wherein the via is laterally located between the first and second portions of the non-conductive material layer; and an insulating material surrounding the non-conductive material layer, wherein the insulating material is different from the non-conductive material. Attached Figure Description

[0007] Many aspects of the invention can be better understood by referring to the accompanying drawings. The components in the drawings are not necessarily to scale. The focus is on clearly illustrating the principles of the invention.

[0008] Figures 1A to 1G An enlarged partial schematic top view illustrating various stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0009] Figures 2A to 2G For embodiments of the present invention, respectively along Figures 1A to 1G The line shown in the image is cut from 2A-2A to 2G-2G. Figures 1A to 1G An enlarged side cross-sectional view of the semiconductor device.

[0010] Figures 3A to 3C An enlarged partial schematic top view illustrating various stages of a method for manufacturing a semiconductor device according to an additional embodiment of the present invention.

[0011] Figures 4A to 4C For embodiments of the present invention, respectively along Figures 3A to 3C The line shown in the image is cut from 4A-4A to 4C-4C. Figures 3A to 3C An enlarged side cross-sectional view of the semiconductor device.

[0012] Figure 5 This is a schematic diagram of a system including a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0013] Embodiments of the present invention include methods, associated apparatus, and systems for manufacturing semiconductor devices, such as memory devices. In several embodiments described below, for example, the method of manufacturing a semiconductor device includes forming openings (e.g., trenches) in an electrically insulating material at least partially over a first conductive feature and a second conductive feature. The first and second conductive features may be metal lines, such as word and / or bit lines of a memory device. The electrically insulating material may include sidewalls that at least partially define the openings. The method may further include forming a ring of non-conductive material on / around the sidewalls of the insulating material. In some embodiments, the ring may have a generally linear shape. The method may further include removing a first portion of the ring to form a first opening over the first conductive feature, and removing a second portion of the ring to form a second opening over the second conductive feature. Finally, conductive material may be deposited into the first and second openings to form first and second conductive vias, respectively, on the first and second conductive features.

[0014] In some aspects of the present invention, the conductive via portions can be formed at a lower cost and / or with higher margin compared to conventional techniques for forming conductive vias. For example, the opening formed in the insulating material can be significantly larger (e.g., having a lower aspect ratio) than the subsequently formed conductive via. Therefore, the opening can be formed via a less precise and therefore more reliable and less costly etching or other process compared to conventional methods of etching high-aspect-ratio holes corresponding to the subsequent dimensions of the conductive via formed therein. Furthermore, forming a ring allows the first and second portions of the ring (which may have dimensions corresponding to the dimensions of the subsequently formed conductive via) to be precisely removed using a selective etching process.

[0015] Numerous specific details are disclosed herein to provide a detailed and useful description of embodiments of the invention. However, those skilled in the art will understand that the technology may have additional embodiments, and that the technology may be described without further reference. Figures 1A to 5 The described embodiments are practiced in several details. For example, some details of memory devices well-known in the art have been omitted to avoid obscuring the technical aspects of the invention. Generally, it should be understood that various other devices and systems besides the specific embodiments disclosed herein are within the scope of the invention.

[0016] As used herein, the terms “vertical,” “horizontal,” “upper,” “lower,” “above,” and “below” may refer to the relative orientation or position of a feature in a semiconductor device, given the orientation shown in the figures. For example, “upper” or “topmost” may refer to a feature positioned closer to the top of the page than another feature. However, these terms should be broadly understood to include semiconductor devices with other orientations, such as inverted or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0017] Those skilled in the art will recognize that the appropriate stages of the methods described herein can be performed at the wafer level or at the die level. Therefore, depending on the context of use, the term "substrate" can refer to a wafer-level substrate or a single die-level substrate. Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. For example, materials can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and / or other suitable techniques. Similarly, for example, materials can be removed using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques. Those skilled in the art will also understand that the techniques may have additional embodiments, and that the techniques may be described without further reference. Figures 1A to 5 The following are some details of the described embodiments in practice.

[0018] Figures 1A to 1G An enlarged partial schematic top view illustrating various stages of a method for manufacturing a semiconductor device 100 (e.g., a memory device) according to an embodiment of the present invention. Figures 2A to 2G For embodiments of the present invention, respectively along Figures 1A to 1G The image shows an enlarged side cross-sectional view of the semiconductor device 100 taken along lines 2A-2A to 2G-2G. Generally, the semiconductor device 100 can be manufactured, for example, as a discrete device or as a portion of a larger wafer or panel. In wafer-level or panel-level manufacturing, the larger structure is formed before being individually divided to form multiple independent structures. For ease of illustration and understanding, Figures 1A to 2G The fabrication of a portion of a single semiconductor device 100 is described. However, those skilled in the art will readily understand that the fabrication of semiconductor device 100 can be scaled down to the wafer and / or panel level, that is, including more components to enable it to be individually divided into two or more semiconductor devices, while incorporating similar features and using similar processes as described herein.

[0019] Figure 1A and 2AThe semiconductor device 100 is described after the following are formed: (i) a first layer 102 comprising a first insulating material 112 and a first conductive feature 122 (e.g., a first metallization layer); (ii) a second layer 104 over the first layer 102 and comprising a second insulating material 114 and a conductive via 124 electrically coupled / connected to a corresponding conductive feature in the first conductive feature 122; (iii) a third layer 106 over the second layer 104 and comprising a third insulating material 116 and a second conductive feature 126 electrically coupled / connected to a corresponding conductive via 126 in the conductive via 124 (e.g., a second metallization layer comprising individually identified first to fifth conductive features of second conductive features 126a to 126e, respectively); and (iv) a fourth layer 108 over the third layer 106 and comprising a fourth insulating material 118. The second conductive feature 126 is in... Figures 1A to 1G The image is partially or completely obscured, and therefore at least partially schematically displayed.

[0020] The first to fourth insulating materials 112 to 118 (collectively referred to as "insulating materials 112 to 118") may include one or more electrically insulating materials, such as passivating materials, dielectric materials, oxides (e.g., silicon oxide), and / or tetraethyl orthosilicate (TEOS), and insulating materials 112 to 118 may be the same or different. In some embodiments, the fourth insulating material 118 includes TEOS and has a thickness between about 2000 and 5000 angstroms (e.g., about 3500 angstroms). The thicknesses of the first to fourth layers 102 to 108 (collectively referred to as "layers 102 to 108") may be the same or different. The first conductive feature 122, the conductive via 124, and the second conductive feature 126 may include metals, such as tungsten, metal alloys, and / or materials containing conductive metals, and may have the same or different dimensions (e.g., width, diameter) and / or arrangement. In some embodiments, the first conductive feature 122 includes copper and the second conductive feature 126 includes tungsten.

[0021] The first conductive feature 122 may be electrically coupled to one or more circuit elements (e.g., wires, traces, interconnects, transistors; not shown) that may be formed in / on a substrate (not shown). The circuit elements may include, for example, memory circuitry (e.g., dynamic random access memory (DRAM) or other types of memory circuitry), controller circuitry (e.g., DRAM controller circuitry), logic circuitry, and / or other circuitry. In some embodiments, the first conductive feature 122 is electrically coupled to one or more complementary metal-oxide-semiconductor (CMOS) circuits.

[0022] The second conductive feature 126 may be a metal line, contact, trace, etc., extending through / along the third layer 106. In some embodiments, for example, the second conductive feature 126 may be a word line and / or bit line electrically coupled to one of the memory elements (not shown). Figure 1A As best seen, the second conductive features 126 may have different planar shapes and / or sizes. In the illustrated embodiment, for example, each of the second conductive features 126 has a rectangular shape. However, in the illustrated embodiment, the first conductive feature 126a and the second conductive feature 126b of the second conductive features have the same size, while the third conductive feature 126c, the fourth conductive feature 126d, the fifth conductive feature 126e, etc. of the second conductive features have different sizes. In the illustrated embodiment, the second conductive features 126 are generally arranged in rows. In other embodiments, the second conductive features 126 may have different shapes (e.g., circular, straight, polygonal, irregular), different sizes, and / or may be arranged in different ways (e.g., in more or fewer rows, irregularly, in a grid, spaced closer or farther apart from each other).

[0023] Figure 1B and 2B This describes a semiconductor device 100 after forming openings 130 (e.g., including a separately identified first opening 130a) through a fourth insulating material 118 of a fourth layer 108 to expose portions of two or more of the second conductive features 126 in each of the openings 130. For example, a portion of the first conductive feature 126a and a portion of the second conductive feature 126b are exposed in the first opening 130a. Photolithography, etching, stamping, dicing, masking, and / or other suitable processes can be used to remove portions of the fourth insulating material 118 to form the openings 130. In some embodiments, one or more additional layers 132 (in...) are formed prior to the openings 130. Figure 2B(Illustrated schematically) may optionally be formed over the fourth layer 108. The additional layer 132 may include one or more resists, anti-reflective coatings (ARC), back-side anti-reflective coatings (BARC), carbon, and / or other suitable layers known in the field of photolithography. In the illustrated embodiment, a portion of an adjacent conductive feature in the second conductive feature 126 is exposed in a corresponding opening in the opening 130. In other embodiments, some or all of the openings 130 may be formed over: (i) all or a portion of a single conductive feature in the second conductive feature 126; (ii) the entire occupied area (e.g., area, planar shape) of one or more of the second conductive features 126; (iii) a larger or smaller occupied area of ​​the second conductive feature 126; (iv) more than two conductive features in the second conductive feature 126; and / or (v) non-adjacent conductive features in the second conductive feature 126.

[0024] refer to Figure 2B In some embodiments, a fourth insulating material 118 is included in each of the openings 130, defining a generally vertical sidewall 134 in each of the openings 130. In other embodiments, the sidewall 134 may be angled / inclined (e.g., relative to the upper surface of the third layer 106), such as Figure 2B The dotted line in the figure is shown and identified by reference numeral 134'. In such embodiments, the opening 130 may have a tapered shape, including a cross-sectional dimension (e.g., radius, diameter, area) that decreases, for example, in the direction toward the third layer 106.

[0025] Figure 1C and 2C This describes a semiconductor device 100 after (i) a non-conductive pad 136 is formed / deposited over a fourth insulating material 118 above a third layer 106 and within an opening 130. The non-conductive pad 136 may comprise a nitride, oxide, or other suitable non-conductive material. Reference Figure 2CThe non-conductive pad 136 may include in each of the openings 130: (i) a vertical portion 138 formed along the sidewall 134 of the opening 130; and (ii) a first horizontal portion 137 formed over the third layer 106 exposed in the opening 130 (e.g., over the portions of the second conductive contact 126 and the third insulating material 116 exposed in the opening 130). In some embodiments, the non-conductive pad 136 may further include a second horizontal portion 139 extending over a fourth insulating material 118 (e.g., the upper surface of the fourth insulating material 118). As described in detail below, portions of the vertical portion 138 of the non-conductive pad 136 may be selectively removed (e.g., etched) and filled to form independent conductive vias electrically coupled to the second conductive feature 126 in the third layer 106. Thus, the thickness T of the non-conductive pad 136 may be selected based on the desired final size (e.g., thickness) of the conductive via. In some embodiments, the thickness T may be less than 100 nanometers, less than 10 nanometers, less than 5 nanometers, less than 1 nanometer, or greater than 100 nanometers. Furthermore, to facilitate selective removal of the non-conductive pad 136, in some embodiments, the non-conductive pad 136 may be formed of a material different from that of the fourth insulating material 118.

[0026] Figure 1D and 2D This describes a semiconductor device 100 after a fifth insulating material 140 is deposited in an opening 130 above a non-conductive pad 136. Figure 1D and 2D Further explanation of the semiconductor device after removing the following: (i) the second horizontal portion 139 of the non-conductive pad 136 ( Figure 2C (i) to retain only the vertical portion 138 and the first horizontal portion 137 in the opening 130; and (ii) any portion of the fifth insulating material 140 deposited over the fourth insulating material 118 (e.g., over the second horizontal portion 139 of the non-conductive pad 136). In some embodiments, photolithography, stamping, plasma etching, wet etching, and / or other suitable processes may be used to remove the second horizontal portion 139 and any of the fifth insulating material 140 thereon. The fifth insulating material 140 may include oxides, photoresist materials, carbon-based spin materials, and / or another electrically insulating material. In some embodiments, the fifth insulating material 140 is a sacrificial material (e.g., an underlayer) configured to be removed during subsequent downstream processing steps. In other embodiments, the fifth insulating material 140 is configured to remain in the semiconductor device 100 after manufacturing and may therefore be, for example, the same material as the fourth insulating material 118. The fifth insulating material 140 may be deposited via a spin coating process or another suitable deposition process.

[0027] As in Figure 1DAs can be best seen, removing the second horizontal portion 139 of the non-conductive pad 136 from each of the separable / disconnectable openings 130 results in the non-conductive pad 136 being separated, such that the vertical portion 138 of the non-conductive pad 136 ( Figure 2D A plurality of rings 150 are formed / defined extending along / around the sidewalls 134 of corresponding openings in opening 130. Referring to the ring 150 formed in the first opening 130a, each ring 150 may include a through-hole portion 152 (e.g., a first or vertical side or edge portion; individually identified as a first through-hole portion 152a and a second through-hole portion 152b), each at least partially positioned above a corresponding conductive feature in the second conductive feature 126. Specifically, the first through-hole portion 152a may be at least partially positioned above the first conductive feature 126a in the second conductive feature, and the second through-hole portion 152b may be at least partially positioned above the second conductive feature 126b in the second conductive feature. The ring 150 may further include connecting portions 154 (e.g., second or horizontal side or edge portions) extending between and connecting the through-hole portions 152. In the illustrated embodiment, the ring 150 has a generally rectangular shape formed by the opposing through-hole portions 152 and the opposing connecting portions 154. In other embodiments, the ring 150 may have other shapes (e.g., circular, polygonal, square, irregular) determined by, for example, the shape and size of the opening 130.

[0028] Figure 1E and 2E This describes a semiconductor device 100 after a mask 160 is formed over the upper surface of the semiconductor device 100 (e.g., formed of a fourth insulating material 118, a fifth insulating material 140, and / or a non-conductive pad 136). The mask 160 may be a photoresist or a suitable photolithographic mask. In the illustrated embodiment, the mask 160 includes a plurality of openings 162 (including a first opening 162a and a second opening 162b, each individually identified) located on corresponding rings in a ring 150. More specifically, in some embodiments, each of the openings 162 may be located on a corresponding via portion 152 of a via portion 152 of the ring 150. For example, in the illustrated embodiment, the first opening 162a is located on a portion of the first via portion 152a, and the second opening 162b is located on a portion of the second via portion 152b. The openings 162 may at least partially overlap with corresponding conductive features in the second conductive features 126. For example, a first opening 162a is superimposed (e.g., vertically aligned) on a first conductive feature 126b of a second conductive feature, and a second opening 162b is superimposed on a second conductive feature 126b of the second conductive features. In some embodiments, the opening 162 may have a thickness T greater than that of the non-conductive pad 136. Figure 2C ) size (e.g., Figure 2EThe width W shown in the diagram exposes a portion of the fourth insulating material 118 and / or a portion of the fifth insulating material 140 in each of the openings 162. In other embodiments, the openings 162 may have different sizes and / or may be positioned differently relative to the rings 150. For example, one or more of the openings 162 may be positioned on each of the rings 150, and the openings 162 may have different sizes and / or shapes from each other, etc.

[0029] Figure 1F and 2F The semiconductor device 100 is described after the following: (i) removing the opening 162 located in the mask 160 ( Figure 1E and 2E (ii) Removal of the non-conductive pad 136 below the opening 162; and (ii) Removal of the mask 160. In some embodiments, a suitable dry etching process, wet etching process, and / or other suitable material ablation process may be used to remove the non-conductive pad 136, which selectively removes only the non-conductive pad 136 exposed in the opening 162, without removing, for example, any portion of the fourth insulating material 118 or the fifth insulating material 140 exposed in the opening 162. In the illustrated embodiment, after the removal process, the semiconductor device 100 includes an opening 170 (e.g., a slot, a via; including a separately identified first opening 170a and a second opening 170b) formed in a ring 150 (e.g., between the fourth insulating material 118 and the fifth insulating material 140) above a corresponding conductive feature in the second conductive feature 126. For example, the first opening 170a is formed above the first conductive feature 126a in the second conductive feature, and the second opening 170b is formed above the second conductive feature 126b in the second conductive feature. In some embodiments, the first opening 170a may be opposite to the second opening 170b along the ring 150. For example, in the illustrated embodiment, the first opening 170a is formed in the first through-hole portion 152a ( Figure 1E In, and the second opening 170b is formed in the second through hole portion 152b opposite to the first through hole portion 152a. Figure 1E )middle.

[0030] Figure 1G and 2G Explanation at an opening of 170 ( Figure 1F and 2FThe semiconductor device 100 is formed / deposited with conductive material 172 to form conductive vias 174 (including separately identified first conductive via 174a and second conductive via 174b) on the second conductive feature 126. The conductive material 172 may include a metal, such as tungsten, copper, silver, aluminum, a metal alloy, a material containing a conductive metal, etc., and is electrically coupled to a portion of the second conductive feature 126 exposed in the opening 170. In some embodiments, the conductive material 172 may be deposited via sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, electroplating, electroless plating, and / or another suitable deposition technique. In some embodiments, a seed material (not shown; e.g., titanium nitride (TiN)) may first be deposited in the opening 170, and then the conductive material 172 may be grown on the seed layer using, for example, a Birch reduction method.

[0031] In the illustrated embodiment, the conductive via 174 is embedded in / alongside the ring 150 of the non-conductive pad 136. That is, the ring 150 and the conductive via 174 may extend together, with portions of the ring 150 extending from / between the conductive via 174, etc. Furthermore, a fourth insulating material 118 is positioned around / outside the periphery defined by the ring 150 and the conductive via 174. Additionally, in the illustrated embodiment, the first horizontal portion 137 of the non-conductive pad 136 ( Figure 2G It remains above the third layer 106 and extends between the conductive vias 174. The conductive vias 174 are electrically isolated through the non-conductive pad 136, the fourth insulating material 118 and / or the fifth insulating material 140.

[0032] In some embodiments, the semiconductor device 100 may be planarized after the deposition of the conductive material 172. In some embodiments, a metallization layer (not shown) may subsequently be formed over the fourth layer 108. The metallization layer may include, for example, metal lines (e.g., words and / or bit lines), or other conductive features electrically coupled to corresponding conductive vias in the conductive vias formed by the conductive material 172.

[0033] In some aspects of the present invention, the conductive via 174 can be formed by the fourth layer 108 at a lower cost and / or with a higher margin compared to conventional techniques for forming conductive vias. For example, see also... Figures 1A to 2GThe opening 130 is significantly larger than the subsequently formed conductive via 174. That is, the aspect ratio of the opening 130 is smaller than that of the subsequently formed conductive via 174. Therefore, compared to conventional methods of etching high aspect ratio holes corresponding to the subsequent dimensions of the conductive via formed therein, the opening 130 can be formed using less precise and therefore more reliable and less costly etching or other processes. Furthermore, the deposition of the non-conductive pad 136 allows for the formation of the opening 170 (corresponding to the size of the subsequently formed conductive via 174) using a more precise selective etching process than if the opening 170 were formed directly in the fourth insulating material 118. In an additional aspect of the invention, the thickness T of the conductive via 174 can be precisely controlled and arbitrarily small via the deposition technique used to deposit the non-conductive pad 136.

[0034] In other embodiments, the method according to the present invention can be used to form any number of conductive vias in openings formed in an insulating material above a conductive contact or wire. For example, continuing to refer to [reference needed] Figures 1A to 2G The second conductive feature 126b in the second conductive feature can be omitted from the third layer 106, and the manufacturing process can be similar to forming the first opening 130a, depositing the non-conductive pad 136, etc. However, when the second conductive feature 126b in the second conductive feature is omitted, only the first opening 170a needs to be formed in the non-conductive pad 136, and the second opening 170b can be omitted. Therefore, the first conductive via 174a can be formed with the same high aspect ratio and has the same advantages as described above, without the need to simultaneously form conductive vias above adjacent or neighboring conductive features (e.g., the second conductive feature 126b in the second conductive feature) in the second conductive feature 126.

[0035] Similarly, one or more of the openings 130 may be formed in the fourth insulating material 118 over more than two of the second conductive features 126 exposed in the openings 130. In some such embodiments, one or two of the connecting portions 154 of the ring 150 may be formed over the corresponding one or more of the second conductive features 126 exposed in the openings 130. Next, openings 170 in the non-conductive pad 136 may be selectively formed in the via portions 152 and / or the connecting portions 154 and the conductive material 172 deposited therein, based on the arrangement of the underlying second conductive features 126, to form conductive vias 174.

[0036] Figures 3A to 3C Enlarged partial schematic top view of various stages in a method for manufacturing a semiconductor device 300 (e.g., a memory device) according to an additional embodiment of the present invention. Figures 4A to 4C For embodiments of the present invention, respectively along Figures 3A to 3CThe image shows an enlarged side cross-sectional view of the semiconductor device 100 taken along lines 4A-4A to 4C-4C. Generally, the semiconductor device 300 can be manufactured in a similar manner and includes the features described in the reference above. Figures 1A to 2G The semiconductor device 100 is a similar component described in detail. For example, in some embodiments, the semiconductor device 300 may be manufactured in the same manner. Figure 1C and 2C The semiconductor device 100 shown in the image represents a stage.

[0037] However, as Figure 3A and 4A As shown, after depositing the non-conductive pad 136 over the third layer 106, the method may include removing the first horizontal portion 137 and the second horizontal portion 139 of the non-conductive pad 136. Figure 2C While retaining the vertical portion 138 of the non-conductive pad 136, the first horizontal portion 137 and the second horizontal portion 139 may be removed using photolithography, stamping, plasma etching, wet etching, and / or other suitable processes. In some embodiments, a straight stamping process may be used to remove the first horizontal portion 137 and the second horizontal portion 139. Figure 4A As can be best seen, after removing the first horizontal portion 137 and the second horizontal portion 139, the vertical portion 138 of the non-conductive pad 136 forms / defines a plurality of rings 150 within the corresponding openings of the opening 130. Furthermore, with the removal of the first horizontal portion 137, the second conductive feature 126 may be partially exposed within the opening 130. For example, the first conductive feature 126a and the second conductive feature 126b of the second conductive features are exposed within the first opening 130a.

[0038] Figure 3A and 4A Further explanation of the semiconductor device 300 after planarization of its upper surface (e.g., defined by non-conductive pads 136 and / or fourth insulating material 118). Planarization ensures that the vertical portion 138 extends from the third layer 106 to the same or substantially the same height as the fourth insulating material 118. In some embodiments, the planarization step may be omitted and may be incorporated into the removal process for removing the first horizontal portion 137 and the second horizontal portion 139 of the non-conductive pads 136, or may be performed at a later manufacturing stage (e.g., referred to below). Figure 3B and 4B (After the stage described in detail) Implementation.

[0039] Figure 3B and 4B The opening 130 is described above the third layer 106 between the rings 150, where the fifth insulating material 140 is deposited. Figure 3A and4A Semiconductor device 300 following the semiconductor device 100 described in detail above. Figure 4B As can be seen best, the fifth insulating material 140 can directly contact the third layer 106, which includes the second conductive feature 126 and the third insulating material 116.

[0040] Figure 3C and 4C The semiconductor device 300 is described after the following: (i) selectively removing a portion of the ring 150; and then (ii) forming a conductive via 174 in the removed portion of the ring 150 above and electrically connected to the corresponding conductive feature in the second conductive feature 126. These stages are consistent with those described above. Figures 1E to 2G The manufacturing stages described in detail are generally similar or identical, including, for example, (i) forming a mask above the upper surface of the semiconductor device 300; (ii) removing non-conductive pads 136 located below openings in the mask; (iii) removing the mask; and (iv) forming / depositing conductive material 172 to form conductive vias 174, wherein non-conductive pads 136 are selectively removed. Compared to the reference above... Figures 1A to 2G The semiconductor device 100 described in detail includes a fifth insulating material 140 (instead of the first horizontal portion 137 of the non-conductive pad 136). Figure 2G The third layer 106 is in direct contact at the center of ring 150 and between adjacent conductive vias in conductive via 174.

[0041] The above references Figures 1A to 4C The detailed description of semiconductor device 100 and / or packages containing semiconductor device 100 and / or semiconductor device 300 can be incorporated into any of numerous larger and / or more complex systems, a representative example of which is... Figure 5 System 590 is schematically shown in the diagram. System 590 may include processor 592, memory 594 (e.g., SRAM, DRAM, flash and / or other memory devices), input / output devices 596, and / or other subsystems or components 598. (See above reference) Figures 1A to 4C The described memory device and / or package may be included Figure 5The resulting system 590 can be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 590 include, but are not limited to: computers and / or other data processors, such as desktop computers, laptop computers, networked appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics devices, network computers, and microcomputers. Additional representative examples of system 590 include lamps, cameras, vehicles, etc. Regarding these and other examples, system 590 can be housed in a single unit or distributed across multiple interconnected units, for example, via a communication network. Accordingly, components of system 590 may include local and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0042] In summary, it should be understood that specific embodiments of the technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Therefore, the invention is not limited except by the appended claims. Furthermore, certain aspects of the new technology described in the context of particular embodiments may be combined or removed in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are required to exhibit such advantages to fall within the scope of the technology. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A portion of the insulating material is removed to define an opening at least partially above the conductive feature, wherein the insulating material includes a sidewall that at least partially defines the opening; A non-conductive material layer is formed that at least partially covers the sidewalls; A portion of the non-conductive material layer is removed to form an opening above the conductive feature; as well as A conductive material is deposited into the opening in the non-conductive material layer to form a conductive via electrically coupled to the conductive feature.

2. The method of claim 1, wherein removing the portion of the non-conductive material layer comprises: A mask is formed over the insulating material and the non-conductive material layers, such that the mask includes an opening over the portion of the non-conductive material layer; and Etch the portion of the non-conductive material layer exposed in the opening in the mask.

3. The method of claim 2, wherein forming the mask further comprises forming the mask such that the opening in the mask is positioned over a portion of the insulating material, and wherein etching the portion of the non-conductive material layer comprises selectively etching the portion of the non-conductive material layer exposed in the opening, without etching the insulating material exposed in the opening.

4. The method of claim 1, wherein the insulating material is a first insulating material, wherein the conductive feature is located in a layer of a second insulating material, and wherein forming the non-conductive material layer comprises depositing the non-conductive material in the opening over (a) the sidewall of the first insulating material and (b) the layer of the second insulating material.

5. The method of claim 4, wherein the method further comprises removing the non-conductive material from above the layer of the second insulating material before removing the portion of the non-conductive material layer.

6. The method of claim 1, wherein forming the non-conductive material layer comprises forming the non-conductive material layer having a straight cross-sectional shape.

7. The method of claim 1, wherein the insulating material is a first insulating material, and wherein the method further comprises depositing a second insulating material into the opening after forming the non-conductive material layer in the opening.

8. The method according to claim 1, wherein the insulating material and the non-conductive material are different.

9. The method of claim 1, wherein the conductive feature is a conductive line extending through an insulating material and electrically coupled to a memory element.

10. A method of manufacturing a semiconductor device, the method comprising: A portion of the insulating material is removed to define an opening at least partially above a first conductive feature and a second conductive feature, wherein the insulating material includes a sidewall that at least partially defines the opening; A non-conductive material layer is formed that at least partially covers the sidewalls; Remove a first portion of the non-conductive material layer to form a first opening above the first conductive feature; Remove a second portion of the non-conductive material layer to form a second opening above the second conductive feature; A conductive material is deposited into the first opening to form a first conductive via electrically coupled to the first conductive feature; as well as The conductive material is deposited into the second opening to form a second conductive via electrically coupled to the second conductive feature.

11. The method of claim 10, wherein the first portion of the non-conductive material layer is opposite to the second portion of the non-conductive material layer.

12. The method of claim 10, wherein forming the non-conductive material layer comprises forming the non-conductive material layer to have a straight cross-sectional shape having opposing first sides and opposing second sides.

13. The method of claim 12, wherein the first portion of the non-conductive material layer is a part of one of the first sides, and wherein the second portion of the non-conductive material layer is a part of the other of the first sides.

14. The method of claim 10, wherein the insulating material is a first insulating material, and wherein forming the non-conductive material layer comprises: The non-conductive material is deposited in the openings above the sidewalls described in (a) and (b) where the second insulating layer having the first and second conductive features is located; and Remove the non-conductive material from above the second insulating layer.

15. A semiconductor device comprising: The first layer contains conductive features; as well as A second layer, which is located above the first layer, wherein the second layer comprises: A through-hole in a conductive material, electrically connected to the conductive feature; A non-conductive material layer, wherein the non-conductive material layer includes a first portion extending away from the through-hole and a second portion extending away from the through-hole, and wherein the through-hole is laterally located between the first portion and the second portion of the non-conductive material layer; and An insulating material is disposed around the non-conductive material layer, wherein the insulating material is different from the non-conductive material.

16. The semiconductor device of claim 15, wherein the non-conductive material layer has a linear shape.

17. The semiconductor device of claim 15, wherein the conductive feature is a first conductive feature, wherein the via is a first via, wherein the first layer further includes a second conductive feature, wherein the second layer further includes a second via located above the second conductive feature and electrically connected to the conductive material of the second conductive feature, and wherein the non-conductive material layer extends between the first conductive feature and the second conductive feature.

18. The semiconductor device of claim 17, wherein the first via is positioned relative to the second via along the non-conductive material layer.

19. The semiconductor device of claim 17, wherein the non-conductive material layer has an annular shape.

20. The semiconductor device of claim 15, wherein the insulating material is a first insulating material, wherein the first layer comprises a second insulating material, and wherein the non-conductive material layer extends over both the second insulating material and a portion of the conductive feature.

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