Power integrated chip and battery management system

Abstract

The present disclosure provides a power integrated chip and a battery management system. The power integrated chip includes a first conductive strip, a first MOS transistor, a second conductive strip, a third conductive strip, a second MOS transistor, and a fourth conductive strip. The power integrated chip disclosed herein can effectively reduce the chip's own resistance and achieve metal heat dissipation.

Description

Technical Field

[0001] The present disclosure relates to a power integrated chip and a battery management system. Background Art

[0002] Rechargeable batteries are widely used in various fields, including electric vehicles and portable devices. During the control process of rechargeable batteries, charge and discharge power switches are required to ensure safety and controllability. Currently, the charge and discharge switches used are typically discrete. In the industry, each charge and discharge switch needs to be soldered to the corresponding circuit board. This method is costly and requires reliability during the processing. For example, the technical solutions provided in US Patent Publication No. US20220190629A1 and others.

[0003] The current industry trend is towards integrated power switches. Because they are located in the flow path between the battery and the load / charger, these switches consume a certain amount of power. This power consumption is accompanied by various issues, such as operating time and heat dissipation. This power consumption can shorten the operating time of rechargeable batteries in portable devices. Summary of the Invention

[0004] In order to solve one of the above technical problems, the present disclosure provides a power integrated chip and a battery management system. According to the power integrated chip of the present disclosure, the resistance of the chip itself can be effectively reduced and metal heat dissipation can be achieved.

[0005] According to one aspect of the present disclosure, a power integrated chip is provided, comprising: a first conductive strip, the first conductive strip being arranged at a first side of the chip and connected to a first pin of the chip, the first conductive strip extending along a first direction of the chip; a first MOS transistor, the first MOS transistor being electrically connected to the first conductive strip, the first MOS transistor comprising one or more MOS transistors; a second conductive strip, one side of the second conductive strip being electrically connected to the first MOS transistor, and current being able to flow through the first pin, the first conductive strip, the first MOS transistor, and the second conductive strip; a third conductive strip being arranged on the other side of the second conductive strip, and current being able to flow through the second conductive strip and the third conductive strip; a second MOS transistor, the second MOS transistor being electrically connected to the third conductive strip, the second MOS transistor comprising one or more MOS transistors; and a fourth conductive strip being arranged at a second side of the chip and connected to a second pin of the chip, the fourth conductive strip extending along the first direction, wherein the second side and the first side are two opposite sides of the chip, and current being able to flow through the third conductive strip, the second MOS transistor, the fourth conductive strip, and the second pin.

[0006] According to the power integrated chip of at least one embodiment of the present disclosure, the first MOS transistor includes two or more MOS transistors connected in parallel, and the second MOS transistor includes two or more MOS transistors connected in parallel.

[0007] According to the power integrated chip of at least one embodiment of the present disclosure, the first MOS transistor is a charge control transistor or a discharge control transistor, the second MOS transistor is a discharge control transistor or a charge control transistor, and the first MOS transistor and the second MOS transistor are NMOS transistors or PMOS transistors.

[0008] According to the power integrated chip of at least one embodiment of the present disclosure, the source of the first MOS transistor is electrically connected to the first conductive band, the drain of the MOS transistor is electrically connected to the second conductive band, the drain of the second MOS transistor is electrically connected to the third conductive band, and the source of the second MOS transistor is electrically connected to the fourth conductive band.

[0009] According to at least one embodiment of the power integrated chip of the present disclosure, the chip includes a third pin and a fourth pin, wherein the third pin is connected to the second conductive strip, the fourth pin is connected to the third conductive strip, and the third pin and the fourth pin can be electrically connected.

[0010] According to the power integrated chip of at least one embodiment of the present disclosure, the lengths of the first pin, the second pin, the third pin, and the fourth pin are equal to or substantially equal to the length or width of the chip; and / or

[0011] The first pin, the second pin, the third pin and the fourth pin are arranged on the back side of the chip.

[0012] According to at least one embodiment of the present disclosure, the power integrated chip includes a fifth pin and a sixth pin. The fifth pin is connected to the first conductive band, and the sixth pin is electrically connected to the gate of the first MOS transistor.

[0013] According to at least one embodiment of the power integrated chip of the present disclosure, the chip includes a seventh pin and an eighth pin, the seventh pin is electrically connected to the gate of the second MOS transistor, and the eighth pin is connected to the fourth conductive band.

[0014] According to the power integrated chip of at least one embodiment of the present disclosure, the fifth pin and the sixth pin, and the seventh pin and the eighth pin are arranged on the same side of the chip or on different sides.

[0015] According to the power integrated chip of at least one embodiment of the present disclosure, when the fifth pin and the sixth pin, and the seventh pin and the eighth pin are arranged on the same side of the chip, the fifth pin, the sixth pin, the seventh pin and the eighth pin are arranged on or near the third side of the chip, wherein the third side is the side between the first side and the second side; or when the fifth pin and the sixth pin, and the seventh pin and the eighth pin are arranged on different sides of the chip, the fifth pin and the sixth pin are arranged on or near the third side of the chip, and the seventh pin and the eighth pin are arranged on or near the fourth side of the chip, wherein the third side and the fourth side are the sides between the first side and the second side and are opposite sides.

[0016] According to the power integrated chip of at least one embodiment of the present disclosure, the fifth pin and the sixth pin, and the seventh pin and the eighth pin are provided on the back side of the chip.

[0017] According to the power integrated chip of at least one embodiment of the present disclosure, the seventh pin and the eighth pin are arranged at or near the third side or at or near the fourth side of the chip.

[0018] According to the power integrated chip of at least one embodiment of the present disclosure, the first direction is a length direction or a width direction of the chip.

[0019] According to at least one embodiment of the present disclosure, the power integrated chip further includes a temperature detection diode to detect the temperatures of the first MOS transistor and the second MOS transistor. The chip is also provided with pins corresponding to the temperature detection diode.

[0020] According to another aspect of the present disclosure, a battery management system includes: the power integrated chip as described in any one of the above items; and a drive unit connected to the fifth pin, the sixth pin, the seventh pin, and the eighth pin.

[0021] According to the battery management system of at least one embodiment of the present disclosure, the first pin and the second pin of the power integrated chip are respectively connected to the low voltage side of the battery and the low voltage side of the load / charger, or respectively connected to the high voltage side of the battery and the high voltage side of the load / charger. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0023] Figure 1 Schematic diagram of the structure of a power integrated chip according to one embodiment of the present disclosure.

[0024] Figure 2 Schematic diagram of the structure of a power integrated chip according to one embodiment of the present disclosure.

[0025] Figure 3 FIG. 1 is an external schematic diagram of a power integrated chip according to an embodiment of the present disclosure.

[0026] Figure 4 Schematic diagram of the structure of a power integrated chip according to one embodiment of the present disclosure.

[0027] Figure 5 is a schematic diagram of a power integrated chip according to one embodiment of the present disclosure.

[0028] Figure 6 is a schematic diagram of a power integrated chip according to one embodiment of the present disclosure.

[0029] Figure 7 is a schematic diagram of a power integrated chip according to one embodiment of the present disclosure.

[0030] Figure 8 is a schematic diagram of a power integrated chip according to one embodiment of the present disclosure.

[0031] Figure 9is a schematic diagram of a power integrated chip according to one embodiment of the present disclosure.

[0032] Figure 10 Schematic diagram of the structure of a power integrated chip according to one embodiment of the present disclosure.

[0033] Figure 11 Schematic diagram of the structure of a power integrated chip according to one embodiment of the present disclosure.

[0034] Figure 12 is a schematic diagram of a battery management system according to one embodiment of the present disclosure.

[0035] Figure 13 is a schematic diagram of a battery management system according to one embodiment of the present disclosure.

[0036] The specific reference numerals in the figure are:

[0037] 10 chips

[0038] 11 First side

[0039] 12 Second side

[0040] 13 Third side

[0041] 14 Fourth side

[0042] 100 First MOS transistor

[0043] 200 Second MOS transistor

[0044] 300 First Conductive Tape

[0045] 400 Second conductive tape

[0046] 500 Third Conductive Band

[0047] 600 Fourth conductive band. DETAILED DESCRIPTION

[0048] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to explain the relevant content and are not intended to limit the present disclosure. It should also be noted that, for ease of description, only the portions relevant to the present disclosure are shown in the accompanying drawings.

[0049] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0050] Unless otherwise stated, the exemplary embodiments / examples shown are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of the various embodiments / examples may be further combined, separated, interchanged, and / or rearranged without departing from the technical concepts of the present disclosure.

[0051] The use of cross hatching and / or shading in the accompanying drawings is generally used to make the boundaries between adjacent components clear. As such, unless otherwise indicated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the accompanying drawings, the sizes and relative sizes of the components may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two successively described processes can be performed substantially simultaneously or in an order opposite to the order described. In addition, the same figure numbers represent the same components.

[0052] When a component is referred to as being “on,” “over,” “connected to,” or “coupled to” another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another component, there are no intervening components present. For this purpose, the term “connected” may refer to a physical connection, an electrical connection, etc., with or without intervening components.

[0053] For descriptive purposes, the present disclosure may use spatially relative terms such as "below," "beneath," "under," "down," "above," "upper," "above," "higher," and "side (e.g., as in "sidewall")," to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, a component described as "below" or "beneath" another component or feature would then be positioned "above" the other component or feature. Thus, the exemplary term "below" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0054] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, the features, integral bodies, steps, operations, parts, assemblies and / or their groups stated are explained, but the presence or addition of one or more other features, integral bodies, steps, operations, parts, assemblies and / or their groups is not excluded. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values and / or the values provided that will be recognized by those of ordinary skill in the art.

[0055] According to one embodiment of the present disclosure, a power integrated chip is provided. The power integrated chip can be used in a battery management system as a charge and discharge switch. External control switches the MOS transistors in the power integrated chip on and off, thereby controlling the charging and discharging of the battery. Of course, based on the principles of the present disclosure, the power integrated chip can also be used in other application scenarios other than battery management systems.

[0056] Figure 1 and Figure 2 An embodiment according to the present disclosure is shown. Figure 1 and Figure 2 As shown, the power integrated chip 10 may include a first MOS transistor 100 and a second MOS transistor 200. The first MOS transistor 100 and the second MOS transistor 200 may be NMOS transistors or PMOS transistors, which may be 12V to 200V MOS transistors. The type of MOS transistor may be a trench gate MOS transistor, a planar gate MOS transistor, a super junction MOS transistor, or a split gate MOS transistor. In the drawings of the present disclosure, NMOS transistors are used as an example for illustration.

[0057] The first MOS transistor 100 may include one or more MOS transistors. In the case of including more than two MOS transistors, the two or more MOS transistors may be connected in parallel to form the first MOS transistor 100. The first MOS transistor 100 may include n MOS transistors 101, 102, 103, ..., and 10n. For example, the gates of the MOS transistor 101, the MOS transistor 102, the MOS transistor 103, ..., and the MOS transistor 10n may be connected together, and their drains may also be connected together.

[0058] The second MOS transistor 200 may include one or more MOS transistors. In the case of including more than two MOS transistors, the two or more MOS transistors may be connected in parallel to form the second MOS transistor 200. The second MOS transistor 200 may include n MOS transistors 201, 202, 203, ..., 20n. For example, the gates of the MOS transistor 201, the MOS transistor 202, the MOS transistor 203, ..., and the MOS transistor 20n may be connected together, and the drains may also be connected together.

[0059] It should be noted that in the present disclosure, preferably, the first MOS transistor 100 and the second MOS transistor 200 each include more than two MOS transistors. Those skilled in the art will understand that when a MOS transistor is turned on, an internal impedance will be formed, which will consume the internal current flowing through it, thereby generating unnecessary power consumption. By connecting multiple MOS transistors in parallel, the impedance of the first MOS transistor 100 and the second MOS transistor 200 can be reduced as a whole, thereby reducing the power consumed by the first MOS transistor 100 and the second MOS transistor 200.

[0060] According to the power integrated chip disclosed in the present invention, a first conductive tape 300 may be included, wherein the first conductive tape 300 may be arranged at or near the first side 11 of the chip 10, and may be connected to the first pin PSC of the chip 10. The first conductive tape 300 may be arranged to extend along a first direction of the chip 10, wherein the first direction may be the length direction (horizontal direction in the figure) or the width direction (vertical direction in the figure) of the chip 10. The figure shows that the first direction is the length direction. Of course, if the chip is in the form of a square, the first direction may be any of the two directions of the square. It should be noted that in the present disclosure, the first direction is preferably the length direction. The extension length of the first conductive tape 300 may be 50% to 100% of the length (or width) of the first side 11 of the chip. In the present disclosure, the extension length of the first conductive tape 300 may preferably be greater than or equal to the length occupied by the first MOS transistor 100.

[0061] exist Figure 1 and Figure 2 , which shows the flow path of the current I. By setting the extension length of the first conductive strip 300 to be longer, the resistance of the first conductive strip itself can be greatly reduced. In this way, when current flows through the first conductive strip, due to the extremely low resistance of the first conductive strip, very little power can be consumed.

[0062] In the present disclosure, the source of the first MOS transistor 100 may be electrically connected to the first conductive strip 300. It should be noted that, in order to clearly indicate the connection relationship of the first MOS transistor 100, Figure 1 In the figure, the connecting line is shown in the first conductive strip 300. Figure 2 As shown, the source of each MOS transistor is connected to the first conductive strip 300. In this way, when the first MOS transistor 100 includes multiple MOS transistors, the sources of each MOS transistor are connected together through the first conductive strip 300. In this way, after the current I flows from the first pin PSC, it passes through the first conductive strip 300 with extremely low resistance and the first MOS transistor 100 with extremely low resistance, which can effectively reduce the power consumption of the chip itself.

[0063] The power integrated chip 10 of the present disclosure may further include a second conductive strip 400, wherein the second conductive strip 400 extends within the chip, and the extension direction may be the first direction described above and the same as the extension direction of the first conductive strip 300. The extension length of the second conductive strip 400 may be 50% to 100% of the length (or width) of the first side 11 of the chip. In the present disclosure, the extension length of the second conductive strip 400 may preferably be greater than or equal to the length occupied by the first MOS transistor 100. The drain of the first MOS transistor 100 is electrically connected to the second conductive strip 400. When the first MOS transistor 100 includes multiple MOS transistors, the drains of the multiple MOS transistors are connected together through the second conductive strip. Similarly, by setting the extension length of the second conductive strip 400 to be longer, the resistance of the second conductive strip 400 can be greatly reduced. In this way, when current flows through the second conductive strip 400, due to the extremely low resistance of the second conductive strip 400, very little power can be consumed.

[0064] The second conductive strip 400 can be connected to the third pin PDC of the chip, so that the current I can flow between the first pin PSC, the first conductive strip 300, the first MOS transistor 100, the second conductive strip 400 and the third pin PDC, with extremely low power consumption.

[0065] The power integrated chip 10 of the present disclosure may further include a third conductive strap 500, wherein the third conductive strap 500 extends within the chip in the first direction described above and in the same direction as the first conductive strap 300. The extension length of the third conductive strap 500 may be 50% to 100% of the length (or width) of the first side 11 of the chip. In the present disclosure, the extension length of the third conductive strap 500 is preferably greater than or equal to the length occupied by the first MOS transistor 100 / the second MOS transistor 200. The drain of the second MOS transistor 200 is electrically connected to the third conductive strap 500. If the second MOS transistor 200 includes multiple MOS transistors, the drains of the multiple MOS transistors are connected together via the third conductive strap 500. Similarly, by setting the extension length of the third conductive strap 500 to be longer, the resistance of the third conductive strap 500 can be significantly reduced. As a result, when current flows through the third conductive strap 500, due to its extremely low resistance, minimal power is consumed.

[0066] The third conductive tape 500 can be connected to the fourth pin PDD of the chip. In this way, the current I can flow between the first pin PSC, the first conductive tape 300, the first MOS transistor 100, the second conductive tape 400, the third pin PDC, the fourth pin PDD, and the third conductive tape 500, and the power consumption is extremely low. In the present disclosure, in order to make the current I flow between the second conductive tape 400 and the third conductive tape 500, the third pin PDC and the fourth pin PDD can be connected outside the chip. For example, after the chip is soldered to the printed circuit board, the third pin PDC and the fourth pin PDD can be electrically connected through a conductive wire provided on the printed circuit board. In addition, the second conductive tape 400 and the third conductive tape 500 can also be arranged as a conductive tape, so that the first MOS transistor and the second MOS transistor can be connected inside the chip. Similarly, in order to illustrate the connection relationship, in Figure 1 Virtual connecting lines are shown in Figure 2 The connection status is shown in the figure.

[0067] The power integrated chip 10 of the present disclosure may further include a fourth conductive strap 600, which is disposed at the second side 12 of the chip and is connected to the second pin PSD of the chip. The fourth conductive strap 600 extends along a first direction, wherein the second side 12 and the first side 11 are opposite sides of the chip, and current can flow through the third conductive strap 500, the second MOS transistor 200, the fourth conductive strap 600, and the second pin PSD. The extension length of the fourth conductive strap 600 may be 50% to 100% of the length (or width) of the second side 12 of the chip. In the present disclosure, the extension length of the fourth conductive strap 600 is preferably greater than or equal to the length occupied by the second MOS transistor 200. By setting the extension length of the fourth conductive strap 600 longer, the resistance of the fourth conductive strap 600 can be significantly reduced. As a result, when current flows through the fourth conductive strap 600, due to its extremely low resistance, minimal power is consumed.

[0068] As can be seen from the above, the power integrated chip 10 according to the present disclosure has very low power consumption. In the above description, current flows into the first pin PSC and out of the second pin PSD, passing through the conductive strip and MOS transistor with extremely low internal resistance. The first pin PSC and the second pin PSD of the power integrated chip are respectively connected to the low-voltage side of the battery and the low-voltage side of the load / charger, or respectively to the high-voltage side of the battery and the high-voltage side of the load / charger.

[0069] The figure shows that the first MOS transistor and the second MOS transistor are NMOS transistors, but they can also be PMOS transistors. The principles are the same and will not be described in detail.

[0070] As shown in the figure, the first MOS transistor 100 is a charge control transistor and the second MOS transistor 200 is a discharge control transistor. However, the first MOS transistor 100 can also be a discharge control transistor and the second MOS transistor 200 can also be a charge control transistor. The principles are the same and will not be repeated here.

[0071] According to a further embodiment of the present disclosure, the power integrated chip further includes a fifth pin SC and a sixth pin GC. The fifth pin SC is connected to the first conductive strip 300, and the sixth pin GC is electrically connected to the gate of the first MOS transistor 100. The fifth pin SC and the sixth pin GC can be connected to a drive unit (described later). Signals provided by the drive unit control the on / off switching of the first MOS transistor 100, thereby controlling charging and discharging. In the present disclosure, the current path between the battery and the load / charger is configured to flow from the first pin PSC to the second pin PSD. Therefore, a large resistor can be connected to the fifth pin SC to prevent current I from flowing out of the fifth pin SC.

[0072] The power integrated chip also includes a seventh pin GD and an eighth pin SD. The eighth pin SD is connected to the fourth conductive strip 600 and is electrically connected to the gate of the second MOS transistor 200. The seventh pin GD and the eighth pin SD can be connected to a drive unit (described later). Signals provided by the drive unit control the on / off switching of the second MOS transistor 200, thereby controlling charging and discharging. In the present disclosure, the current path between the battery and the load / charger is configured to flow from the first pin PSC to the second pin PSD. Therefore, a large resistor can be connected to the eighth pin SD to prevent current I from flowing out of the eighth pin SD.

[0073] The fifth pin and the sixth pin, and the seventh pin and the eighth pin are arranged on the same side of the chip. Figure 1 and Figure 2 As shown, the third pin can be arranged on the third side 13 of the chip, and the third pin and the fourth pin can be arranged on the fourth side 14.

[0074] In addition, Figure 3 FIG2 shows an external schematic diagram of a chip according to the above-described embodiment of the present disclosure.

[0075] According to the chip structure of the above embodiment of the present disclosure, a good heat dissipation effect can also be provided. Usually, the heat dissipation of the chip is carried out by air contact. In the process of heat dissipation by air contact, the heat is dissipated by contacting the plastic shell of the chip package with the air, but the heat dissipation effect of this method is not ideal. However, in the present disclosure, heat can be dissipated by metal on the basis of air contact heat dissipation. In the present disclosure, the length of the four conductive strips is set to be longer, for example, equal to or close to the length (width) of the chip, so that after the chip is soldered to the printed circuit board (PCB), it can have a large contact area with the copper foil of the printed circuit board, so that heat can be dissipated through the copper foil. That is to say, the relevant PAD (PSC, PDC, PDD, PSD) of the chip of the present disclosure can be set to be very long, and connected to the printed circuit of the PCB through the PAD, so that metal heat dissipation can be achieved.

[0076] In this disclosure, Figure 3 The device structure shown is only schematic. It can extend from the side of the chip or be set on the back of the chip. Figure 4 and Figure 5 Schematic diagram of the pins arranged on the back of the chip is shown in FIG. In this embodiment, all pins can be arranged on the back of the chip. As an example, metal can be directly grown on the DRAIN end (the drain of the MOS transistor) of the wafer as each conductive strip, and then packaged. The grown metal is exposed for soldering to the PCB. Figure 6A schematic diagram showing that all pins are arranged on the back of the chip.

[0077] According to another embodiment of the present disclosure, see, for example, Figure 7 、 Figure 8 and Figure 9 .

[0078] The fifth pin and the sixth pin, and the seventh pin and the eighth pin are arranged on different sides of the chip. Figure 7-Figure 9 As shown, the fifth and sixth pins can be set on the third side 13 of the chip. The seventh and eighth pins can be set on the fourth side 14 of the chip. The third and fourth pins can be set on the third side 13 or the fourth side 14. Except for the above features, the content of this alternative embodiment is the same as that of the previously described embodiment and will not be repeated here.

[0079] In this other embodiment, similarly, each pin can be set on the side of the chip or on the back of the chip. Figures 4 to 6 The contents of the SPI pins are the same, the only difference is whether the fifth and sixth pins, and the seventh and eighth pins are on the same side or different sides of the chip.

[0080] In addition, in each of the above embodiments, a temperature detection diode 700 may also be integrated, for example, see Figure 10 In the example of FIG, the temperature detection diode 700 can be used for temperature detection, and two corresponding pins PS and NS can be provided for the temperature detection diode. In addition, in the embodiment of the present disclosure, one temperature detection diode can be used to detect the temperature of the first MOS transistor and the temperature of the second MOS transistor. Two temperature detection diodes can also be provided to detect the temperature of the first MOS transistor and the temperature of the second MOS transistor, respectively. For example, Figure 11 shown.

[0081] According to a further embodiment of the present disclosure, a battery management system is also provided. Figure 10 A schematic diagram of the battery management system is shown.

[0082] FIG. 12 shows a case where a power integrated chip is set at the low-voltage side B- of the battery and the low-voltage side P- of the power supply / load. The control chip may include a drive unit, which may receive a control signal from the MCU to control the MOS transistor of the power integrated chip, thereby controlling the current I flowing between B- and P-, thereby controlling the charge and discharge current. The MCU may communicate with the outside based on a communication IC. For these features, reference may be made to the description of the prior art, which is not the invention of this application and will not be repeated here. Figure 13The figure shows the case where the power integrated chip is set at the high voltage side B+ of the battery and the high voltage side P+ of the power supply / load. The principle is the same as that of the low voltage side, so it will not be described in detail. Figure 1 、 Figure 2 、 Figure 7 and Figure 8 The current shown in FIG is the direction of charge current, and the discharge current may be in the opposite direction.

[0083] In the prior art, when using power switches as charging and discharging switches, each power switch needs to be soldered to a printed circuit board, which is costly and unreliable. In the present disclosure, the power MOS transistors are integrated into a single chip, significantly reducing assembly costs and time. Crucially, the design of the present disclosure allows for extremely low power consumption of the integrated chip.

[0084] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in an appropriate manner in any one or more embodiments / methods or examples. In addition, those skilled in the art may combine and combine different embodiments / methods or examples described in this specification and the features of different embodiments / methods or examples, unless they are contradictory.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0086] Those skilled in the art will appreciate that the above embodiments are merely intended to clearly illustrate the present disclosure and are not intended to limit the scope of the present disclosure. Other changes or modifications may be made based on the above disclosure, and such changes or modifications are still within the scope of the present disclosure.

Claims

1. A power integrated chip, characterized in that: include: a first conductive tape, the first conductive tape being disposed at a first side of the chip and connected to a first pin of the chip, and extending along a first direction of the chip; a first MOS transistor, the first MOS transistor being electrically connected to the first conductive band, the first MOS transistor comprising one or more MOS transistors; a second conductive strip, one side of the second conductive strip being electrically connected to the first MOS transistor, and current being able to flow through the first pin, the first conductive strip, the first MOS transistor, and the second conductive strip; a third conductive tape, the third conductive tape being disposed on the other side of the second conductive tape, and current being able to flow through the second conductive tape and the third conductive tape; a second MOS transistor, the second MOS transistor being electrically connected to the third conductive band, the second MOS transistor comprising one or more MOS transistors; as well as a fourth conductive strap, the fourth conductive strap being disposed at a second side of the chip and connected to a second pin of the chip, the fourth conductive strap extending along the first direction, wherein the second side and the first side are two opposite sides of the chip, and current can flow through the third conductive strap, the second MOS transistor, the fourth conductive strap, and the second pin; The chip includes a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin; The third pin is connected to the second conductive strip, the fourth pin is connected to the third conductive strip, and the third pin is electrically connected to the fourth pin; The fifth pin is connected to the first conductive strip, and the sixth pin is electrically connected to the gate of the first MOS transistor; The seventh pin is electrically connected to the gate of the second MOS transistor, and the eighth pin is connected to the fourth conductive strip; The first MOS transistor includes two or more MOS transistors connected in parallel, and the second MOS transistor includes two or more MOS transistors connected in parallel.

2. The power integrated chip according to claim 1, wherein: The first MOS transistor is a charge control transistor or a discharge control transistor, the second MOS transistor is a discharge control transistor or a charge control transistor, and the first MOS transistor and the second MOS transistor are NMOS transistors or PMOS transistors.

3. The power integrated chip according to claim 1, wherein: The source of the first MOS transistor is electrically connected to the first conductive strip, the drain of the MOS transistor is electrically connected to the second conductive strip, the drain of the second MOS transistor is electrically connected to the third conductive strip, and the source of the second MOS transistor is electrically connected to the fourth conductive strip.

4. The power integrated chip according to claim 1, wherein: The lengths of the first pin, the second pin, the third pin, and the fourth pin are equal to or substantially equal to the length or width of the chip; and / or The first pin, the second pin, the third pin and the fourth pin are arranged on the back side of the chip.

5. The power integrated chip according to claim 1, wherein: The fifth pin and the sixth pin, and the seventh pin and the eighth pin are arranged on the same side of the chip or on different sides.

6. The power integrated chip according to claim 5, wherein: In a case where the fifth pin and the sixth pin, and the seventh pin and the eighth pin are arranged on the same side of the chip, the fifth pin, the sixth pin, the seventh pin and the eighth pin are arranged on or near a third side of the chip, wherein the third side is a side between the first side and the second side; or In the case where the fifth pin and the sixth pin, and the seventh pin and the eighth pin are arranged on different sides of the chip, the fifth pin and the sixth pin are arranged on or near the third side of the chip, and the seventh pin and the eighth pin are arranged on or near the fourth side of the chip, wherein the third side and the fourth side are sides between the first side and the second side and are opposite sides.

7. The power integrated chip according to claim 5, wherein: The fifth pin, the sixth pin, and the seventh pin and the eighth pin are provided on the back side of the chip.

8. The power integrated chip according to claim 1, wherein: The seventh pin and the eighth pin are arranged on or near the third side or on or near the fourth side of the chip.

9. The power integrated chip according to claim 1, wherein: The first direction is the length direction or the width direction of the chip.

10. The power integrated chip according to claim 1, wherein: The chip further includes a temperature detection diode to detect the temperature of the first MOS transistor and the second MOS transistor. The chip is further provided with a pin corresponding to the temperature detection diode.

11. A battery management system, characterized in that: include: The power integrated chip according to any one of claims 1 to 8; A driving unit is connected to the fifth pin, the sixth pin, the seventh pin and the eighth pin.

12. The battery management system according to claim 11, wherein: The first pin and the second pin of the power integrated chip are respectively connected to the low voltage side of the battery and the low voltage side of the load / charger, or respectively connected to the high voltage side of the battery and the high voltage side of the load / charger.

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