Dicing structure for memory devices

Abstract

The present disclosure relates to a scribe structure for a memory device. Apparatuses and methods for fabricating a chip are described. An example method includes forming at least one first dielectric layer over a substrate; forming at least one second dielectric layer over the first dielectric layer; forming a cap layer over the at least one second dielectric layer; forming a trench over the substrate by etching; covering at least one edge surface of the at least one first dielectric layer in the trench with a liner; forming a hole through a portion of the cap layer and the at least one second dielectric layer; depositing a conductive layer on the cap layer and the liner in the hole; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Description

Technical Field

[0001] This disclosure relates to a sharding structure for a memory device. Background Technology

[0002] High data reliability, high memory access speed, low power consumption, and reduced chip size are desirable characteristics of semiconductor memories. In recent years, some semiconductor devices, such as dynamic random access memory (DRAM) devices, have incorporated low-k films of insulating materials such as silicon oxycarbide (SiOC) and silicon carbonitride (SiCN), which have low dielectric constants (k) and exhibit weak polarization between conductive layers. The inclusion of these low-k films reduces parasitic capacitance between conductive layers and thus enables high-speed operation of electronic circuitry within the semiconductor device.

[0003] However, low-k materials exhibit weak thermomechanical properties. For example, compared to silicon dioxide (SiO2) and silicon nitride (Si3N4) films, low-k films show lower adhesion to adjacent conductive layers or conductive components (e.g., interconnects). Additionally, low-k materials are brittle. After semiconductor devices are formed on a semiconductor wafer, the wafer is diced into semiconductor chips. Cracks may form during the dicing process. These cracks can propagate through the film interface between the low-k film and another dielectric film (e.g., between SiO2 and SiOC films, between SiCN / SiO2 films, etc.) and reach the device formation region of the semiconductor device, leading to lower semiconductor device yields.

[0004] To reduce cracking during the dicing process, trenches can be formed in the dicing film, for example, by etching through the layer containing the low-k film before dicing. However, the edge surface of the low-k film facing the trench tends to have a recessed shape due to the brittle nature of the low-k material. To form conductive pillar bumps on the wires coupled to interconnects running through the layers, a conductive seed layer can be formed as an initial step in the electroplating of the conductive material. However, because the conductive seed layer deposited on the recessed portions of the low-k film tends to be discontinuous from one recessed portion to another, the deposited layer cannot serve as a seed layer. Summary of the Invention

[0005] In one aspect, this disclosure relates to an apparatus comprising: a multilayer structure including: a first circuit region, a second circuit region, and a dicing region between the first circuit region and the second circuit region; a substrate spanning the first circuit region and the second circuit region; and a plurality of dielectric layers over the substrate and spanning the first circuit region and the second circuit region, the plurality of dielectric layers having trenches in the dicing region, the trenches including edge surfaces having roughness; and at least one liner covering the edge surfaces of the plurality of dielectric layers to provide a surface smoother than the edge surfaces.

[0006] In another aspect, this disclosure relates to a semiconductor chip comprising: a substrate; a plurality of dielectric layers disposed above the substrate, the plurality of dielectric layers including edge surfaces having roughness; and at least one liner covering the edge surfaces of the plurality of dielectric layers to provide a smoother surface than the edge surfaces.

[0007] In another aspect, this disclosure relates to a method of manufacturing a chip, the method comprising: forming at least one first dielectric layer over a substrate; forming at least one second dielectric layer over the at least one first dielectric layer; forming a capping layer over the at least one second dielectric layer; forming a trench over the substrate by etching; covering at least one edge surface of the at least one first dielectric layer in the trench with a liner; forming a hole through a portion of the capping layer and the at least one second dielectric layer; depositing a conductive layer in the hole, on the capping layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating. Attached Figure Description

[0008] Figure 1 This is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2A This is a top view of a semiconductor chip according to an embodiment of the present disclosure.

[0010] Figure 2B This is a top view of a semiconductor chip according to an embodiment of the present disclosure.

[0011] Figure 3 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 4 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 5 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 6A This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 6B This is a vertical cross-sectional view of a portion of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 7This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 8A This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 8B This is a vertical cross-sectional view of a portion of a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 9 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 10 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 11 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 12 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 13 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 14 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 15 This is a vertical cross-sectional view of a schematic structure of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0026] Various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects of embodiments in which this disclosure may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the embodiments of this disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made, without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0027] Figure 1This is a layout diagram of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1 This is a plan view illustrating a schematic configuration of the layout of a plurality of circuit regions 108 and dicing regions 110 formed on a semiconductor device 100. In some embodiments, the semiconductor device 100 may be a semiconductor wafer. The semiconductor device 100 may include a mask region 102. The semiconductor device 100 may be fabricated using photopatterning by applying a mask (e.g., photoresist) to each mask region 102. The semiconductor device 100 may include a boundary region 104 along the periphery of the mask region 102.

[0028] In some embodiments, circuit regions 108 may be arranged in a matrix, and each circuit region 108 may have a rectangular shape. In each circuit region 108, transistors and circuit components, such as conductive interconnects, may be arranged. For example, the transistors and circuit components may include a plurality of memory cells, one or more circuits providing memory access functions such as read and write operations to the memory cells, and control circuitry for controlling the circuits.

[0029] Figure 1 The semiconductor wafer 100 may be in a state prior to being divided into semiconductor chips. In some embodiments, each of the semiconductor chips may be chip 106a. In another embodiment, each of the semiconductor chips may be chip 106b. A dicing region 110 may be disposed around each circuit region 108. The dicing region 110 may include a circuit edge 112 surrounding each chip 106a of each circuit region 108. In some embodiments, the circuit edge 112 may include a group of test elements (not shown) that includes test circuitry. The dicing region 110 may also include trenches 116 between the circuit edges 112 adjacent to the chips, and further include a dicing center region 114 between the trenches 116. In some embodiments, a portion of the dicing region 110 may be etched to provide the trenches 116. In some embodiments, dicing lines may be defined in the dicing center region 114 for separating the semiconductor wafer 100 into individual semiconductor chips 106a. In some embodiments, dicing lines may be defined in the trench 116 for separating the semiconductor wafer 100 into individual semiconductor chips 106b.

[0030] Figure 2A This is a top view of a semiconductor chip 106a according to an embodiment of the present disclosure. The semiconductor chip 106a may include a circuit region 108 surrounded by circuit edges 112. In some embodiments, [the following is omitted as the text is incomplete and requires further context]. Figure 1The semiconductor wafer 100 can be separated into a chip 106a by a dicing step. The dicing step can be performed along a dicing line 202a in the dicing center region 114. After the dicing step, a portion 114' of the dicing center region 114 can remain outside the trench 116 of the semiconductor chip 106a. A capping layer 206a can be disposed on top of the semiconductor chip 106a and includes the dicing center region 114, circuit edges 112, and circuit regions 108. The capping layer 206a may include vias and conductive pillars 204 disposed in the circuit regions 108 that pass through the capping layer 206a. The conductive pillars 204 can be coupled to pads of the chip 106a.

[0031] Figure 2B This is a top view of a semiconductor chip 106b according to an embodiment of the present disclosure. The semiconductor chip 106b may include a circuit region 108 surrounded by circuit edges 112 of the semiconductor chip 106a. In some embodiments, Figure 1 The semiconductor wafer 100 can be separated into chip 106b via a dicing step. Figure 1 A dicing step is performed on the dicing line 202b in the trench 116. After the dicing step, a portion 208 of the trench 116 may remain attached to the circuit edge 112 and circuit region 108 of the semiconductor chip 106b. A capping layer 206b may be disposed on top of the semiconductor chip 106b, including the circuit edge 112 and circuit region 108. The capping layer 206b may include vias and conductive pillars 204 disposed in the circuit region 108. The conductive pillars 204 may be coupled to pads of the chip 106b. In some embodiments, the capping layer 206a or capping layer 206b may be a dielectric film and may contain silicon nitride (Si3N4) and / or silicon carbide (SiC). In some embodiments, the conductive pillars 204 may contain copper (Cu) or nickel (Ni).

[0032] exist Figures 3 to 15 In the following description, some embodiments relate to a wafer having trench 116, a scribe center region disposed between the trenches, and dicing lines in the scribe center region. Alternatively, some embodiments relate to a wafer having trenches and dicing lines in the trenches (not shown). However, each embodiment is not limited to one of these wafers; dicing lines may be provided in the scribe center region or in the trenches in each of the following embodiments.

[0033] In some embodiments, the capping layer and the liner may together comprise a dielectric material, such as silicon nitride (Si3N4) and / or silicon carbide (SiC). The liner may cover the edge surface of the lower dielectric film (e.g., a low-k film). The edge surface of the lower dielectric film may have roughness. For example, the edge surface of the lower dielectric film may have a recessed portion. In another example, the edge surface of the lower dielectric film may be non-uniform. The liner may cover the edge surface of the upper dielectric film above the lower dielectric film.

[0034] Figure 3 This is a vertical cross-sectional view of a schematic structure of a portion 300 of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, the portion 300 of the semiconductor device 100 may be a multilayer structure. The portion 300 of the semiconductor device 100 may include a semiconductor substrate 314. For example, the semiconductor substrate 314 may include a single-crystal silicon substrate. Alternatively, the semiconductor substrate 314 may include silicon oxide (SiO2). The portion 300 of the semiconductor device 100 may include a sub-region 302 of a circuit region 108. The semiconductor substrate 314 may include a through electrode 312 in the sub-region 302. The portion 300 of the semiconductor device 100 may also include a dielectric layer 316 disposed on the semiconductor substrate 314. In some embodiments, the dielectric layer 316 may include a dielectric film (e.g., low-k films 336a to 336e) comprising a low-k insulating material having a low dielectric constant (k) that exhibits weaker polarization between conductive components relative to other dielectric materials such as silicon dioxide (SiO2). For example, the low-k insulating material may comprise silicon oxycarbide (SiOC) and / or silicon carbonitride (SiCN). A portion 300 of the semiconductor device 100 may also include a dielectric layer 318 (e.g., dielectric films 338a to 338c) disposed on the dielectric layer 316. In some embodiments, the dielectric layer 318 may comprise silicon dioxide (SiO2). The dielectric layer 318 may also comprise a material such as phosphorus (P) or boron (B). The semiconductor substrate 314, dielectric layers 316, and 318 may be insulated from each other by a dielectric layer 340 disposed between adjacent dielectric layers 316 and 318 and between the semiconductor substrate 314 and a dielectric layer 316 adjacent to the semiconductor substrate 314. In some embodiments, the dielectric layer 340 may comprise silicon nitride (Si3N4).

[0035] A portion 300 of the semiconductor device 100 may further include a diced region 304 disposed between circuit region 108 and another circuit region (not shown). A sub-region 302 of circuit region 108 includes conductive lines 332a to 332e disposed in dielectric films 336a to 336e, respectively. In some embodiments, conductive lines 332a to 332e may comprise copper (Cu). Sub-region 302 of circuit region 108 may also include conductive lines 334a and 334b ​​disposed in dielectric films 338a and 338c, respectively, in dielectric layer 318. In some embodiments, conductive lines 334a and 334b ​​may comprise aluminum (Al). A portion 300 of the semiconductor device 100 may include interconnects 330 disposed in sub-region 302 of circuit region 108. Interconnects 330 may include through electrodes, each through electrode disposed through two adjacent layers of dielectric layers 316 and 318 and a dielectric layer 340 between said two adjacent layers. Interconnect 330 can couple (e.g., electrically connect) conductive lines 332a to 332e and conductive lines 334a and 334b ​​to through electrode 312. In some embodiments, another interconnect may be further disposed in circuit edges 308a and 308b and / or in the dicing center region 310 of portion 300 of semiconductor device 100. In some embodiments, other interconnects may be included in a test circuit (not shown) disposed in circuit edges 308a and 308b and / or in the dicing center region 310.

[0036] A portion 300 of the semiconductor device 100 may further include a capping layer 320 above one of the dielectric layers 318. In some embodiments, the capping layer 320 may be a dielectric layer comprising silicon nitride (Si3N4) and / or silicon carbide (SiC). The capping layer 320 and the dielectric layer 340 prevent the diffusion of conductive materials (e.g., copper diffusion). The capping layer 320 may include holes in a sub-region 302 of the circuit region 108. A portion 300 of the semiconductor device 100 may further include a conductive seed layer 328 in the holes in the dielectric layer 318. The conductive seed layer 328 is on the conductive line 334a. The conductive seed layer 328 may be at one end of the interconnect 330, opposite to the other end of the interconnect 330 on the semiconductor substrate 314. A portion 300 of the semiconductor device 100 may also include conductive pillars 326 passing through the capping layer 320 and the dielectric film 338a serving as the top layer of the dielectric layer 318. Conductive pillars 326 may be disposed on a conductive seed layer 328 in a sub-region 302 of circuit region 108. In some embodiments, conductive pillars 326 may comprise a conductive material, such as copper (Cu) or nickel (Ni). Interconnects 330 may couple conductive pillars 326 and conductive lines 334a to 334b ​​and 332a to 332e to through electrodes 312. In some embodiments, a portion of the dielectric layer 318 containing conductive lines 334a beneath the capping layer 320 may have a thickness T1 greater than the thickness T2 of the portion of the dielectric layer 318 between the circuit edge 308a and the conductive pillar 326 in the same cross-section. In some embodiments, a portion of the dielectric layer 318 having a greater thickness may comprise the conductive pillar 326. In some embodiments, a portion of the dielectric layer 318 having a greater thickness may be within the circuit edge 308a. The thicker portion of dielectric layer 318 can provide support for sub-region 302 and diced region 304 containing interconnect 330, thereby suppressing cracks around interconnects in sub-region 302 and circuit edge 308a.

[0037] The dicing region 304 may include circuit edges 308a and 308b adjacent to a circuit region (e.g., circuit region 108 including sub-region 302 and another circuit region (not shown)). The dicing region 304 may also include a dicing center region 310 between the circuit edges 308a and 308b. In some embodiments, a cutting line 342 may be provided in the center of the dicing center region 310. The dicing region 304 may also include trenches 306a and 306b. In some embodiments, a cutting line may be provided in the center of the trenches 306a and 306b. The trenches 306a and 306b may prevent the cutting forces in the dicing center region 310 or the trenches 306a and 306b from causing and propagating cracks in the various layers. In some embodiments, a portion 300 of the semiconductor device 100 may include one or more liners 324a to 324d disposed in trenches 306a and 306b, the liners respectively covering at least a portion of the edge surfaces of dielectric layers 316 and 318 facing trenches 306a and 306b. Each of the liners 324a to 324d may include a dielectric layer, such as silicon nitride (Si3N4) and / or silicon carbide (SiC). The liners 324a and 324b in trench 306a may cover portions 322a and 322b of the edge surfaces of dielectric layers 316 and 318 facing trench 306a. In some embodiments, portions 322a and 322b may include recessed portions of dielectric films 336a to 336e facing the edge surfaces of trench 306a. Each of the recessed portions in portions 322a and 322b may correspond to each of the dielectric films 336a to 336e between the dielectric layers 340 above and below each dielectric film.

[0038] Reference Figures 4 to 8B The process of providing trenches 306a and 306b, liners 324a to 324d, and conductive pillars 326 of a portion 300 of a semiconductor device 100 according to various embodiments of the present disclosure is described. Figures 4 to 8B The semiconductor substrate 314, dielectric layers 316 and 318 disposed on the semiconductor substrate 314, conductive lines 332a to 332e and 334a to 334b, through electrode 312, and interconnect 330 coupling the conductive lines 332a to 332e and 334a to 334b ​​to the through electrode 312 have a common characteristic with the semiconductor substrate 314, dielectric layers 316 and 318 disposed on the semiconductor substrate 314, conductive lines 332a to 332e and 334a to 334b ​​to the through electrode 312. Figure 3 The semiconductor substrate 314, dielectric layers 316 and 318, conductive lines 332a to 332e and 334a to 334b, through electrode 312, and interconnect 330 have similar structures. Therefore, for the sake of brevity, the description of the structure of the semiconductor substrate 314, dielectric layers 316 and 318, conductive lines 332a to 332e and 334a to 334b, through electrode 312, and interconnect 330 is omitted.

[0039] Figure 4This is a vertical cross-sectional view of a schematic structure of a portion 400 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4 It can be in the process of forming Figure 3A cross-sectional view of a portion 400 of the semiconductor device 100 after etching trenches 306a and 306b. Trenches 306a and 306b can be formed by photolithography and etching. Prior to the etching process (not shown), cut regions 402a and 402b may include a semiconductor substrate 314 and dielectric layers 316 and 318. For example, one of the dielectric layers 340 may be formed on the semiconductor substrate 314. Each of the dielectric layers 316 (e.g., dielectric films 336a to 336e comprising a low-k material) may be formed sequentially with each of the dielectric layers 340, and through electrodes for conductive lines 332a to 332e and coupling conductive lines 332a to 332e may be formed through the dielectric layers 316 and 340. In some embodiments, the dielectric layer 316 comprising a low-k material film is formed, for example, by a chemical vapor deposition (CVD) method. Dielectric layers 318 (e.g., dielectric layers 338a to 338c comprising silicon dioxide (SiO2)) and each of dielectric layers 340 may be repeatedly formed over dielectric layer 316, while conductive lines 334a and 334b ​​and through electrodes coupling conductive lines 334a to conductive lines 334b ​​may be formed through dielectric layer 318. In some embodiments, sub-regions 302 of dielectric film 338a containing wires 334a and circuit edges 308a may have a thickness greater than the region of dielectric film 338a between sub-regions 302 and circuit edges 308a. In some embodiments, some regions of diced central region 310 containing wires and interconnects may have a thickness greater than the central region containing dicing lines between regions containing interconnects. The thicker portions of dielectric film 338a may provide support for portions 400 containing interconnects 330, thereby suppressing cracks around interconnects 330 in sub-regions 302 and regions containing interconnects in diced central region 310. To form trenches 306a and 306b by etching, a photographic process can be used to provide a pattern of trenches 306a and 306b over dielectric film 338a. A photoresist (not shown) can be applied over dielectric film 338a to cover circuit edges 308a, 308b and dicing center region 310 of circuit region 108 and dicing region 304. In some embodiments, the photoresist can be a positive photoresist that can be removed by exposure to light (e.g., ultraviolet (UV) light). The photoresist may not cover dicing regions 402a and 402b, thus exposing dicing regions 402a and 402b for etching. Etching can be dry etching or wet etching. Therefore, dielectric layers 316 and 318 in dicing regions 402a and 402b can be removed, and trenches 306a and 306b can be formed in dicing regions 402a and 402b. In some embodiments, dry etching may be performed until etching stops at the semiconductor substrate 314. Therefore, trenches 306a and 306b may be disposed on or above the semiconductor substrate 314.The photoresist above the dielectric film 338a can be removed, exposing sub-region 302, circuit edges 308a and 308b, and the capping layer 320 on the dicing center region 310. The trench 306a may have edge surfaces comprising portions 322a and 322b of the dielectric films 336a to 336e facing the trench 306a, as shown. Figure 4 As shown in the figure. Parts 322a and 322b may include recesses that may be generated during the etching process and post-etching processes (e.g., dry ashing and wet cleaning) used to remove the photoresist.

[0040] The surface roughness of the lining facing the trench can be controlled by applying a thick dielectric material. Figure 5 This is a vertical cross-sectional view of a schematic structure of a portion 500 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 5 This can be a cross-sectional view of a portion 500 of a semiconductor device 100 after dielectric material 502 has been deposited over a dielectric film 338a and onto the edge surfaces of dielectric layers 316 and 318 deposited in trenches 306a and 306b. In some embodiments, dielectric material 502 can be, for example, silicon nitride (Si3N4) and / or silicon carbide (SiC). Dielectric material 502 may cover the top surface of dielectric film 338a and the edge surfaces of dielectric layers 316 and 318 facing trenches 306a and 306b, respectively, said edge surfaces including portions 322a and 322b of the edge surface of dielectric layer 318 facing trench 306a. In some embodiments, dielectric material 502 may be applied using a CVD method. Dielectric material 502 may be applied thick enough to reduce the surface roughness of liners 504a to 504d facing trenches 306a and 306b. For example, liners 504a to 504d may be thicker than cover layer 320 or liners 324a to 324d.

[0041] The surface roughness of the liner facing the trench can be further controlled by removing a roughened surface from the liner. In some embodiments, the etching (e.g., dry etching) cycle can be controlled. Figure 6A This is a vertical cross-sectional view of a schematic structure of a portion 600 of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, the top portion of the dielectric material 502 and the non-uniform surfaces of the liners 504a to 504d facing the trenches 306a and 306b are removable. Therefore, a capping layer 320 may be formed over the dielectric film 338a, and liners 324a to 324d covering the edge surfaces of dielectric layers 316 and 318 continuous with the capping layer 320 may be formed in the trenches 306a and 306b. The dielectric material 502 at the bottom of the trenches 306a and 306b is removable, and the semiconductor substrate 314 at the bottom of the trenches 306a and 306b is exposed.

[0042] Figure 6B This is a vertical cross-sectional view of a schematic structure of a portion 600 of a semiconductor device 100 according to an embodiment of the present disclosure. The capping layer 320 can be patterned using photolithography. A photoresist (not shown), such as a positive photoresist, can be applied to the capping layer 320. A mask (not shown) is provided over the photoresist. The mask may include an opening above the interconnect 330. The portion 600 below the opening can be exposed to UV light from above to remove the photoresist below the opening. Furthermore, etching (e.g., dry etching) can be performed to provide a hole 602 through the dielectric film 338a. The hole 602 may be disposed above the interconnect 330. In some embodiments, etching can be performed until a conductive line 334a on one end of the interconnect 330 in the dielectric film 338a is exposed. The photoresist can be removed in a post-etching process (e.g., dry ashing and wet cleaning).

[0043] After removing the photoresist, a barrier and conductive seed layer 604 may be deposited to cover the capping layer 320, the hole 602, and the trenches 306a and 306b. In some embodiments, the barrier and conductive seed layer 604 may be deposited by a physical vapor deposition (PVD) method, such as sputtering. The barrier and conductive seed layer 604 may comprise a barrier film and a conductive seed film. The barrier and conductive seed layer 604 may cover the hole 602, including the edge surface and bottom of the hole 602. The barrier and conductive seed layer 604 may include a conductive seed layer 328 at the bottom of the hole 602 on the exposed conductive line 334a. Figure 6B As described, dielectric layers 316 and 318 may have edge surfaces facing trenches 306a and 306b. A portion of the edge surfaces of dielectric layers 316 and 318 (including portions 322a and 322b in dielectric layer 316), extending up to dielectric film 338b, may be covered by liners 324a and 324b. Liner 324a may cover a portion 322a containing a recessed portion of the edge surface of dielectric layer 316. Liner 324a may further cover the edge surface of dielectric layer 318 facing trench 306a, continuous with capping layer 320. Similarly, liner 324b may cover the edge surfaces of dielectric layers 316 and 318 facing trench 306a, including portion 322b. Therefore, the top surfaces of liners 324a to 324d and the top surface of capping layer 320 may be covered by barrier and conductive seed layer 604. Because the liners 324a and 324b have less uniform surfaces compared to portions 322a and 322b, the barrier and conductive seed layer 604 can be deposited continuously and seamlessly on the top surface of portion 600. Therefore, Figure 3 The conductive pillar 326 can be successfully formed by electroplating on the conductive seed layer 328.

[0044] In some embodiments, the liner may cover the edge surface of the roughened lower dielectric film (e.g., a low-k film) facing the trench, but not the edge surface of the upper dielectric film above the lower dielectric film in the trench.

[0045] Figure 7 This is a vertical cross-sectional view of a schematic structure of a portion 700 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 7 The semiconductor substrate 314, dielectric layers 316 and 318, capping layer 320, sub-region 302, and dicing region 304 in 8 have the same characteristics as... Figure 3 The semiconductor substrate 314, dielectric layers 316 and 318, capping layer 320, sub-region 302, and dicing region 304 have similar structures. Therefore, for the sake of brevity, the description of the structure of the semiconductor substrate 314, dielectric layers 316 and 318, capping layer 320, sub-region 302, and dicing region 304 is omitted.

[0046] In some embodiments, a portion 700 of the semiconductor device 100 may include one or more liners 702a to 702d disposed in trenches 306a and 306b, the liners covering at least a portion of the edge surface of the dielectric layer 316. For example, liners 702a to 702d may comprise a dielectric material, such as silicon nitride (Si3N4) and / or silicon carbide (SiC). In some embodiments, portions 322a and 322b of the edge surface of the dielectric layer 316 in trench 306a may include recessed portions of dielectric films 336a to 336e facing the trench 306a. Liners 702a to 702d may cover the edge surface of the dielectric layer 316. For example, liners 702a and 702b in trench 306a may cover portions 322a and 322b. Liners 702a to 702d may not cover the edge surfaces of dielectric layer 318 facing trenches 306a and 306b. For example, in some embodiments, one or more of the layers 338 of dielectric layer 318 may be kept exposed by liners 702a to 702d.

[0047] The roughness of the liner surface facing the trench can be further controlled by removing the surface from the liner. In some embodiments, the etching (e.g., dry etching) cycle can be controlled. Figure 8AThis is a vertical cross-sectional view of a schematic structure of a portion 800 of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, the top portion of the dielectric material 502 and the non-uniform surfaces of the liners 504a to 504d facing trenches 306a and 306b can be removed by etching, the etching cycle being longer than the etching performed to form the liners 324a to 324d. Therefore, portions of the liners 324a to 324d covering at least a portion of the edge surfaces of the dielectric layer 318 facing trenches 306a and 306b can also be removed. Therefore, liners 702a to 702d can be formed covering the edge surfaces of the dielectric layer 316. Liners 702a and 702b can cover portions 322a and 322b including recessed portions of the edge surfaces of the dielectric layer 316. Liners 702a to 702d may not cover the edge surfaces of the dielectric layer 318 facing trenches 306a and 306b. In some embodiments, liners 702a and 702b may be continuous (e.g., without multiple recessed portions). In some embodiments, the surfaces of liners 702a and 702b may be smoother than portions 322a and 322b of the edge surface of dielectric layer 316.

[0048] Figure 8B This is a vertical cross-sectional view of a schematic structure of a portion 800 of a semiconductor device 100 according to an embodiment of the present disclosure. The overlay layer 320 is patterned using photolithography and etching to provide the aperture 602, similar to previous references. Figure 6B The patterning and etching of the cover layer 320 to provide the hole 602 is described and shown in the figure; therefore, for the sake of brevity, the description of patterning and etching to provide the hole is omitted.

[0049] After providing the aperture 602, a barrier and conductive seed layer 802 may be deposited to cover the capping layer 320, the aperture 602, and the trenches 306a and 306b. The deposition method and materials of the barrier and conductive seed layer 802 may be similar to those of the barrier and conductive seed layer 604; therefore, for simplicity, a description of the deposition method and materials of the barrier and conductive seed layer 802 is omitted. The barrier and conductive seed layer 802 may cover the aperture 602, including the edge surface and bottom of the aperture 602. The barrier and conductive seed layer 802 may include a conductive seed layer 328 at the bottom of the aperture 602. The conductive seed layer 328 may be disposed on the exposed conductive wire 334a. The barrier and conductive seed layer 802 may also be disposed in the trenches 306a and 306b. In some embodiments, the barrier and conductive seed layer 802 may continuously cover the edge surfaces of the liners 702a to 702d and the dielectric layer 318 facing the trenches 306a and 306b. The liners 702a to 702d may provide surfaces on which the barrier and conductive seed layer 802 may be deposited continuously and seamlessly. Therefore, Figure 7The conductive pillar 326 can be successfully formed by electroplating on the conductive seed layer 328.

[0050] In some embodiments, the liner and the dielectric film of the dielectric layer beneath the cover layer may together comprise a dielectric material, such as silicon dioxide (SiO2). In some embodiments, the liner may cover the roughened edge surface of the lower dielectric film (e.g., a low-k film) facing the trench, but not the edge surface of the upper dielectric film above the lower dielectric film in the trench.

[0051] Figure 9 This is a vertical cross-sectional view of a schematic structure of a portion 900 of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, the portion 900 of the semiconductor device 100 may be a multilayer structure. Figure 9 The multi-layered structure shown in the example is similar to that in the previous reference. Figure 3 Describe and illustrate the structure in the diagram. For example, Figures 9 to 15 The semiconductor substrate 914, dielectric layers 916 and 918, capping layer 920, sub-region 902, and dicing region 904 have the same characteristics as those in the semiconductor substrate 914, dielectric layers 916 and 918, capping layer 920, sub-region 902, and dicing region 904. Figure 3 The semiconductor substrate 914, dielectric layers 916 and 918, capping layer 920, sub-region 902, and dicing region 904 have similar structures. Therefore, for the sake of brevity, the description of the structure of the semiconductor substrate 914, dielectric layers 916 and 918, capping layer 920, sub-region 902, and dicing region 904 is omitted.

[0052] In some embodiments, a portion 900 of the semiconductor device 100 may include one or more liners 924a to 924d disposed in trenches 906a and 906b, the liners covering at least a portion of the edge surface of a dielectric layer 916. The dielectric layer 916 may comprise a low-k film. The liners 924a to 924d may comprise a dielectric material, such as silicon dioxide (SiO2). In some embodiments, the edge surface of the dielectric layer 916 may include portions 922a and 922b. Portions 922a and 922b may include recessed portions in the edge surface of dielectric films 936a to 936e facing the trench 906a. Each recessed portion in portions 922a and 922b may correspond to each of the dielectric films 936a to 936e between dielectric layers 940 above and below each dielectric film. The liners 924a to 924d may cover portions 922a and 922b. The liners 924a to 924d may not cover the edge surfaces of the dielectric layer 918 facing the trenches 906a and 906b. For example, in some embodiments, one or more of the layers 938 of the dielectric layer 918 may be kept exposed by the liners 924a to 924d.

[0053] Figure 10This is a vertical cross-sectional view of a schematic structure of a portion 1000 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 10 It can be in the process of forming Figure 9 A cross-sectional view of a portion 1000 of the semiconductor device 100 after etching trenches 906a and 906b. Trenches 906a and 906b can be formed by photolithography and etching. Prior to the etching process (not shown), cut regions 1002a and 1002b may include a semiconductor substrate 914, dielectric layers 916 and 918, and a capping layer 920. Each of the dielectric layers 916 (e.g., dielectric films 936a to 936e comprising a low-k material) and each of the dielectric layers 918 (e.g., dielectric films 938a to 938c) may be formed sequentially, while conductive lines 932a to 932e and through electrodes coupling conductive lines 932a to 932e may be formed through dielectric layers 916 and 940. In some embodiments, the dielectric layer 916 comprising a low-k material film is formed, for example, by a chemical vapor deposition (CVD) method.

[0054] The dielectric layer 918 (e.g., dielectric films 938a to 938c comprising silicon dioxide (SiO2)) can be repeatedly formed, while conductive lines 934a and 934b and through electrodes coupling conductive lines 934a to conductive lines 934b can be formed through the dielectric layer 918. In some embodiments, at least one dielectric film 938a disposed as the top layer of the dielectric layer 918 can be formed as plasma-enhanced tetraethyl orthosilicate (PE TEOS).

[0055] In some embodiments, the thickness of the dielectric film 938a containing the conductive line 934a beneath the cover layer 920 may be greater than the thickness of the dielectric film 938a between the circuit edge 908a and the interconnect 930 in the same cross-section. The thicker portion of the dielectric film 938a can provide support for the sub-region 902 and the diced region 904 containing the interconnect 930, thereby suppressing cracks around the interconnect in the sub-region 902 and the circuit edge 908a.

[0056] A capping layer 920 may be formed on a dielectric film 938a on top of a dielectric layer 918. Trench 906a and 906b may be provided by photolithography and etching, removing dielectric layers 916 and 918 and capping layer 920 from cut regions 1002a and 1002b. The process of providing trench 906a and 906b may be similar to that described in the previous reference. Figure 4 The trenches 306a and 306b are described and shown in the figure by photolithography and etching; therefore, for the sake of brevity, the description of photolithography and etching to provide trenches 906a and 906b in the cut areas 1002a and 1002b is omitted.

[0057] The surface roughness of the liner facing the trench can be further controlled by applying a thick dielectric material. Figure 11 This is a vertical cross-sectional view of a schematic structure of a portion 1100 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 11 This can be a cross-sectional view of a portion 1100 of a semiconductor device 100 after dielectric material 1102 is deposited over dielectric film 938a and in trenches 906a and 906b to form dielectric layers 1104a to 1104c on capping layer 920 and liners 1106a to 1106d in trenches 906a and 906b. Dielectric layers 1104a to 1104c may cover the entire capping layer 920. Liners 1106a to 1106d may cover the edge surfaces of dielectric layers 916 and 918 facing trenches 906a and 906b, including portions 922a and 922b of the edge surface of dielectric layer 918 facing trench 906a. In some embodiments, dielectric material 1102 may be silicon dioxide (SiO2) formed as plasma-enhanced tetraethyl orthosilicate (PETEOS) applied using a CVD method. The dielectric material 1102 may be applied thick enough to reduce the surface roughness of the liners 1106a to 1106d covering portions 922a and 922b.

[0058] The surface roughness of the liner facing the trench can be further controlled by removing non-uniform portions of the dielectric material from the liner. In some embodiments, the etching (e.g., dry etching) cycle can be controlled to completely remove the liner above the low-k film. Figure 12 This is a vertical cross-sectional view of a schematic structure of a portion 1200 of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, the non-uniform surfaces of dielectric layers 1104a to 1104c and liners 1106a to 1106d facing trenches 906a and 906b can be removed by etching. Therefore, portions of liners 1106a to 1106d covering the edge surfaces of dielectric layer 918 facing trenches 906a and 906b can also be removed. Therefore, liners 924a to 924d covering the edge surfaces of dielectric layer 916 can be formed. Liners 924a and 924c may cover portions 922a and 922b containing recessed portions of the edge surfaces of dielectric layer 916. Liners 924a to 924d may not cover the edge surfaces of dielectric layer 918 facing trenches 906a and 906b. In some embodiments, liners 924a and 924d may be continuous (e.g., without multiple recessed portions). In some embodiments, the surfaces of liners 924a and 924b may be smoother than portions 922a and 922b of the edge surface of dielectric layer 916.

[0059] Figure 13This is a vertical cross-sectional view of a schematic structure of a portion 1300 of a semiconductor device 100 according to an embodiment of the present disclosure. The overlay layer 920 is patterned using photolithography and etching to provide the aperture 1302, similar to previous references. Figure 6B The patterning and etching of the cover layer 320 to provide the hole 602 is described and shown in the figure; therefore, for the sake of brevity, the description of patterning and etching to provide the hole is omitted.

[0060] After providing the aperture 1302, a barrier and conductive seed layer 1304 may be deposited to cover the capping layer 920, the aperture 1302, and the liners 924a to 924d. The deposition method and materials of the barrier and conductive seed layer 1304 may be similar to those of the barrier and conductive seed layers 604 and 802; therefore, for simplicity, a description of the deposition method and materials of the barrier and conductive seed layer 1304 is omitted. The barrier and conductive seed layer 1304 may cover the aperture 1302, including the edge surface and bottom of the aperture 1302. The barrier and conductive seed layer 1304 may include a conductive seed layer 928 at the bottom of the aperture 1302. The conductive seed layer 928 may be disposed on exposed conductive lines 934a. The barrier and conductive seed layer 1304 may also be disposed in trenches 906a and 906b. In some embodiments, the barrier and conductive seed layer 1304 may continuously cover the edge surfaces of the liners 924a to 924d and the dielectric layer 918 facing the trenches 906a and 906b. The liners 924a to 924d may provide surfaces on which the barrier and conductive seed layer 1304 may be deposited continuously and seamlessly. Therefore, Figure 9 The conductive pillar 926 can be successfully formed by electroplating on the conductive seed layer 928.

[0061] The roughness of the liner surface facing the trench can be further controlled by removing a roughened surface from the liner. In some embodiments, an etching (e.g., dry etching) cycle can be controlled to remove a portion of the liner or retain the liner, comprising silicon dioxide (SiO2) formed as plasma-enhanced tetraethyl orthosilicate (PETEOS), as will be... Figures 14 to 15 As described in the text.

[0062] Figure 14 This is a vertical cross-sectional view of a schematic structure of a portion 1400 of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, the portion 1400 of the semiconductor device 100 may be a multilayer structure. Figure 14 The multi-layered structure 1400 shown in the image is similar to that in the previous reference. Figure 3 Describe and illustrate the structure in the diagram. For example, Figure 14 The semiconductor substrate 1412, dielectric layers 1414 and 1416, capping layer 1418, sub-region 1402, and dicing region 1404 have the same characteristics as those in the semiconductor substrate 1412, dielectric layers 1414 and 1416, capping layer 1418, sub-region 1402, and dicing region 1404. Figure 3The semiconductor substrate 314, dielectric layers 316 and 318, capping layer 320, sub-region 302, and dicing region 304 have similar structures. Therefore, for the sake of brevity, the description of the structure of semiconductor substrate 1412, dielectric layers 1414 and 1416, capping layer 1418, sub-region 1402, and dicing region 1404 is omitted.

[0063] In some embodiments, a portion 1400 of the semiconductor device 100 may include one or more liners 1424a to 1424d disposed in trenches 1406a and 1406b, the liners covering at least a portion of the edge surface of the dielectric layer 1414. The dielectric layer 1414 may comprise a low-k film. The liners 1424a to 1424d may comprise a dielectric material, such as silicon dioxide (SiO2). In some embodiments, the edge surface of the dielectric layer 1414 may include portions 1422a and 1422b. Portions 1422a and 1422b may include recessed portions in the edge surface of the dielectric layer 1414 facing the trench 1406a. Liners 1424a to 1424d may cover portions of 1422a and 1422b and a portion of the edge surfaces of dielectric layer 1416 facing trenches 1406a and 1406b, such as the edge surface of dielectric film 1420c adjacent to dielectric layer 1414. Liners 1424a to 1424d may not cover a portion of the edge surfaces of dielectric layer 1416 facing trenches 1406a and 1406b, such as the edge surface of dielectric film 1420a beneath cover layer 1418. For example, in some embodiments, one or more of layers 1420 of dielectric layer 1416 may be kept exposed by liners 1424a to 1424d. Liners 1424a to 1424d, together with the edge surfaces of dielectric film 1420a and possibly dielectric film 1420b, may provide surfaces on which barrier and conductive seed layers can be deposited continuously and seamlessly. Therefore, conductive pillars can be successfully formed through electroplating.

[0064] Figure 15 This is a vertical cross-sectional view of a schematic structure of a portion 1500 of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, the portion 1500 of the semiconductor device 100 may be a multilayer structure. Figure 15 The multi-layered structure shown in the example is similar to that in the previous reference. Figure 3 Describe and illustrate the structure in the diagram. For example, Figure 15 The semiconductor substrate 1512, dielectric layers 1514 and 1516, capping layer 1518, sub-region 1502, and dicing region 1504 have the same characteristics as... Figure 3The semiconductor substrate 314, dielectric layers 316 and 318, capping layer 320, sub-region 302, and dicing region 304 have similar structures. Therefore, for the sake of brevity, the description of the structure of semiconductor substrate 1512, dielectric layers 1514 and 1516, capping layer 1518, sub-region 1502, and dicing region 1504 is omitted.

[0065] In some embodiments, a portion 1500 of the semiconductor device 100 may include one or more liners 1524a to 1524d disposed in trenches 1506a and 1506b, the liners covering at least a portion of the edge surface of the dielectric layer 1514. The dielectric layer 1514 may comprise a low-k film. The liners 1524a to 1524d may comprise a dielectric material, such as silicon dioxide (SiO2). In some embodiments, the edge surface of the dielectric layer 1514 may include portions 1522a and 1522b. Portions 1522a and 1522b may include recessed portions in the edge surface of the dielectric layer 1514 facing the trench 1506a. Liners 1524a to 1524d may cover portions 1522a and 1522b and the edge surfaces of dielectric layer 1516 facing trenches 1506a and 1506b, such as the edge surfaces of dielectric films 1520a to 1520c between dielectric layer 1514 and capping layer 1518. Liners 1524a to 1524d may provide surfaces on which barrier and conductive seed layers may be deposited continuously and seamlessly. Thus, conductive pillars may be successfully formed by electroplating.

[0066] By providing a liner on the edge surface of a rough dielectric layer (e.g., a low-k film), barrier and conductive seed layers can be deposited continuously and seamlessly on the top surface of a semiconductor device. Therefore, conductive pillars can be successfully formed by electroplating through the barrier and conductive seed layers.

[0067] Although various embodiments have been disclosed in this disclosure, those skilled in the art will understand that the scope of this disclosure extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses, as well as their obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and remain within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form different embodiments. Therefore, it is intended that the scope of at least some aspects of this disclosure should not be limited to the specific disclosed embodiments described above.

Claims

1. An apparatus comprising: A multi-layered structure, comprising: A first circuit region, a second circuit region, and a segmented area between the first circuit region and the second circuit region; A substrate that spans the first circuit region and the second circuit region; Multiple dielectric layers are disposed above the substrate and span the first circuit region and the second circuit region, the multiple dielectric layers having trenches in the dicing region, the trenches including edge surfaces with roughness; as well as Multiple additional dielectric layers, each of which is located between adjacent dielectric layers; as well as At least one liner covering the edge surfaces of the plurality of dielectric layers and the plurality of additional dielectric layers to provide a smoother surface than the edge surfaces, wherein the at least one liner comprises a dielectric material.

2. The device according to claim 1, wherein the plurality of dielectric layers are a plurality of first dielectric layers. The multilayer structure further includes at least one second dielectric layer above the plurality of first dielectric layers, and The plurality of first dielectric layers comprise a first material, the dielectric constant of which is lower than that of a second material contained in the at least one second dielectric layer.

3. The device of claim 2, wherein the at least one liner comprises the second material.

4. The device according to claim 3, wherein the second material comprises silicon dioxide (SiO2).

5. The device of claim 2, further comprising a cover layer on the at least one second dielectric layer, the cover layer comprising a third material. The at least one liner therein comprises the third material.

6. The device according to claim 5, wherein the third material comprises at least one of silicon nitride (Si3N4) or silicon carbide (SiC).

7. The device of claim 5, wherein the at least one liner comprises a surface continuous with the cover layer.

8. The device of claim 2, wherein the at least one liner is further configured to cover at least a portion of the edge surface of the at least one second dielectric layer.

9. The device of claim 8, wherein the at least one liner is further configured to cover the edge surface of the at least one second dielectric layer.

10. The device according to claim 2, further comprising: The wires in the at least one second dielectric layer in the circuit region; The conductive seed layer on the wire; as well as A conductive post is disposed in a hole in at least one second dielectric layer, the conductive post being disposed on the conductive seed layer.

11. The device of claim 10, wherein the conductive post comprises at least one of copper or nickel.

12. A semiconductor chip comprising: Substrate; Multiple dielectric layers are disposed above the substrate, and the multiple dielectric layers include edge surfaces with roughness. Multiple additional dielectric layers, each of which is located between adjacent dielectric layers; as well as At least one liner covering the edge surfaces of the plurality of dielectric layers and the plurality of additional dielectric layers to provide a smoother surface than the edge surfaces, wherein the at least one liner comprises a dielectric material.

13. The semiconductor chip of claim 12, wherein the at least one liner comprises silicon dioxide (SiO2).

14. The semiconductor chip of claim 12, wherein the at least one liner comprises at least one of silicon nitride (Si3N4) or silicon carbide (SiC).

15. The semiconductor chip of claim 12, wherein the plurality of dielectric layers are a plurality of first dielectric layers, and wherein the semiconductor chip further comprises at least one second dielectric layer, and The at least one liner further covers at least a portion of the edge surface of the at least one second dielectric layer.

16. A method for manufacturing a chip, the method comprising: At least one first dielectric layer is formed over the substrate; At least one additional dielectric layer is formed above the at least one first dielectric layer; At least one second dielectric layer is formed over the at least one additional dielectric layer; A capping layer is formed over the at least one second dielectric layer; Trenches are formed over the substrate by etching; A liner is used to cover at least one edge surface of the at least one first dielectric layer and the at least one additional dielectric layer in the trench, wherein the liner comprises a dielectric material; Forming a hole through a portion of the cover layer and the at least one second dielectric layer; A conductive layer is deposited in the hole, on the cover layer, and on the liner; as well as Conductive pillars are formed on the conductive layer in the hole by electroplating.

17. The method of claim 16, further comprising depositing a dielectric material after forming the trench to simultaneously form the capping layer and the liner.

18. The method of claim 16, further comprising depositing a dielectric material to cover the capping layer and the trench.

19. The method of claim 18, wherein the dielectric material is deposited using plasma-enhanced tetraethyl orthosilicate (PE TEOS).

20. The method of claim 16, further comprising etching to remove a portion of the liner and leave another portion of the liner, the other portion covering the edge surface of the at least one first dielectric layer in the trench.

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