Semiconductor structure and method of forming the same

Abstract

The application discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate, and forming a core layer on the substrate; forming a spacing groove extending along a first direction and a plurality of first grooves arranged in parallel along the first direction in the core layer, the spacing groove has a size along a second direction less than or equal to twice a side wall width, and the first groove has a size along the second direction greater than twice the side wall width, in the first direction, adjacent first grooves are communicated through the spacing groove, or the first groove and the spacing groove are arranged in parallel along the second direction, wherein the second direction is parallel to a surface of the substrate and perpendicular to the first direction; forming a side wall covering a side wall of the first groove, and the side wall is also filled in the spacing groove as a spacing layer; after the spacing layer is formed, the remaining core layer is removed to form a second groove; and taking the side wall and the spacing layer as a mask, etching the substrate along the first groove and the second groove to form a target pattern. The embodiment of the application is favorable to improving the precision of pattern transfer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] In the development of integrated circuits, the functional density (i.e. the number of interconnects in each chip) usually increases gradually while the geometric size (i.e. the smallest component size that can be produced by process steps) gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, with the continuous shrinking of technology nodes, improving the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the accuracy of pattern transfer.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a plurality of first target structures located in the substrate, the first target structures extending along a first direction and arranged parallel to each other along a second direction, the second direction being parallel to the surface of the substrate and perpendicular to the first direction; a plurality of second target structures located in the substrate, the second target structures extending along the first direction and arranged parallel to each other along the second direction, wherein, in the second direction, the second target structures are located between adjacent first target structures and isolated from the first target structures; wherein, a first spacing exists between the second target structures and adjacent first target structures, and in the region between adjacent first target structures along the first direction, adjacent second target structures have a second spacing, the second spacing being less than or equal to twice the first spacing; or, a first spacing exists between the second target structures and adjacent first target structures, and a second spacing exists between adjacent second target structures on one side of the first target structure, the second spacing being less than or equal to twice the first spacing.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate on which a core layer is formed; forming in the core layer a spacer trench extending along a first direction and a plurality of parallel first trenches extending along the first direction, the spacer trench and the first trenches forming sidewalls, wherein the dimension of the spacer trench along a second direction is less than or equal to twice the width of the sidewalls, and the dimension of the first trenches along the second direction is greater than twice the width of the sidewalls; in the first direction, adjacent first trenches are connected through the spacer trench, or the first trenches and the spacer trenches are connected through the spacer trench. The grooves are arranged parallel to the second direction, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction; a sidewall is formed covering the sidewall of the first groove, the sidewall exposing the remaining space of the first groove, and the sidewall is also filled in the spacer groove, the sidewall in the spacer groove serving as a spacer layer; after forming the spacer layer, the remaining core layer is removed to form a second groove, in the second direction, adjacent second grooves are isolated by the sidewall or spacer layer; using the sidewall and spacer layer as a mask, the substrate is etched along the first and second grooves to form the target pattern.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure in which a second target structure has a first spacing with an adjacent first target structure, and in a region between adjacent first target structures along the first direction, adjacent second target structures have a second spacing, the second spacing being less than or equal to twice the first spacing; or, the second target structure has a first spacing with an adjacent first target structure, and adjacent second target structures on one side of the first target structure have a second spacing, the second spacing being less than or equal to twice the first spacing; in this invention, during the formation of the semiconductor structure, it is typically achieved by forming raised sidewalls and spacer layers on the substrate, and then... The first and second target structures are formed in the substrate beneath the space enclosed by the spacer layer. The sidewalls and spacer layer are typically formed using the sidewalls of the trenches and spacer slots in the core layer as supports. Compared to forming the first and second target structures directly in the substrate, by forming spacer slots with smaller dimensions in the second direction, the sidewalls fill the spacer slots as spacer layers during the formation of the trench sidewalls. Therefore, it is easier to form sidewalls and spacer layers with smaller dimensions in the second direction, and the dimensions and positions of the sidewalls and spacer layers are more precise. This is beneficial for accurately controlling the graphic accuracy of the first and second target structures, and correspondingly improves the accuracy of graphic transmission. Furthermore, the first spacing is determined by the width of the sidewalls, and the second spacing is less than or equal to twice the first spacing. This allows the sidewalls to fill the spacer slots, thereby isolating the heads of adjacent first target structures. Compared to directly using a mask layer to isolate the heads of the first target structures, as the feature size of integrated circuits continues to decrease, the probability of the heads of adjacent first target structures merging due to the proximity effect of the mask layer at the head-to-head position of the first target structures is reduced. While ensuring the isolation of the heads of the first target structures, the heads of the first target structures are brought as close as possible, forming a smaller, more compact semiconductor structure, thus improving... The method for forming the semiconductor structure is described above; or, there is a second spacing between adjacent second target structures on one side of the first target structure. Compared with the scheme of directly using a mask layer to isolate adjacent second target structures, as the feature size of the integrated circuit continues to decrease, the probability of adjacent second target structures merging due to the proximity effect generated by the mask layer when forming adjacent second target structures is reduced. While ensuring that adjacent second target structures are isolated from each other, the second target structures are brought as close as possible to form a semiconductor structure with smaller size and more compact components, thus improving the method for forming the semiconductor structure. In summary, the embodiments of the present invention are beneficial to improving the accuracy of pattern transmission.

[0010] In the forming method provided by this embodiment of the invention, the second direction is parallel to the surface of the core layer and perpendicular to the first direction, forming a sidewall covering the sidewall of the first trench. The sidewall also fills the spacer groove, and the sidewall in the spacer groove serves as a spacer layer. After forming the spacer layer, the remaining core layer is removed to form a second trench. In the second direction, adjacent second trenches are isolated by the sidewall or the spacer groove. In this embodiment of the invention, the sidewall and spacer layer are formed on the substrate. Using the sidewall and spacer layer as a mask, the substrate is etched along the first trench and the second trench to form a target pattern. The sidewall and spacer layer are formed on the substrate to... The sidewalls and spacer layers are masks. The substrate is etched along the first and second trenches to form the target pattern. Compared with the method of directly forming the target pattern in the substrate, by forming spacer grooves with smaller dimensions in the second direction, the sidewalls are formed on the sidewalls of the first trench and fill the spacer grooves during the formation of the sidewalls. Therefore, it is easy to form sidewalls and spacer layers with smaller dimensions in the second direction, and the size and position accuracy of the sidewalls and spacer layers are higher. This is beneficial for accurately controlling the pattern accuracy of the formed target pattern and improving the accuracy of pattern transfer. Furthermore, when adjacent first trenches pass through the spacer in the first direction... When the trenches are connected, the spacer layer formed in the spacer trench isolates the heads of adjacent first trenches. Compared with the solution of directly using a mask layer to isolate the heads of the first trenches, as the feature size of integrated circuits continues to decrease, the probability of the heads of adjacent first trenches merging due to the proximity effect of the mask layer at the head-to-head position of the first trench is reduced. While ensuring that the heads of the first trenches are isolated from each other, the heads of the first trenches are brought as close as possible, forming a smaller and more compact semiconductor structure, thus improving the semiconductor structure formation method; or, when the first trench and the spacer trench are along the second direction When arranged in parallel, adjacent second trenches are isolated from each other in the second direction by the sidewalls or spacers. Compared with the scheme of directly using a mask layer to isolate adjacent second trenches, as the feature size of integrated circuits continues to decrease, the probability of adjacent second trenches merging due to the proximity effect caused by the mask layer when forming adjacent second trenches is reduced. While ensuring the isolation of adjacent second trenches, the second trenches are brought as close as possible to form a smaller and more compact semiconductor structure, thus improving the semiconductor structure formation method. In summary, the embodiments of the present invention, by forming spacers, are beneficial to improving the accuracy of pattern transfer. Attached Figure Description

[0011] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 5 and Figure 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figure 7 and Figure 8 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0014] Figures 9 to 29 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0015] Figures 30 to 33 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0016] The accuracy of pattern transfer needs improvement. This paper analyzes the reasons for this need in conjunction with a semiconductor structure formation method.

[0017] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0018] Reference Figure 1 and Figure 2 ,in, Figure 2 yes Figure 1 A cross-sectional view along the AA direction shows a substrate 20 on which a dielectric layer 30 is formed; a mask layer 40 is formed on the dielectric layer 30, and a mask opening 41 is formed in the mask layer 40.

[0019] Reference Figure 3 and Figure 4 ,in, Figure 4 yes Figure 3 A top view shows the dielectric layer 30 being etched along the mask opening 41 using the mask layer 40 as an etching mask, forming a trench 31 in the dielectric layer 30.

[0020] As the feature size of integrated circuits continues to decrease, the distance between the trenches 31 becomes closer and closer. Consequently, the distance between the mask openings 41 in the mask layer used to form the trenches 31 also becomes closer and closer. Adjacent mask openings 41 are prone to proximity effects, especially when forming head-to-head trenches 31. The mask openings 41 at head-to-head positions (e.g., ...) Figure 2As shown by the dashed circle in the middle, the mask openings 41 are prone to merging at head-to-head positions due to the proximity effect, resulting in the corresponding trenches 31 merging at head-to-head positions; or, if the mask openings 41 are too close together at head-to-head positions due to the proximity effect, etching along the mask openings 41 will easily aggravate the proximity effect, thereby increasing the likelihood of the formed trenches 31 merging at head-to-head positions (e.g., as shown by the dashed circle in the middle). Figure 3 The probability of merging (shown by the dashed circle) will affect the transmission of patterns. In addition, in the prior art, in order to reduce the proximity effect of adjacent patterns, it is difficult to accurately transmit patterns with small distances, thus making it difficult to form semiconductor structures with smaller size and more compact components.

[0021] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which a core layer is formed; forming in the core layer a spacer trench extending along a first direction and a plurality of parallel first trenches extending along the first direction, the spacer trench and the first trenches serving to form sidewalls, wherein the dimension of the spacer trench along a second direction is less than or equal to twice the width of the sidewalls, and the dimension of the first trenches along the second direction is greater than twice the width of the sidewalls; in the first direction, adjacent first trenches are connected through the spacer trench, or the first trenches and the first trenches are connected through the spacer trench. The spacer grooves are arranged parallel to each other along the second direction, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction; a sidewall is formed covering the sidewall of the first trench, the sidewall exposing the remaining space of the first trench, and the sidewall is also filled in the spacer groove, the sidewall in the spacer groove serving as a spacer layer; after forming the spacer layer, the remaining core layer is removed to form a second trench, in the second direction, adjacent second trenches are isolated by the sidewall or the spacer layer; using the sidewall and the spacer layer as a mask, the substrate is etched along the first trench and the second trench to form a target pattern.

[0022] In the formation method provided by this embodiment of the invention, sidewalls and spacer layers are formed on a substrate. Using the sidewalls and spacer layers as masks, the substrate is etched along the first and second trenches to form a target pattern. Compared with the scheme of directly forming the target pattern in the substrate, by forming spacer grooves with smaller dimensions in the second direction, the sidewalls are formed on the sidewalls of the first trench and fill the spacer grooves during the formation of the sidewalls of the first trench. Therefore, it is easy to form sidewalls and spacer layers with smaller dimensions in the second direction, and the size and position accuracy of the sidewalls and spacer layers are higher. This is beneficial for accurately controlling the pattern accuracy of the formed target pattern and correspondingly improving the pattern transfer accuracy. Furthermore, when adjacent first trenches are connected through the spacer grooves in the first direction, the spacer layers formed in the spacer grooves isolate the heads of adjacent first trenches. Compared with the scheme of directly using mask layers to isolate the heads of the first trenches, as the feature size of integrated circuits continues to decrease, the mask layer at the head-to-head position of the first trench is reduced. The proximity effect reduces the probability of adjacent first trench heads merging, ensuring isolation between the heads of the first trenches while keeping them as close as possible to form a smaller, more compact semiconductor structure, thus improving the semiconductor structure formation method. Alternatively, when the first trench and the spacer trench are arranged parallel to each other along the second direction, adjacent second trenches are isolated by the sidewalls or spacer layers in the second direction. Compared to directly using a mask layer to isolate adjacent second trenches, as the feature size of integrated circuits continues to decrease, the probability of adjacent second trenches merging due to the proximity effect generated when the mask layer forms adjacent second trenches is reduced. This ensures isolation between adjacent second trenches while keeping them as close as possible to form a smaller, more compact semiconductor structure, thus improving the semiconductor structure formation method. In summary, the embodiments of the present invention, by forming spacer trenches, are beneficial to improving the accuracy of pattern transfer.

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figure 5 and Figure 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, wherein, Figure 6 It is a top view. Figure 5 yes Figure 6 A cross-sectional view along the AA direction.

[0025] The semiconductor structure includes: a substrate 11; and a plurality of first target structures 141 located in the substrate 11, wherein the first target structures 141 are arranged along a first direction (e.g., ...). Figure 6Extending in the X direction and along the second direction (e.g.) Figure 6 The first target structure 141 is arranged in parallel along the Y direction, which is parallel to the surface of the substrate 11 and perpendicular to the first direction. A plurality of second target structures 151 are located in the substrate 11, extending along the first direction and arranged in parallel along the second direction. In the second direction, the second target structures 151 are located between adjacent first target structures 141 and isolated from them. A first spacing s1 exists between the second target structures 151 and adjacent first target structures 141. In the region between adjacent first target structures 141 along the first direction, adjacent second target structures 151 have a second spacing s2, which is less than or equal to twice the first spacing s1.

[0026] In this embodiment, during the formation of the semiconductor structure, the first target structure 141 and the second target structure 151 are typically formed in the substrate below the space enclosed by the sidewalls and spacers after forming raised sidewalls and spacers on the substrate. Furthermore, the sidewalls and spacers are typically formed using the sidewalls of trenches and spacers in the core layer as supports. Compared to directly forming the first and second target structures in the substrate, by forming spacers with smaller dimensions in the second direction, the sidewalls fill the spacers as spacers during the formation of the trench sidewalls. Therefore, it is easier to form sidewalls and spacers with smaller dimensions in the second direction, and the size and position accuracy of the sidewalls and spacers are higher. This is beneficial for precisely controlling the pattern accuracy of the first target structure 141 and the second target structure 151, and correspondingly improves the precision of pattern transfer. Furthermore, the first spacing s1 is determined by the width of the sidewall, and the second spacing s2 is less than or equal to twice the first spacing s1. This allows the sidewall to fill the gap, thereby isolating the heads of adjacent first target structures 141. Compared with the scheme of directly using a mask layer to isolate the heads of the first target structures, as the feature size of the integrated circuit continues to decrease, the probability of the heads of adjacent first target structures 141 merging due to the proximity effect of the mask layer at the head-to-head position of the first target structures 141 is reduced. While ensuring that the heads of the first target structures 141 are isolated from each other, the heads of the first target structures 141 are made as close as possible, forming a smaller and more compact semiconductor structure, thus improving the semiconductor structure formation method. In summary, the embodiments of the present invention are beneficial to improving the accuracy of pattern transmission.

[0027] Moreover, in this embodiment, by forming a spacer layer with a smaller size in the second direction, the second spacing s2 is smaller in the second direction, thereby giving the second target structure 151 on both sides of the spacer layer a larger process window, which is beneficial to the formation of the second target structure 151.

[0028] In this embodiment, the substrate 11 includes a substrate structure layer 101, which includes a substrate. Taking a planar transistor as an example of the formed semiconductor structure, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, when the formed semiconductor structure is a finned field-effect transistor, the substrate can also be a substrate with fins.

[0029] The substrate structure layer 101 may also include other structures, such as gate structures, doped regions, shallow trench isolation (STI) structures, and dielectric layers, etc., in which devices (e.g., MOS transistors or SRAM devices) are formed. Specifically, the substrate structure layer 101 also includes an interlayer dielectric layer (not shown) formed on the substrate and contact plugs (CT) (not shown) formed in the interlayer dielectric layer.

[0030] In this embodiment, the substrate 11 includes a dielectric layer 111. Specifically, the dielectric layer 111 is located on top of the substrate structure layer 101.

[0031] In this embodiment, the dielectric layer 111 is an inter-metal dielectric (IMD) layer, used to achieve electrical isolation between metal interconnect structures in the back end of line (BEOL) process. As an example, the dielectric layer 111 is a first inter-metal dielectric layer used to achieve electrical isolation between first metal interconnects (i.e., M1 layers). Here, the first metal interconnect refers to the metal interconnect structure closest to the contact hole plug.

[0032] In other embodiments, the dielectric layer may also be another inter-metal dielectric located on the first metal interconnect, used to achieve electrical isolation between other interconnect structures. For example, the dielectric layer may be a second inter-metal dielectric, used to achieve electrical isolation between the second metal interconnect and the via interconnect structure located between the second metal interconnect and the first metal interconnect.

[0033] Therefore, the dielectric layer 111 is made of a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). In this embodiment, the dielectric layer 111 is made of one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the dielectric layer 111 is made of an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0034] The first target structure 141 and the second target structure 151 are corresponding structures formed according to different process requirements.

[0035] In this embodiment, the first target structure 141 is located in the dielectric layer 111, and the first target structure 141 is a first metal interconnect (not shown). The second target structure 151 is located in the dielectric layer 111, and the second target structure 151 is a second metal interconnect (not shown). The first metal interconnect and the second metal interconnect are isolated from each other by the dielectric layer 111.

[0036] It should be noted that the first metal interconnect and the second metal interconnect are metal interconnects on the same layer.

[0037] The first metal interconnect is used to electrically connect with the front interconnect structure below it, thereby realizing the electrical connection between the corresponding front interconnect structure and other circuits. The second metal interconnect is used to electrically connect with the front interconnect structure below it, thereby realizing the electrical connection between the corresponding front interconnect structure and other circuits.

[0038] In this embodiment, the material of the first metal interconnect includes one or more of copper, aluminum, and copper alloys, and the material of the second metal interconnect includes one or more of copper, aluminum, and copper alloys, thereby enabling the first and second metal interconnects to achieve better conductivity.

[0039] In this embodiment, in the second direction, the second target structure 151 is located between adjacent first target structures 141 and isolated from the first target structure 141, so both the first target structure 141 and the second target structure 151 are target structures with island characteristics.

[0040] The first metal interconnect and the second metal interconnect are both located in the dielectric layer 111, which isolates the first metal interconnect and the second metal interconnect from each other.

[0041] Figure 7 and Figure 8 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention, wherein, Figure 8 It is a top view. Figure 7 yes Figure 8 A cross-sectional view along the AA direction.

[0042] The similarities between the embodiments of the present invention and the foregoing embodiments will not be repeated here. The difference between the embodiments of the present invention and the foregoing embodiments is that: there is a first distance s1 between the second target structure 153 and the adjacent first target structure 143, and there is a second distance s2 between the adjacent second target structure 153 on one side of the first target structure 143, and the second distance s2 is less than or equal to twice the first distance s1.

[0043] A second spacing s2 is provided between adjacent second target structures 153 on one side of the first target structure 143. The second spacing s2 is formed by a raised isolation layer. Compared with the scheme of directly using a mask layer to isolate adjacent second target structures 153 from each other, as the feature size of the integrated circuit continues to decrease, the probability of adjacent second target structures 153 merging due to the proximity effect generated when the mask layer forms adjacent second target structures 153 is reduced. While ensuring that adjacent second target structures 153 are isolated from each other, the second target structures 153 are made as close as possible to form a semiconductor structure with smaller size and more compact components. This improves the semiconductor structure formation method. In summary, the embodiments of the present invention are beneficial to improving the accuracy of pattern transmission.

[0044] In this embodiment, the first target structure 143 is a first metal interconnect, and the second target structure 153 is a second metal interconnect. Both the first metal interconnect and the second metal interconnect are used to realize the electrical connection between the SRAM device formed in the substrate and the external circuit.

[0045] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0046] Figures 9 to 29 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0047] refer to Figure 9 A substrate 10 is provided, on which a core layer 300 is formed.

[0048] In this embodiment, the substrate 10 includes a substrate structure layer 100, which includes a substrate. Taking a planar transistor as an example of the formed semiconductor structure, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, when the formed semiconductor structure is a finned field-effect transistor, the substrate can also be a substrate with fins.

[0049] The substrate structure layer 100 may also include other structures, such as gate structures, doped regions, shallow trench isolation (STI) structures, and dielectric layers, wherein devices (e.g., MOS transistors or SRAM devices) are formed in the substrate structure layer 100. Specifically, the substrate structure layer 100 also includes an interlayer dielectric layer (not shown) formed on the substrate and contact (CT) plugs (not shown) formed in the interlayer dielectric layer.

[0050] In this embodiment, the step of providing the substrate 10 includes: a dielectric layer 110 and a hard mask material layer 200 located on the dielectric layer 110.

[0051] In this embodiment, the dielectric layer 110 is an inter-metal dielectric (IMD) layer, used to achieve electrical isolation between metal interconnect structures in the back end of line (BEOL) process. As an example, the dielectric layer 110 is a first inter-metal dielectric layer used to achieve electrical isolation between first metal interconnects (i.e., M1 layers). Here, the first metal interconnect refers to the metal interconnect structure closest to the contact hole plug.

[0052] In other embodiments, the dielectric layer may also be another inter-metal dielectric located on the first metal interconnect, used to achieve electrical isolation between other interconnect structures. For example, the dielectric layer may be a second inter-metal dielectric, used to achieve electrical isolation between the second metal interconnect and the via interconnect structure located between the second metal interconnect and the first metal interconnect.

[0053] Therefore, the dielectric layer 110 is made of a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). In this embodiment, the dielectric layer 110 is made of one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the dielectric layer 110 is made of an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0054] After the hard mask material layer 200 is patterned, the pattern is transferred downward through the patterned hard mask material layer 200. The hard mask material layer 200 helps to improve the stability of the patterning process and the accuracy of pattern transfer.

[0055] In this embodiment, the material of the hard mask (HM) material layer 200 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, and tungsten nitride. As an example, the hard mask material layer 200 is a metallic hard mask material layer, and the material of the hard mask material layer 200 is titanium nitride.

[0056] The core layer 300 provides a platform foundation for the subsequent formation of the spacer slot, the first trench, and the second trench, thereby transmitting the graphics downwards. The first trench defines the shape and position of a portion of the target graphic, while the second trench defines the shape and position of the remaining target graphics, which consequently improves the graphic accuracy of the target graphics.

[0057] In addition, side walls will be formed on the side walls of the core layer 300, and the core layer 300 will also provide support for the formation of the side walls.

[0058] The core layer 300 will be removed subsequently. Therefore, the material of the core layer 300 is one that is easy to remove, thereby reducing the difficulty of removing the core layer 300 and minimizing damage to other films located below the core layer 300. Therefore, the material of the core layer 300 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning film (APF) materials, spin-on carbon (SOC), and silicon carbide. In this embodiment, the core layer 300 is amorphous silicon (a-Si).

[0059] Reference Figures 10 to 17 In the core layer 300, a first direction (e.g.) is formed. Figure 17The spacer groove 330 extends in the X direction (as shown in the middle X direction), and a plurality of parallel first grooves 310 extend along the first direction. The spacer groove 330 and the first grooves 310 are used to form sidewalls. The spacer groove 330 extends along the second direction (as shown in the middle X direction). Figure 17 The dimension w1 of the first groove 310 (in the Y direction) is less than or equal to twice the width of the sidewall, and the dimension w2 of the first groove 310 in the second direction is greater than twice the width of the sidewall. In the first direction, adjacent first grooves 310 are connected by the spacer 330. The second direction is parallel to the surface of the base 10 and perpendicular to the first direction.

[0060] Subsequently, a sidewall is formed covering the sidewall of the first trench 310. The sidewall exposes the remaining space of the first trench 310 and also fills the spacer groove 330. The sidewall in the spacer groove 330 serves as a spacer layer. After the spacer layer is formed, the remaining core layer 300 is removed to form a second trench. Using the sidewall and spacer layer as a mask, the substrate 10 is etched along the first trench 310 and the second trench to form a target pattern. Compared with the method of directly forming the target pattern in the substrate, by forming a spacer groove 330 with a smaller size in the second direction, the sidewall is formed on the sidewall of the first trench 310 and fills the spacer groove 330 during the formation of the sidewall of the first trench 310. Therefore, it is easy to form a sidewall and spacer layer with a smaller size in the second direction, and the size and position of the sidewall and spacer layer are more accurate. This is correspondingly beneficial for accurately controlling the formed target pattern. The improved pattern accuracy correspondingly enhances the pattern transmission accuracy. Furthermore, when adjacent first trenches 310 are connected via the spacer 330 in the first direction, the spacer layer formed in the spacer 330 isolates the heads of adjacent first trenches 310. Compared to the scheme of directly using a mask layer to isolate the heads of the first trenches, as the feature size of the integrated circuit continues to decrease, the probability of the heads of adjacent first trenches 310 merging due to the proximity effect of the mask layer at the head-to-head position of the first trenches 310 is reduced. While ensuring the isolation of the heads of the first trenches 310, the heads of the first trenches 310 are brought as close as possible, forming a smaller and more compact semiconductor structure, thus improving the semiconductor structure formation method. In summary, the embodiment of the present invention, by forming the spacer 330, is beneficial to improving the pattern transmission accuracy.

[0061] Furthermore, in this embodiment, by forming a spacer layer with a smaller size in the second direction, the process of etching the target patterns on both sides of the spacer layer using the spacer layer as a mask has a larger process window, which is beneficial to the formation of the target patterns.

[0062] In this embodiment, the dimension w1 of the spacer groove 330 along the second direction is less than or equal to twice the width of the sidewall. When the sidewall is formed subsequently, the sidewall can fill the spacer groove 330, so that the spacer layer is formed at the same time as the sidewall, which simplifies the process and improves the process efficiency.

[0063] In this embodiment, the dimension w2 of the first trench 310 along the second direction is greater than twice the width of the sidewall. After the sidewall is formed, when the sidewall layer is filled in the spacer groove 330, there is still space between the sidewalls in the first trench 310, so that the substrate 10 can be etched using the remaining space of the first trench 310.

[0064] In this embodiment, in the first direction, adjacent first trenches 310 are connected by the spacer groove 330. After a spacer layer is formed in the spacer groove 330, the spacer layer is used to isolate adjacent first trenches 310 in the extension direction of the first trench 310.

[0065] In this embodiment, the first groove 310 is formed after the spacer 330 is formed.

[0066] The spacer groove 330 is smaller in size than the first trench 310. Therefore, the spacer groove 330 is formed first, which helps to reduce the influence of the larger first trench 310 in the core layer 300 on the position of the spacer groove 330. Moreover, the spacer groove 330 can be used to define the position of the first trench 310 formed later.

[0067] Reference Figure 10 and Figure 11 ,in, Figure 11 It is a top view. Figure 10 yes Figure 11 A cross-sectional view along the BB direction shows that the step of forming the spacer groove 330 in the core layer 300 includes: forming a first mask layer 400 on the core layer 300, wherein a first opening 410 is formed in the first mask layer 400, and the extension direction of the first opening 410 is a first direction.

[0068] The first mask layer 400 is used as an etching mask for forming the spacer 330, and the first opening 410 is used to define the size, position and morphology of the spacer 330.

[0069] Reference Figure 12 and Figure 13 ,in, Figure 13 It is a top view. Figure 12 yes Figure 13 A cross-sectional view along the BB direction shows the core layer 300 exposed by the first opening 410 removed, forming the spacer groove 330.

[0070] Using the first opening 410 as a mask opening, the core layer 300 exposed by the first opening 410 is removed, thereby transferring the pattern of the first opening 410 to the core layer 300, which is beneficial to improving the morphological quality and dimensional accuracy of the spacer slot 330.

[0071] In this embodiment, the core layer 300 is etched using a dry etching process to form the spacer groove 330.

[0072] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the substrate 10 at the bottom of the spacer groove 330. At the same time, the dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the spacer groove 330.

[0073] In this embodiment, after the spacer 330 is formed, the first mask layer 400 is removed.

[0074] Remove the first mask layer 400 to prepare for subsequent processes.

[0075] Reference Figure 14 and Figure 15 ,in, Figure 15 It is a top view. Figure 14 yes Figure 15 A cross-sectional view along the AA direction shows that the step of forming the first trench 310 in the core layer 300 includes: forming a second mask layer 500 on the core layer 300, wherein the second mask layer 500 has a plurality of parallel second openings 520 extending along the first direction, and the dimension w1 of the spacer groove 330 along the second direction is (e.g., ...). Figure 13 (As shown) is smaller than the dimension w3 of the second opening 520 along the second direction, and in the first direction, adjacent second openings 520 are connected by the spacer slot 330.

[0076] The second mask layer 500 is used as an etching mask for forming the first trench 310, and the second opening 520 is used to define the size, position and morphology of the first trench 310.

[0077] The dimension w1 of the spacer groove 330 along the second direction is smaller than the dimension w3 of the second opening 520 along the second direction. In the first direction, adjacent second openings 520 are connected through the spacer groove 330. Therefore, the dimension w2 of the first groove 310 formed with the second opening 520 as a mask opening is the same as the dimension w3 of the second opening 520 along the second direction. Thus, the dimension w1 of the spacer groove 330 along the second direction is smaller than the dimension w2 of the first groove 310 along the second direction. In the first direction, adjacent first grooves 310 are connected through the spacer groove 330.

[0078] Reference Figure 16 and Figure 17 ,in, Figure 17 It is a top view. Figure 16 yes Figure 17 A cross-sectional view along the AA direction shows the core layer 300 exposed by the second opening 520 removed, forming the first trench 310.

[0079] In this embodiment, the core layer 300 is etched using a dry etching process to form the first trench 310.

[0080] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the substrate 10 at the bottom of the first trench 310. At the same time, the dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the first trench 310.

[0081] In this embodiment, after the first trench 310 is formed, the second mask layer 500 is removed.

[0082] Remove the second mask layer 500 to prepare for subsequent processes.

[0083] Continue to refer to Figure 17 In the step of forming the first groove 310, in the first direction, adjacent first grooves 310 are connected by the spacer 330, and the first groove 310 and the connected spacer 330 partially overlap at the head position.

[0084] The first groove 310 and the connected spacer groove 330 partially overlap at the head position, which helps to ensure that the spacer groove 330 between adjacent first grooves 310 is connected. Furthermore, during the formation of the spacer groove 330, the spacer groove 330 along the first direction (e.g., Figure 17 The length of the spacer 330 (as shown in the X direction) is increased to increase the process window for forming the spacer 330.

[0085] like Figure 17 As shown, Figure 17 The dashed box in the figure represents the original outline of the spacer slot 330.

[0086] Correspondingly, such as Figure 15 As shown, in the step of forming the second mask layer 500 on the core layer 300, in the first direction, the second opening 520 also exposes the adjacent partial spacer groove 330.

[0087] Reference Figures 18 to 21 A sidewall 350 is formed that covers the sidewall of the first trench 310. The sidewall 350 exposes the remaining space of the first trench 310 and is also filled in the spacer groove 330. The sidewall 350 in the spacer groove 330 serves as a spacer layer 340.

[0088] The sidewall 350 is used to subsequently isolate the second trench from the first trench 310, preventing the second trench from becoming connected to the first trench 310, and ensuring that the spacing between adjacent second trenches and first trenches 310 meets the designed minimum space. The spacer layer 340 is used to isolate adjacent first trenches 310 in the first direction and adjacent second trenches in the second direction. Furthermore, when the pattern of the second trench and first trench 310 is subsequently transferred to the substrate 10, the sidewall 350 serves as a mask for etching the substrate 10. Additionally, the sidewall 350 is used to adjust the spacing between the second trench and first trench 310 in the second direction.

[0089] The sidewall 350 is made of a material that is etch-selective with the core layer 300. The material of the sidewall 350 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the sidewall layer 150 is titanium oxide.

[0090] Therefore, in this embodiment, the material of the spacer layer 340 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the spacer layer 340 is titanium oxide.

[0091] Reference Figure 18 and Figure 19 ,in, Figure 19 It is a top view. Figure 18 yes Figure 19 A cross-sectional view along the AA direction shows that the steps of forming the sidewall 350 include: forming a sidewall material layer 600 that conformally covers the top of the core layer 300, the bottom and sidewall of the first trench 310, and the bottom and sidewall of the spacer groove 330, wherein the sidewall material layer 600 is in contact with the sidewall of the spacer groove 330 opposite to the sidewall.

[0092] The sidewall material layer 600 is used to form the sidewall 350 and the spacer layer 340. The sidewall material layer 600 located on the opposite sidewall of the spacer groove 330 is in contact with the spacer groove 330, so that the sidewall material layer 600 fills the spacer groove 330.

[0093] In this embodiment, the sidewall material layer 600 is formed using atomic layer deposition (ALD).

[0094] The sidewall material layer 600 formed by atomic layer deposition has good thickness uniformity and good step coverage, which allows the sidewall material layer 600 to cover the top of the core layer 300, the bottom and sidewall of the first trench 310, and the bottom and sidewall of the spacer groove 330 in good shape preservation.

[0095] In this embodiment, the material of the sidewall material layer 600 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, and is used to directly form the sidewall 350 and the spacer layer 340.

[0096] Reference Figure 20 and Figure 21 ,in, Figure 21 It is a top view. Figure 20 yes Figure 21 In the cross-sectional view along the AA direction, the sidewall material layer 600 located at the top of the core layer 300 and the bottom of the first trench 310 is removed, and the sidewall material layer 600 located in the sidewall of the first trench 310 and the spacer groove 330 is retained as the sidewall 350, and the sidewall 350 filled in the spacer groove 330 is used as the spacer layer 340.

[0097] Removing the sidewall material layer 600 located at the top of the core layer 300 and the bottom of the first trench 310 can better expose the top surface of the core layer 300, thereby reducing the difficulty of the subsequent removal of the core layer 300 and preparing for the subsequent pattern transfer using the sidewall 350 and the spacer layer 340 as etching masks.

[0098] In this embodiment, a dry etching process is used to remove the sidewall material layer 600 located at the top of the core layer 300 and the bottom of the first trench 310.

[0099] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the sidewall 350 and the substrate 10. At the same time, the dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the sidewall 350 and the spacer layer 340.

[0100] Reference Figure 22 and Figure 23 ,in, Figure 23 It is a top view. Figure 22 yes Figure 23 In a cross-sectional view along the AA direction, after the spacer layer 340 is formed, the remaining core layer 300 is removed to form a second trench 320. In the second direction, adjacent second trenches 320 are isolated by the sidewall 350 or the spacer layer 340.

[0101] The second groove 320 is used to define the shape, size, and position of a portion of the target graphic formed in the substrate 10. In this embodiment, by first forming the first groove 310 in the core layer 300 and then using the sidewall 350 and the spacer layer 340 to form the second groove 320, the graphic accuracy of the first groove 310 and the second groove 320 is improved, thereby improving the graphic accuracy of the target graphic and correspondingly improving the accuracy of graphic transmission.

[0102] Furthermore, the formation of the first trench 310 and the second trench 320 in this embodiment is beneficial to improving the process window for forming the first trench 310 and the second trench 320 (e.g., improving the optical proximity effect or alleviating the limitation of photolithography process resolution), thereby ensuring the pattern accuracy of the first trench 310 and the second trench 320.

[0103] In this embodiment, a maskless etching process is used to remove the core layer 300. The etching selectivity ratios between the core layer 300, the sidewalls 350, the isolation layer 340, and the substrate 10 are all relatively high. Therefore, the damage to other film layers is minimal during the removal of the core layer 300. Consequently, a maskless etching process can be used to remove the core layer 300, thereby simplifying the process steps and reducing costs. Furthermore, by selecting a maskless etching process, the process window for forming the second trench 320 is significantly increased.

[0104] In this embodiment, a wet etching process is used to remove the core layer 300. The wet etching process removes the core layer 300 through a chemical reaction, which helps to reduce damage to the sidewalls 350 and the isolation layer 340, and also helps to completely remove the core layer 300. In this embodiment, the material of the core layer 300 is amorphous silicon, and the etching solution used in the wet etching process is a mixed solution of Cl2 and HBr or a TMAH solution.

[0105] Reference Figures 24 to 29 Using the sidewall 350 and the spacer layer 340 as a mask, the substrate 10 is etched along the first trench 310 and the second trench 320 to form the target pattern.

[0106] The first groove 310 and the second groove 320 have high morphological quality, dimensional accuracy and positional accuracy, thereby improving the graphic accuracy of the target graphic and correspondingly improving the accuracy of graphic transmission.

[0107] Reference Figure 24 and Figure 25 ,in, Figure 25 It is a top view. Figure 24 yes Figure 25 A cross-sectional view along the AA direction, using the sidewall 350 and spacer layer 340 as masks, the step of etching the substrate 10 along the first trench 310 and the second trench 320 includes: etching the hard mask material layer 200 along the first trench 310 and the second trench 320, forming a mask opening (not shown) in the hard mask material layer 200, the mask opening serving as a target pattern, and the remaining hard mask material layer 200 serving as a hard mask layer 230, wherein the mask opening formed by etching along the first trench 310 serves as the first target pattern 210, and the mask opening formed by etching along the second trench 320 serves as the second target pattern 220.

[0108] The hard mask layer 230 is used as a mask for the patterned dielectric layer 110. The patterns of the first trench 310 and the second trench 320 are transferred to the hard mask layer 230, and the pattern accuracy of the mask openings is correspondingly high.

[0109] Reference Figure 26 and Figure 27 ,in, Figure 27 It is a top view. Figure 26 yes Figure 27 A cross-sectional view along the AA direction shows that after the target pattern is formed, the forming method further includes: using the hard mask layer 230 as a mask, etching the dielectric layer 110 along the mask opening to form interconnect trenches (not shown), wherein the interconnect trench corresponding to the first target pattern 210 is the first interconnect trench 120, and the interconnect trench corresponding to the second target pattern 220 is the second interconnect trench 130.

[0110] The first interconnect trench 120 and the second interconnect trench 130 provide spatial locations for the formation of metal interconnects. The high pattern precision of the mask openings improves the pattern precision of the interconnect trenches, ensuring that the morphology and layout of the metal interconnects meet design requirements, thereby improving the performance of the metal interconnects. It should be noted that as circuit integration increases, the design complexity of the subsequent metal wiring becomes increasingly higher, and the spacing between adjacent metal interconnects becomes smaller. By forming the first trench 310 and the second trench 320 as described above, the positional accuracy, morphological quality, and dimensional accuracy of the metal interconnects are significantly improved, thereby enhancing the performance and reliability of the semiconductor structure.

[0111] In this embodiment, after the interconnect trench is formed, the mask layer 230 is removed to prepare for the subsequent formation of metal interconnects.

[0112] Reference Figure 28 and Figure 29 ,in, Figure 29 It is a top view. Figure 28 yes Figure 29 A cross-sectional view along the AA direction shows that a first metal interconnect 140 is formed in the first interconnect trench 120, and a second metal interconnect 150 is formed in the second interconnect trench 130.

[0113] The first metal interconnect 140 is used to electrically connect with the underlying front interconnect structure, thereby realizing the electrical connection between the corresponding front interconnect structure and other circuits.

[0114] In this embodiment, the material of the first metal interconnect 140 includes one or more of copper, aluminum, and copper alloys to achieve better conductivity.

[0115] The second metal interconnect 150 is used to electrically connect with the underlying front interconnect structure, thereby enabling the corresponding front interconnect structure to be electrically connected to other circuits.

[0116] In this embodiment, the material of the second metal interconnect includes one or more of copper, aluminum, and copper alloys to achieve better conductivity.

[0117] Figures 30 to 33 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.

[0118] The similarities between this embodiment and the foregoing embodiments will not be repeated here. The difference between this embodiment and the foregoing embodiments is that: the first groove 312 and the spacer groove 332 are along the second direction (e.g., Figure 33 (As shown in the Y direction) Arranged in parallel.

[0119] Reference Figures 32 to 33 ,in, Figure 33 It is a top view. Figure 32 yes Figure 33 In a cross-sectional view along the AA direction, the first groove 312 and the spacer groove 332 are arranged parallel to each other along the second direction.

[0120] When the first groove 312 and the spacer 332 are arranged parallel to each other along the second direction, adjacent second grooves (located in the second direction) are... Figure 33At the core layer 302 location, the second trenches are isolated by the sidewalls or spacers. Compared with the solution of directly using a mask layer to isolate adjacent second trenches, as the feature size of the integrated circuit continues to decrease, the probability of adjacent second trenches merging due to the proximity effect caused by the mask layer when forming adjacent second trenches is reduced. While ensuring the isolation of adjacent second trenches, the second trenches are brought as close as possible to form a smaller and more compact semiconductor structure, thus improving the semiconductor structure formation method. In summary, the embodiment of the present invention, by forming spacer trenches 332, is beneficial to improving the accuracy of pattern transfer.

[0121] In this embodiment, the metal interconnects subsequently formed in the first trench 312 and the second trench are used to realize the electrical connection between the SRAM device formed in the substrate and the external circuit.

[0122] Specifically, in conjunction with reference Figure 30 and Figure 31 ,in, Figure 31 It is a top view. Figure 30 yes Figure 31 In the cross-sectional view along the AA direction, during the step of forming the second mask layer 502 on the core layer 302, the second opening 522 in the second mask layer 502 and the spacer groove 332 are arranged parallel to each other along the second direction, thereby forming the first trench 312 which is arranged parallel to the spacer groove 332 along the second direction.

[0123] For a detailed description of the formation method described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0124] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; Multiple first target structures are located in the substrate, the first target structures extend along a first direction and are arranged in parallel along a second direction, the second direction being parallel to the surface of the substrate and perpendicular to the first direction; Multiple second target structures are located in the substrate. The second target structures extend along the first direction and are arranged in parallel along the second direction. In the second direction, the second target structures are located between adjacent first target structures and are isolated from the first target structures. Wherein, the second target structure has a first spacing with the adjacent first target structure, and in the region between the adjacent first target structures along the first direction, the adjacent second target structures have a second spacing, the second spacing being less than or equal to twice the first spacing; Alternatively, the second target structure has a first spacing with the adjacent first target structure, and the adjacent second target structures on one side of the first target structure have a second spacing, wherein the second spacing is less than or equal to twice the first spacing.

2. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a dielectric layer; The first target structure is located in the dielectric layer, and the first target structure is a first metal interconnect. The second target structure is located in the dielectric layer, and the second target structure is a second metal interconnect.

3. The semiconductor structure as described in claim 2, characterized in that, The dielectric layer material includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.

4. The semiconductor structure as described in claim 2, characterized in that, The material of the first metal interconnect includes one or more of copper, aluminum, and copper alloys, and the material of the second metal interconnect includes one or more of copper, aluminum, and copper alloys.

5. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a core layer is formed; In the core layer, a spacer groove extending along a first direction and a plurality of parallel first trenches extending along the first direction are formed. The spacer groove and the first trenches are used to form sidewalls. The dimension of the spacer groove along a second direction is less than or equal to twice the width of the sidewalls, and the dimension of the first trenches along the second direction is greater than twice the width of the sidewalls. In the first direction, adjacent first trenches are connected by the spacer grooves. Alternatively, the first trenches and the spacer grooves are arranged in parallel along the second direction, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction. A sidewall is formed that covers the sidewall of the first trench, the sidewall is exposed in the remaining space of the first trench, and the sidewall is also filled in the spacer groove, the sidewall in the spacer groove serving as a spacer layer; After the spacer layer is formed, the remaining core layer is removed to form a second trench. In the second direction, adjacent second trenches are isolated from each other by the sidewall or the spacer layer. Using the sidewalls and spacer layer as a mask, the substrate is etched along the first and second trenches to form the target pattern.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, After the spacer slots are formed, the first trench is formed.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The step of forming the sidewall includes: forming a sidewall material layer that conformally covers the top of the core layer, the bottom and sidewall of the first trench, and the bottom and sidewall of the spacer trench, wherein the sidewall material layers located on the opposite sidewall of the spacer trench are in contact with each other; Remove the sidewall material layers located at the top of the core layer and the bottom of the first trench, retain the sidewall material layers located in the sidewalls of the first trench and the spacer groove as sidewalls, and fill the sidewalls in the spacer groove as spacer layers.

8. The method for forming a semiconductor structure as described in claim 5, characterized in that, In the step of forming the first groove, adjacent first grooves are connected by the spacer groove in the first direction, and the first groove and the connected spacer groove partially overlap at the head position.

9. The method for forming a semiconductor structure as described in claim 5, characterized in that, The step of forming a spacer groove in the core layer includes: forming a first mask layer on the core layer, wherein a first opening is formed in the first mask layer, and the extension direction of the first opening is a first direction; Remove the core layer exposed by the first opening to form the spacer groove; After the spacer groove is formed, the first mask layer is removed.

10. The method for forming a semiconductor structure as described in claim 5, characterized in that, The step of forming a first trench in the core layer includes: forming a second mask layer on the core layer, wherein a plurality of parallel second openings are formed in the second mask layer extending along the first direction, the size of the spacer groove along the second direction is smaller than the size of the second opening along the second direction, and in the first direction, adjacent second openings are connected through the spacer groove, or the second openings and the spacer groove are arranged parallel to each other along the second direction; Remove the core layer exposed by the second opening to form the first trench; After the first trench is formed, the second mask layer is removed.

11. The method for forming a semiconductor structure as described in claim 5, characterized in that, The core layer is etched using a dry etching process to form the spacer trench.

12. The method for forming a semiconductor structure as described in claim 5, characterized in that, The core layer is etched using a dry etching process to form the first trench.

13. The method for forming a semiconductor structure as described in claim 5, characterized in that, In the step of forming the second trench, the core layer is removed using a wet etching process.

14. The method for forming a semiconductor structure as described in claim 7, characterized in that, The sidewall material layer is formed using atomic layer deposition (ALD) technology.

15. The method for forming a semiconductor structure as described in claim 5, characterized in that, The core layer material includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning materials, spin-coated carbon, and silicon carbide.

16. The method for forming a semiconductor structure as described in claim 5, characterized in that, The sidewall material includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

17. The method for forming a semiconductor structure as described in claim 5, characterized in that, In the step of providing a substrate, the substrate includes: a dielectric layer and a hard mask material layer located on the dielectric layer; The step of etching the substrate along the first trench and the second trench using the sidewall and the spacer layer as masks includes: etching the hard mask material layer along the first trench and the second trench, forming a mask opening in the hard mask material layer, the mask opening serving as a target pattern, and the remaining hard mask material layer serving as a hard mask layer, wherein the mask opening formed by etching along the first trench serves as the first target pattern, and the mask opening formed by etching along the second trench serves as the second target pattern; After forming the target pattern, the forming method further includes: using the hard mask layer as a mask, etching the dielectric layer along the mask opening to form interconnect trenches, wherein the interconnect trenches corresponding to the first target pattern are first interconnect trenches and the interconnect trenches corresponding to the second target pattern are second interconnect trenches; forming a first metal interconnect line in the first interconnect trench and forming a second metal interconnect line in the second interconnect trench.

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