Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device may include: a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers alternately stacked; and a plurality of via plugs respectively and exclusively connected to the plurality of word lines by vertically penetrating the word line stack in the via plug region. When viewed from a top view, the via plugs may have a Z-shaped pattern arrangement in a row direction. The diameter of the via plugs may increase in the row direction.

Description

Technical Field

[0001] The present disclosure relates to a three-dimensional semiconductor device including a plurality of via plugs having different vertical lengths arranged in a zigzag pattern. Background Art

[0002] Recently, the increase in capacity and miniaturization of three-dimensional semiconductor devices have been continuously carried out. As a result, signal delay and voltage drop phenomena caused by the stacking of three-dimensional semiconductor devices have emerged as special problems. Summary of the Invention

[0003] Embodiments of the present invention provide a three-dimensional semiconductor device including a via plug region provided between cell regions and a method for manufacturing the three-dimensional semiconductor device.

[0004] Embodiments of the present invention provide a three-dimensional semiconductor device in which cells in a cell region share the same word line and a method for manufacturing the three-dimensional semiconductor device.

[0005] Embodiments of the present invention are directed to providing a three-dimensional semiconductor device having via plugs arranged in a Z-shaped pattern in a via plug region and a method for manufacturing the three-dimensional semiconductor device.

[0006] Embodiments of the present invention provide a three-dimensional semiconductor device including via plugs having different diameters and a method for manufacturing the three-dimensional semiconductor device.

[0007] According to an embodiment of the present invention, a three-dimensional semiconductor device may include: a first cell region, a second cell region, and a via plug region provided between the first cell region and the second cell region; a word line stack provided in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers alternately stacked; and a plurality of via plugs vertically penetrating the word line stack in the via plug region and respectively and exclusively connected to the plurality of word lines. When viewed from a top view, the via plugs may be arranged in a zigzag pattern in a row direction. The diameter of the via plugs may increase in the row direction.

[0008] According to an embodiment of the present invention, a three-dimensional semiconductor device may include: a first cell region, a second cell region, and a via plug region provided between the first cell region and the second cell region; a word line stack provided in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers alternately stacked; and a plurality of via plugs vertically penetrating the word line stack and respectively and exclusively connected to the plurality of word lines. All of the plurality of word lines may horizontally extend from the first cell region across the via plug region to the second cell region. When viewed from a top view, the plurality of via plugs may have a zigzag pattern arrangement in a row direction.

[0009] According to an embodiment of the present invention, a three-dimensional semiconductor device may include: a first cell region and a via plug region; a word line stack disposed in the first cell region and the via plug region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers alternately stacked; and a plurality of via plugs respectively and exclusively connected to the plurality of word lines by vertically penetrating the word line stack in the via plug region. All of the plurality of word lines may extend laterally from the first cell region to the via plug region. When viewed from a top view, the diameters of the plurality of via plugs may increase in a row direction.

[0010] Since the three-dimensional semiconductor device according to the embodiment of the present invention includes a via plug region disposed between cell regions, a single word line control circuit can be used to control cells in two cell regions.

[0011] In the three-dimensional semiconductor device according to the embodiment of the present invention, since cells in the cell region share the same word line, the area occupied by the device can be reduced.

[0012] In the three-dimensional semiconductor device according to the embodiment of the present invention, since the via plugs are arranged in a Z-shaped pattern in the via plug region, the area occupied by the device can be reduced.

[0013] Therefore, the productivity of the device can be improved, and the unit cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A and Figure 1B illustrate the layout of a cell region and a via plug region of a three-dimensional semiconductor device according to an embodiment of the present invention.

[0015] Figure 1C illustrate Figure 1A the layout of an enlarged view of region A of

[0016] Figure 1D illustrate the layout of the diameters of a plurality of via plugs provided in one of a plurality of Figure 1C sites provided in

[0017] Figure 1E illustrate a top view of the average diameter of via plugs provided in a plurality of positions provided in Figure 1C

[0018] Figure 2 is a longitudinal cross-sectional view of a three-dimensional semiconductor device according to an embodiment of the present invention.

[0019] Figures 3A to 3C , Figures 4 to 16 , Figure 17A and Figure 17B and Figure 18It is a diagram illustrating a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention.

[0020] Figure 19A and Figure 19B It is a block diagram illustrating the configuration of a memory system according to an embodiment of the present invention.

[0021] Figure 19C and Figure 19D It is a block diagram illustrating the configuration of a computing system according to an embodiment of the present invention. Detailed Description

[0022] Figure 1A and Figure 1B It is a diagram illustrating the layout of the cell regions CAa and CAb and the via plug region VA of a three-dimensional semiconductor device according to an embodiment of the present invention. Refer to Figure 1A In, the via plug region VA can be provided between the cell regions CAa and CAb. The cell regions CAa and CAb can include memory cells. The cell regions CAa and CAb can include a first cell region CAa located on one side of the via plug region VA and a second cell region CAb located on the other side of the via plug region VA. The via plug region VA can include via plugs to be connected to a decoding circuit of a control word line. The cell regions CAa and CAb and the via plug region VA can be arranged or disposed side by side in a first direction.

[0023] Refer to Figure 1B In, the via plug regions VAa, VAb, and VAc can be distributed to be adjacent to the side edges of the cell regions CAa and CAb in a first direction. For example, the via plug regions VAa, VAb, and VAc can include a first via plug region VAa adjacent to the left side edge of the first cell region CAa, a second via plug region VAb adjacent to the right side edge of the second cell region CAb, and a third via plug region VAc between the first cell region CAa and the second cell region CAb. The memory cells in each of the cell regions CAa and CAb can be connected to one of the via plug regions VAa, VAb, and VAc provided adjacent to the cell region.

[0024] Figure 1C It is a diagram illustrating Figure 1A the layout of an enlarged view of region A of. Refer to Figure 1C, the via plug region VA can be divided into a plurality of positions Sa to Sh arranged in the row direction R. The three-dimensional semiconductor device may include a plurality of via plugs Vp in a plurality of positions Sa to Sh provided in the via plug region VA. The same number of via plugs Vp can be provided in each of the positions Sa to Sh. The via plugs Vp can be arranged to vertically penetrate the word line stack WS, and the word line stack WS extends from the first unit region CAa across the via plug region VA to the second unit region CAb in the row direction. The via plugs Vp can be alternately arranged in a zigzag pattern in the row direction. There may be more or fewer than the positions shown. For example, the number of positions Sa to Sh can be seven or less, or nine or more. In the drawings, each of the positions Sa to Sh is shown to have four via plugs Vp, but the present invention is not limited thereto. For example, each of the positions Sa to Sh may include five or more via plugs Vp, or may include less than four via plugs Vp.

[0025] Figure 1D illustrates the setting in Figure 1C one of the plurality of positions Sa to Sh shown, the layout of the diameters D1 to D8 of the plurality of via plugs V1 to V8. Refer to Figure 1D , the diameters D1 to D8 of the first via plug V1 to the eighth via plug V8 provided in each of the positions Sa to Sh can gradually increase in the row direction R. In an embodiment, eight via plugs V1 to V8 can be placed in each of the plurality of positions Sa to Sh, and can be arranged in a zigzag pattern. For example, the eight via plugs V1 to V8 can be arranged in two rows shown by the lower center line CLa and the upper center line CLb. Due to the zigzag pattern, the two rows of via plugs V1 to V8 can be offset relative to each other. Among the diameters D1 to D8 of the via plugs V1 to V8, two adjacent diameters can be reduced in size in the row direction R, but the diameters D1 to D8 of the via plugs V1 to V8 can increase overall (increasing trend) in the row direction R. In the zigzag pattern, the centers of the lower via plugs V1, V3, V5, and V7 can be aligned with the lower center line CLa, and the centers of the upper via plugs V2, V4, V6, and V8 can be aligned with the upper center line CLb. The row direction gaps or row direction pitches P1 to P7 between the centers of the via plugs V1 to V8 can be the same in the row direction R. In some parts or some embodiments, the diameters D1 to D8 of the via plugs V1 to V8 can be greater than the row direction pitches P1 to P7. That is, some of the via plugs V1 to V8 can partially overlap each other in the column direction C, as Figure 1D shown. In another embodiment, the row direction pitches P1 to P7 can increase in the row direction R. Although some of the adjacent row direction pitches in the row direction R can decrease, the pitches P1 to P7 can increase overall in the row direction R.

[0026] Figure 1E is a top view illustrating the average diameters Da to Dh of the via plugs Va to Vh provided at multiple positions Sa to Sh. Further referring to Figure 1C , in an embodiment, the average diameters Da to Dh of the via plugs Va to Vh may increase in the row direction R, that is, Da < Db < Dc < Dd < De < Df < Dg < Dh. In another embodiment, the positions Sa to Sh may be arranged randomly. In this case, the average diameters Da to Dh of the via plugs Va to Vh may be arranged randomly, and there is no tendency for the diameter size to increase in any direction. For example, the average diameters Da to Dh of the via plugs Va to Vh may be slightly different from each other. That is, Da ≠ Db ≠ Dc ≠ Dd ≠ De ≠ Df ≠ Dg ≠ Dh. In another embodiment, some of the via plugs Va to Vh may have the same diameter, while others may have different diameters, as will be described with reference to other drawings of the present disclosure below.

[0027] Figure 2 is a longitudinal sectional view of a three-dimensional semiconductor device according to an embodiment of the present invention. In Figure 2 , the longitudinal sectional views taken along the lines I-I′ and II-II′ of Figure 1C overlap. According to Figures 1A to 1E and Figure 2 , a three-dimensional semiconductor device according to an embodiment of the present invention may include a first unit region CAa, a second unit region CAb, a via plug region VA provided between the first unit region CAa and the second unit region CAb, a word line stack 30, and a via plug Vp. The word line stack 30 may extend in the row direction across all of the first unit region CAa, the via plug region VA, and the second unit region CAb. The word line stack 30 may include a lower insulating layer 21 laminated on the lower layer 10, a plurality of word lines 31 and a plurality of interlayer insulating layers 23 alternately laminated with each other, and an upper insulating layer 24.

[0028] Each of the first unit region CAa and the second unit region CAb may include a plurality of vertical channel structures (not shown) vertically penetrating the word line stack 30 and a plurality of memory cells. That is, each word line 31 may be turned on and off simultaneously in the first unit region CAa and the second unit region CAb. For example, the word line 31 may include a metal such as tungsten (W).

[0029] The word line 31 of the word line stack 30 can extend horizontally from the first unit region CAa across the via plug region VA to the second unit region CAb. That is to say, the word line 31 can extend to the two unit regions CAa and CAb without being cut or disconnected in the via plug region VA. Each word line 31 can be commonly connected to a plurality of memory cells provided in the first unit region CAa and the second unit region CAb. Therefore, the memory cells in the first unit region CAa and the second unit region CAb can share the word line 31, and the word line 31 can turn on and off the memory cells in the first unit region CAa and the second unit region CAb simultaneously. Further refer to Figure 1A , because the memory cells located in the first unit region CAa and the second unit region CAb are turned on and off simultaneously through the via plug Vp, and because the via plug region VA is provided between the first unit region CAa and the second unit region CAb, the operation time delay and power supply difference caused by the resistance and capacitance of the cells in the first unit region CAa and the second unit region CAb can be minimized. In addition, because one word line control circuit can turn on / off the memory cells in the two unit regions CAa and CAb simultaneously or exclusively, the word line control circuit can be simplified, the circuit area can be reduced, and the two-dimensional size of the three-dimensional semiconductor device can be reduced. That is to say, because more three-dimensional semiconductor chips can be integrated on one wafer, the productivity can be improved and the unit cost can be reduced.

[0030] The lower insulating layer 21, the interlayer insulating layer 23, and the upper insulating layer 24 can include an insulating material such as silicon oxide to insulate the stacked word lines 31.

[0031] Each via plug Vp can be connected to one of the word lines 31 by vertically penetrating the word line stack 30. The side surface of the via plug Vp and the side surface of the word line 31 can be insulated. The via plug Vp can include a columnar conductive core and a cylindrical insulating lining having a side wall surrounding the core. The conductive core can include a conductor such as a metal, and the lining can include an insulating material such as silicon oxide. In an embodiment, a barrier material such as titanium nitride can also be included between the conductive core and the lining.

[0032] The lower ends of the via plugs Vp can be electrically connected to the word lines 31 respectively and exclusively. Therefore, the via plugs Vp can have different vertical lengths. For the convenience of understanding this embodiment, as an example, the vertical lengths of the via plugs Vp are described as gradually increasing. Therefore, each via plug Vp can exclusively provide voltage or current to the corresponding word line 31.

[0033] The lower layer 10 may include a logic device layer. For example, the lower layer 10 may include transistors, vertical conductive wirings, lateral conductive wirings, and a conductive common source layer disposed on a lower substrate. The lower substrate may include a silicon layer, the transistors may include MOS transistors, and the vertical conductive wirings and the lateral conductive wirings may include metal wirings. The conductive common source layer may be disposed in the form of a plate below the lower insulating layer 21 of the word line stack 30. The conductive common source layer may include a doped polysilicon layer or a metal silicide layer. The lower layer 10 may include an insulating material such as silicon oxide or silicon nitride.

[0034] The three-dimensional semiconductor device may further include a cover insulating layer 25, contact plugs 35, and metal wirings 36. The cover insulating layer 25 may cover the word line stack 30 and the via plugs Vp. The cover insulating layer 25 may include an insulating material such as silicon oxide. The contact plugs 35 may be respectively connected to the via plugs Vp by penetrating through the cover insulating layer 25. The metal wirings 36 may be disposed on the cover insulating layer 25 and may be respectively connected to the contact plugs 35. The contact plugs 35 and the metal wirings may include a metal such as tungsten (W), a barrier metal such as titanium nitride (TiN), or other conductive materials.

[0035] Figures 3A to 3C , Figures 4 to 16 , Figure 17A and Figure 17B and Figure 18 are diagrams illustrating a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. In these diagrams, the longitudinal sectional views taken along lines I-I' and II-II' in Figure 1C are overlapping, but adjacent patterns in the plan view or top view may be spaced apart in the diagonal direction.

[0036] Referring to Figure 3A , a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention may include forming an insulating layer stack 20 on the lower layer 10 and forming a hard mask pattern 41 on the insulating layer stack 20. The insulating layer stack 20 may include a lower insulating layer 21, a plurality of sacrificial insulating layers 22 and a plurality of interlayer insulating layers 23 alternately stacked, and an upper insulating layer 24. The lower insulating layer 21, the interlayer insulating layer 23, and the upper insulating layer 24 may include an insulating material such as silicon oxide. The sacrificial insulating layer 22 may include an insulating material such as silicon nitride having an etching selectivity with respect to the lower insulating layer 21, the interlayer insulating layer 23, and the upper insulating layer 24. The hard mask pattern 41 may have a plurality of openings Op. The insulating layer stack 20 may be divided into a first unit region CAa, a second unit region CAb, and a via plug region VA. The via plug region VA may be divided into a plurality of positions Sa to Sh.

[0037] Figure 3B is a top view showing the arrangement of the openings Op of the hard mask pattern 41 Figure 3A . Referring to Figure 3B , the openings Op may be arranged in a zigzag pattern such that the openings Op may be offset from each other in the row direction R and the column direction C. Since each of the openings Op in positions Sa to Sh must be individually exposed by a trimming process, the openings Op may be arranged to be spaced apart in the row direction R so as not to overlap in the column direction C. The same number of openings Op may be provided in each of positions Sa to Sh. Although it is described that four openings Op are formed in each of positions Sa to Sh, in an embodiment, more than four openings Op may be formed in each of positions Sa to Sh. For example, several to dozens of openings Op may be formed in each of positions Sa to Sh.

[0038] Figure 3C is a layout example showing a position where the diameters D1 to D8 of the plurality of openings Op of the hard mask pattern 41 are set according to the pitches P1 to P7. Referring to Figure 3C , the corresponding diameters D1 to D8 of the first opening Op1 to the eighth opening Op8 may be the same. Additionally, the corresponding pitches P1 to P7 of the first opening Op1 to the eighth opening Op8 may be the same. The pitches P1 to P7 may be greater than the diameters D1 to D8. Thus, in the column direction C, the openings Op may not overlap. In another embodiment, the pitches P1 to P7 may increase in magnitude along the row direction R.

[0039] Referring to Figure 4 , the method may further include forming a first hole pattern H1 in the insulating layer stack 20 by performing a first hole forming process. For example, the first hole forming process may include forming a first photoresist pattern 45a and forming the first hole pattern H1 by performing a first etching process using the first photoresist pattern 45a and the hard mask pattern 41 as an etching mask. The first photoresist pattern 45a may expose one of the outermost openings Op of the hard mask pattern 41 in each of positions Sa to Sh. For example, the opening Op that is the farthest in the row direction in each of positions Sa to Sh may be exposed. The first hole pattern H1 may extend downward into the interior of the insulating layer stack 20 under the hard mask pattern 41.

[0040] Referring to Figure 5, the method may further include forming a second hole pattern H2 in the insulating layer stack 20 by performing a second hole forming process and further deepening the first hole pattern H1. The second hole forming process may include forming a second photoresist pattern 45b that exposes an opening OP adjacent to the opening Op previously exposed in the first hole forming process of the hard mask pattern 41. The second photoresist pattern 45b may be formed by shrinking the first photoresist pattern 45a, and the second hole pattern H2 and the deepened first hole pattern H1 may be formed by a second etching process using the second photoresist pattern 45b and the hard mask pattern 41 as an etching mask.

[0041] Referring Figure 6 and Figure 7 , the method may further include forming a third hole pattern H3 and a fourth hole pattern H4 in the insulating layer stack 20 by performing a third hole forming process and a fourth hole forming process. The first hole pattern H1 and the second hole pattern H2 may be further deepened with each additional hole forming process. In the third hole forming process, the second photoresist pattern 45b may be shrunk to a third photoresist pattern 45c to expose an additional opening Op of the hard mask pattern 41. In the fourth hole forming process, the third photoresist pattern 45c may be shrunk to a fourth photoresist pattern 45d that exposes an additional opening Op of the hard mask pattern 41.

[0042] In Figures 4 to 7 , the openings Op of the hard mask pattern 41 in each of the positions Sa to Sh may be sequentially exposed in the row direction. Similar to 3C, the openings Op of the hard mask pattern 41 in each of the positions Sa to Sh may be set to be spaced apart in the row direction R.

[0043] As described above, forming four hole patterns H1 to H4 in each of the positions Sa to Sh has been described, but more hole patterns may be formed in each of the positions Sa to Sh in the method disclosed herein. For example, several to dozens of hole patterns may be formed in each of the positions Sa to Sh. Therefore, the hole forming process may be repeated until all the openings Op of the hard mask pattern 41 in each of the positions Sa to Sh are exposed.

[0044] Referring Figure 8 , the method may further include performing a first thinning process. The first thinning process may include forming a first mask pattern 51 that covers one of the positions Sa to Sh (e.g., the first position Sa) and exposes the remaining positions Sb to Sh, and further etching the hole patterns H1 to H4 in the exposed positions Sb to Sh by a first depth d1. Thereafter, the first mask pattern 51 may be removed, and a filling insulating material may be filled in the hole patterns H1 to H4. For simplicity of the drawings, the reference numerals of the filling insulating material have been omitted.

[0045] Referring to Figure 9 , the method may further include a second thinning process. The second thinning process may include forming a second mask pattern 52 that covers at least two of positions Sa to Sh (e.g., a first position Sa and a second position Sb) and exposes the remaining positions Sc to Sh, and further etching the hole patterns H1 to H4 of the exposed positions Sc to Sh to a second depth d2. In the drawings, the first position Sa and the second position Sb are shown adjacent to each other, but in other embodiments, the first position Sa and the second position Sb may be spaced apart from each other. The reference numerals of the hole patterns H1 to H4 have been omitted to avoid complicating the drawings. Thereafter, the second mask pattern 52 may be removed and the hole patterns may be filled with a filling insulating material.

[0046] Referring to Figures 10 to 14 , the method may further include performing a third thinning process to a seventh thinning process. The third thinning process to the seventh thinning process may include forming a third mask pattern 53, a fourth mask pattern 54, a fifth mask pattern 55, a sixth mask pattern 56, and a seventh mask pattern 57 that cover and expose some of the positions Sa to Sh, respectively, and further etching the hole patterns H1 to H4 of the exposed some positions to one of a third depth d3, a fourth depth d4, a fifth depth d5, a sixth depth d6, and a seventh depth d7. Although the positions Sa to Sh are described as adjacent to each other and sequentially exposed in the drawings, the adjacent positions are not necessarily sequentially exposed. Each of the third thinning process to the seventh thinning process may include removing the third mask pattern 53 to the seventh mask pattern 57 and filling the hole patterns with a filling insulating material, respectively.

[0047] Figure 15 is a diagram illustrating the inner wall profiles of representative hole patterns Ha to Hh formed in respective positions Sa to Sh. The inner wall profiles have been exaggerated to facilitate understanding of the technical features of the present invention. Referring to Figure 15 , the inner walls of the hole patterns Ha to Hh may be tapered. Further referring to Figures 8 to 14 , the inner walls of the hole patterns Ha to Hh may have a stepped shape or a pedestal shape SS depending on the number of executions of the above-described thinning process. Since it is assumed that the thinning process etches the hole patterns Ha to Hh by the same depths d1 to d7, the pedestal shape SS of the hole patterns Ha to Hh may be formed at the same height. However, in other embodiments, the depths d1 to d7 of the thinning process may be different from each other. Therefore, the pedestal shape SS of the hole patterns Ha to Hh may be formed at different heights.

[0048] Referring to Figure 16 , the method may further include forming conductive vias plugs Vp in the hole patterns Ha to Hh by performing a via plug formation process.

[0049] Figure 17A and Figure 17B is a longitudinal cross-sectional view conceptually illustrating a through-hole plug forming process according to an embodiment of the present invention. The base shape SS of Figure 15 is omitted.

[0050] Referring to Figure 17A and Figure 17B , the through-hole plug forming process may include filling a through-hole insulator Vi in hole patterns Ha to Hh, forming holes that vertically penetrate the through-hole insulator Vi to expose each sacrificial insulating layer 22, filling a conductive material in the holes of the through-hole insulator Vi, and forming through-hole plugs Vp that respectively contact the sacrificial insulating layer 22 by performing a planarization process.

[0051] Referring to Figure 17A , the through-hole plug Vp may have a vertical sidewall profile. For example, the through-hole plug Vp may have a columnar shape. The through-hole insulator Vi may have a filler shape.

[0052] Referring to Figure 17B , the through-hole plug Vp may have an inclined sidewall profile. For example, the through-hole plug Vp may have an inverted conical shape or a stud shape. The through-hole insulator Vi may have a lining shape.

[0053] The through-hole insulator Vi may include silicon oxide or metal oxide. The through-hole plug Vp may include metal. In Figure 17A and Figure 17B , the diameters of the through-hole plugs Vp may be the same. For ease of understanding the technical features of the present invention, the through-hole plugs Vp are shown in an exaggerated form.

[0054] Referring to Figure 18 , the method may further include forming a covering insulating layer 25 above the insulating layer stack 20 and forming a word line stack 30 by replacing the sacrificial insulating layer 22 with word lines 31. The word line stack 30 may include a lower insulating layer 21, an interlayer insulating layer 23 and word lines 31 that are alternately stacked, and an upper insulating layer 24. The covering insulating layer 25 may include silicon oxide having an etching selectivity with respect to the sacrificial insulating layer 22. The word lines 31 may include a conductor such as metal.

[0055] Thereafter, referring to Figure 2 , the method may further include forming contact plugs 35 that vertically penetrate the covering insulating layer 25 and forming metal wirings 36 above the covering insulating layer 25 and the contact plugs 35.

[0056] Figure 19A is a block diagram illustrating the configuration of a memory system 1000 according to an embodiment of the present invention. Referring to Figure 19A, the memory system 1000 according to an embodiment of the present invention may include a memory device 1200 and a controller 1100. The memory device 1200 may store data information having various data types such as text, graphics, and software code. The memory device 1200 may include a non-volatile memory. In addition, the memory device 1200 may include a three-dimensional semiconductor device described with reference to Figures 1A to 2 . The controller 1100 may be connected to a host and the memory device 1200. The controller 1100 may access the memory device 1200 in response to a request from the host. For example, the controller 1100 may control operations of the memory device 1200 such as read, write, erase, and background. The controller 1100 may include, for example, a random access memory (RAM) 1110, a central processing unit (CPU) 1120, a host interface 1130, an error correction code (ECC) circuit 1140, and a memory interface 1150. Here, the RAM 1110 may be used as an operation memory for the CPU 1120, a cache memory between the memory device 1200 and the host, a buffer memory between the memory device 1200 and the host, etc. As a reference, the RAM 1110 may be replaced with a static random access memory (SRAM), a read-only memory (ROM), etc. The CPU 1120 may control the overall operation of the controller 1100. For example, the CPU 1120 may operate firmware such as a flash translation layer (FTL) stored in the RAM 1110. The host interface 1130 may be connected to the host interface. For example, the controller 1100 may communicate with the host through various interface protocols, including at least one of the following protocols: USB (Universal Serial Bus) protocol, MMC (MultiMedia Card) protocol, PCI (Peripheral Component Interconnect) protocol, PCI-E (PCI-Express) protocol, ATA (Advanced Technology Attachment) protocol, Serial-ATA protocol, Parallel-ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, IDE (Integrated Drive Electronics) protocol, proprietary protocol, etc. The ECC circuit 1140 may use the error correction code ECC to detect and correct errors included in the data read from the memory device 1200. The memory interface 1150 may be interfaced with the memory device 1200. For example, the memory interface 1150 may include a NAND interface or a NOR interface. The buffer memory may temporarily store data to be sent to the outside via the host interface 1130 or may temporarily store data sent from the memory device 1200 via the memory interface 1150. In addition, the controller 1100 may further include a ROM storing code data for interfacing with the host. As described above, since the memory system 1000 according to an embodiment of the present invention includes the memory device 1200 having improved performance, the performance of the memory system 1000 may be improved.

[0057] Figure 19B is a block diagram illustrating the configuration of a memory system 1000' according to an embodiment of the present invention. Hereinafter, repeated descriptions will be omitted. Referring to Figure 19B , a memory system 1000' according to an embodiment of the present invention may include a memory device 1200' and a controller 1100. In addition, the controller 1100 may include a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, etc. The memory device 1200' may include a non-volatile memory. In addition, the memory device 1200' may include a three-dimensional semiconductor device described with reference to Figures 1A to 2 . In addition, the memory device 1200' may include a multi-chip package having a plurality of memory chips. The plurality of memory chips may be divided into a plurality of groups, and the plurality of groups may communicate with the controller 1100 through a first channel CH1 to a k-th channel CHk. In addition, the memory chips belonging to one group may communicate with the controller 1100 through a common channel. As a reference, the memory system 1000' may be modified such that one memory chip is connected to one channel. As described above, since the memory system 1000' according to an embodiment of the present invention includes a memory device 1200' with improved performance, the performance of the memory system 1000' can also be improved. Specifically, since the memory device 1200' includes a multi-chip package, the memory device 1200' may have an increased data storage capacity and an improved operation speed.

[0058] Figure 19C is a block diagram illustrating the configuration of a computing system 2000 according to an embodiment of the present invention. Hereinafter, repeated descriptions will be omitted. Referring to Figure 19C , a computing system 2000 according to an embodiment of the present invention may include a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, etc. The memory device 2100 may store data provided through the user interface 2400 and data processed by the CPU 2200. In addition, the memory device 2100 may be electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, etc. through the system bus 2600. For example, the memory device 2100 may be connected to the system bus 2600 through a controller (not shown) or may be directly connected to the system bus 2600. When the memory device 2100 is directly connected to the system bus 2600, the functions of the controller may be executed by the CPU 2200, the RAM 2300, etc. Here, the memory device 2100 may include a non-volatile memory. In addition, the memory device 2100 may include a reference toFigures 1A to 2 The described three-dimensional semiconductor device. The computing system 2000 may include a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a PMP (portable multimedia player), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, one of devices capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, or an RFID device. Since the computing system 2000 according to an embodiment of the present invention includes a memory device 2100 having improved performance, the performance of the computing system 2000 can also be improved.

[0059] Figure 19D is a block diagram illustrating a computing system 3000 according to an embodiment of the present invention. Refer to Figure 19D, a computing system 3000 according to an embodiment of the present invention may include a software layer, which includes an operating system 3200, applications 3100, a file system 3300, a translation layer 3400, etc. Additionally, the computing system 3000 may include a hardware layer such as a memory device 3500. The operating system 3200 may manage the software and hardware resources of the computing system 3000 and may control the central processing unit to execute programs. The applications 3100 may include various application programs executed by the computing system 3000. For example, the applications 3100 may include utility software executed by the operating system 3200. The file system 3300 refers to the logical structure for managing data, files, etc. existing in the computing system 3000. The file system 3300 may organize the files or data to be stored in the memory device 3500 according to rules. The file system 3300 may be determined based on the operating system 3200 for the computing system 3000. For example, when the operating system 3200 is the Windows series of Microsoft Corporation, the file system 3300 may include File Allocation Table (FAT), NT File System (NTFS), etc. Additionally, when the operating system 3200 is the Unix / Linux series, the file system 3300 may include Extended File System (EXT), Unix File System (UFS), Journaling File System (JFS), etc. Although the operating system 3200, applications 3100, and file system 3300 are described in separate blocks, the applications 3100 and file system 3300 may be included in the operating system 3200. The translation layer 3400 may convert an address into a format suitable for the memory device 3500 in response to a request from the file system 3300. For example, the translation layer 3400 may convert the logical address generated by the file system 3300 into the physical address of the memory device 3500. Here, the mapping information between the logical address and the physical address may be stored in an address translation table. For example, the translation layer 3400 may include a Flash Translation Layer (FTL), a Universal Flash Link Layer (ULL), etc. The memory device 3500 may include a non-volatile memory. In addition, the memory device 3500 may include the three-dimensional semiconductor device described with reference to Figures 1A to 2 Because the computing system 3000 according to an embodiment of the present invention includes a memory device 3500 with improved performance, the performance of the computing system 3000 can be improved.

[0060] Although the technical features of the present invention have been specifically described according to the above embodiments, it should be noted that the above embodiments are for illustrative purposes only and are not used to limit the present invention. Additionally, those of ordinary skill in the art will understand that various changes and modifications can be made without departing from the scope of the present disclosure.

[0061] Cross-reference to related applications

[0062] This application claims priority to Korean Patent Application No. 10-2021-0044510, filed on April 6, 2021, which is hereby incorporated by reference in its entirety.

Claims

1. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: A first unit region, a second unit region, and a via plug region disposed between the first unit region and the second unit region; A word line stack, the word line stack being disposed in the first unit region, the via plug region, and the second unit region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers alternately stacked; And A plurality of via plugs, the plurality of via plugs being respectively and exclusively connected to the plurality of word lines by vertically penetrating the word line stack in the via plug region, Wherein, when viewed from a top view, the plurality of via plugs are arranged in a zigzag pattern in a row direction, The diameters of the plurality of via plugs increase in the row direction, Each of the plurality of word lines is commonly connected to memory cells respectively disposed in the first unit region and the second unit region, such that the memory cells respectively disposed in the first unit region and the second unit region are simultaneously turned on and off through one of the plurality of via plugs, The via plug region is divided into a plurality of positions arranged in the row direction, Each of the plurality of positions includes the same number of the via plugs arranged in a zigzag pattern, In each of the plurality of positions, when viewed from the top view, at least two of the plurality of via plugs overlap each other in a column direction, and The via plugs disposed in each of the plurality of positions have different vertical lengths.

2. The three-dimensional semiconductor device according to claim 1, wherein The average value of the diameters of the via plugs in each of the plurality of positions increases in the row direction.

3. The three-dimensional semiconductor device according to claim 1, wherein, The via plugs are formed in vias vertically penetrating the word line stack, and The inner wall of the via has a pedestal shape formed on the inner wall.

4. The three-dimensional semiconductor device according to claim 3, wherein, The first via in the via in the first position of the plurality of positions has a different number of pedestal shapes from the second via in the via in the second position of the plurality of positions.

5. The three-dimensional semiconductor device according to claim 1, wherein, The plurality of via plugs have different vertical lengths.

6. The three-dimensional semiconductor device according to claim 1, wherein, The word lines extend laterally from the first unit region across the via plug region to the second unit region.

7. The three-dimensional semiconductor device according to claim 1, wherein, When viewed from a top view, the pitch of the plurality of via plugs in the row direction is the same.

8. The three-dimensional semiconductor device according to claim 1, wherein, The pitch of the plurality of via plugs increases in the row direction.

9. The three-dimensional semiconductor device according to claim 1, wherein, The plurality of via plugs have vertical sidewall profiles.

10. The three-dimensional semiconductor device according to claim 1, wherein, The plurality of via plugs have inclined sidewall profiles.

11. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: A first unit region, a second unit region, and a via plug region disposed between the first unit region and the second unit region; A word line stack, the word line stack being disposed in the first unit region, the via plug region, and the second unit region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers alternately stacked; And A plurality of via plugs, the plurality of via plugs being respectively and exclusively connected to the plurality of word lines by vertically penetrating the word line stack, Each of the plurality of word lines extends laterally from the first cell region across the via plug region to the second cell region, and when viewed from a top view, the plurality of via plugs form a Z shape in the row direction, wherein each of the plurality of word lines is commonly connected to memory cells respectively provided in the first cell region and the second cell region, such that the memory cells respectively provided in the first cell region and the second cell region are simultaneously turned on and off through one of the plurality of via plugs, wherein the via plug region is divided into a plurality of positions arranged in the row direction, wherein each of the plurality of positions includes the same number of the via plugs arranged in a Z-shaped pattern, wherein, in each of the plurality of positions, when viewed from the top view, at least two of the plurality of via plugs overlap each other in the column direction, and wherein the via plugs provided in each of the plurality of positions have different vertical lengths.

12. The three-dimensional semiconductor device according to claim 11, wherein, the plurality of via plugs are respectively formed in vias vertically penetrating the word line stack, and at least one of the vias has a pedestal shape formed on an inner wall.

13. The three-dimensional semiconductor device according to claim 12, wherein, the vias provided at one of the plurality of positions each have the same number of pedestal shapes.

14. The three-dimensional semiconductor device according to claim 12, wherein, the vias provided at different positions have different numbers of pedestal shapes.

15. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: a first cell region, a second cell region, and a via plug region provided between the first cell region and the second cell region; a word line stack provided in the first cell region, the second cell region, and the via plug region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers alternately stacked; and a plurality of via plugs, the plurality of via plugs are respectively and exclusively connected to the plurality of word lines by vertically penetrating the word line stack in the via plug region, wherein each of the plurality of word lines extends laterally from the first cell region across the via plug region to the second cell region, and when viewed from a top view, the diameters of the plurality of via plugs increase in the row direction, wherein each of the plurality of word lines is commonly connected to memory cells respectively provided in the first cell region and the second cell region, such that the memory cells respectively provided in the first cell region and the second cell region are simultaneously turned on and off through one of the plurality of via plugs, wherein the via plug region is divided into a plurality of positions arranged in the row direction, wherein each of the plurality of positions includes the same number of the via plugs arranged in a Z-shaped pattern, Among them, in each of the plurality of positions, when viewed from the top view, at least two of the plurality of via plugs overlap each other in the column direction, and Among them, the via plugs provided in each of the plurality of positions have different vertical lengths.

16. The three-dimensional semiconductor device according to claim 15, wherein, the via plugs are formed in vias vertically penetrating the word line stack, the vias have a pedestal shape formed on the inner wall, and the number of pedestal shapes of the vias in one of the plurality of positions is different from the number of pedestal shapes of the vias in another of the plurality of positions.

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