Method of forming a cmos image sensor

Abstract

The application provides a forming method of a CMOS image sensor, comprising: providing a substrate, the substrate comprising a substrate front surface and a substrate back surface; forming an isolation groove on the substrate front surface by an integrated etching process; forming a photodiode region in the remaining substrate, the isolation groove being adjacent to the photodiode region; filling the isolation groove with polysilicon to form an isolation structure; and forming a connection hole on the isolation structure. The application adopts an integrated etching process to form a groove and a deep groove in the substrate from the substrate front surface at one time, then fills the groove and the deep groove with polysilicon to form an isolation structure, and then forms a connection hole on the isolation structure. The method has simple preparation process, and the potential can be connected from the front surface. The isolation structure has inhibiting effect on the crosstalk, dark current and random telegraph noise of the surface of the photodiode region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a CMOS image sensor. Background Technology

[0002] As CIS (CMOS image sensors) continue to shrink in pixel size, N-type ion implantation in the photodiode region is becoming increasingly concentrated to maintain high FWC (full-well capacitance) and sensitivity. This can potentially lead to crosstalk between photodiode regions. To suppress electrical and optical crosstalk, deep-trench isolation (DTI) structures are widely used. FDTI (front-side DTI, full-depth DTI) offers stronger crosstalk suppression compared to BDTI (back-side DTI) because it penetrates the photodiode layer.

[0003] The existing FDTI process involves first etching shallow trenches -> then etching elongated deep trenches -> filling them with doped polysilicon -> etching back the doped polysilicon -> filling the shallow trenches with silicon oxide. For example, please refer to... Figure 1 First, a substrate 110 is provided. The substrate 110 can be a wafer. The substrate 110 is divided into a front side and a back side. Etching of the substrate 110 begins from the front side and stops inside the substrate 110, forming shallow trenches 120. Next, please refer to... Figure 2 Starting from the bottom of the shallow trench 120, etching continues towards the back of the substrate, stopping within the substrate 110 to form the deep trench 130. Next, please refer to... Figure 3 Polysilicon, which may be doped polysilicon, is filled into both shallow trench 120 and deep trench 130. Next, N-type ions are filled into the remaining substrate 110 to form photodiode regions. Shallow trench 120 and deep trench 130 are adjacent to the photodiode regions. If there are at least two photodiode regions, the shallow trench 120 and deep trench 130 together serve as isolation trenches to separate the photodiodes, with one isolation trench between every two photodiodes. Next, please refer to... Figure 4 and Figure 5 The polysilicon in the shallow trench 120 is removed, and oxide is filled into the shallow trench 120. In this way, the oxide in the shallow trench 120 and the polysilicon in the deep trench 130 together form an isolation structure, which separates the photodiode. Next, please refer to... Figure 6The back side of the substrate is etched to expose a deep trench 130. A connection hole 140 is formed on the deep trench 130. The connection hole 140 can connect the potential connection point. If other devices need to use it, they can be directly connected through the connection hole 140.

[0004] However, this fabrication method is complex, and if the isolation structure needs to be connected to a potential, it can only be connected through a hole made by an electrode on the back of the substrate, which is even more complicated. Summary of the Invention

[0005] The purpose of this invention is to provide a method for forming a CMOS image sensor, which can form an isolation trench in one step and form a connection hole on the front side of the substrate.

[0006] To achieve the above objectives, the present invention provides a method for forming a CMOS image sensor, comprising:

[0007] A substrate is provided, the substrate comprising opposing front and back sides;

[0008] An isolation trench is formed on the front side of the substrate using an integrated etching process;

[0009] A photodiode region is formed within the remaining substrate, and the isolation trench is adjacent to the photodiode region;

[0010] Fill the isolation trench with polysilicon to form an isolation structure; and

[0011] Connection holes are formed on the isolation structure.

[0012] Optionally, in the method for forming the CMOS image sensor, the isolation trench includes a shallow trench and a deep trench, the cross-sectional area of ​​the shallow trench is larger than the cross-sectional area of ​​the deep trench, and the first end of the deep trench is connected to the bottom of the shallow trench.

[0013] Optionally, in the method for forming the CMOS image sensor, the second end of the deep trench has a certain distance from the back side of the substrate.

[0014] Optionally, in the method for forming the CMOS image sensor, after forming the connection hole on the isolation structure, the method further includes: grinding the back side of the substrate so that the ground back side of the substrate exposes the surface of the second end of the deep trench.

[0015] Optionally, in the method for forming the CMOS image sensor, the polysilicon is doped polysilicon.

[0016] Optionally, in the method for forming the CMOS image sensor, there are multiple isolation slots.

[0017] Optionally, in the method for forming the CMOS image sensor, there are multiple photodiode regions.

[0018] Optionally, in the method for forming the CMOS image sensor, there are multiple isolation structures.

[0019] Optionally, in the method for forming the CMOS image sensor, each of the isolation structures has a connection hole on its surface.

[0020] Optionally, in the method for forming the CMOS image sensor, the substrate includes a wafer.

[0021] The method for forming a CMOS image sensor provided by this invention includes: providing a substrate, the substrate including a front side and a back side of the substrate; forming an isolation trench on the front side of the substrate using an integrated etching process; forming a photodiode region in the remaining substrate, the isolation trench being adjacent to the photodiode region; filling the isolation trench with polysilicon to form an isolation structure; and forming a connection hole on the isolation structure. The FDTI fabrication technology of this patent employs an integrated etching process, starting from the front side of the substrate and etching trenches and deep trenches in one step, then filling the trenches and deep trenches with polysilicon to form an isolation structure, and subsequently forming a connection hole on the isolation structure. This method has a simple fabrication process, and the potential can be accessed from the front side. Furthermore, the isolation structure suppresses crosstalk, dark current, and random telegraph noise on the surface of the photodiode region. Attached Figure Description

[0022] Figures 1 to 6 This is a schematic diagram of the existing technology for forming a CMOS image sensor;

[0023] Figure 7 This is a flowchart of a method for forming a CMOS image sensor according to an embodiment of the present invention;

[0024] Figures 8 to 11 This is a schematic diagram illustrating the formation of a CMOS image sensor according to an embodiment of the present invention;

[0025] Figure 11 This is a schematic diagram of the back side of the substrate after grinding following the formation of the connection hole in an embodiment of the present invention;

[0026] In the figure: 110-substrate, 120-shallow trench, 130-deep trench, 140-connection hole, 210-substrate, 220-shallow trench, 230-deep trench, 240-connection hole. Detailed Implementation

[0027] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0028] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0029] As CIS (image sensors) continue to shrink in pixel size, N-type ion implantation in the photodiode region is becoming increasingly concentrated to maintain high FWC (full-well capacitance) and sensitivity, potentially leading to crosstalk between photodiode regions. To suppress electrical and optical crosstalk, deep-trench isolation (DTI) structures are widely used. FDTI (front-side DTI, full-depth DTI) offers stronger crosstalk suppression than BDTI (back-side DTI) because it penetrates the photodiode layer. However, existing FDTI formation methods are complex, and connecting the isolation structure to a potential requires vias on the back of the substrate, further complicating the process. This invention provides a novel method for forming FDTI.

[0030] Please refer to Figure 7 The present invention provides a method for forming a CMOS image sensor, comprising:

[0031] S11: Provide a substrate, the substrate including opposing front and back sides;

[0032] S12: An isolation trench is formed on the front side of the substrate by an integrated etching process;

[0033] S13: A photodiode region is formed in the remaining substrate, and the isolation trench is adjacent to the photodiode region;

[0034] S14: Filling the isolation trench with polysilicon to form an isolation structure; and

[0035] S15: A connection hole is formed on the isolation structure.

[0036] Please refer to Figure 8 This invention can be applied to ultra-small pixel image sensors with a pixel size < 0.8 μm. A substrate 210 is provided, which can be a wafer. The substrate 210 is divided into a front side and a back side. An isolation trench, wider at the top and narrower at the bottom, is formed within the substrate 210 using an integrated etching technique (AIO technique). Multiple isolation trenches are used in this invention. The isolation trenches include a shallow trench 220 (upper) and a deep trench 230 (lower). The integrated etching technique can simultaneously etch both wide and narrow structures. Compared to existing technologies that require two or more steps for etching, this invention can directly etch the structure in one step, simplifying the process. The first end of the deep trench 230 is connected to the bottom of the shallow trench 220, and the connection point can be the center point of the bottom of the shallow trench 220. The opening of the shallow trench 220 faces the front side of the substrate, and the deep trench 230 faces the back side of the substrate. The second end of the deep trench 230 is at a certain distance from the back side of the substrate. The deep trench 230, in its cross-section parallel to the back side of the substrate, can be circular or square; therefore, the deep trench 230 can be cylindrical or cuboid. The shallow trench 220 has an inverted trapezoidal longitudinal section, with the waist serving as the sidewall of the shallow trench 220. The longer side (bottom) is located on the front side of the substrate, and the shorter side (top) is located on the bottom wall of the shallow trench 220. The cross-sectional area of ​​the shallow trench 220 is larger than that of the deep trench 230; more specifically, the cross-sectional area of ​​the deep trench 230 is smaller than the area of ​​the bottom wall of the shallow trench 220.

[0037] Next, please refer to Figure 9 In the substrate between the isolation trenches, photodiode regions (PDs) are formed by implanting N-type ions. If there are multiple isolation trenches, there are multiple photodiode regions. Each isolation trench is adjacent to a single photodiode region, and the multiple isolation trenches and multiple photodiode regions are spaced apart. The shallow trenches 220 and deep trenches 230 are filled with polysilicon, which can be doped polysilicon. The polysilicon completely fills the shallow trenches 220 and deep trenches 230. The combination of the filled shallow trenches 220 and deep trenches 230 forms an isolation structure. The method of filling with polysilicon is existing technology and will not be described in detail here.

[0038] Next, please refer to Figure 10A connection hole 240 is formed on the polysilicon surface within the shallow trench 220 on the front side of the substrate 210. The method for forming the connection hole 240 is prior art and will not be described in detail here. The number of connection holes 240 is not limited, and there can be multiple isolation structures; preferably, each isolation structure has one connection hole on its surface. In the prior art, since the shallow trench is filled with oxide and the deep trench is filled with polysilicon, the connection hole must be made on the polysilicon-doped side. Therefore, a portion of the back side of the substrate must be ground or etched to allow the connection hole to be led out in the polysilicon of the deep trench. However, in this embodiment of the invention, since the shallow trench is already filled with polysilicon, the connection hole can be led out on the front side of the substrate, which is simpler than leading out the connection hole on the back side of the substrate. The formation of the connection hole is prior art and will not be described in detail here.

[0039] Next, please refer to Figure 11 The back side of the substrate is ground or etched to expose the surface of the second end of the deep trench 230, thus thinning the substrate 210 overall and exposing the second end of the deep trench 230 on the back side of the substrate. In other words, the first end of the deep trench 230 is connected to the bottom of the shallow trench 220, and the second end, previously close to and at a certain distance from the back side of the substrate, is now exposed by etching or grinding the back side of the substrate. This isolation structure composed of the shallow trench 220 and the deep trench 230 completely separates the photodiode region. As CIS technology develops towards smaller pixel sizes, to maintain high FWC (full-well capacitance) and sensitivity, N-type ion implantation in the photodiode region becomes increasingly concentrated, potentially causing crosstalk between photodiode regions. Therefore, the isolation structure can suppress electrical and optical crosstalk.

[0040] In summary, the method for forming a CMOS image sensor provided in this embodiment of the invention includes: providing a substrate, the substrate including a front side and a back side of the substrate; forming an isolation trench on the front side of the substrate using an integrated etching process; forming a photodiode region in the remaining portion of the substrate, the isolation trench being adjacent to the photodiode region; filling the isolation trench with polysilicon to form an isolation structure; and forming a connection hole on the isolation structure. The FDTI fabrication technology of this patent employs an integrated etching process, starting from the front side of the substrate and etching trenches and deep trenches in a single step, then filling the trenches and deep trenches with polysilicon to form an isolation structure, and subsequently forming a connection hole on the isolation structure. This method has a simple fabrication process, and the potential can be accessed from the front side. Furthermore, the isolation structure suppresses crosstalk, dark current, and random telegraph noise on the surface of the photodiode region.

[0041] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method of forming a CMOS image sensor, characterized by, The application relates to a method for manufacturing a substrate, comprising: providing a substrate, the substrate comprising a substrate front side and a substrate back side; forming an isolation groove on the substrate front side by an integrated etching process; forming a photodiode region in the remaining substrate, the isolation groove being adjacent to the photodiode region; filling the isolation groove with polysilicon to form an isolation structure; and forming a connection hole on the isolation structure. The isolation groove comprises a shallow trench and a deep trench, the cross-sectional area of the shallow trench being larger than that of the deep trench, the first end of the deep trench being connected to the bottom of the shallow trench, and the second end of the deep trench being a certain distance from the substrate back side. After forming the connection hole on the isolation structure, the method further comprises grinding the substrate back side so that the ground substrate back side exposes the surface of the second end of the deep trench.

2. The method for forming a CMOS image sensor according to claim 1, wherein The polysilicon is doped polysilicon.

3. The method for forming a CMOS image sensor according to claim 1, wherein The isolation groove is multiple.

4. The method for forming a CMOS image sensor according to claim 1, wherein The photodiode region is multiple.

5. The method for forming a CMOS image sensor according to claim 1, wherein The isolation structure is multiple.

6. The method for forming a CMOS image sensor according to claim 1, wherein Each of the isolation structures has a connection hole.

7. The method for forming a CMOS image sensor according to claim 6, wherein The substrate comprises a wafer.

8. The method for forming a CMOS image sensor according to claim 1, wherein ​

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