Semiconductor device and method of forming the same

Abstract

A semiconductor device includes a substrate, a gate structure, a source / drain region, a first silicide layer, a second silicide layer, and a contact. The gate structure encloses at least one nanostructure channel vertical stack. The source / drain region is adjacent to the gate structure. The first silicide layer includes a first metal component on the source / drain region. The second silicide layer includes a second metal component different from the first metal component and is on the first silicide layer. The contact is on the second silicide layer. Embodiments of the present application also relate to methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. However, this shrinkage also increases the complexity of handling and manufacturing ICs. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor device, including: a substrate; a gate structure enclosing at least one nanostructured channel vertical stack; a source / drain region adjacent to the gate structure; a first silicide layer including a first metal component located on the source / drain region; a second silicide layer including a second metal component different from the first metal component, the second silicide layer being located on the first silicide layer; and a contact located on the second silicide layer.

[0004] Other embodiments of this application provide a semiconductor device, including: a substrate; a vertically stacked nanostructure located above the substrate; an N-type source / drain region adjacent to a first end of the nanostructure; a P-type source / drain region adjacent to a second end of the nanostructure; a P-type silicide layer located on the P-type source / drain region; an N-type silicide layer located on the N-type source / drain region and the P-type source / drain region; and a contact located on the N-type silicide layer.

[0005] Further embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first source / drain region and a second source / drain region on and in a substrate, the first source / drain region and the second source / drain region being laterally separated; forming a first silicide layer on the second source / drain region while masking the first source / drain region; forming a second silicide layer on the first source / drain region and the second source / drain region; and forming a contact on the second silicide layer above the first source / drain region and the second source / drain region. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A , Figure 1B These are schematic top views and cross-sectional side views of portions of an IC device manufactured according to embodiments of the present invention.

[0008] Figures 2A to 15 These are views of various embodiments of an IC device at various stages of manufacturing according to various aspects of the present invention.

[0009] Figure 16 , Figure 17 This is a flowchart illustrating a method for manufacturing a semiconductor device according to various aspects of the present invention. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] Terms indicating relative degrees, such as “about” and “basic,” should be interpreted as those of ordinary skill in the art would take into account current technical specifications. Generally, the term “basic” indicates a more stringent tolerance than the term “about.” For example, a thickness of “about 100 units” would include a wider range of values ​​than “basic 100 units,” such as 70 units to 130 units (+ / - 30%), while “basic 100 units” would include a smaller range of values, such as 95 units to 105 units (+ / - 5%). Similarly, such tolerances (+ / - 30%, + / - 5%, etc.) may depend on the process and / or equipment and should not be interpreted as more or less restrictive than those of ordinary skill in the art would consider normal for the technology in question, except that “about,” as a relative term, is not as stringent as “basic” when used in a similar context.

[0013] This invention relates generally to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructure devices (e.g., gate-all-around FETs (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel FETs, and nanoribbon transistors). At advanced technology nodes, device performance can be sensitive to the contact resistance between the source / drain epitaxial structure and the source / drain contacts (or “plugs”). Many devices employ a single work function silicide at each of the N-type and P-type epitaxial sites. N-type metal-oxide-semiconductor (NMOS) transistors can achieve better contact resistance if the silicide work function is close to the conduction band of silicon. However, P-type metal-oxide-semiconductor (PMOS) transistors exhibit excessively high silicide / epitaxy interface resistance. P-type epitaxial structures may also require high activation. Therefore, P-type dopant implantation can be implemented, which incurs higher costs due to the added photolithography operations.

[0014] Embodiments of the present invention utilize a front-end process (FEOL) dielectric hard mask (HM; or "spacer layer") on the N-type epitaxial structure during P+ implantation and P-function silicide processes. Using self-aligned P+ implantation prevents P+ implantation into the NMOS region. A self-aligned double silicide process combined with high P-type epitaxial activation can be achieved without additional photolithography costs. The use of double silicide for better contact resistance combined with self-aligned P+ implantation improves speed performance and reduces costs.

[0015] Nanostructured transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0016] Figure 1A , Figure 1B A schematic cross-sectional side view of a portion of the nanostructure device 20 is shown. Figure 1A This is a schematic side view of a portion of the nanostructure device 20 according to various embodiments. Figure 1B According to various other embodiments, along Figure 1A A schematic side view of a portion of the nanostructured device 20 with cross-sectional line BB.

[0017] refer to Figure 1A and Figure 1B The nanostructure device 20 may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). The nanostructure device 20 is formed above and / or within the substrate 110 and typically includes semiconductor fins 32 that span and / or wrap around and are located above the isolation structure 36, protruding from and separated by the isolation structure 36 (see...). Figure 1B The gate structure 200 of the semiconductor channels 22A-22C (optionally referred to as "nanostructures") controls the current flowing through the channels 22A-22C.

[0018] The nanostructure device 20 is shown to include three channels 22A-22C, which are laterally adjacent via source / drain components 82P, 82N (collectively referred to as "source / drain components 82") and are covered and surrounded by a gate structure 200. Typically, the number of channels 22 is two or more, such as three ( Figure 1A , Figure 1B (4 or more). The gate structure 200 controls the current flowing through the channels 22A-22C to and from the source / drain components 82 based on the voltage applied to the gate structure 200 and the source / drain components 82.

[0019] In some embodiments, the fin structure 32 comprises silicon. In some embodiments, the nanostructure device 20 comprises an NFET, and its source / drain components 82 comprise silicon-phosphorus (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, combinations thereof, etc. In some embodiments, the nanostructure device 20 comprises a PFET, and its source / drain components 82 comprise undoped or doped silicon-germanium (SiGe) to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or other suitable semiconductor materials. Typically, the source / drain components 82 may comprise any combination of suitable semiconductor materials and suitable dopants.

[0020] Each of channels 22A-22C comprises a semiconductor material, such as silicon or a silicon compound, such as silicon germanium. Channels 22A-22C are nanostructures (e.g., having dimensions in the range of a few nanometers) and may each have an elongated shape and extend in the X direction. In some embodiments, each of channels 22A-22C has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of channels 22A-22C may be rectangular, circular, square, toroidal, elliptical, hexagonal, or a combination thereof.

[0021] In some embodiments, the lengths of channels 22A-22C (e.g., measured in the X direction) may differ from one another, for example due to gradual tapering during the fin etching process (see...). Figure 3A , Figure 3B In some embodiments, the length of channel 22A may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22C. Each of channels 22A-22C may not have a uniform thickness (e.g., along the X-axis direction), for example due to channel trimming processes used to increase the spacing between channels 22A-22C (e.g., measured in the Z-axis direction) to increase the gate structure fabrication process window. For example, the middle portion of each of channels 22A-22C may be thinner than the two ends of each of channels 22A-22C. Such a shape can be collectively referred to as a "dog bone" shape, and... Figure 1A As shown in the image.

[0022] In some embodiments, the spacing between channels 22A-22C (e.g., between channel 22B and channel 22A or channel 22C) is in the range of about 8 nanometers (nm) to about 12 nm. In some embodiments, the thickness of each of channels 22A-22C (e.g., measured in the Z direction) is in the range of about 5 nm to about 8 nm. In some embodiments, the width of each of channels 22A-22C (e.g., measured in the Y direction, not in the Z direction) is... Figure 1AThe image shows that the wavelength (orthogonal to the XZ plane) is at least about 8 nm.

[0023] Gate structures 200 are respectively disposed above and between channels 22A-22C. In some embodiments, the gate structure 200 is disposed above and between channels 22A-22C, where channels 22A-22C are silicon channels for N-type devices or silicon-germanium channels for P-type devices. In some embodiments, the gate structure 200 includes an interface layer (IL) 210, one or more gate dielectric layers 600, and one or more power function adjustment layers 900 (see...). Figure 15 ) and metal filler layer 290.

[0024] An interface layer 210, which may be an oxide of the material used for channels 22A-22C, is formed on the exposed regions of channels 22A-22C and the top surface of fin 32. The interface layer 210 facilitates adhesion of the gate dielectric layer 600 to channels 22A-22C. In some embodiments, the interface layer 210 has a thickness of about 5 angstroms (Å) to about 50 angstroms (Å). In some embodiments, the interface layer 210 has a thickness of about 10 Å. An interface layer 210 that is too thin may exhibit voids or insufficient adhesion. An interface layer 210 that is too thick will consume the gate fill window, which is related to threshold voltage adjustment and resistance as described above. In some embodiments, the interface layer 210 is doped with a dipole, such as lanthanum, for threshold voltage adjustment.

[0025] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 Å to about 100 Å.

[0026] In some embodiments, the gate dielectric layer 600 may include dopants of varying concentrations to achieve threshold voltage adjustment, such as metal ions driven into the high-k gate dielectric from La2O3, MgO, Y2O3, TiO2, Al2O3, Nb2O5, etc., or boron ions driven into B2O3. As an example, for N-type transistor devices, a higher concentration of lanthanum ions reduces the threshold voltage compared to a layer with a lower concentration or no lanthanum ions, while the opposite is true for P-type devices. In some embodiments, the gate dielectric layer 600 of certain transistor devices (e.g., I / O transistors) does not contain dopants present in certain other transistor devices (e.g., N-type core logic transistors or P-type I / O transistors). In N-type I / O transistors, for example, a relatively high threshold voltage is desired, thus making it preferable that the high-k dielectric layer of the I / O transistor is free of lanthanum ions, which would otherwise reduce the threshold voltage.

[0027] In some embodiments, the gate structure 200 further includes one or more function metal layers, collectively referred to as function metal layer 900. When configured as an NFET, the function metal layer 900 of the nanostructure device 20 may include at least an N-type function metal layer, an in-situ capping layer, and an oxygen barrier layer. In some embodiments, the N-type function metal layer is or includes an N-type metallic material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The in-situ capping layer is formed on the N-type function metal layer and may include TiN, TiSiN, TaN, or other suitable materials. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen diffusion into the N-type function metal layer, which would cause an undesirable shift in the threshold voltage. The oxygen barrier layer may be formed of a dielectric material that can prevent oxygen from penetrating into the N-type function metal layer and can protect the N-type function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the function metal layer 900 includes more or fewer layers than those described.

[0028] The power-function metal layer 900 may also include one or more barrier layers comprising metal nitrides such as TiN, WN, MoN, TaN, etc. Each of the one or more barrier layers may have a thickness ranging from about 5 Å to about 20 Å. Including one or more barrier layers provides additional threshold voltage adjustment flexibility. Typically, each additional barrier layer increases the threshold voltage. Therefore, for NFETs, higher threshold voltage devices (e.g., IO transistor devices) may have at least one or more additional barrier layers, while lower threshold voltage devices (e.g., core logic transistor devices) may have few or no additional barrier layers. For PFETs, higher threshold voltage devices (e.g., IO transistor devices) may have few or no additional barrier layers, while lower threshold voltage devices (e.g., core logic transistor devices) may have at least one or more additional barrier layers. Following the preceding discussion, the threshold voltage is described in terms of amplitude. As an example, NFET IO transistors and PFET IO transistors may have similar threshold voltages in terms of amplitude, but with opposite polarities, such as +1 volt for an NFET IO transistor and -1 volt for a PFET IO transistor. Therefore, because each additional barrier layer increases the absolute value of the threshold voltage (e.g., +0.1 volts / layer), such an increase leads to an increase in the threshold voltage (amplitude) of the NFET transistor and a decrease in the threshold voltage (amplitude) of the PFET transistor.

[0029] Gate structure 200 also includes a metal filler layer 290. The metal filler layer 290 may include a conductive material such as Co, W, Ru, or combinations thereof. In some embodiments, the metal filler layer 290 is or includes a compound or alloy based on Co, W, or Ru, comprising one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, or combinations thereof. Between channels 22A-22C, the metal filler layer 290 is circumferentially surrounded by one or more function metal layers 900 (in the cross-sectional view), which are then circumferentially surrounded by a gate dielectric layer 600, which is circumferentially surrounded by an interface layer 210. Gate structure 200 may also include an adhesive layer formed between one or more function layers 900 and the metal filler layer 290 to increase adhesion. For simplicity, the adhesive layer is not shown. Figure 1A , Figure 1B This is shown in detail in the text.

[0030] Located above the gate dielectric layer 600 and the gate fill layer 290 are a first capping layer 204 and a second capping layer 295. The first capping layer 204 protects the gate structure 200. In some embodiments, the first capping layer 204 is or includes a dielectric material such as SiO2, SiN, SiCN, SiOCN, a high-k dielectric material (e.g., Al2O3), etc. In some embodiments, the first capping layer 204 has a thickness in the range of about 1 nm to about 5 nm (e.g., in the Z-axis direction). The first capping layer 204 can prevent current leakage after one or more etching operations, which can be performed to form gate contacts, source / drain contacts 120, isolation structures (e.g., source / drain contact isolation structures), etc. In some embodiments, the first capping layer 204 is or includes a dielectric material harder than, for example, the second capping layer 295, such as alumina or other suitable dielectric materials.

[0031] The second capping layer 295, also known as a "self-aligned capping" (SAC) layer, provides protection for the underlying gate structure 200 and can also serve as a CMP stop layer when the source / drain contacts 120 are planarized after their formation. The second capping layer 295 can be a dielectric layer comprising a dielectric material such as SiO2, SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, or ZrAlO2. x HfAlO x HfSiO x Al2O3, BN, or other suitable dielectric materials. In some embodiments, the second capping layer 295 may be separated by a support structure over the longer gate structure and channel. In some embodiments, the width (X direction) of the second capping layer 295 is in the range of about 8 nm to about 40 nm.

[0032] The nanostructure device 20 also includes a gate spacer 41 disposed on the sidewalls of the gate dielectric layer 600 and IL 210 above channel 22A, and an internal spacer 74 disposed on the sidewalls of IL 210 between channels 22A-22C. The internal spacer 74 is also disposed between channels 22A-22C. The gate spacer 41 and the internal spacer 74 may comprise a dielectric material, such as a low-k material, such as SiOCN, SiON, SiN, or SiOC. In some embodiments, one or more additional spacer layers 49 now abut the gate spacer 41, such as... Figure 1A As shown in the image.

[0033] The nanostructure device 20 may also include a source / drain contact 120 formed above the source / drain component 82. Figure 1A , Figure 1BAs shown in the diagram; collectively referred to as "source / drain contact 120"). Source / drain contact 120 may comprise conductive materials such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or combinations thereof. Source / drain contact 120 may be surrounded by a barrier layer (not shown), such as SiN or TiN, which helps prevent or reduce material diffusion from and into source / drain contact 120. In some embodiments, the height of source / drain contact 120 may range from about 1 nm to about 50 nm. In some embodiments, spacer layer 133 is present between source / drain contact 120 and the second capping layer 295, spacer layers 41 / 49, and gate structure 200. In some embodiments, spacer layer 133 is or includes one or more of SiN, SiCN, SiOCN, high-k dielectrics, SiO2, etc. The spacer layer 133 may have a thickness ranging from about 2 nm to about 6 nm. The spacer layer 133 is configured to prevent electrical short circuits between the gate structure 200 and the source / drain contacts 120.

[0034] A silicide layer 118P, 118N (or collectively referred to as "silicide layer 118") is formed between the source / drain component 82 and the source / drain contact 120 to at least reduce the source / drain contact resistance. The silicide layer 118N may also be referred to as an "N-type power function silicide". The silicide layer 118N includes a portion that contacts the source / drain component 82N and a portion that contacts the silicide layer 118P above the source / drain component 82P. In some embodiments, the silicide layer 118N is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. The silicide layer 118N may have a thickness in the range of about 1 nm to about 10 nm. A thickness less than about 1 nm may result in insufficient reduction of contact resistance. A thickness exceeding approximately 10 nm could lead to an electrical short circuit with nanostructure 22. In some embodiments, the silicide layer 118N is present below and in contact with the spacer layer 133, such as... Figure 1A As shown in the image.

[0035] The silicide layer 118P can also be referred to as a "P-type power function silicide". In some embodiments, the silicide layer 118P includes a first silicide layer 118P1 and a silicide layer 118N. The first silicide layer 118P1 may be in contact with the source / drain component 82P. In some embodiments, the first silicide layer 118P1 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The first silicide layer 118P1 may have a thickness in the range of about 1 nm to about 10 nm. A thickness less than about 1 nm may result in insufficient reduction of contact resistance. A thickness greater than about 10 nm may result in an electrical short circuit with the nanostructure 22. In some embodiments, the first silicide layer 118P1 exists below and in contact with the spacer layer 133, such as Figure 1A As shown in the image.

[0036] In some embodiments, the P+ dopant may be present in the P+ doped region 103R of the source / drain component 82P beneath the first silicide layer 118P1 (see...). Figure 11C In ), this will refer to Figure 11C More detailed description. P+ dopant can be implanted before the formation of the first silicide layer 118P1, and can include, for example, Ga, B, C, Sn, etc. Using P+ implantation can reduce contact resistance. The concentration of P+ dopant in the source / drain region 82P can be approximately 1 x 10⁻⁶. 18 cm -3 To approximately 1x10 21 cm -3 Within that range. Exceeding approximately 1×10 21 cm -3 The second P-type epitaxial region 82P1 of the source / drain region 82P may be damaged. The implantation depth of the P+ dopant can range from about 3 nm to about 10 nm. The region implanted with the P+ dopant may not fully react with the metal used to form the silicide layer. Therefore, the P+ doped region 103R can remain below the first silicide layer 118P1.

[0037] The silicide layer 118N located above the source / drain component 82P may have the same or similar material composition as the silicide layer 118N located above the source / drain component 82N, and may have a different thickness than the silicide layer 118N located above the source / drain component 82N. In some embodiments, the first silicide layer 118P1 is thicker than the portion of the silicide layer 118N located above the source / drain component 82P. In some embodiments, the ratio of the thickness of the first silicide layer 118P1 to the thickness of the silicide layer 118N above the source / drain component 82P is in the range of about 3 to about 5. The fact that the first silicide layer 118P1 is thicker than the silicide layer 118N can reduce the contact resistance between the source / drain contact 120 and the source / drain component 82P. In some embodiments, the thickness of the silicide layer 118N on the source / drain component 82N is substantially the same as the thickness of the first silicide layer 118P1 on the source / drain component 82P.

[0038] In some embodiments, the nanostructure device 20 further includes an interlayer dielectric (ILD) 130 (see... Figure 1B ILD 130 provides electrical isolation between the various components of the nanostructured device 20 discussed above, such as between the gate structure 200 and the source / drain contacts 120 therebetween. An etch stop layer (not shown) may be formed prior to the formation of ILD 130 and may be laterally positioned between ILD 130 and the gate spacer 41 and vertically positioned between ILD 130 and the source / drain components 82. In some embodiments, the etch stop layer is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO2. x HfAlO x HfSiO x Al2O3 or other suitable materials. In some embodiments, the thickness of the etch stop layer is in the range of about 1 nm to about 5 nm. In some embodiments, the etch stop layer may contact the source / drain contact 120 in the absence of ILD 130 (e.g., completely removed before forming the source / drain contact 120). For example, the etch stop layer may be trimmed in the X-axis direction before forming the source / drain contact 120 to improve the filling quality of the source / drain contact 120.

[0039] Figure 16 , Figure 17A flowchart of a method 1000, 2000 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of the present invention is shown. Methods 1000, 2000 are merely examples and are not intended to limit the invention to what is expressly shown in methods 1000, 2000. Additional steps may be provided before, during, and after methods 1000, 2000, and for additional embodiments of the method, some described steps may be replaced, eliminated, or moved. For simplicity, not all steps are described in detail herein. The following describes workpieces at different stages of manufacturing according to embodiments of methods 1000, 2000 (… Figures 2A to 15 The partial perspective views and / or cross-sectional views shown in the figures are described in methods 1000 and 2000. To avoid ambiguity, in all figures, the X direction is perpendicular to the Y direction and the Z direction is perpendicular to both the X and Y directions. It should be noted that because the workpiece can be manufactured into a semiconductor device, the workpiece may be referred to as a semiconductor device depending on the context.

[0040] Figures 2A to 15 These are perspective and cross-sectional views of intermediate stages in the fabrication of FETs (such as nanosheet FETs) according to some embodiments. Figure 2A , Figure 3A , Figure 4A , Figure 5A and Figure 6A A three-dimensional view is shown. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11C , Figure 12B , Figure 13B and Figure 14B It shows along Figure 2A , Figure 3A , Figure 4A , Figure 5A and Figure 6A The side view shown is taken from the reference section B-B' (gate cut). Figure 4C , Figure 5C , Figure 6C , Figure 6D , Figure 7A , Figure 8A , Figure 9A , Figure 9C , Figure 9D , Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 14A It shows along Figure 4AThe side view shown is taken from the reference section C-C' (channel / fin cut). Figure 14C An alternative embodiment in the XZ plane is shown.

[0041] exist Figure 2A and Figure 2B A substrate 110 is provided. The substrate 110 can be a semiconductor substrate, such as a bulk semiconductor, which can be doped (e.g., using p-type or n-type dopants) or undoped. The semiconductor material of the substrate 110 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium; or combinations thereof. Other substrates, such as single-layer, multi-layer, or gradient substrates, can be used.

[0042] Further in Figure 2A and Figure 2B In this configuration, a multilayer stack 25 or "lattice" is formed over a substrate 110 of alternating layers of first semiconductor layers 21A-21C (collectively referred to as first semiconductor layer 21) and second semiconductor layers 23A-23C (collectively referred to as second semiconductor layer 23). In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for n-type nanoFETs, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 may be formed of a second semiconductor material suitable for p-type nanoFETs, such as silicon germanium, etc. Each layer of the multilayer stack 25 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0043] Three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown. In some embodiments, the multilayer stack 25 may include one or two of each of the first semiconductor layer 21 and the second semiconductor layer 23, or four or more of each of the first semiconductor layer 21 and the second semiconductor layer 23. Although the multilayer stack 25 is shown as including the second semiconductor layer 23C as the bottom layer, in some embodiments, the bottom layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0044] Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form the channel region of the nano-FET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region. The high etch selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form the channel region of the nanostructure FET.

[0045] exist Figure 3A and Figure 3B In this process, fins 32 are formed in the substrate 110 and nanostructures 22 and 24 are formed in the multilayer stack 25, corresponding to Figure 16 Step 1100. In some embodiments, nanostructures 22, 24 and fins 32 can be formed by etching trenches in the multilayer stack 25 and substrate 110. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. Etching can be anisotropic. The first nanostructures 22A-22C (hereinafter also referred to as “channels”) are formed by the first semiconductor layer 21, and the second nanostructure 24 is formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 can range from about 18 nm to about 100 nm. For simplicity, portions of device 10 are shown in... Figure 3A and Figure 3B As shown, it includes two fins 32. Figures 2A to 15 The process 1000 shown can be extended to any number of fins, and is not limited to this. Figures 3A to 15 The two fins 32 shown.

[0046] Fins 32 and nanostructures 22, 24 can be patterned using any suitable method. For example, fins 32 and nanostructures 22, 24 can be formed using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for spacing smaller than that achievable using a single, direct photolithography process. As an example of a multi-patterning process, a sacrificial layer can be formed and patterned using a photolithography process over a substrate. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fins 32.

[0047] Figure 3A and Figure 3BA fin 32 with tapered sidewalls is shown, such that the width of each of the fins 32 and / or nanostructures 22, 24 increases continuously in the direction toward the substrate 110. In such an embodiment, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the fins 32 and nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

[0048] exist Figure 3A and Figure 3B An isolation region 36 is formed adjacent to the fin 32, which may be a shallow trench isolation (STI) region. The isolation region 36 can be formed by depositing an insulating material over the substrate 110, the fin 32, and the nanostructures 22, 24, and between adjacent fins 32 and nanostructures 22, 24. The insulating material can be an oxide, such as silicon oxide, nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. In some embodiments, a liner (not shown separately) can be formed first along the surface of the substrate 110, the fin 32, and the nanostructures 22, 24. Subsequently, a filler material, such as those discussed above, can be formed over the liner.

[0049] The insulating material undergoes removal processes, such as chemical mechanical polishing (CMP), etching back, and combinations thereof, to remove excess insulating material above the nanostructures 22 and 24. After the removal processes are complete, the top surfaces of the nanostructures 22 and 24 can be exposed and flush with the insulating material.

[0050] The insulating material is then recessed to form the isolation region 36. After recessing, the upper portions of the nanostructures 22, 24 and the fins 32 can protrude between adjacent isolation regions 36. The isolation region 36 may have a flat, convex, concave, or a combination thereof top surface, as shown. In some embodiments, the isolation region 36 is recessed by an acceptable etching process, such as using an oxide such as dilute hydrofluoric acid (dHF) for removal, which is selective to the insulating material and leaves the fins 32 and nanostructures 22, 24 substantially unchanged.

[0051] Figures 2A to 3B An embodiment of forming fins 32 and nanostructures 22, 24 is shown (e.g., post-etching). In some embodiments, fins 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in a dielectric layer (e.g., pre-etching). The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

[0052] Further in Figure 3A and Figure 3BSuitable wells (not shown separately) can be formed in fins 32, nanostructures 22, 24, and / or isolation regions 36. Using a mask, n-type impurity implantation can be performed in the p-type region of substrate 110, and p-type impurity implantation can be performed in the n-type region of substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary p-type impurities may include boron, boron fluoride, indium, etc. Annealing can be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during the epitaxial growth of fins 32 and nanostructures 22, 24 can avoid separate implantation, but in-situ and implantation doping can be used together.

[0053] exist Figures 4A to 4C In the middle, a pseudo-gate structure 40 is formed above fins 32 and / or nanostructures 22, 24, corresponding to Figure 16 Step 1200. A dummy gate layer 45 is formed over the fins 32 and / or nanostructures 22, 24. The dummy gate layer 45 may be made of a material with high etch selectivity relative to the isolation region 36. The dummy gate layer 45 may be a conductive, semi-conductive, or non-conductive material and may be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. A mask layer 47, which may include, for example, silicon nitride, silicon oxynitride, etc., is formed over the dummy gate layer 45. In some embodiments, a gate dielectric layer (not shown for simplicity) is formed before the dummy gate layer 45 between the dummy gate layer 45 and the fins 32 and / or nanostructures 22, 24. In some embodiments, the mask layer 47 includes a first mask layer 47A in contact with the dummy gate layer 45 and a second mask layer 47B located above the first mask layer 47A. The first mask layer 47A may be or include materials that are the same as or different from the material of the second mask layer 47B.

[0054] A spacer layer 41 is formed above the sidewalls of the mask layer 47 and the dummy gate layer 45, corresponding to Figure 16Step 1300. According to some embodiments, the spacer layer 41 is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The spacer layer 41 can be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. According to some embodiments, an anisotropic etching process is used to remove the portion of the spacer material layer located between the dummy gate structures 40. In some embodiments, the spacer layer 41 includes a first spacer layer 41A in contact with the nanostructure 22A, the gate dielectric layer 43, the dummy gate layer 45, and the first mask layer 47A and the second mask layer 47B. A second spacer layer 41B of the spacer layer 41 may be in contact with the first spacer layer 41A and the nanostructure 22A. The first spacer layer 41A may be or include a material that is the same as or different from the material of the second spacer layer 41B.

[0055] Figures 4A to 4C A process for forming spacer layer 41 is illustrated. In some embodiments, spacer layer 41 is formed alternately or additionally after the removal of dummy gate layer 45. In such an embodiment, dummy gate layer 45 is removed, leaving an opening, and spacer layer 41 can be formed by conformally coating the material of spacer layer 41 along the sidewalls of the opening. The conformally coated material can then be removed from the bottom of the top surface of the opening corresponding to the uppermost channel (e.g., channel 22A) before forming an active gate such as gate structure 200.

[0056] Although Figures 4A to 4C Not specifically shown, but in some embodiments, the hybrid fin 94 is formed after the isolation region 36 and before the dummy gate structure 40 is formed. The hybrid fin 94 can be formed by first depositing a pad layer 93 to cover... Figure 4B The nanostructures 22 and 24 shown are stacked, and then a fill layer 95 is deposited to fill the remaining portion of the openings located between the stacks in a self-aligned process. Excess material on the nanostructure 22A, including the pad layer 93 and the fill layer 95, is then removed, for example, by a planarization process such as CMP. If included, a gate isolation structure 99 is then formed over the hybrid fin 94.

[0057] exist Figures 5A to 5CIn this process, an etching process is performed to etch the portions of the protruding fins 32 and / or nanostructures 22, 24 that are not covered by the dummy gate structure 40, thereby producing the structure shown. The recess can be anisotropic, thereby protecting and not etching the portion of the fin 32 directly beneath the dummy gate structure 40 and the spacer layer 41. According to some embodiments, the top surface of the recessed fin 32 can be substantially coplanar with the top surface of the isolation region 36, as shown. According to some other embodiments, the top surface of the recessed fin 32 can be lower than the top surface of the isolation region 36. For simplicity, Figure 5C The image shows a vertically stacked assembly of three nanostructures 22, 24 after the etching process. Typically, the etching process can be used to form any number of vertically stacked nanostructures 22, 24 above the fin 32. In some embodiments, the second mask layer 47B is exposed after the etching process, for example, due to the removal of the upper portions of the spacer layers 41A, 41B during the etching process.

[0058] Figures 6A to 6D The internal spacer 74 is shown, corresponding to Figure 16 Step 1300. A selective etching process is performed to recess the end portions of the nanostructure 24 exposed by the openings in the spacer layer 41 without substantially eroding the nanostructure 22. After the selective etching process, a groove 64 is formed at the location where the removed end portions of the nanostructure 24 were once located. The resulting structure... Figure 6A , Figure 6C It is displayed in the middle.

[0059] refer to Figure 6D Next, an internal spacer layer is formed to fill the recesses 64 in the nanostructure 22 formed by the previous selective etching process. The internal spacer layer can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon carbonitride oxycarbonitride (SiOCN), etc., formed by a suitable deposition method such as PVD, CVD, ALD, etc. An etching process, such as anisotropic etching, is performed to remove the portion of the internal spacer layer disposed outside the recesses 64 in the nanostructure 24. The remaining portion of the internal spacer layer (e.g., the portion disposed inside the recesses 64 in the nanostructure 24) forms the internal spacer 74. The resulting structure is... Figure 6D It is displayed in the middle.

[0060] Figures 7A to 8BThe diagram illustrates the formation of source / drain regions 82, including an N-type source / drain region 82N and a P-type source / drain region 82P. In the illustrated embodiment, the source / drain regions 82N and 82P are epitaxially grown from an epitaxial material. In some embodiments, the source / drain regions 82N and 82P are stressed in their respective channels 22A-22C to improve performance. The source / drain regions 82N and 82P are formed such that each dummy gate structure 40 is disposed between corresponding adjacent pairs of source / drain regions 82. In some embodiments, a spacer layer 41 separates the source / drain regions 82 from the dummy gate layer 45 by an appropriate lateral distance to prevent bridging to the subsequently formed gate of the resulting device.

[0061] like Figure 7A , Figure 7B As shown, the N-type source / drain region 82N can be formed prior to the formation of the P-type source / drain region 82P. In some embodiments, the first N-type epitaxial region 82N0 is grown in the first epitaxial process. The first N-type epitaxial region 82N0 can be formed on the exposed surface of the fin 32 located in certain portions of the opening 550 (see Figure 1). Figure 6D This simultaneously masks other portions of the opening 550. A first N-type epitaxial region 82N0 is also formed on the exposed surface of the nanostructure 22 and may not be formed substantially on the internal spacer 74. After the first N-type epitaxial region 82N0 is formed in the first epitaxial process, a second N-type epitaxial region 82N1 is formed in the second epitaxial process. In some embodiments, the second epitaxial process differs from the first epitaxial process, for example, in terms of the flow rate ratio, temperature, pressure, or other suitable parameters of the constituent gases. In some embodiments, there is a smooth transition between the first and second epitaxial processes, allowing the first epitaxial region 82N0 and the second epitaxial region 82N1 to be formed without substantially interrupting the flow of the constituent gases. The second N-type epitaxial region 82N1 may extend from the upper surface of the first epitaxial region 82N0 on the fin 32 to the level at or near the upper surface of the nanostructure 22A. Figure 7A As shown, the second N-type epitaxial region 82N1 may extend above the level of the gate dielectric layer 43 and contact the spacer layer 41. In some embodiments, the second N-type epitaxial region 82N1 may have a concave upper surface (as shown) or a substantially flat or convex surface. (See reference...) Figure 1A , Figure 1B As described, the N-type epitaxial regions 82N0 and 82N1 can be or include SiP, SiAs, SiSb, SiPA, SiP:As:Sb, etc.

[0062] After forming the N-type source / drain region 82N, a second spacer layer 65 can be formed as a conformal thin layer covering the spacer layer 41, the hard mask layer 47, the N-type source / drain region 82N, and the exposed surfaces of the nanostructures 22, fins 32, and internal spacers 74 located in the opening 550. The second spacer layer 65 protects the N-type source / drain region 82N in subsequent processes. In some embodiments, the second spacer layer 65 is or includes SiN, SiCN, SiOCN, SiO, a high-k dielectric material, or other suitable materials. The second spacer layer 65 can be deposited with a thickness ranging from about 2 nm to about 6 nm. The second spacer layer 65 can be a front-end process (FEOL) dielectric hard mask layer and can be referred to as dielectric hard mask layer 65.

[0063] exist Figure 7C , Figure 7D In the process, after the second spacer layer 65 is formed, the spacer layer is removed. Figure 7B , Figure 7C The portion of the second spacer layer 65 shown above the opening 550 restores the opening 550 and exposes the fin 32 and nanostructure 22 for use in p-type epitaxial growth (see, for example). Figure 8A In some embodiments, a photoresist layer 67 is formed and patterned to expose the opening 550 while masking the second spacer layer 65 above the N-type source / drain region 82N, as shown. After the photoresist layer 67 is formed and patterned, the exposed portions of the second spacer layer 65 are removed by, for example, a suitable etching process, such as isotropic or anisotropic etching using an etchant that is selective to the material of the second spacer layer 65 and substantially does not corrode the underlying structure. The photoresist layer 67 can then be removed, for example, by ashing, rinsing, and / or other suitable removal methods.

[0064] exist Figure 8A , Figure 8B In this process, a P-type source / drain region 82P is formed in an opening 550 on the exposed portion of the fin 32 and nanostructure 22. The P-type source / drain region 82P can be formed after the formation of the N-type source / drain region 82N. In some embodiments, a first P-type epitaxial region 82P0 is grown in a third epitaxial process. The first P-type epitaxial region 82P0 can be formed on the exposed surface of the fin 32 located in certain portions of the opening 550 (see...). Figure 7CThe remaining portion of the N-type source / drain region 82N formed by the opening 550 is masked by the second spacer layer 65. A first P-type epitaxial region 82P0 is also formed on the exposed surface of the nanostructure 22 and may not be formed on the internal spacer 74. After the first P-type epitaxial region 82P0 is formed in the third epitaxial process, a second P-type epitaxial region 82P1 is formed in the fourth epitaxial process. In some embodiments, the fourth epitaxial process differs from the third epitaxial process, for example, in terms of the flow rate ratio, temperature, pressure, or other suitable parameters of the constituent gases. In some embodiments, there is a smooth transition between the third and fourth epitaxial processes, allowing the first epitaxial region 82P0 and the second epitaxial region 82P1 to be formed without substantially interrupting the flow of the constituent gases. The second P-type epitaxial region 82P1 may extend from the upper surface of the first epitaxial region 82P0 on the fin 32 to the level at or near the upper surface of the nanostructure 22A. Figure 8A As shown, the second P-type epitaxial region 82P1 may extend above the level of the gate dielectric layer 43 and contact the spacer layer 41. In some embodiments, the second P-type epitaxial region 82P1 may have a concave upper surface (as shown) or a substantially flat or convex surface. (See reference...) Figure 1A , Figure 1B As described, the P-type epitaxial regions 82P0 and 82P1 can be or include SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, etc. The source / drain region 82P material can be subjected to compressive strain in the channel region. The source / drain region 82P can have a surface protruding from the corresponding surface of the fin and can have a small facet. In some embodiments, adjacent source / drain regions 82 can be merged to form a single source / drain region 82 adjacent to two adjacent fins 32.

[0065] After forming the P-type source / drain region 82P, another second spacer layer 65R is formed as a conformal thin layer covering the second spacer layer 65 and the P-type source / drain region 82P, such as Figure 8A , Figure 8B As shown in the diagram. The second spacer layer 65R can be similar to the second spacer layer 65 in many respects. In some embodiments, the second spacer layer 65R is or includes SiN, SiCN, SiOCN, SiO, a high-k dielectric material, or other suitable materials. The second spacer layer 65R can be deposited with a thickness ranging from about 2 nm to about 6 nm. Figure 8A , Figure 8B As shown, the second spacer layer 65R can be formed with a distinct downward step at the end of the second spacer layer 65 in the prominent display areas 800C, 800D, thereby making the second spacer layer 65R discontinuous on either side of the end of the second spacer layer 65. (Reference) Figure 8C, Figure 8D In some embodiments, the second spacer layer 65R is continuous and exhibits a smooth transition at the end of the second spacer layer 65. The second spacer layer 65R may be a FEOL dielectric hard mask layer and may be referred to as the second dielectric hard mask layer 65R.

[0066] After forming the second spacer layer 65R, a third spacer layer 85 is formed over the second spacer layer 65R as a conformal thin layer. In some embodiments, the third spacer layer 85 is formed by depositing a dielectric material, such as SiN, SiCN, SiOCN, SiO, a high-k dielectric material, or other suitable materials. The third spacer layer 85 may be a FEOL dielectric hard mask layer and may be referred to as the third dielectric hard mask layer 65R. The third spacer layer 85 may be deposited with a thickness ranging from about 2 nm to about 6 nm. In some embodiments, the third spacer layer 85 is or includes a material different from the material of the second spacer layers 65, 65R. For example, the third spacer layer 85 may be a thin layer of SiCN, and one or more of the second spacer layers 65, 65R may be thin layers of SiN. The formation of the second spacer layers 65, 65R and the third spacer layer 85 corresponds to Figure 16 Step 1400.

[0067] After the third spacer layer 85 is formed, the ILD 130 can be formed on top of the third spacer layer 85. In some embodiments, the ILD 130 is formed by depositing a dielectric material, such as SiO, SiN, SiC, SiOCN, SiOC, SiCN, AlO, AlON, ZrSi, ZrO, ZrN, ZrAlO, LaO, HfO, HfSi, YO, TiO, TaO, TaCN, ZnO, etc. Due to the presence of the second pad layer 65 above the N-type source / drain region 82N, the ILD 130 can have a larger width above the P-type source / drain region 82P than above the N-type source / drain region 82N. The ILD 130 can have a larger aspect ratio above the N-type source / drain region 82N than above the P-type source / drain region 82P. The aspect ratio may be related to the ability of the deposition process to fill the opening without forming voids. A larger aspect ratio is generally associated with greater difficulty in filling the opening. Therefore, if any of the spacer layers 65, 65R, and 85 were formed to a thickness greater than approximately 6 nm, the aspect ratio and the difficulty of forming a void-free ILD 130 could increase to a level that is not achievable by known deposition processes. Another reason for keeping the thickness of the spacer layers 65, 65R, and 85 below approximately 6 nm per layer is to avoid completely filling the opening above the source / drain region 82 with the spacer layers 65, 65R, and 85 without leaving any space to fill the ILD 130.

[0068] like Figure 8A , Figure 8B As shown, the third spacer layer 85 can be formed with a distinct downward step at the end of the second spacer layer 65R in the prominent display areas 800C, 800D, thereby making the third spacer layer 85 discontinuous on either side of the end of the second spacer layer 65R. (Reference) Figure 8C , Figure 8D In some embodiments, the third spacer layer 85 is continuous and presents a smooth transition at the end of the second spacer layer 65R.

[0069] Figures 9A to 9D The formation of the active gate structure 200 is shown, corresponding to Figure 16 Step 1500. Channels 22A-22C are released by removing nanostructure 24, mask layer 47, and dummy gate layer 45. A planarization process, such as CMP, is performed to flush the top surfaces of the dummy gate layer 45 and the gate spacer layer 41. The planarization process may also remove the mask layer 47 on the dummy gate layer 45 and portions of the gate spacer layer 41 along the sidewalls of the mask layer 47. Therefore, the top surface of the dummy gate layer 45 is exposed.

[0070] Next, the dummy gate layer 45 is removed in an etching process to form the recess 92. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the spacer layer 41. When the dummy gate layer 45 is etched, the dummy gate dielectric (if present) may be used as an etch stop layer. The dummy gate dielectric may then be removed after the dummy gate layer 45 has been removed.

[0071] Nanostructure 24 is removed to release nanostructure 22. After removal of nanostructure 24, nanostructure 22 forms a plurality of horizontally extending (e.g., parallel to the main upper surface of substrate 110) nanosheets. In some embodiments, nanostructure 24 is removed by a selective etching process using an etchant selective to the material of nanostructure 24, thereby removing nanostructure 24 without substantially eroding nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, combinations thereof, etc.

[0072] In some embodiments, nanostructure 24 is removed and nanostructure 22 is patterned to form the channel regions of the PFET and NFET. However, in some embodiments, nanostructure 24 can be removed and nanostructure 22 can be patterned to form the channel region of the NFET, and nanostructure 22 can be removed and nanostructure 24 can be patterned to form the channel region of the PFET. In some embodiments, nanostructure 22 can be removed and nanostructure 24 can be patterned to form the channel region of the NFET, and nanostructure 24 can be removed and nanostructure 22 can be patterned to form the channel region of the PFET. In some embodiments, nanostructure 22 can be removed and nanostructure 24 can be patterned to form the channel regions of the PFET and NFET.

[0073] In some embodiments, the nanosheet 22 is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. Reshaping can be performed using a selective isotropic etching process on the nanosheet 22. After reshaping, the nanosheet 22 can have a dog-bone shape, wherein the central portion of the nanosheet 22 is thinner along the X-direction than the peripheral portion.

[0074] Then a replacement gate 200 is formed. Figure 15 This is a detailed view of a portion of the gate structure 200. The gate structure 200 typically includes an interface layer (IL, or "first IL" below) 210, at least one gate dielectric layer 600, a power function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interface layer 240 or a second power function layer 700.

[0075] refer to Figure 15 In some embodiments, the first IL 210 comprises an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the first IL 210 may comprise another suitable type of dielectric material. The first IL 210 has a thickness in the range of about 5 angstroms to about 50 angstroms.

[0076] Still referencing Figure 15 A gate dielectric layer 600 is formed over the first IL 210. In some embodiments, an atomic layer deposition (ALD) process is used to form the gate dielectric layer 600 to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is implemented using between about 40 and 80 deposition cycles in a temperature range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and / or H2O as precursors. Such an ALD process can form the first gate dielectric layer 220 to have a thickness in the range of about 10 angstroms to about 100 angstroms.

[0077] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, wherein at least one includes a dopant, such as lanthanum, magnesium, yttrium, etc., which can be driven in by an annealing process to modify the threshold voltage of the nanostructured device 20A-20E.

[0078] Further reference Figure 15 A second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 further provides improved thermal stability to the gate structure 200 and serves to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is accomplished by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer comprises one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO, or other suitable materials. In a specific embodiment, the high-k capping layer comprises titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited by ALD at a temperature of about 40 to about 450 degrees Celsius using about 40 to about 100 cycles. Thermal annealing is then performed to form a second IL 240, which in some embodiments may be or include TiSiNO. After forming the second IL 240 by thermal annealing, atomic layer etching (ALE) with artificial intelligence (AI) control can be cyclically performed to remove the high-k capping layer without substantially removing the second IL 240. Each cycle may include a first pulse of WCl5 followed by an Ar purge, followed by a second pulse of O2, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window for further multi-threshold voltage adjustment via metal gate patterning.

[0079] Further in Figure 15In some embodiments, after forming the second IL 240 and removing the high-k capping layer, a power function blocking layer 700 is optionally formed on the gate structure 200. The power function blocking layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a specific embodiment, the power function blocking layer 700 is TiN. The power function blocking layer 700 can have a thickness ranging from about 5 to about 20. Including the power function blocking layer 700 provides additional threshold voltage adjustment flexibility. Typically, the power function blocking layer 700 increases the threshold voltage for NFET transistor devices and decreases the threshold voltage (amplitude) for PFET transistor devices.

[0080] In some embodiments, a function metal layer 900, comprising at least one of an N-type function metal layer, an in-situ capping layer, or an oxygen barrier layer, is formed on the function barrier layer 700. The N-type function metal layer is or comprises an N-type metallic material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type function metal layer can be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and / or other suitable methods, and has a thickness between about 10 Å and 20 Å. An in-situ capping layer is formed on the N-type function metal layer. In some embodiments, the in-situ capping layer is or comprises TiN, TiSiN, TaN, or another suitable material, and has a thickness between about 10 Å and 20 Å. An oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen diffusion into the N-type function metal layer, which would cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that can prevent oxygen penetration into the N-type function metal layer and can protect the N-type function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using an ALD and has a thickness between about 10 Å and about 20 Å.

[0081] Figure 15A metal filler layer 290 is also shown. In some embodiments, an adhesive layer (not shown separately) is formed between the oxygen barrier layer of the function metal layer and the metal filler layer 290. The adhesive layer may promote and / or enhance the adhesion between the metal filler layer 290 and the function metal layer 900. In some embodiments, the adhesive layer may be formed from a metal nitride using an ALD, such as TiN, TaN, MoN, WN, or another suitable material. In some embodiments, the thickness of the adhesive layer is between about 10 Å and about 25 Å. The metal filler layer 290 may be formed on the adhesive layer and may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. In some embodiments, the metal filler layer 290 may be deposited using methods such as CVD, PVD, plating, and / or other suitable processes. In some embodiments, a seam 510, which may be an air gap, is formed vertically in the metal filler layer 290 between channels 22A, 22B. In some embodiments, the metal filler layer 290 is conformally deposited on the function metal layer 900. The joint 510 may be formed due to the merging of films deposited on the sidewalls during conformal deposition. In some embodiments, the joint 510 is not present between adjacent channels 22A, 22B.

[0082] exist Figures 9A to 9D In this configuration, after the gate structure 200 is formed, a first capping layer 204 and a second capping layer 295 are located above the gate dielectric layer 600 and the gate fill layer 290. The first capping layer 204 protects the gate structure 200. In some embodiments, the first capping layer 204 is or includes a dielectric material such as SiO2, SiN, SiCN, SiOCN, a high-k dielectric material (e.g., Al2O3), etc. The first capping layer 204 can prevent current leakage after one or more etching operations, which can be performed to form gate contacts, source / drain contacts 120, isolation structures (e.g., source / drain contact isolation structures), etc. In some embodiments, the first capping layer 204 is or includes a dielectric material harder than, for example, the second capping layer 295 (such as alumina) or other suitable dielectric materials.

[0083] The second capping layer 295, also known as a "self-aligned capping" (SAC) layer, provides protection for the underlying gate structure 200 and can also serve as a CMP stop layer when the source / drain contacts 120 are planarized after their formation. The second capping layer 295 can be a dielectric layer comprising a dielectric material such as SiO2, SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, or ZrAlO2. x HfAlO x HfSiO xAl2O3, BN, or other suitable dielectric materials. In some embodiments, the second capping layer 295 may be separated by a support structure over the longer gate structure and channel. In some embodiments, the width (X direction) of the second capping layer 295 is in the range of about 8 nm to about 40 nm.

[0084] exist Figures 9A to 9D In the process, the upper surface of the P-type source / drain region 82P is exposed by removing the portions of ILD130, the third spacer layer 85, and the second spacer layer 65R located above the P-type source / drain region 82P, corresponding to... Figure 16 Step 1600. In some embodiments, a patterned masking layer 98 is used to expose the source / drain region 82 while protecting other areas of the device 10. The N-type source / drain region 82N is protected by the second spacer layers 65, 65R during the formation of the contact opening 950 over the P-type source / drain region 82P. In some embodiments, forming the contact opening 950 includes one or more etching processes that remove the horizontal (XY plane) portions of the second spacer layer 65R and the third spacer layer 85 located above the P-type source / drain region 82P. During etching the third spacer layer 85, the sidewalls (vertical portions) of the third spacer layer 85 may be trimmed (e.g., thinned) over the P-type source / drain region 82P, as shown. The horizontal portion of the third spacer layer 85 may be completely removed over the N-type source / drain region 82N. Depending on how narrow the opening over the N-type source / drain region 82N is, the second spacer layers 65, 65R may be retained after the contact opening 950 is formed. Therefore, the N-type source / drain region 82N is protected by the second spacer layers 65 and 65R.

[0085] Figure 9C , Figure 9D The formation of the contact opening 950 according to an embodiment is shown, wherein the third spacer layer 85 is completely removed above the N-type source / drain region 82N. Figure 9C and Figure 9D ), and remove the horizontal portion of the second spacer layer 65R ( Figure 9D ).like Figure 9C As shown, the third spacer layer 85 can be completely removed above the N-type source / drain region 82N, while the second spacer layers 65 and 65R remain essentially intact after the contact opening 950 is formed. Therefore, the opening above the N-type source / drain region 82N can be wider than... Figure 9A The opening shown is such that the N-type source / drain region 82N remains protected by the second spacer layers 65, 65R in subsequent processes. Figure 9DIn this process, the horizontal portion of the second spacer layer 65R is removed, leaving the second spacer layer 65 substantially intact, thereby protecting the N-type source / drain region 82N by the second spacer layer 65. In some embodiments, the second spacer layer 65 is slightly thinned during the formation of the contact opening 950.

[0086] exist Figure 10A , Figure 10B In the P-type source / drain region 82P, dopant 103 is implanted, which may optionally be subsequently annealed. Dopant 103 may include implantation depths ranging from about 3 nm to about 10 nm and concentrations of about 10. 18 cm -3 To about 10 21 cm -3 P-type implants within the range, such as Ga, B, C, Sn, etc., are typically implanted globally, allowing the P-type implants to be implanted into the P-type source / drain region 82P, and also into the exposed regions of the second spacer layers 65, 65R, the second capping layer 295, and ILD 130. The implanted dopant 103 enhances the activation of the P-type source / drain region 82P. By using the spacer layers 65, 65R, 85 already positioned appropriately above the N-type source / drain region 82N, additional photolithography operations for implantation can be avoided, resulting in significant cost savings and reduced process complexity.

[0087] exist Figures 11A to 11C In the process, the first silicide layer 118P1 (or "P-function silicide") is formed in the P-type source / drain region 82P, corresponding to... Figure 17 Step 2100. In some embodiments, a P-type metal layer 115 is formed as a conformal thin layer over the exposed portion of the second P-type epitaxial region 82P1. The P-type metal layer 115 may be formed over the exposed portions of the spacer layers 65, 65R, 85, ILD130, the second capping layer 295, and the gate isolation structure 99. The P-type metal layer 115 may be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc.

[0088] After forming the P-type metal layer 115, the first silicide layer 118P1 can be formed by annealing the device 10 having the P-type metal layer 115 in contact with the second P-type epitaxial region 82P1. After annealing, the first silicide layer 118P1 can be or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The silicide of the first silicide layer 118P1 can diffuse in the region below the spacer layers 85, 65R, such as... Figure 11AAs shown in the diagram, the thickness of the first silicide layer 118P1 can range from about 1 nm to about 10 nm. Below about 1 nm, the contact resistance at the P-type source / drain region 82P may be too high. Above about 10 nm, the first silicide layer 118P1 may be short-circuited with the channel 22A.

[0089] refer to Figure 11C In some embodiments, the P+ implantation region of the P-type source / drain region 82P may not fully react with the P-type metal layer 115 to form the first silicide layer 118P1. Therefore, the P+ doped region 103R can remain below the first silicide layer 118P1, as shown in the figure.

[0090] exist Figure 12A , Figure 12B In the process, after forming the first silicide layer 118P1, the unreacted portion of the P-type metal layer 115 is removed, followed by the removal of the remaining portions of the spacer layers 65, 65R, and 85, exposing the N-type source / drain region 82N, corresponding to... Figure 17 Step 2200. Removing the spacer layers 65, 65R, 85 above the source / drain regions 82 prepares for subsequent silicide formation. By removing the spacer layers 65, 65R, 85, which are thicker above the N-type source / drain regions 82N than above the P-type source / drain regions 82P, the width of the silicide layers to be formed in the subsequent processing can be substantially the same. Removing unreacted portions of the P-type metal layer 115 and the spacer layers 65, 65R, 85 may include one or more selective etching operations on each of the layers to be removed. Figure 12B As shown, the portions of spacer layers 65, 65R, and 85 located below ILD 130 can be retained after the removal operation.

[0091] exist Figure 13A , Figure 13B In the process of removing the P-type metal layer 115 and spacer layers 65, 65R, 85, a third spacer layer 133 is formed on the sidewalls of the remaining portions of the cover layer 295, spacer layer 41, ILD 130, and spacer layers 65, 65R, 85, corresponding to... Figure 17 Step 2300. The third spacer layer 133 is bonded to and physically contacts the first silicide layer 118P1 and the N-type source / drain region 82N. The formation of the third spacer layer 133 can be similar in many respects to the reference. Figures 8A to 8DThe third spacer layer 85 is described. In some embodiments, the third spacer layer 133 is deposited as a conformal thin layer of a material, which may be or include SiN, SiCN, SiOCN, SiO, a high-k dielectric material, or other suitable materials. The third spacer layer 133 may be deposited with a thickness ranging from about 2 nm to about 6 nm. In some embodiments, the third spacer layer 133 is or includes a material different from the material of the second spacer layers 65, 65R. For example, the third spacer layer 133 may be a thin layer of SiCN, and one or more of the second spacer layers 65, 65R may be a thin layer of SiN. The horizontal portion of the third spacer layer 133 located above the source / drain region 82 is removed to expose the source / drain region 82. The third spacer layer 133 helps prevent short circuits between the gate structure 200 and the source / drain contact 120.

[0092] After forming the third spacer layer 133, an N-type metal layer 135 is formed over the source / drain region 82, the third spacer layer 133, the capping layer 295, and the ILD 130. In some embodiments, the N-type metal layer 135 is formed as a conformal thin layer and does not completely fill the opening above the source / drain region 82. The N-type metal layer 135 may be or include Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or another suitable material. After forming the N-type metal layer 135, a second silicide layer 118N is formed on the source / drain region 82 by an annealing operation, corresponding to... Figure 17Step 2400. In some embodiments, the second silicide layer 118N is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. The second silicide layer 118N may diffuse into the region below the third spacer layer 133. In some embodiments, the lower surface of the third spacer layer 133 is in complete contact with the second silicide layer 118N, for example, when the second silicide layer 118N diffuses in the X-axis direction to contact the inner spacer 74. In some embodiments, the lower surface of the third spacer layer 133 is in partial contact with the second silicide layer 118N and the second N-type epitaxial region 82N1, for example, when the second silicide layer 118N diffuses below the third spacer layer 133 but does not extend into the inner spacer 74. In some embodiments, the lower surface of the third spacer layer 133 does not contact the second silicide layer 118N, for example, when the second silicide layer 118N does not diffuse beneath the third spacer layer 133. The second silicide layer 118N may have a thickness in the range of about 1 nm to about 10 nm. Below about 1 nm, the thickness of the second silicide layer 118N may not sufficiently reduce the contact resistance. Above about 10 nm, the second silicide layer 118N may short-circuit with the channel 22A.

[0093] exist Figures 14A to 14C In the process, after forming the third spacer layer 133 and the second silicide layer 118N, the unreacted portion of the N-type metal layer 135 is removed, and the source / drain contact 120 is formed, corresponding to... Figure 17Step 2500. In some embodiments, the unreacted N-type metal layer 135 is removed by one or more etching operations that selectively apply material to the N-type metal layer 135 without significantly corroding the underlying structure. After the N-type metal layer 135 is removed, the source / drain contact 120 is formed by filling the opening above the source / drain region 82 with, for example, plug metal. In some embodiments, the source / drain contact 120 is formed by depositing a material that is or includes a conductive material such as Co, W, Ru, combinations thereof. In some embodiments, the source / drain contact 120 is or includes a compound or alloy based on Co, W, or Ru, which includes one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, etc. Source / drain contacts 120 are bonded to the second silicide layer 118N and contact the third spacer layer 133 and the hybrid fin 94. A description of device 10 and its illustration in numerous figures are given with reference to a GAA FET comprising a vertically stacked assembly including nanostructures 22. In some embodiments, the first silicide layer 118P1 and the second silicide layer 118N are formed in the source / drain region 82 of the FinFET device, which in Figure 14C As shown in the image.

[0094] Additional processing can be performed to complete the fabrication of the nanostructure device 20. For example, gate contacts can be formed to electrically couple to the gate structure 200. Interconnect structures can then be formed over the source / drain contacts 120 and the gate contacts. The interconnect structures may include multiple dielectric layers surrounding a metal component, including conductive traces and conductive vias, which form electrical connections between devices (such as the nanostructure device 20) on the substrate 110 and electrical connections to IC devices outside the IC device 10. In some embodiments, a second capping layer (not shown) is present over the source / drain contacts 120. A configuration in which only the capping layer 295 is present over the gate structure 200 (e.g., no second capping layer is present over the source / drain contacts 120) can be considered a “single SAC” structure, and a configuration in which both capping layer 295 and a second capping layer are present can be considered a “dual SAC” structure.

[0095] The implementation offers advantages. By using a FEOL dielectric hard mask (HM) on the N-epitaxial region and maintaining the HM through P+ implantation and P-function silicide processes, a self-aligned dual-silicide process combined with high-P epitaxial region activation can be achieved without additional P+ photomask costs. Specifically, by using front-end process (FEOL) spacer layers (e.g., spacer layers 65, 65R, 85) on the N-type epitaxial structure 82N during P+ implantation and P-function silicide processes, P+ implantation into the NMOS region can be prevented. Therefore, a self-aligned dual-silicide process combined with high-P-type epitaxial activation can be achieved without additional photolithography costs. The use of dual silicides for better contact resistance combined with self-aligned P+ implantation improves speed performance and reduces costs.

[0096] According to at least one embodiment, the device includes a substrate, a gate structure, source / drain regions, a first silicide layer, a second silicide layer, and contacts. The gate structure encloses at least one vertically stacked nanostructure channel. The source / drain regions are adjacent to the gate structure. The first silicide layer includes a first metal component located on the source / drain regions. The second silicide layer includes a second metal component different from the first metal component and is located on the first silicide layer. The contacts are located on the second silicide layer.

[0097] According to at least one embodiment, the device includes a substrate and a vertically stacked nanostructure above the substrate. An N-type source / drain region is adjacent to a first end of the nanostructure. A P-type source / drain region is adjacent to a second end of the nanostructure. A P-type silicide layer is located on the P-type source / drain region. An N-type silicide layer is located on both the N-type and P-type source / drain regions. Contacts are located on the N-type silicide layer.

[0098] According to at least one embodiment, the method includes: forming a first source / drain region and a second source / drain region on and in a substrate, the first source / drain region being laterally separated from the second source / drain region; forming a first silicide layer on the second source / drain region while masking the first source / drain region; forming a second silicide layer on the first source / drain region and the second source / drain region; and forming a contact on the second silicide layer above the first source / drain region and the second source / drain region.

[0099] Some embodiments of this application provide a semiconductor device, including: a substrate; a gate structure enclosing at least one nanostructured channel vertical stack; a source / drain region adjacent to the gate structure; a first silicide layer including a first metal component located on the source / drain region; a second silicide layer including a second metal component different from the first metal component, the second silicide layer being located on the first silicide layer; and a contact element located on the second silicide layer. In some embodiments, the first silicide layer includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, or OsSi. In some embodiments, the second silicide layer includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, or YbSi. In some embodiments, the first silicide layer is thicker than the second silicide layer. In some embodiments, the source / drain region includes a doped region, the doped region including implants in contact with the first silicide layer. In some embodiments, the implants include implants with a depth ranging from about 3 nanometers to about 10 nanometers and a concentration of about 10. 18 cm -3 To about 10 21 cm -3 The semiconductor device comprises Ga, B, C, or Sn within the range of [missing information]. In some embodiments, the semiconductor device includes: a hybrid fin adjacent to the source / drain region. In some embodiments, the semiconductor device includes: a second source / drain region adjacent to the gate structure; a third silicide layer contacting the second source / drain region; and a second contact contacting the third silicide layer. In some embodiments, the third silicide layer has the same material as the second silicide layer. In some embodiments, the semiconductor device includes: a first spacer layer along the sidewall of the contact, the first spacer layer being bonded to the second silicide layer; and a second spacer layer located between the first spacer layer and the gate structure.

[0100] Other embodiments of this application provide a semiconductor device comprising: a substrate; a vertically stacked nanostructure located above the substrate; an N-type source / drain region adjacent to a first end of the nanostructure; a P-type source / drain region adjacent to a second end of the nanostructure; a P-type silicide layer located on the P-type source / drain region; an N-type silicide layer located on the N-type source / drain region and the P-type source / drain region; and a contact located on the N-type silicide layer. In some embodiments, the ratio of the thickness of the P-type silicide layer to the thickness of the N-type silicide layer above the P-type source / drain region is in the range of about 3:1 to about 5:1. In some embodiments, the thickness of the N-type silicide layer on the N-type source / drain region is substantially the same as the combined thickness of the N-type silicide layer and the P-type silicide layer on the P-type source / drain region. In some embodiments, the semiconductor device includes a spacer layer located on the sidewall of the contact, wherein the N-type silicide layer and the P-type silicide layer extend beneath the spacer layer. In some embodiments, the N-type source / drain region includes SiP, SiAs, SiSb, SiPAs, or SiP:As:Sb; and the P-type source / drain region includes SiGe:B, SiGe:B:Ga, SiGe:Sn, or SiGe:B:Sn.

[0101] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first source / drain region and a second source / drain region on and in a substrate, the first source / drain region being laterally separated from the second source / drain region; forming a first silicide layer on the second source / drain region while masking the first source / drain region; forming a second silicide layer on the first source / drain region and the second source / drain region; and forming a contact on the second silicide layer above the first source / drain region and the second source / drain region. In some embodiments, the method includes: forming a first dielectric hard mask on the first source / drain region before forming the second source / drain region; wherein, during the formation of the first silicide layer, the first source / drain region is masked by the first dielectric hard mask. In some embodiments, the method includes: forming a second dielectric hard mask on the dielectric hard mask and the second source / drain region; and exposing the second source / drain region by removing a horizontal portion of the second dielectric hard mask located above the second source / drain region before forming a first silicide layer. In some embodiments, the method includes: removing the first dielectric hard mask and the second dielectric hard mask before forming a second silicide layer; and forming a third dielectric hard mask before forming a second silicide layer. In some embodiments, the method further includes: performing P+ implantation on the second source / drain region while the first source / drain region is masked by the first dielectric hard mask; wherein the first source / drain region is an N-type epitaxial region, and forming the first silicide layer includes forming a P-type work function silicide layer.

[0102] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: Substrate; A gate structure encapsulating at least one nanostructured channel vertically stacked component; The source / drain region is adjacent to the gate structure; The first silicide layer includes a first metal component that directly and physically contacts the source / drain regions; The second silicide layer includes a second metal component that is different from the first metal component, and the second silicide layer is in direct physical contact with the first silicide layer. The contact element directly and physically contacts the second silicide layer; The second source / drain region is adjacent to the gate structure; The third silicide layer is in direct physical contact with the second source / drain region, and the third silicide layer has the same material as the second silicide layer; as well as The second contact contacts the third silicide layer.

2. The semiconductor device according to claim 1, wherein, The first silicide layer includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, or OsSi.

3. The device according to claim 1, wherein, The second silicide layer includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, or YbSi.

4. The semiconductor device according to claim 1, wherein, The first silicide layer is thicker than the second silicide layer.

5. The semiconductor device according to claim 1, wherein, The source / drain region includes a doped region, which includes implants that are in contact with the first silicide layer.

6. The semiconductor device according to claim 5, wherein, The injected material comprises substances with a depth ranging from about 3 nanometers to about 10 nanometers and a concentration of about 10. 18 cm -3 To about 10 21 cm -3 The range of Ga, B, C or Sn, wherein the approximation is within ±30% of the described value.

7. The semiconductor device according to claim 1, comprising: The hybrid fin is adjacent to the source / drain region.

8. The semiconductor device of claim 1, wherein the first silicide layer has a thickness in the range of 1 nm to 10 nm.

9. The semiconductor device according to claim 1, wherein, The second silicide layer has a thickness in the range of 1 nm to 10 nm.

10. The semiconductor device of claim 1, comprising: A first spacer layer is bonded to the second silicide layer along the sidewall of the contact element; as well as The second spacer layer is located between the first spacer layer and the gate structure.

11. A semiconductor device, comprising: Substrate; A vertically stacked nanostructure is located above the substrate; The N-type source / drain region is adjacent to the first end of the nanostructure; The P-type source / drain region is adjacent to the second end of the nanostructure; The P-type silicide layer directly and physically contacts the P-type source / drain region; The N-type silicide layer directly and physically contacts the N-type source / drain region, and also directly and physically contacts the P-type silicide layer on the P-type source / drain region; as well as The contact element directly and physically contacts the N-type silicide layer.

12. The semiconductor device according to claim 11, wherein, The ratio of the thickness of the P-type silicide layer to the thickness of the N-type silicide layer above the P-type source / drain region is in the range of about 3:1 to about 5:1, wherein "about" means within ±30% of the described value.

13. The semiconductor device according to claim 11, wherein, The thickness of the N-type silicide layer on the N-type source / drain region is substantially the same as the combined thickness of the N-type silicide layer and the P-type silicide layer on the P-type source / drain region.

14. The semiconductor device of claim 11, comprising: A spacer layer is located on the sidewall of the contact, wherein the N-type silicide layer and the P-type silicide layer extend beneath the spacer layer.

15. The semiconductor device according to claim 11, wherein: The N-type source / drain region includes SiP, SiAs, SiSb, SiPAs, or SiP:As:Sb; and The P-type source / drain region includes SiGe:B, SiGe:B:Ga, SiGe:Sn, or SiGe:B:Sn.

16. A method of forming a semiconductor device, comprising: A first source / drain region and a second source / drain region are formed on and in the substrate, the first source / drain region and the second source / drain region being laterally separated; A first silicide layer is formed on the second source / drain region, while simultaneously masking the first source / drain region; A second silicide layer is formed on the first silicide layer, and a third silicide layer is formed on the first source / drain region; as well as Contacts are formed on the second silicide layer above the first source / drain region and the second source / drain region. The first silicide layer includes a first metal component that directly and physically contacts the second source / drain region; The second silicide layer includes a second metal component that is different from the first metal component, and the second silicide layer is in direct physical contact with the first silicide layer; as well as The third silicide layer is in direct physical contact with the first source / drain region, and the third silicide layer has the same material as the second silicide layer.

17. The method of claim 16, comprising: Before forming the second source / drain region, a first dielectric hard mask is formed on the first source / drain region; During the formation of the first silicide layer, the first source / drain region is masked by the first dielectric hard mask.

18. The method of claim 17, comprising: A second dielectric hard mask is formed on the first dielectric hard mask and the second source / drain region; as well as Before forming the first silicide layer, the second source / drain region is exposed by removing the horizontal portion of the second dielectric hard mask located above the second source / drain region.

19. The method of claim 18, comprising: Before forming the second silicide layer, the first dielectric hard mask and the second dielectric hard mask are removed; as well as A third dielectric hard mask is formed before the second silicide layer is formed.

20. The method of claim 17, further comprising: P+ injection is performed on the second source / drain region, while the first source / drain region is masked by the first dielectric hard mask; Wherein, the first source / drain region is an N-type epitaxial region, and the formation of the first silicide layer includes the formation of a P-type work function silicide layer.

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