A neural synapse device with global gate and local gate synergistic regulation and a preparation method thereof

Abstract

The application discloses a neural synapse device with global gate and local gate synergic regulation and a preparation method thereof. The neural synapse device with global gate and local gate synergic regulation comprises a substrate, a back gate electrode formed on the substrate and covering the whole substrate as a global gate, a back gate dielectric layer formed on the back gate electrode, a channel layer which is a two-dimensional semiconductor material and is formed on the back gate dielectric layer, source and drain electrodes formed on both sides of the channel layer, a top gate dielectric layer covering the above structure, and a top gate electrode formed on the top gate dielectric layer and covering part of the channel region as a local gate. By respectively applying a forward voltage to only the local gate, applying a forward voltage to only the global gate or applying a forward voltage to both the local gate and the global gate, the device realizes neural synapse plasticity with different weights, obtains specific modulation function and realizes transmission of multi-dimensional complex information.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a neural synapse device with global gate and local gate synergistic regulation and a preparation method thereof. BACKGROUND

[0002] Traditional computers are all based on von Neumann computing architecture, which can cope with most computing tasks, but still cannot meet the computing needs of large data. Supercomputers and other devices are proposed to solve the problem of large data computing, but the problems of large floor area, high cost, strong operation professionalism, and huge power consumption limit their promotion and application. Therefore, it is necessary to find another more efficient computing device to realize the computing task of large data. Neuromorphic computing as a new computing mode can fundamentally solve the problem of separation of storage and computing unit in traditional computers, avoid the problem of dramatic increase in cost caused by frequent data transmission and high-density integration, and has great development potential.

[0003] Neural synapse devices as the basic functional unit of neuromorphic computing can simulate the signal transmission from the front end to the back end of the biological synapse and play a key role in weight alternation calculation. However, traditional neural synapse devices are only composed of a synapse front end and a synapse back end, which cannot meet the needs of neuromorphic computing with different weight modulation and the processing of complex information, and new multi-terminal synapse devices with different modulation capabilities need to be developed.

[0004] Molybdenum sulfide and other two-dimensional materials are a new type of semiconductor material, which not only has excellent mobility, sub-threshold swing, high on-off ratio and other characteristics, but also has atomic thickness, and can work at the size of a single atom, making it possible to shrink the size of the transistor along the Moore's law route. Using two-dimensional materials to prepare new neural synapse devices has important significance in flexible gate regulation, especially the combination of global gate and local gate, which can greatly improve the specific regulation of synapse weight, and has the advantages of simple structure, easy control, and low power consumption. SUMMARY

[0005] The application discloses a neural synapse device with global gate and local gate synergic regulation, which comprises a substrate, a back gate electrode formed on the substrate and covering the whole substrate as a global gate, a back gate dielectric layer formed on the back gate electrode, a channel layer which is a two-dimensional semiconductor material and is formed on the back gate dielectric layer, source and drain electrodes formed on both sides of the channel layer, a top gate dielectric layer covering the above structure, and a top gate electrode formed on the top gate dielectric layer and covering part of the channel area as a local gate.

[0006] In the neural synapse device with global gate and local gate synergic regulation, the back gate dielectric layer or the top gate dielectric layer is preferably HfO2, ZrO2 or TiO2.

[0007] In the neural synapse device with global gate and local gate synergic regulation, the length of the global gate is preferably 2-10 mu m, and the width is preferably 1-9 mu m.

[0008] In the neural synapse device with global gate and local gate synergic regulation, the two-dimensional semiconductor material is preferably MoS2, WS2, ReS2 or HfS2.

[0009] In the neural synapse device with global gate and local gate synergic regulation, the thickness of the two-dimensional semiconductor material is preferably 1-10 nm.

[0010] The application further discloses a preparation method of the neural synapse device with global gate and local gate synergic regulation, which comprises the following steps: forming a back gate electrode on a substrate and making the back gate electrode cover the whole substrate as a global gate; forming a back gate dielectric layer on the back gate electrode; forming a two-dimensional semiconductor material on the back gate dielectric layer as a channel layer; forming source and drain electrodes on both sides of the channel layer; covering a top gate dielectric layer on the above structure; forming a top gate electrode on the top gate dielectric layer and making the top gate electrode cover part of the channel area as a local gate; and applying a forward voltage to the local gate, the global gate or both the local gate and the global gate respectively, so that the device realizes neural synapse plasticity with different weights, obtains specific modulation function and realizes transmission of multi-dimensional complex information.

[0011] In the preparation method of the neural synapse device with global gate and local gate synergic regulation, the back gate dielectric layer or the top gate dielectric layer is preferably HfO2, ZrO2 or TiO2.

[0012] In the neural synapse device preparation method with the global gate and the local gate synergistically regulated according to the application, preferably, the length of the global gate is 2-10 mu m; and the width is 1-9 mu m.

[0013] In the neural synapse device preparation method with the global gate and the local gate synergistically regulated according to the application, preferably, the two-dimensional semiconductor material is MoS2, WS2, ReS2 or HfS2.

[0014] In the neural synapse device preparation method with the global gate and the local gate synergistically regulated according to the application, preferably, the thickness of the two-dimensional semiconductor material is 1-10 nm.

[0015] Beneficial effects:

[0016] (1) Breaking the traditional computer working mode, solving the computing bottleneck problem existing in the Von Neumann computing architecture, providing a high-efficiency brain-like computing electronic device, simulating the biological neural synapse function mode, and realizing high-efficiency neural network computing.

[0017] (2) Using two-dimensional semiconductor material as the channel, solving the problems of short channel, leakage current and electron scattering caused by size micro-etching of traditional silicon-based semiconductor material, and ensuring that the device size can continue to advance to sub-nanometer size according to Moore's law.

[0018] (3) By designing the structure of the global gate and the local gate, the synergistic neural synapse characteristics with global regulation function and local regulation function are realized, which has important significance for realizing multi-dimensional neural network computing with specific neural morphological regulation requirements. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a flow chart of the neural synapse device preparation method with the global gate and the local gate synergistically regulated.

[0020] Figures 2 to 7 It is a structure schematic diagram of each stage of the neural synapse device preparation method with the global gate and the local gate synergistically regulated.

[0021] As Figures 8A to 8C It is a running schematic diagram of the neural synapse device with the global gate and the local gate synergistically regulated. DETAILED DESCRIPTION

[0022] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application. The described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0023] In the description of the present application, it should be noted that the terms "upper", "lower", "vertical", "horizontal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0024] In addition, many specific details of the present application are described below, such as the structure, material, size, processing and technology of the device, in order to make the present application more clearly understood. However, as those skilled in the art can understand, the present application can be implemented without these specific details. Unless specifically indicated below, each part in the device can be composed of materials known to those skilled in the art, or materials with similar functions developed in the future can be used.

[0025] Figure 1 is a flow chart of a preparation method of a neural synapse device cooperatively regulated by a global gate and a local gate. As shown in Figure 1 , the preparation method of the neural synapse device cooperatively regulated by the global gate and the local gate comprises the following steps:

[0026] Step S1, a silicon wafer is prepared as a substrate 100 for preparing a neural synapse device cooperatively regulated by a global gate and a local gate. The substrate can also be glass, SiC, etc.

[0027] Step S2, a back gate electrode 101 is formed on the substrate 100 by physical vapor deposition, the back gate electrode 101 covers the entire substrate 100, serving as a global gate of the device, as shown in Figure 2 . The material of the global gate is preferably Pt, and can also be Au, Al, Pd, etc. The thickness is preferably 70 nm, and can range from 50 nm to 150 nm.

[0028] Step S3, a back gate dielectric layer HfO2 102 with a thickness of 10 nm to 30 nm is prepared on the back gate electrode 101 by atomic layer deposition technology, as shown in Figure 3As shown. The atomic layer deposition temperature is 200℃~260℃. The material of the back gate dielectric layer can also be an oxide insulating layer such as ZrO2 or TiO2.

[0029] Step S4: A 1nm-10nm thick MoS2 two-dimensional semiconductor material is fabricated on the back gate dielectric layer 102 using a mechanical lift-off method as the channel layer 103. Figure 4 As shown. The channel layer material can also be two-dimensional semiconductor materials such as WS2, ReS2, and HfS2. The length of the two-dimensional semiconductor material is preferably 10 μm, and can range from 5 μm to 30 μm; the width is preferably 5 μm, and can range from 2 μm to 20 μm.

[0030] Step S5: Using physical vapor deposition, an Au layer of 50 nm to 150 nm thickness is grown on both sides of the channel layer 103 as the source electrode 104 and the drain electrode 105, as shown below. Figure 5 As shown. The source and drain electrodes can also be made of metallic materials such as Pt, Al, and Pd.

[0031] Step S6: Using atomic layer deposition (ALD) technology, a top gate dielectric layer HfO2¹O6 with a thickness of 10 nm to 30 nm is prepared on the above structure, such as... Figure 6 As shown. The preferred temperature for atomic layer deposition is 200℃~260℃. The material of the top gate dielectric layer can also be an oxide insulating layer such as ZrO2 or TiO2.

[0032] Step S7: A top-gate electrode Pt107 with a thickness of 50 nm to 150 nm is grown on the top-gate dielectric layer 106 using physical vapor deposition. The top-gate electrode only covers a portion of the channel as a local gate, such as... Figure 7 As shown. The length of the top gate electrode is preferably 5 μm, and can range from 2 μm to 10 μm; the width is preferably 2 μm, and can range from 1 μm to 9 μm. The material of the top gate electrode can also be metallic materials such as Au, Al, and Pd.

[0033] like Figure 7 As shown, the neural synaptic device that coordinates the global gate and the local gate includes: a substrate 100; a back gate electrode 101 formed on the substrate 100, covering the entire substrate, serving as a global gate; a back gate dielectric layer 102 formed on the back gate electrode 101; a channel layer 103, which is a two-dimensional semiconductor material, formed on the back gate dielectric layer 102; a source electrode 104 and a drain electrode 105 formed on both sides of the channel layer 103; a top gate dielectric layer 106 covering the above structure; and a top gate electrode 107 formed on the top gate dielectric layer 106, covering part of the channel region, serving as a local gate.

[0034] like Figures 8A to 8CAs shown by applying positive voltage to the local gate 107 at the top and the global gate 101 at the bottom respectively, the device realizes unequal weight neural synapse plasticity, obtains specific modulation function, and realizes transmission of multi-dimensional complex information. Figure 8A As shown in FIG. 1C, a schematic diagram of applying positive voltage to the local gate at the top only is shown. Figure 8B As shown in FIG. 1D, a schematic diagram of applying positive voltage to the global gate at the bottom only is shown. Figure 8C As shown in FIG. 1E, a schematic diagram of applying positive voltage to the local gate at the top and the global gate at the bottom is shown.

[0035] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical range disclosed by the present application can be easily thought by those skilled in the art, and should be covered within the protection scope of the present application.

Claims

1. A neural synaptic device that coordinates global and local gate modulation, characterized in that, include: Substrate; A back gate electrode is formed on the substrate, covering the entire substrate, and serves as a global gate. A back gate dielectric layer is formed on the back gate electrode; A channel layer, which is a two-dimensional semiconductor material, is formed on the back gate dielectric layer; Source and drain electrodes are formed on both sides of the channel layer; A top gate dielectric layer covers the channel layer, the source electrode, and the drain electrode; The top gate electrode is formed on the top gate dielectric layer, covering a portion of the channel region, and serves as a local gate. By applying a positive voltage only to the local gate, only to the global gate, or both the local and global gates, the device achieves unequal weighted synaptic plasticity, obtains specific modulation functions, and enables the transmission of multidimensional complex information.

2. The neural synaptic device with coordinated global and local gate modulation according to claim 1, characterized in that, The back gate dielectric layer or the top gate dielectric layer is any one or a combination of HfO2, ZrO2, and TiO2.

3. The neural synaptic device with coordinated global and local gate modulation according to claim 1, characterized in that, The length of the local gate is 2μm to 10μm; the width is 1μm to 9μm.

4. The neural synaptic device with coordinated global and local gate modulation according to claim 1, characterized in that, The two-dimensional semiconductor material is any one or a combination of MoS2, WS2, ReS2, and HfS2.

5. The neural synaptic device with coordinated global and local gate modulation according to claim 1, characterized in that, The thickness of the two-dimensional semiconductor material is 1 nm to 10 nm.

6. A method for fabricating a neural synaptic device with coordinated control of global and local gates, characterized in that, Includes the following steps: A back gate electrode is formed on the substrate, covering the entire substrate, to serve as a global gate. A back gate dielectric layer is formed on the back gate electrode; A two-dimensional semiconductor material is formed on the back gate dielectric layer as a channel layer; Source and drain electrodes are formed on both sides of the channel layer; A top gate dielectric layer is covered on the channel layer, the source electrode, and the drain electrode; A top gate electrode is formed on the top gate dielectric layer, covering a portion of the channel region to serve as a local gate. By applying a positive voltage only to the local gate, only to the global gate, or both the local and global gates, the device achieves unequal weighted synaptic plasticity, obtains specific modulation functions, and enables the transmission of multidimensional complex information.

7. The method for fabricating a neural synaptic device with coordinated global and local gate control according to claim 6, characterized in that, The back gate dielectric layer or the top gate dielectric layer is any one or a combination of HfO2, ZrO2, and TiO2.

8. The method for fabricating a neural synaptic device with coordinated global and local gate control according to claim 6, characterized in that, The length of the local gate is 2μm to 10μm; the width is 1μm to 9μm.

9. The method for fabricating a neural synaptic device with coordinated global and local gate control according to claim 6, characterized in that, The two-dimensional semiconductor material is any one or a combination of MoS2, WS2, ReS2, and HfS2.

10. The method for fabricating a neural synaptic device with coordinated global and local gate control according to claim 6, characterized in that, The thickness of the two-dimensional semiconductor material is 1 nm to 10 nm.

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