A dual binary four-level pulse amplitude modulation signal processing method and system

Abstract

The present application provides a PAM4-DB signal processing method and system, which obtain a PAM4-DB signal, wherein the PAM4-DB signal is obtained by encoding a PAM4 signal, and the code element correlation of the PAM4 signal is eliminated during the encoding process; the PAM4-DB signal is shunted to multiple comparison circuits, and the PAM4-DB signal is processed by each comparison circuit respectively to obtain a first logic level signal; an exclusive OR circuit is used to perform exclusive OR processing on some first logic level signals in all first logic level signals, and an inversion circuit is used to perform level inversion processing on the first logic level signal after the exclusive OR processing and the first logic level signal that is not subjected to the exclusive OR processing to obtain a second logic level signal; an addition circuit is used to add all the second logic level signals to obtain a PAM4 signal, so as to realize decoding of the PAM4-DB signal by a simple circuit and simplify the decoding process.

Description

Technical Field

[0001] The present application belongs to the technical field of high-speed serial communication, and in particular, relates to a dual binary four-level pulse amplitude modulation signal processing method and system. Background Art

[0002] With the continuous development of human civilization and science and technology, people's living standards are improving day by day, and the demand for high-speed communication is becoming more and more urgent. Point-to-point serial communication technology has emerged. Point-to-point serial communication technology converts multiple low-speed parallel signals at the sending end into high-speed serial signals, and then converts them back into low-speed parallel signals at the receiving end after being transmitted through transmission media such as optical cables or copper wires. This point-to-point serial communication makes full use of the channel capacity of the transmission medium, reduces the number of channels and chip pins while increasing the signal transmission speed, thereby significantly reducing communication costs and complexity.

[0003] Higher transmission speeds also mean more challenges. PAM4 (fourth-order pulse amplitude modulation) signal modulation is gradually being replaced by PAM4-duobinary (duobinary-fourth-level pulse amplitude modulation, referred to as PAM4-DB) signal modulation. After obtaining the PAM4-DB signal through the PAM4-DB signal adjustment method, how to simplify the decoding process is an urgent problem to be solved. Summary of the invention

[0004] The present application provides a dual binary four-level pulse amplitude modulation signal processing method and system.

[0005] On the one hand, the present application provides a dual binary four-level pulse amplitude modulation signal processing method, characterized in that the method includes:

[0006] Obtaining a duobinary four-level pulse amplitude modulation signal, wherein the duobinary four-level pulse amplitude modulation signal is obtained by encoding a four-level pulse amplitude modulation signal, and the symbol correlation of the four-level pulse amplitude modulation signal is eliminated during the encoding process of the four-level pulse amplitude modulation signal;

[0007] Dividing the duobinary four-level pulse amplitude modulation signal to a plurality of comparison circuits, wherein the duobinary four-level pulse amplitude modulation signal is processed by each comparison circuit respectively to obtain a first logic level signal, wherein the number of the first logic level signals is the same as the number of the comparison circuits;

[0008] Using an XOR circuit to perform XOR processing on some of the first logic level signals in all the first logic level signals, and using an inversion circuit to perform level inversion processing on the first logic level signals after the XOR processing and the first logic level signals not subjected to the XOR processing, to obtain second logic level signals;

[0009] All second logic level signals are added by using an adding circuit to obtain the four-level pulse amplitude modulation signal.

[0010] Optionally, encoding the four-level pulse amplitude modulation signal to obtain a dual binary four-level pulse amplitude modulation signal comprises:

[0011] Precoding the four-level pulse amplitude modulation signal to eliminate symbol correlation of the four-level pulse amplitude modulation signal;

[0012] The precoded four-level pulse amplitude modulation signal is subjected to duo-binary modulation to obtain the duo-binary four-level pulse amplitude modulation signal.

[0013] Optionally, the precoding the four-level pulse amplitude modulation signal includes:

[0014] With b k =(a k +b k-1 )mod4 pre-codes the four-level pulse amplitude modulation signal, a k is the four-level pulse amplitude modulation signal, a k The level values ​​include 0, 1, 2 and 3, b k is the output of the current precoding of the four-level pulse amplitude modulation signal, b k-1 is the output of the last precoding of the four-level pulse amplitude modulation signal;

[0015] The performing duo-binary modulation on the precoded four-level pulse amplitude modulation signal to obtain the duo-binary four-level pulse amplitude modulation signal comprises:

[0016] Using c k =b k +b k-1 The precoded four-level pulse amplitude modulation signal is subjected to dual binary modulation, c k is the dual binary four-level pulse amplitude modulation signal, c k The level values ​​include 0, 1, 2, 3, 4, 5 and 6.

[0017] Optionally, the step of shunting the duobinary four-level pulse amplitude modulation signal to a plurality of comparison circuits, wherein the duobinary four-level pulse amplitude modulation signal is processed by each comparison circuit respectively to obtain a first logic level signal comprises:

[0018] The dual binary four-level pulse amplitude modulation signal is split into eight signals by a broadband splitter, wherein the first signal to the eighth signal are sequentially input into the first comparison circuit to the eighth comparison circuit;

[0019] The level of the input signal is compared with the threshold level by using the first comparison circuit to the eighth comparison circuit to obtain the first logic level signal of each comparison circuit.

[0020] Optionally, the first comparison circuit corresponds to a first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level;

[0021] The levels of the duobinary four-level pulse amplitude modulation signal include a first level to a seventh level;

[0022] The relationship between the first level to the seventh level and the first threshold level to the sixth threshold level is: the first level is less than the first threshold level, the first threshold level is less than the second level, the second level is less than the second threshold level, the second threshold level is less than the third level, the third level is less than the third threshold level, the third threshold level is less than the fourth level, the fourth level is less than the fourth threshold level, the fourth threshold level is less than the fifth level, the fifth level is less than the fifth threshold level, the fifth threshold level is less than the sixth level, the sixth level is less than the sixth threshold level, and the sixth threshold level is less than the seventh level.

[0023] Optionally, the using of an XOR circuit to perform XOR processing on some of the first logic level signals in all the first logic level signals, and using an inversion circuit to perform level inversion processing on the first logic level signals after the XOR processing and the first logic level signals not subjected to the XOR processing, to obtain the second logic level signal comprises:

[0024] Using an XOR gate to perform XOR processing on the first logic level signals output by the first comparison circuit and the second comparison circuit;

[0025] Using an XOR gate to perform XOR processing on the first logic level signals output by the third comparison circuit and the fourth comparison circuit;

[0026] Using an XOR gate to perform XOR processing on the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit;

[0027] An inverter is used to perform level inversion processing on the first logic level signal after the XOR processing and the first logic level signal without the XOR processing to obtain a second logic level signal.

[0028] On the other hand, the present application provides a dual binary four-level pulse amplitude modulation signal processing system, the system comprising: a signal acquisition circuit, a shunt circuit, a plurality of comparison circuits, an XOR circuit, an inversion circuit and an addition circuit;

[0029] The signal acquisition circuit is used to obtain a duobinary four-level pulse amplitude modulation signal, wherein the duobinary four-level pulse amplitude modulation signal is obtained by encoding a four-level pulse amplitude modulation signal, and the code element correlation of the four-level pulse amplitude modulation signal is eliminated during the encoding process of the four-level pulse amplitude modulation signal;

[0030] The shunt circuit is used to shunt the duobinary four-level pulse amplitude modulation signal to the plurality of comparison circuits, the duobinary four-level pulse amplitude modulation signal is processed by each comparison circuit respectively to obtain a first logic level signal, and the number of the first logic level signals is the same as the number of the comparison circuits;

[0031] The XOR circuit is used to perform XOR processing on some of the first logic level signals among all the first logic level signals respectively;

[0032] The inversion circuit is used to perform level inversion processing on the first logic level signal after the XOR processing and the first logic level signal without the XOR processing to obtain a second logic level signal;

[0033] The adding circuit is used to perform addition processing on all second logic level signals to obtain the four-level pulse amplitude modulation signal.

[0034] Optionally, the system further comprises: an encoding circuit, configured to encode the four-level pulse amplitude modulation signal to obtain a dual binary four-level pulse amplitude modulation signal;

[0035] The encoding circuit encodes the duobinary four-level pulse amplitude modulation signal, which includes: pre-encoding the four-level pulse amplitude modulation signal to eliminate the code element correlation of the four-level pulse amplitude modulation signal; and performing duobinary modulation on the pre-coded four-level pulse amplitude modulation signal to obtain the duobinary four-level pulse amplitude modulation signal.

[0036] Optionally, the shunting circuit is a broadband shunter, which shuns the dual binary four-level pulse amplitude modulation signal into eight signals, and the first signal to the eighth signal are sequentially input into the first comparison circuit to the eighth comparison circuit; the first comparison circuit to the eighth comparison circuit compares the level of the input signal with the threshold level to obtain the first logic level signal of each comparison circuit;

[0037] wherein the first comparison circuit corresponds to a first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level;

[0038] The levels of the duobinary four-level pulse amplitude modulation signal include a first level to a seventh level;

[0039] The relationship between the first level to the seventh level and the first threshold level to the sixth threshold level is: the first level is less than the first threshold level, the first threshold level is less than the second level, the second level is less than the second threshold level, the second threshold level is less than the third level, the third level is less than the third threshold level, the third threshold level is less than the fourth level, the fourth level is less than the fourth threshold level, the fourth threshold level is less than the fifth level, the fifth level is less than the fifth threshold level, the fifth threshold level is less than the sixth level, the sixth level is less than the sixth threshold level, and the sixth threshold level is less than the seventh level.

[0040] Optionally, the XOR circuit is an XOR gate, and the inverting circuit is an inverter;

[0041] The XOR gate is used to perform XOR processing on the first logic level signals output by the first comparison circuit and the second comparison circuit; perform XOR processing on the first logic level signals output by the third comparison circuit and the fourth comparison circuit; and perform XOR processing on the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit;

[0042] The inverter is used to perform level inversion processing on the first logic level signal after the XOR processing and the first logic level signal without the XOR processing to obtain a second logic level signal.

[0043] On the other hand, the present application provides a storage medium, in which a computer program code is stored. When the computer program code is executed, the above-mentioned dual binary four-level pulse amplitude modulation signal processing method is implemented.

[0044] The above-mentioned dual binary four-level pulse amplitude modulation signal processing method and system obtain a dual binary four-level pulse amplitude modulation signal, which is obtained by encoding the four-level pulse amplitude modulation signal, and the code element correlation of the four-level pulse amplitude modulation signal is eliminated in the encoding process of the four-level pulse amplitude modulation signal; the dual binary four-level pulse amplitude modulation signal is shunted to a plurality of comparison circuits, and the dual binary four-level pulse amplitude modulation signal is processed by each comparison circuit respectively to obtain a first logic level signal, and the number of the first logic level signals is the same as the number of the comparison circuits; the exclusive OR circuit is used to perform exclusive OR processing on some of the first logic level signals in all the first logic level signals, and the inversion circuit is used to perform level inversion processing on the first logic level signal after the exclusive OR processing and the first logic level signal that has not been subjected to the exclusive OR processing to obtain a second logic level signal; the addition circuit is used to perform addition processing on all the second logic level signals to obtain a four-level pulse amplitude modulation signal, and the dual binary four-level pulse amplitude modulation signal is decoded by using simple circuits such as the comparison circuit, the exclusive OR circuit, the inversion circuit and the addition circuit, thereby simplifying the decoding process. In addition, the code element correlation of the four-level pulse amplitude modulation signal is eliminated during the encoding process of the four-level pulse amplitude modulation signal, so as to avoid the bit error at the previous moment from being transmitted to the next moment, thereby reducing the bit error rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 is a flow chart of a dual binary four-level pulse amplitude modulation signal processing method provided in an embodiment of the present application;

[0047] Figure 2 It is a coding schematic diagram provided in an embodiment of the present application;

[0048] Figure 3 It is a decoding schematic diagram provided in an embodiment of the present application;

[0049] Figure 4 It is a structural schematic diagram of a dual binary four-level pulse amplitude modulation signal processing system provided in an embodiment of the present application;

[0050] Figure 5 It is a structural schematic diagram of another dual binary four-level pulse amplitude modulation signal processing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] See also Figure 1 , which shows an optional process of a dual binary four-level pulse amplitude modulation signal processing method provided in an embodiment of the present application, which may include the following steps:

[0053] 101: Obtain a PAM4-DB signal, wherein the PAM4-DB signal is obtained by encoding the PAM4 signal, and the symbol correlation of the PAM4 signal is eliminated during the encoding process of the PAM4 signal. By eliminating the symbol correlation, the bit error at the previous moment is prevented from being transmitted to the next moment, thereby reducing the bit error rate.

[0054] In this embodiment, the PAM4-DB signal is obtained by encoding the PAM4 signal at the transmitting end. After encoding the PAM4-DB, the transmitting end sends it to the receiving end. The receiving end decodes the received PAM4-DB signal to restore the PAM4 signal. Figure 1 Describe the decoding process of the receiver after receiving the PAM4-DB signal.

[0055] A feasible way for the transmitter to encode the PAM4 signal to obtain the PAM4-DB signal is to precode the PAM4 signal to eliminate the symbol correlation of the PAM4 signal; and perform dual binary (DB) modulation on the precoded PAM4 signal to obtain the PAM4-DB signal. The reason for precoding before DB modulation of the signal is:

[0056] If the unprecoded PAM4 signal is DB-encoded to obtain a PAM4-DB signal, the logic of DB encoding is b n =a n +a n-1 , signal a for receiving decision at the receiving end n =b n -a n-1 It is the inverse operation of DB coding. Therefore, the sampling decision value a at the current moment is n is the sampling decision value a at the previous moment n-1 closely related, if the sampling decision value a at the previous moment n-1If a misjudgment occurs, it will cause a bit error at the current moment, and it will continue to be transmitted, causing error transmission. The way to solve the error transmission is to perform pre-coding before DB encoding to eliminate the correlation of code elements and avoid error transmission.

[0057] One way to precode the PAM4 signal includes: k =(a k +b k-1 )mod4 precodes the PAM4 signal, a k For PAM4 signal, a k The level values ​​include 0, 1, 2 and 3, b k is the output of the current precoding of the PAM4 signal, b k-1 It is the output of the last precoding of the PAM4 signal.

[0058] One method of performing dual binary modulation on the precoded PAM4 signal to obtain a PAM4-DB signal includes: using c k =b k +b k-1 The precoded PAM4 signal is modulated by dual binary. k For PAM4-DB signal, c k The level values ​​include 0, 1, 2, 3, 4, 5 and 6.

[0059] like Figure 2 The coding diagram shown in the figure shows a PAM4 signal. k The level values ​​include 0, 1, 2 and 3. The precoded PAM4 signal is b k , bk=(a k +b k-1 )mod4, the precoded signal is still a PAM4 signal, including four level values, namely 0, 1, 2 and 3. mod is a remainder function, and its application is not described in this embodiment.

[0060] The pre-coded PAM4 signal is DB-encoded to form a PAM4-DB signal. Let the PAM4-DB signal be c k , c k =b k +b k-1 The original four-level signal is converted into a seven-level signal, namely the PAM4-DB signal.

[0061] The truth table of the PAM4-DB signal is as follows:

[0062]

[0063]

[0064] Among them, the four-level signal indicates that the signal has four level values, such as 0, 1, 2 and 3, and the seven-level signal indicates that the signal has seven level values, such as 0, 1, 2, 3, 4, 5 and 6. Figure 2 Delay T b Indicates the output b of the last precoding of the PAM4 signal k-1 .

[0065] 102: Divide the PAM4-DB signal to a plurality of comparison circuits, wherein the PAM4-DB signal is processed by each comparison circuit respectively to obtain a first logic level signal, wherein the number of the first logic level signals is the same as the number of the comparison circuits.

[0066] The shunting is to input the PAM4-DB signal to each comparison circuit simultaneously or sequentially. In this embodiment, one way of shunting and processing using the comparison circuit is as follows:

[0067] The PAM4-DB signal is split into eight signals by using a broadband splitter, wherein the first signal to the eighth signal are sequentially input into the first comparison circuit to the eighth comparison circuit; then the level of the input signal is compared with the threshold level by using the first comparison circuit to the eighth comparison circuit to obtain the first logic level signal of each comparison circuit.

[0068] The threshold levels corresponding to the first comparison circuit to the eighth comparison circuit may be the same or different. For example, one way is: the first comparison circuit corresponds to the first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to the fourth threshold level, the third comparison circuit corresponds to the second threshold level, the fifth comparison circuit corresponds to the third threshold level, the seventh comparison circuit corresponds to the fifth threshold level, and the eighth comparison circuit corresponds to the sixth threshold level.

[0069] The levels of the PAM4-DB signal include the first level to the seventh level, such as 0 to 6 mentioned above. The relationship between the first level to the seventh level and the first threshold level to the sixth threshold level is: the first level is less than the first threshold level, the first threshold level is less than the second level, the second level is less than the second threshold level, the second threshold level is less than the third level, the third level is less than the third threshold level, the third threshold level is less than the fourth level, the fourth level is less than the fourth threshold level, the fourth threshold level is less than the fifth level, the fifth level is less than the fifth threshold level, the fifth threshold level is less than the sixth level, the sixth level is less than the sixth threshold level, and the sixth threshold level is less than the seventh level.

[0070] In this embodiment, the eight-way signal splitting and the use of the above six threshold levels for comparison are merely exemplary descriptions, and this embodiment is not limiting.

[0071] 103: Perform XOR processing on some of the first logic level signals among all the first logic level signals respectively by using an XOR circuit.

[0072] 104: Perform level inversion processing on the first logic level signal after the XOR processing and the first logic level signal without the XOR processing by using an inversion circuit to obtain a second logic level signal.

[0073] The XOR circuit is used to determine whether at least two logic level signals input into the XOR circuit are the same. If they are the same, a low level 0 is output, and if they are different, a high level is output, and decoding is performed through XOR processing. In this embodiment, two first logic level signals can be XOR processed, such as using an XOR gate to XOR two first logic level signals. The two first logic level signals input by different XOR gates are different, so that multiple first logic level signals can be XOR processed simultaneously through multiple XOR gates. The inverting circuit is used to convert the level, 1 to 0, 0 to 1, for example, which can be achieved by an inverter.

[0074] Combining the eight-way signals and eight comparison circuits described above, one way to perform XOR processing and level inversion processing is as follows:

[0075] The first logic level signals output by the first comparison circuit and the second comparison circuit are subjected to XOR processing by using an XOR gate; the first logic level signals output by the third comparison circuit and the fourth comparison circuit are subjected to XOR processing by using an XOR gate; the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit are subjected to XOR processing by using an XOR gate; the first logic level signal after XOR processing and the first logic level signal without XOR processing are subjected to level inversion processing by using an inverter to obtain a second logic level signal.

[0076] 105: Use an adding circuit to add all the second logic level signals to obtain a PAM4 signal.

[0077] Combine the following Figure 3 The circuit structure shown illustrates the decoding process of this embodiment. The PAM4-DB signal is split into eight signals through a broadband splitter and enters the next stage. The signals are compared with the threshold voltage through the eight comparison circuits of the next stage and converted into the first logic level signal. Assume that the seven level values ​​of the AM4-DB signal are recorded as V1, V2, V3, V4, V5, V6 and V7, which are the first to seventh levels, and the values ​​can be 0 to 6; the eight comparison circuits correspond to six threshold levels, which are recorded as VA, VB, VC, VD, VE and VF, which are the first to sixth threshold levels, and the relationship between these six threshold levels and the above seven levels is as follows:

[0078] V1 <VA<V2<VB<V3<VC<V4<VD<V5<VE<V6<VF<V7;

[0079] Through this relationship, the first threshold level to the sixth threshold level can be set. The values ​​of the six threshold levels are not limited in this embodiment. Figure 3 The eight comparison circuits shown can be eight high-speed comparators to increase the processing speed. The eight high-speed comparators are respectively recorded as A, D1, B, D2, C, D3, E and F, which are the first comparison circuit to the eighth comparison circuit respectively; the threshold levels corresponding to these eight comparison circuits are VA, VD, VB, VD, VC, VD, VE and VF, which is consistent with the above description that "the first comparison circuit corresponds to the first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to the fourth threshold level, the third comparison circuit corresponds to the second threshold level, the fifth comparison circuit corresponds to the third threshold level, the seventh comparison circuit corresponds to the fifth threshold level, and the eighth comparison circuit corresponds to the sixth threshold level". If the level of the signal input to the eight comparison circuits is st, the truth table after passing through the eight comparison circuits is as follows:

[0080]

[0081] The outputs of comparison circuit A and comparison circuit D1 are integrated into one signal through the XOR gate again, the outputs of comparison circuit B and comparison circuit D2 are integrated into one signal through the XOR gate again, the outputs of comparison circuits C and D3 are integrated into one signal through the XOR gate again, and the XOR-processed signals and the outputs of the above-mentioned comparison circuits VE and VF, a total of five signals, enter the next level.

[0082] The truth table after XOR processing is as follows. The XOR in the truth table represents the XOR circuit:

[0083]

[0084] The five signals mentioned above are each converted to high or low levels through an inverter, 1 is converted to 0 and 0 is converted to 1.

[0085] The truth table is as follows. The inverter in the truth table represents an inverting circuit:

[0086]

[0087]

[0088] The level-converted signals are added through the adding circuit, and the resulting signal is the PAM4 signal obtained by decoding the PAM4-DB signal. The PAM4 signal that is pre-coded to eliminate the correlation between code elements and then DB-encoded is decoded through the above-mentioned simple circuits such as the comparison circuit, XOR circuit, inversion circuit and adding circuit. The truth table after addition by the adding circuit is as follows, and SUN in the truth table represents the adding circuit:

[0089]

[0090] The above-mentioned dual binary four-level pulse amplitude modulation signal processing method obtains a PAM4-DB signal, which is obtained by encoding a PAM4 signal, and the code element correlation of the PAM4 signal is eliminated during the encoding process of the PAM4 signal; the PAM4-DB signal is shunted to multiple comparison circuits, and the PAM4-DB signal is processed by each comparison circuit respectively to obtain a first logic level signal, and the number of first logic level signals is the same as the number of comparison circuits; using an exclusive OR circuit to perform exclusive OR processing on some of the first logic level signals in all the first logic level signals, and using an inversion circuit to perform level inversion processing on the first logic level signal after the exclusive OR processing and the first logic level signal that has not been subjected to the exclusive OR processing to obtain a second logic level signal; using an addition circuit to add all the second logic level signals to obtain a PAM4 signal, and realize the decoding of the PAM4-DB signal using simple circuits such as a comparison circuit, an exclusive OR circuit, an inversion circuit and an addition circuit, thereby simplifying the decoding process. In addition, the code element correlation of the PAM4 signal is eliminated during the encoding process of the PAM4 signal to avoid the bit error at the previous moment being transmitted to the next moment, thereby reducing the bit error rate.

[0091] Corresponding to the above method embodiment, the present application also provides a dual binary four-level pulse amplitude modulation signal processing system, whose structure is as follows: Figure 4 As shown, it may include: a signal acquisition circuit 10, a shunt circuit 20, and a plurality of comparison circuits 30 ( Figure 4 The ellipsis indicates that there may be multiple comparison circuits 30 ), an XOR circuit 40 , an inversion circuit 50 , and an addition circuit 60 .

[0092] The signal acquisition circuit 10 is used to obtain a PAM4-DB signal. The PAM4-DB signal is obtained by encoding the PAM4 signal, and the code element correlation of the PAM4 signal is eliminated during the encoding process of the PAM4 signal. By eliminating the code element correlation, the error code at the previous moment is avoided from being transmitted to the next moment, thereby reducing the bit error rate.

[0093] In this embodiment, the PAM4-DB signal is obtained by encoding the PAM4 signal at the transmitting end. After encoding the PAM4-DB, the transmitting end sends it to the receiving end. The receiving end decodes the received PAM4-DB signal to restore the PAM4 signal. Figure 4 The dual binary four-level pulse amplitude modulation signal processing system shown can be integrated at the receiving end, so that the receiving end can use Figure 4 The system shown decodes the PAM4-DB signal. One feasible way for the transmitter to encode the PAM4 signal to obtain the PAM4-DB signal is to precode the PAM4 signal to eliminate the symbol correlation of the PAM4 signal; and perform dual binary (DB) modulation on the precoded PAM4 signal to obtain the PAM4-DB signal. The reason for precoding before DB modulation of the signal is:

[0094] If the unprecoded PAM4 signal is DB-encoded to obtain a PAM4-DB signal, the logic of DB encoding is b n =a n +a n-1 , signal a for receiving decision at the receiving end n =b n -a n-1 It is the inverse operation of DB coding. Therefore, the sampling decision value a at the current moment is n is the sampling decision value a at the previous moment n-1 closely related, if the sampling decision value a at the previous moment n-1 If a misjudgment occurs, it will cause a bit error at the current moment, and it will continue to be transmitted, causing error transmission. The way to solve the error transmission is to perform pre-coding before DB encoding to eliminate the correlation of code elements and avoid error transmission.

[0095] One way to precode the PAM4 signal includes: k =(a k +b k-1 )mod4 precodes the PAM4 signal, a k For PAM4 signal, a k The level values ​​include 0, 1, 2 and 3, b k is the output of the current precoding of the PAM4 signal, b k-1 is the output of the last precoding of the PAM4 signal. One method of performing dual binary modulation on the precoded PAM4 signal to obtain a PAM4-DB signal includes: using c k =b k +b k-1 The precoded PAM4 signal is modulated by dual binary. k For PAM4-DB signal, ck The level values ​​include 0, 1, 2, 3, 4, 5 and 6.

[0096] The shunt circuit 20 is used to shunt the PAM4-DB signal to multiple comparison circuits 30. The PAM4-DB signal is processed by each comparison circuit 30 to obtain a first logic level signal. The number of first logic level signals is the same as the number of comparison circuits. The shunt circuit 20 can be a broadband shunt, which shunts the PAM4-DB signal into eight signals. The first signal to the eighth signal are sequentially input into the first comparison circuit to the eighth comparison circuit; the first comparison circuit to the eighth comparison circuit compares the level of the input signal with the threshold level to obtain the first logic level signal of each comparison circuit.

[0097] The first comparison circuit corresponds to the first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to the fourth threshold level, the third comparison circuit corresponds to the second threshold level, the fifth comparison circuit corresponds to the third threshold level, the seventh comparison circuit corresponds to the fifth threshold level, and the eighth comparison circuit corresponds to the sixth threshold level.

[0098] The levels of the PAM4-DB signal include the first level to the seventh level; the relationship between the first level to the seventh level and the first threshold level to the sixth threshold level is: the first level is less than the first threshold level, the first threshold level is less than the second level, the second level is less than the second threshold level, the second threshold level is less than the third level, the third level is less than the third threshold level, the third threshold level is less than the fourth level, the fourth level is less than the fourth threshold level, the fourth threshold level is less than the fifth level, the fifth level is less than the fifth threshold level, the fifth threshold level is less than the sixth level, the sixth level is less than the sixth threshold level, and the sixth threshold level is less than the seventh level.

[0099] The XOR circuit 40 is used to perform XOR processing on some of the first logic level signals among all the first logic level signals.

[0100] The inversion circuit 50 is used to perform level inversion processing on the first logic level signal after the XOR processing and the first logic level signal without the XOR processing to obtain a second logic level signal.

[0101] The XOR circuit 40 may be an XOR gate, and the inverting circuit 50 may be an inverter; the XOR gate is used to perform XOR processing on the first logic level signal output by the first comparison circuit and the second comparison circuit; perform XOR processing on the first logic level signal output by the third comparison circuit and the fourth comparison circuit; and perform XOR processing on the first logic level signal output by the fifth comparison circuit and the sixth comparison circuit. In this embodiment, the dual binary four-level pulse amplitude modulation signal processing system may include multiple XOR gates, each of which performs XOR processing on two first logic level signals. The inverter is used to perform level inversion processing on the first logic level signal after XOR processing and the first logic level signal without XOR processing to obtain a second logic level signal.

[0102] The adding circuit 60 is used to add all the second logic level signals to obtain a PAM4 signal.

[0103] In this embodiment, the description of the shunt circuit 20, the plurality of comparison circuits 30, the XOR circuit 40, the inverting circuit 50 and the adding circuit 60 can be found in the above embodiments and will not be repeated here.

[0104] See also Figure 5 , which shows an optional structure of another dual binary four-level pulse amplitude modulation signal processing system, and can also include: a coding circuit 70, used to encode the PAM4 signal to obtain a PAM4-DB signal; wherein the coding circuit encodes the PAM4-DB signal including: precoding the PAM4 signal to eliminate the code element correlation of the PAM4 signal; performing dual binary modulation on the precoded PAM4 signal to obtain the PAM4-DB signal, and the detailed process can be found in the above description.

[0105] The encoding circuit can be used to encode the PAM4 signal to obtain the PAM4-DB signal, which is sent to the receiving end for decoding. Since the dual-binary four-level pulse amplitude modulation signal processing system can both encode the PAM4 signal to obtain the PAM4-DB signal and decode the PAM4-DB signal to restore the PAM4 signal, any device that integrates the dual-binary four-level pulse amplitude modulation signal processing system can serve as both the transmitter and the receiver of the PAM4-DB signal.

[0106] The above-mentioned dual binary four-level pulse amplitude modulation signal processing system obtains a PAM4-DB signal, which is obtained by encoding the PAM4 signal, and the code element correlation of the PAM4 signal is eliminated during the encoding process of the PAM4 signal; the PAM4-DB signal is shunted to multiple comparison circuits, and the PAM4-DB signal is processed by each comparison circuit respectively to obtain a first logic level signal, and the number of first logic level signals is the same as the number of comparison circuits; using an exclusive OR circuit to perform exclusive OR processing on some of the first logic level signals in all the first logic level signals, and using an inversion circuit to perform level inversion processing on the first logic level signal after the exclusive OR processing and the first logic level signal that has not been subjected to the exclusive OR processing to obtain a second logic level signal; using an addition circuit to add all the second logic level signals to obtain a PAM4 signal, and realize the decoding of the PAM4-DB signal using simple circuits such as a comparison circuit, an exclusive OR circuit, an inversion circuit and an addition circuit, thereby simplifying the decoding process. In addition, the code element correlation of the PAM4 signal is eliminated during the encoding process of the PAM4 signal to avoid the bit error at the previous moment being transmitted to the next moment, thereby reducing the bit error rate.

[0107] The embodiment of the present application further provides a storage medium, in which a computer program code is stored. When the computer program code is executed, the above-mentioned dual binary four-level pulse amplitude modulation signal processing method is implemented.

[0108] It should be noted that the various embodiments in this specification can be described in a progressive manner, and the features recorded in the various embodiments in this specification can be replaced or combined with each other. Each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0109] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0110] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0111] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A dual binary four-level pulse amplitude modulation signal processing method, characterized in that: The method comprises: Obtaining a duobinary four-level pulse amplitude modulation signal, wherein the duobinary four-level pulse amplitude modulation signal is obtained by encoding a four-level pulse amplitude modulation signal, and the symbol correlation of the four-level pulse amplitude modulation signal is eliminated during the encoding process of the four-level pulse amplitude modulation signal; Dividing the duobinary four-level pulse amplitude modulation signal to a plurality of comparison circuits, wherein the duobinary four-level pulse amplitude modulation signal is processed by each comparison circuit respectively to obtain a first logic level signal, wherein the number of the first logic level signals is the same as the number of the comparison circuits; Using an XOR circuit to perform XOR processing on some of the first logic level signals in all the first logic level signals, and using an inversion circuit to perform level inversion processing on the first logic level signals after the XOR processing and the first logic level signals not subjected to the XOR processing, to obtain second logic level signals; All second logic level signals are added by using an adding circuit to obtain the four-level pulse amplitude modulation signal.

2. The method according to claim 1, characterized in that The encoding of the four-level pulse amplitude modulation signal to obtain a dual binary four-level pulse amplitude modulation signal comprises: Precoding the four-level pulse amplitude modulation signal to eliminate symbol correlation of the four-level pulse amplitude modulation signal; The precoded four-level pulse amplitude modulation signal is subjected to duo-binary modulation to obtain the duo-binary four-level pulse amplitude modulation signal.

3. The method according to claim 2, characterized in that The precoding of the four-level pulse amplitude modulation signal comprises: With b k =(a k +b k-1 )mod4 pre-codes the four-level pulse amplitude modulation signal, a k is the four-level pulse amplitude modulation signal, a k The level values ​​include 0, 1, 2 and 3, b k is the output of the current precoding of the four-level pulse amplitude modulation signal, b k-1 is the output of the last precoding of the four-level pulse amplitude modulation signal; The performing duo-binary modulation on the precoded four-level pulse amplitude modulation signal to obtain the duo-binary four-level pulse amplitude modulation signal comprises: Using c k =b k +b k-1 The precoded four-level pulse amplitude modulation signal is subjected to dual binary modulation, c k is the dual binary four-level pulse amplitude modulation signal, c k The level values ​​include 0, 1, 2, 3, 4, 5 and 6.

4. The method according to any one of claims 1 to 3, characterized in that The step of shunting the duobinary four-level pulse amplitude modulation signal to a plurality of comparison circuits, wherein the duobinary four-level pulse amplitude modulation signal is processed by each comparison circuit respectively to obtain a first logic level signal comprises: The dual binary four-level pulse amplitude modulation signal is split into eight signals by a broadband splitter, wherein the first signal to the eighth signal are sequentially input into the first comparison circuit to the eighth comparison circuit; The level of the input signal is compared with the threshold level by using the first comparison circuit to the eighth comparison circuit to obtain the first logic level signal of each comparison circuit.

5. The method according to claim 4, characterized in that The first comparison circuit corresponds to a first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level; The levels of the duobinary four-level pulse amplitude modulation signal include a first level to a seventh level; The relationship between the first level to the seventh level and the first threshold level to the sixth threshold level is: the first level is less than the first threshold level, the first threshold level is less than the second level, the second level is less than the second threshold level, the second threshold level is less than the third level, the third level is less than the third threshold level, the third threshold level is less than the fourth level, the fourth level is less than the fourth threshold level, the fourth threshold level is less than the fifth level, the fifth level is less than the fifth threshold level, the fifth threshold level is less than the sixth level, the sixth level is less than the sixth threshold level, and the sixth threshold level is less than the seventh level.

6. The method according to claim 4, characterized in that The method of performing XOR processing on some of the first logic level signals in all the first logic level signals respectively by using an XOR circuit, and performing level inversion processing on the first logic level signals after the XOR processing and the first logic level signals not subjected to the XOR processing by using an inversion circuit to obtain the second logic level signal comprises: Using an XOR gate to perform XOR processing on the first logic level signals output by the first comparison circuit and the second comparison circuit; Using an XOR gate to perform XOR processing on the first logic level signals output by the third comparison circuit and the fourth comparison circuit; Using an XOR gate to perform XOR processing on the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit; An inverter is used to perform level inversion processing on the first logic level signal after the XOR processing and the first logic level signal without the XOR processing to obtain a second logic level signal.

7. A dual binary four-level pulse amplitude modulation signal processing system, characterized in that: The system comprises: a signal acquisition circuit, a current shunting circuit, a plurality of comparison circuits, an XOR circuit, an inverting circuit and an adding circuit; The signal acquisition circuit is used to obtain a duobinary four-level pulse amplitude modulation signal, wherein the duobinary four-level pulse amplitude modulation signal is obtained by encoding a four-level pulse amplitude modulation signal, and the code element correlation of the four-level pulse amplitude modulation signal is eliminated during the encoding process of the four-level pulse amplitude modulation signal; The shunt circuit is used to shunt the duobinary four-level pulse amplitude modulation signal to the plurality of comparison circuits, the duobinary four-level pulse amplitude modulation signal is processed by each comparison circuit respectively to obtain a first logic level signal, and the number of the first logic level signals is the same as the number of the comparison circuits; The XOR circuit is used to perform XOR processing on some of the first logic level signals among all the first logic level signals respectively; The inversion circuit is used to perform level inversion processing on the first logic level signal after the XOR processing and the first logic level signal without the XOR processing to obtain a second logic level signal; The adding circuit is used to perform addition processing on all second logic level signals to obtain the four-level pulse amplitude modulation signal.

8. The system according to claim 7, characterized in that The system further comprises: an encoding circuit for encoding the four-level pulse amplitude modulation signal to obtain a dual binary four-level pulse amplitude modulation signal; The encoding circuit encodes the duobinary four-level pulse amplitude modulation signal, which includes: pre-encoding the four-level pulse amplitude modulation signal to eliminate the code element correlation of the four-level pulse amplitude modulation signal; and performing duobinary modulation on the pre-coded four-level pulse amplitude modulation signal to obtain the duobinary four-level pulse amplitude modulation signal.

9. The system according to claim 7 or 8, characterized in that: The shunting circuit is a broadband shunter, which shuns the dual binary four-level pulse amplitude modulation signal into eight signals, and the first signal to the eighth signal are sequentially input into the first comparison circuit to the eighth comparison circuit; the first comparison circuit to the eighth comparison circuit compares the level of the input signal with the threshold level to obtain a first logic level signal of each comparison circuit; wherein the first comparison circuit corresponds to a first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level; The levels of the duobinary four-level pulse amplitude modulation signal include a first level to a seventh level; The relationship between the first level to the seventh level and the first threshold level to the sixth threshold level is: the first level is less than the first threshold level, the first threshold level is less than the second level, the second level is less than the second threshold level, the second threshold level is less than the third level, the third level is less than the third threshold level, the third threshold level is less than the fourth level, the fourth level is less than the fourth threshold level, the fourth threshold level is less than the fifth level, the fifth level is less than the fifth threshold level, the fifth threshold level is less than the sixth level, the sixth level is less than the sixth threshold level, and the sixth threshold level is less than the seventh level.

10. The system according to claim 9, characterized in that The XOR circuit is an XOR gate, and the inverting circuit is an inverter; The XOR gate is used to perform XOR processing on the first logic level signals output by the first comparison circuit and the second comparison circuit; Performing an exclusive OR process on the first logic level signals output by the third comparison circuit and the fourth comparison circuit; performing an exclusive OR process on the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit; The inverter is used to perform level inversion processing on the first logic level signal after the XOR processing and the first logic level signal without the XOR processing to obtain a second logic level signal.

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