Multilevel output driver circuit and method

Abstract

The application discloses a multi-level output driving circuit and method. The circuit comprises a signal selection module configured to select a to-be-transmitted signal of a corresponding channel according to an externally input signal; a weight generation module configured to generate weight data according to the weight of an output eye diagram; wherein the weight of the output eye diagram and the weight data are both multi-bit binary data; a coefficient transmission module configured to perform weight control on the to-be-transmitted signal according to the weight data to generate data containing weight information; and a weight adjustment and data output module configured to perform weight adjustment and pulse amplitude modulation calculation according to weight adjustment control data, the to-be-transmitted signal and the data containing weight information to generate four-level pulse amplitude modulation data PAM4. Compared with the prior art, the embodiment of the application enriches the mode of eye diagram adjustment and can be applied to eye diagram misadjustment caused by different transmission environments.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a multi-level output driving circuit and method. BACKGROUND

[0002] With the evolution of signal transmission rate from 28G to higher speed, the use of traditional single-channel modulation mode is limited. PAM (Pulse Amplitude modulation) signal can use multiple signal levels, so that each signal period can transmit more bits of digital signal, thereby greatly improving the transmission rate. Therefore, the four-level pulse amplitude modulation (PAM4) mode emerges as the times require. The PAM4 signal is composed of four levels, and each signal period can transmit 2 bits of signal, and the transmission rate is doubled compared with the traditional single-channel modulation mode. In the prior art, whether the PAM4 signal is attenuated and deteriorated can be analyzed by eye diagram analysis method. Due to the high transmission rate, the PAM4 signal will produce loss in the transmission process, so that the existing PAM4 signal eye diagram has a misadjustment problem. SUMMARY

[0003] The main purpose of the embodiments of the present application is to provide a multi-level output driving circuit and method, which aims to enrich the eye diagram adjustment mode to adapt to the eye diagram misadjustment problem caused by different transmission environments.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application provide a multi-level output driving circuit, which comprises:

[0005] A signal selection module is configured to select the to-be-transmitted signal of the corresponding channel according to the externally input signal;

[0006] A weight generation module is configured to generate weight data according to the weight of the output eye diagram; wherein the weight of the output eye diagram and the weight data are both multi-bit binary data;

[0007] A coefficient transmission module is configured to perform weight control on the to-be-transmitted signal according to the weight data, and generate data containing weight information;

[0008] A weight adjustment and data output module is configured to perform weight adjustment and pulse amplitude modulation calculation according to the weight adjustment control data, the to-be-transmitted signal and the data containing weight information, and generate four-level pulse amplitude modulation data PAM4.

[0009] To achieve the above-mentioned purpose, the embodiments of the present application provide a multi-level output driving method, which can be applied to the multi-level output driving circuit described in any embodiment of the present application, and the method comprises the following steps:

[0010] The signal selection module controls the selection of the to-be-transmitted signal of the corresponding channel according to the externally input signal;

[0011] The weight generation module generates weight data according to the weight of the output eye diagram; wherein the weight of the output eye diagram and the weight data are both multi-bit binary data;

[0012] The coefficient transmission module controls the weight of the to-be-transmitted signal according to the weight data, and generates data containing weight information;

[0013] The weight adjustment and data output module performs weight adjustment and pulse amplitude modulation calculation according to the weight adjustment control data, the to-be-transmitted signal and the data containing weight information, and generates four-level pulse amplitude modulation data PAM4.

[0014] The multi-level output driving circuit and method proposed in the application realize weight adjustment in a digital manner of DAC, and set a weight adjustment and data output module in the multi-level output driving circuit to adjust the MSB of the data containing weight information <m:1> / LSB <m:1>The weight adjustment and the pulse amplitude modulation calculation are performed, and the purpose of adjusting the generated pulse amplitude modulation data level is achieved. Compared with adjusting the eye diagram by using an analog implementation manner, the embodiment of the application can not only realize the processing of reducing the middle eye diagram, but also realize the processing of increasing the upper and lower eye diagrams, and can more widely cope with the eye diagram RLM misadjustment problem caused by different transmission environments. In addition, the embodiment of the application transmits the data signal in a binary form, and the change of the transmission level corresponding to one code value is small, so that more accurate fine adjustment of the eye diagram can be realized. In addition, the operation process in the principle of the embodiment of the application does not have a requirement on the transmission rate, the power consumption is determined by the to-be-transmitted signal rate, the adjustment process does not generate additional power consumption, and the calculation demand is small. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a structural schematic diagram of a multi-level output driving circuit provided by the embodiment of the application;

[0016] Figure 2 is a structural schematic diagram of a weight adjustment and data output module provided by the embodiment of the application;

[0017] Figure 3 is a structural schematic diagram of another weight adjustment and data output module provided by the embodiment of the application;

[0018] Figure 4 is a structural schematic diagram of still another weight adjustment and data output module provided by the embodiment of the application;

[0019] Figure 5 is a structural schematic diagram of an output summation module provided by the embodiment of the application;

[0020] Figure 6 is a structural schematic diagram of a weight generation module provided by the embodiment of the application;

[0021] Figure 7 is a flow schematic diagram of a multi-level output driving method provided by the embodiment of the application. DETAILED DESCRIPTION

[0022] The application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings, not all the structures.

[0023] The embodiment of the application provides a multi-level output driving circuit, which can be applied to a high-speed Serdes circuit and realizes one-way adjustment of an output eye diagram. Figure 1 is a structural schematic diagram of a multi-level output driving circuit provided by the embodiment of the application. Referring to Figure 1 The multi-level output driving circuit 100 comprises a signal selection module 110, a weight generation module 120, a coefficient transmission module 130, and a weight adjustment and data output module 140. The signal selection module 110 is configured to select the to-be-transmitted signals of corresponding channels according to an externally input signal. The weight generation module 120 is configured to generate weight data according to the weight of an output eye diagram; wherein the weight of the output eye diagram and the weight data are both multi-bit binary data. The coefficient transmission module 130 is configured to perform weight control on the to-be-transmitted signals according to the weight data, to generate data containing weight information. The weight adjustment and data output module 140 is configured to perform weight adjustment and pulse amplitude modulation calculation according to weight adjustment control data, the to-be-transmitted signals, and the data containing weight information, to generate four-level pulse amplitude modulation data.

[0024] The input end of the signal selection module 110 receives an externally input signal, and the signal selection module 110 inputs high-bit transmission signals MSB and low-bit transmission signals LSB. At least two output ends of the signal selection module 110 respectively output to-be-transmitted signals MSB / LSB of corresponding channels, and transmit the to-be-transmitted signals MSB / LSB to the coefficient transmission module 130 and the weight adjustment and data output module 140. In this way, data preparation can be achieved by setting the signal selection module 110.

[0025] The input end of the weight generation module 120 receives output eye diagram weight, and the output eye diagram weight comprises initial weight data co <m:1>and a weight polarity co_polar. Wherein the output eye weight is a multi-bit binary data is referred to as the initial weight data co <m:1>for multi-bit binary data, m is a natural number. In an embodiment, m > 7 to convert MSB and LSB to higher bit binary data, improving the accuracy of signal transmission. The output eye diagram weight co <m:1>The / co_polar determines the initial weight of each MSB / LSB of the signal to be transmitted, thereby determining the eye height of each eye in the eye diagram. The output end of the weight generation module 120 outputs the weight data C <m:1> / CB <m:1>The weight data C <m:1> / CB <m:1>The output is fed to the coefficient transfer module 130. In this case, the output eye pattern weight is multi-bit binary data, and correspondingly, the weight data is multi-bit binary data. The weight data includes a maximum weight code value C <m:1>and the maximum weight code value complement CB <m:1>.

[0026] The input of the coefficient transfer module 130 receives the signal to be transmitted MSB / LSB output by the signal selection module 110 and the weight data C output by the weight generation module 120 <m:1> / CB <m:1>The coefficient transmission module 130 combines the MSB / LSB of the data to be transmitted with the weight data C <m:1> / CB <m:1>The operation processing is performed to determine data including weight information. The data including weight information includes high bit data MSB including weight information <m:1>and low bit data LSBs including weight information <m:1>The output of the coefficient transfer module 130 will contain data MSB <m:1> / LSB <m:1>The output of the weight adjustment and data output module 140 is connected to the input of the coefficient transmission module 130.

[0027] The input of the weight adjustment and data output module 140 receives the to-be-transmitted signal MSB / LSB output by the signal selection module 110 and the data MSB containing weight information output by the coefficient transmission module 130 <m:1> / LSB <m:1>, and weight adjustment control data adj <n:1>. wherein the weight adjustment control data adj <n:1>the value of the data MSB containing the weight information <m:1> / LSB <m:1>weight adjustment is performed. Since the data MSB <m:1> / LSB <m:1>For multi-bit binary data, then, the weight adjustment control data adj <n:1>The data MSB containing the weight information can be <m:1> / LSB <m:1>one or more of the plurality of transmitters adjusts the weight. If the weight adjustment control data adj <n:1>If valid, the weight adjustment and data output module 140 will output the data MSB containing the weight information <m:1> / LSB <m:1>, the signal to be transmitted MSB / LSB and weight adjustment control data adj <n:1>The operation is performed to obtain pulse amplitude modulation data PAM4 with weight-adjustable information. The pulse amplitude modulation data PAM4 adjusted by the weight is transmitted to a signal transmitting module (TX) for data and parallel-to-serial transmission.

[0028] Exemplarily, the working process of the multi-level output driving circuit 100 is that the coefficient transmission module 130 transmits the to-be-transmitted signal MSB / LSB output by the signal selection module 110 and the weight data C output by the weight generation module 120 to the weight adjustment module 140. <m:1> / CB <m:1>The operation is performed to generate two m-bit binary codes containing high and low level information of MSB / LSB of the signal to be transmitted, i.e. data MSB containing weight information <m:1> / LSB <m:1>; when weight adjustment control data adj <n:1>If not 0, code value is adjusted to make the weight corresponding to the m-bit binary code of the transmission level to be adj <n:1>The m bits of LSB data are divided by 2, and then full add operation is performed with the m bits of MSB data. Since the MSB / LSB both contain high and low signals, after the sum operation, PAM4 containing four level information is obtained, as shown in Table 1.

[0029] Table 1

[0030] MSB LSB MSB+LSB / 2 0 0 0 0 1 1 / 2 1 0 1 1 1 3 / 2

[0031] The weight adjustment of the pulse amplitude modulation data PAM4 is reflected in the adjustment of the eye height in the eye diagram. Exemplarily, the weight adjustment control data adj <n:1>Whether it is effective can be judged according to actual eye diagram and simulation results. RLM (level separation mismatch ratio) refers to the proportion of the minimum eye height in the average eye height in the multiple eyes formed when two or more pulse level signals are transmitted, and is a quantity representing whether the eye diagram distribution is ideal. The closer RLM is to 1, the more ideal the eye diagram distribution is. For PAM4, the eye diagram distribution includes three eye heights, and in an ideal state, the three eye heights are equal. However, due to different attenuations of the channel to different levels, the eye diagram distribution changes, the middle eye diagram increases or decreases, and the value of RLM is small, which cannot meet the needs of signal transmission. At this time, by setting the weight adjustment control data adj <n:1>Effectively, adjustment to the eye height in the eye diagram can be achieved, for example, to achieve a middle eye diagram reduction or to achieve an upper and lower eye diagram increase. Thus, by adjusting the eye height, adjustment to the RLM can be achieved such that the RLM is greater than 0.96, and in one embodiment, the RLM is greater than 0.98.

[0032] The embodiment of the present application adopts a digital method of the DAC to achieve weight adjustment. By setting a weight adjustment and data output module 140 in the multi-level output driving circuit, the data MSB containing weight information is outputted to the DAC 130, and the weight adjustment is achieved by adjusting the weight of the DAC 130. <m:1> / LSB <m:1>The weight adjustment and the pulse amplitude modulation calculation are performed, and the adjustment of the generated pulse amplitude modulation data level is realized. Compared with adjusting the eye diagram by using an analog implementation mode, the embodiment of the application can not only realize the processing of reducing the middle eye diagram, but also realize the processing of increasing the upper and lower eye diagrams, and can more widely cope with the eye diagram RLM misadjustment problem caused by different transmission environments. In addition, the embodiment of the application transmits the data signal in a binary form, and the change of the transmission level corresponding to one code value is small, so that more accurate fine adjustment of the eye diagram can be realized. In addition, the operation process in the principle of the embodiment of the application does not have a requirement on the transmission rate, the power consumption is determined by the to-be-transmitted signal rate, the adjustment process does not generate additional power consumption, and the calculation demand is small.

[0033] With reference to Figure 1 In an embodiment, the signal selection module 110 includes a first data selector 111 and a second data selector 112. The control end of the first data selector 111 is connected to the high-bit selection control signal sel<1>, the first data input end of the first data selector 111 is connected to the MSB, and the second data input end of the first data selector 111 is connected to the LSB; the output end of the first data selector 111 outputs the MSB, that is, the first data selector 111 selects and outputs the MSB. The control end of the second data selector 112 is connected to the low-bit selection control signal sel<0>, the first data input end of the second data selector 112 is connected to the MSB, and the second data input end of the second data selector 112 is connected to the LSB; the output end of the second data selector 112 outputs the LSB, that is, the second data selector 112 selects and outputs the LSB.

[0034] With reference to Figure 1 In an embodiment, the coefficient delivery module 130 includes a third data selector 131 and a fourth data selector 132. The control end of the third data selector 131 is connected to the MSB, the first data input end of the third data selector 131 is connected to the C <m:1>, a second data input terminal of the third data selector 131 is connected to the CB <m:1>; output of third data selector 131 outputs MSB <m:1>; wherein MSB <m:1>For C <m:1>or CB <m:1>, depending on the value of the MSB. The control terminal of the fourth data selector 132 is connected to the LSB, and the first data input terminal of the fourth data selector 132 is connected to the C <m:1>, a second data input of the fourth data selector 132 is connected to the CB <m:1>; output of fourth data selector 132 outputs LSB <m:1>; wherein LSB <m:1>For C <m:1>or CB <m:1>, depending on the value of the LSB.

[0035] Figure 2 is a structural schematic diagram of a weight adjustment and data output module provided by an embodiment of the present application. Referring to Figure 2 In an embodiment, the weight adjustment and data output module 140 comprises a high-bit weight adjustment module 141, a low-bit weight adjustment module 142, a high-bit summation module 143, a low-bit summation module 144, and an output summation module 145. The high-bit weight adjustment module 141 is configured to adjust the high bits of the weight according to the MSB and the weight adjustment control data adj <n:1>, to generate high-bit weight adjustment code values a1...an; where n is a positive integer. The low-bit weight adjustment module 142 is configured to generate low-bit weight adjustment code values a1...an according to the LSBs and the weight adjustment control data adj <n:1>The low bit weight adjustment code values b1...bn are generated. The high bit summation module 143 is arranged to recombine the high bit weight adjustment code values with 0 to obtain mbits high bit weight adjustment data an,..., ai,..., a1; and the MSB <m:1>with high bit weight adjustment data an,…, ai,…, a1 are summed to obtain a high bit adjustment signal msb <m:1>The low bit summation module 144 is configured to recombine the low bit weight adjustment code value with 0 to obtain the mbits low bit weight adjustment data bn,…,bi,…,b1; and the LSB <m:1>with low bit weight adjustment data bn,…,bi,…,b1 summing, to obtain low bit adjustment signal lsb <m:1>The output summation module 145 is arranged to sum the msb <m:1>and lsb <m:1>summed to PAM4.

[0036] wherein a first input of the high-bit summation module 143 is connected to MSB <m:1>, a second input of the high-bit summation module 143 is connected to an,..., ai,..., a1, an output of the high-bit summation module 143 outputs msb <m:1>. The first input of the low bit sum module 144 is connected to the LSB <m:1>, a second input of the low-order summation module 144 is connected to bn,…,bi,…,b1, an output of the low-order summation module 144 outputs lsb <m:1>.

[0037] In the above embodiments, the LSB division by 2 can be performed on the LSBs of the result of the multiplication of the LSBs of the first and second input values. <m:1>before weight adjustment is performed, or after the LSBs <m:1>After weight adjustment is performed, i.e. lsb <m:1>may be LSB <m:1>Data after 2, also LSB <m:1>Data not removed 2, specific needs to be determined according to the value of n. If in the LSB <m:1>LSB division by 2 can be performed prior to weight adjustment, and the LSBs can be input to the second input of the low bit summation module 144 <m>, LSB <m:1>, so that the LSBs of the data can be extracted from the LSBs of the image data <m:1>after 2 with bn,..., bi,..., bl summing, resulting in lsb <m:1>is LSB <m:1>Data after 2. If the LSB <m:1>After weight adjustment, LSB divide 2 is performed to obtain lsb <m:1>is LSB <m:1>Data not excluded 2, can be summed in the output module 145 lsb <m:1>The processing of the exception 2 is performed.

[0038] Based on the above embodiments, the following will be described in detail for several values of n, but not as a limitation of the present application.

[0039] Continuing to refer to Figure 2 In an embodiment, n≥2; the high weight adjustment module 141 includes: a first NOT gate 1411 and a 1-nth third AND gate 1412. The input end of the first NOT gate 1411 is connected to the MSB, and the output end of the first NOT gate 1411 outputs the opposite data MSB_B of the MSB. The first input end of the 1st third AND gate 1412 is connected to the weight adjustment control data adj<1>, the second input end of the 1st third AND gate 1412 is connected to the MSB_B, and the output end of the 1st third AND gate 1412 outputs the 1st high weight adjustment code value a1. The first input end of the i-th third AND gate 1412 is connected to the weight adjustment control data adj , the second input end of the third AND gate 1412 of the i-th stage is connected with MSB_B, and the output end of the third AND gate 1412 of the i-th stage outputs the i-th high weight adjustment code value ai; wherein i is a positive integer, and 1≤i≤n. The third AND gate 1412 of the n-th stage, the first input end of the third AND gate 1412 of the n-th stage is connected with the weight adjustment control data adj <n>The second input end of the nth third AND gate 1412 is connected to MSB_B, and the output end of the nth third AND gate 1412 outputs the nth high-bit weight adjustment code value a(n).

[0040] The low-bit weight adjustment module 142 comprises a second NOT gate 1421 and 1-nth fourth AND gates 1422. The input end of the second NOT gate 1421 is connected to LSB, and the output end of the second NOT gate 1421 outputs the opposite data LSB_B of LSB. The first input end of the 1st fourth AND gate 1422 is connected to the weight adjustment control data adj<1>, the second input end of the 1st fourth AND gate 1422 is connected to LSB_B, and the output end of the 1st fourth AND gate 1422 outputs the 1st low-bit weight adjustment code value b1. The first input end of the i-th fourth AND gate 1422 is connected to the weight adjustment control data adj , the second input end of the fourth AND gate of the i-th stage 1422 is connected with the LSB_B, and the output end of the fourth AND gate of the i-th stage 1422 outputs the low bit weight adjustment code value bi of the i-th stage; wherein i is a positive integer, and 1≤i≤n. The first input end of the fourth AND gate of the n-th stage 1422 is connected with the weight adjustment control data adj <n>The second input terminal of the nth stage fourth AND gate 1422 is connected to the LSB_B, and the output terminal of the nth stage fourth AND gate 1422 outputs the nth stage low bit weight adjustment code value b(n).

[0041] With continued reference to Figure 2 In one embodiment, the first input terminal of the high bit summation module 143 is connected to the MSB <m:1>, a second input of the high-bit summation module 143 is connected to an,..., ai,..., ai; an output of the high-bit summation module 143 outputs msb <m:1>The first input of the low bit sum module 144 is connected to the LSB of the output of the first adder 142 <m>, LSB <m:1>, a second input of the low- bit summation module 144 is connected to bn,..., bi,..., b1; the low- bit summation module 144 is configured to sum the LSBs <m:1>after 2 and bn,...,bi,...,b1sum, lsb at the output of the low bit sum module 144 <m:1>The first input of the output summation module is connected to the msb <m:1>, a second input of the output summation module is connected to the lsb <m:1>; output sum module is set to sum the lsb <m:1>with msb <m:1>A full adder sum is performed to obtain PAM4.

[0042] The embodiment of the present application sets that when n≥2, the LSB is divided by 2 in the calculation of the LSB <m:1>The weight adjustment is performed before the LSB adjustment, so that the low bit weight adjustment code values bn,..., bi,..., b1 do not change with the LSB <m:1>The deviation caused by the high weight adjustment code values an,..., ai,..., a1 not divided by 2.

[0043] Figure 3 is another structure diagram of a weight adjustment and data output module provided by an embodiment of the present application. Referring to Figure 3 In an embodiment, n = 1, that is, adj <n:1>For 1 bit, the weight adjustment of the circuit is 1 bit mode. The high bit weight adjustment module 141 includes a first AND gate 1413, the first input end of the first AND gate 1413 is connected to the weight adjustment control data adj, the second input end of the first AND gate 1413 is connected to the MSB, and the output end of the first AND gate 1413 outputs the high bit weight adjustment code value a. The low bit weight adjustment module 142 includes a second AND gate 1423, the first input end of the second AND gate 1423 is connected to the weight adjustment control data adj, the second input end of the second AND gate 1423 is connected to the LSB, and the output end of the second AND gate 1423 outputs the low bit weight adjustment code value b.

[0044] Continuing to refer to Figure 3 In an embodiment, the first input end of the high bit summation module 143 is connected to the MSB <m:1>, a second input end of the high-bit summation module 143 is connected to a; an output end of the high-bit summation module 143 outputs msb <m:1>. The first input of the low bit sum module 144 is connected to the LSB <m:1>, a second input of the low sum module 144 is connected to b; an output of the low sum module 144 outputs lsb <m:1>The first input of the output summation module 145 is connected to the msb <m:1>, a second input of the output summation module 145 is tapped into the lsb <m:1>; output sum module 145 is set to add the lsb <m:1>after 2 with msb <m:1>A full adder is performed to obtain DATA <m:1>, DATA <m:1>for PAM4 data.

[0045] in combination Figure 1 and Figure 3 For example, with m = 7 (7-bit numerology), i.e., MSB <m:1>for MSB <7:1>, a is 0, 0, 0, 0, 0, 0, a, msb <m:1>For msb <7:1>, LSB <m:1>for LSB <7:1>, b is 0, 0, 0, 0, 0, 0, b, lsb <m:1>lsb <7:1>, DATA <m:1>DATA<7:1> is for the working principle of the multi-level output driving circuit.

[0046] The maximum code value of data that can be transmitted by 7 bits is 128, and the maximum weight code value of each eye height is 42, that is, co<7:1> = 0101010. Assuming that co<7:1> is 0101010 (42) and adj is 0 (that is, the eye height is not adjusted), the three eyes in the eye diagram are the same size, and the corresponding weight is 42. Assuming that co<7:1> is greater than or equal to 43 and adj is 0 (that is, the eye height is not adjusted), the middle eye becomes larger, and the corresponding size is the same as the code value of co<7:1>, and the upper and lower eyes are reduced by the same code value; in the case of co<7:1> being greater than or equal to 43, adj must be 0, otherwise the code value will overflow and transmission error will occur. Assuming that co<7:1> is less than or equal to 42 and adj is 1 (that is, the eye height is adjusted), compared with adj being 0, the middle eye is reduced by one code value, and the upper and lower eyes have the same size as the code value of co<7:1>.

[0047] Next, the case where adj is 0 and co<7:1> takes 38, 42, 43 and 46 respectively is analyzed in detail. Assuming that the heights of the three eyes from bottom to top are H1, H2 and H3.

[0048] 1) When co<7:1> is 38; co_polar takes a positive value: 0.

[0049] The C<7:1> and CB<7:1> output by the weight generation module 120 are 0100110 (38) and 1011010 (90) respectively; the MSB<7:1> and LSB<7:1> are 90 and 38 respectively; the full add operation of MSB<7:1> (taking the value 90 or 38) and LSB<7:1> (taking the value 90 or 38) is performed to obtain 45, 83, 121 four states, and H1 = 38, H2 = 38, H3 = 38.

[0050] Therefore, the three eyes are equal in size, and the relative eye height is 38 code values.

[0051] 2) When co<7:1> is 42; co_polar takes a positive value: 0.

[0052] The C<7:1> and CB<7:1> output by the weight generation module 120 are 0101010 (42) and 1010110 (86) respectively; the MSB<7:1> and LSB<7:1> are 86 and 42 respectively; the full add operation of MSB<7:1> (taking the value 86 or 42) and LSB<7:1> (taking the value 86 or 42) is performed to obtain 43, 85, 127 four states, and H1 = 42, H2 = 42, H3 = 42.

[0053] Therefore, three eyes are equal in size, and the relative eye height is 42 code values.

[0054] 3) When co<7:1> is 43; co_polar takes value positive: 0.

[0055] The C<7:1> and CB<7:1> output by the weight generation module 120 are 0101011 (43) and 1010101 (85), respectively; the MSB<7:1> and LSB<7:1> are 85 and 43, respectively; the MSB<7:1> (taking value 85 or 43) and the LSB<7:1> (taking value 85 or 43) are full added, 42, 85, 127 four states, and H1=42, H2=43, H3=42.

[0056] Therefore, the middle eye is the largest, and the relative eye height is 43 code values; the two side eyes are equal in size, and the relative eye height is 42 code values.

[0057] 4) When co<7:1> is: 46; co_polar takes value positive: 0.

[0058] The C<7:1> and CB<7:1> output by the weight generation module 120 are 0101110 (46) and 1010010 (82), respectively; the MSB<7:1> and LSB<7:1> are 82 and 46, respectively; the MSB<7:1> (taking value 82 or 46) and the LSB<7:1> (taking value 82 or 46) are full added, 41, 87, 123 four states, and H1=36, H2=46, H3=36.

[0059] Therefore, the middle eye is the largest, and the relative eye height is 46 code values; the two side eyes are equal in size, and the relative eye height is 36 code values.

[0060] Next, the case where adj is 1 and co<7:1> takes 42 is analyzed in detail.

[0061] 1) When co<7:1> takes 42, co_polar takes value positive: 0.

[0062] The C<7:1> and CB<7:1> outputted by the weight generating module 120 are 0101010 (42) and 1010110 (86) respectively; the MSB<7:1> and LSB<7:1> are 86 and 42 respectively; the MSB<7:1> and LSB<7:1> are transmitted to the weight adjusting and data output module 140, the MSB and adj are operated to obtain a, the LSB and adj are operated to obtain b, the MSB<7:1> and 0, 0, 0, 0, 0, 0, a are operated to obtain msb<7:1>, the LSB<7:1> and 0, 0, 0, 0, 0, 0, b are operated to obtain lsb<7:1>, and the msb<7:1> and lsb<7:1> are 87 and 42 respectively; 44, 85, 127 four states, and H1=42, H2=41, H3=42.

[0063] Therefore, the middle eye is the smallest, and the relative eye height is 41 code values; the upper and lower eyes are equal in size, and the relative eye height is 42 code values; compared with adj being 0, two low level (2 and 44) weights are added by 1, the middle eye code value is reduced by 1, and the upper and lower eyes are unchanged.

[0064] From the above analysis, the relationship between the code value of the relative eye height of the output eye diagram and co<7:1> can be summarized as follows:

[0065] In the case of co<7:1>≤42:

[0066] adj=0: H1=H2=H3=co<7:1>

[0067] adj=1: H2=co<7:1>-1

[0068] H1=H3=co<7:1>

[0069] In the case of co<7:1>≥43: adj must be 0, otherwise the code value will overflow.

[0070] adj=0: H1=H3=128-2*co<7:1>

[0071] H2=co<7:1>

[0072] Therefore, by operating the MSB and LSB with the control bits 0, 0, 0, 0, 0, 0, a and 0, 0, 0, 0, 0, 0, b having the weight adjusting code value information respectively, the binary data signal msb<7:1> / lsb<7:1> having the weight adjustable information is finally obtained, 1bit mode, and the LSB division by 2 can be performed on the LSB <m:1>before weight adjustment, or after the LSBs <m:1>The weight adjustment is performed after this is because for binary data, the lowest bit is 1, and in 1 bit mode, even if the LSB <m:1>After weight adjustment, LSB division by 2 is performed, and the weight adjustment bit is still 1, so the weight adjustment will not be affected by the division by 2.

[0073] In one embodiment, for LSB division by 2, the weight adjustment is performed on the LSB <m:1>After weight adjustment, the process involves the high-order summation module 143 as an adder, the low-order summation module 144 as an adder, and the output summation module 145 including an adder. The first input terminal of the high-order summation module 143 is connected to the MSB. <m:1>, a second input of the high bit summation module is connected to a; an output of the high bit summation module outputs msb <m:1>. The first input of the low bit sum module 144 is connected to the LSB <m:1>, a second input of the low sum module 144 is connected to b; an output of the low sum module 144 outputs lsb <m:1>The first input of the output summation module 145 is connected to the msb <m:1>, the second input of the output summation module 145 is connected to the lsb <m:1>, the output summing module 145 is arranged to sum the lsbs <m:1>after 2 with msb <m:1>PAM4 is obtained by full adder summation. In this way, after dividing lsb<7:1> by two, full adder operation is performed with msb<7:1>, and finally the output code value weight-adjustable MSB and 1 / 2*LSB signals are output.

[0074] In an embodiment, for the LSB division by 2, the LSB is divided by 2 in the same way as the MSB division by 2, and the LSB division by 2 is performed in the same way as the MSB division by 2. <m:1>In the manner performed prior to weight adjustment, the high sum module 143 is a sum module, the low sum module 144 is a sum module, and the output sum module 145 includes a sum module. The first input of the high sum module 143 is connected to the MSB <m:1>, a second input end of the high-bit summation module 143 is connected to a; an output end of the high-bit summation module 143 outputs msb <m:1>. The first input of the low bit sum module 144 is connected to the LSB <m>, LSB <m:1>, a second input of the low sum module 144 is connected to b; the low sum module 144 is configured to sum the LSB <m:1>after 2 and b sum, output lsb at output of low bit sum module <m:1>The first input of the output summation module 145 is connected to the msb <m:1>, the second input of the output summation module 145 is connected to the lsb <m:1>, the output summing module 145 is arranged to sum the lsbs <m:1>with msb <m:1>Full adder is performed to obtain PAM4.

[0075] From the above analysis, it can be seen that the data signal is transmitted in the form of binary in the embodiment of the application, wherein one code value corresponds to a small change in transmission level, and more accurate fine adjustment of an eye diagram can be realized. The 1bit weight adjustment mode structure provided in the embodiment of the application realizes the processing of reducing the middle eye diagram and increasing the upper and lower eye diagrams.

[0076] Figure 4 is another structure diagram of a weight adjustment and data output module provided in the embodiment of the application. Referring to Figure 4 In one embodiment, n=2 and m=7. The high-bit weight adjustment module 141 includes a first NOT gate 1411, a first-stage third AND gate 1412 and a second-stage third AND gate 1412; the low-bit weight adjustment module 142 includes a second NOT gate 1421, a first-stage fourth AND gate 1422 and a second-stage fourth AND gate 1422; the high-bit summation module 143 includes two stages of adders 1431; and the low-bit summation module 144 includes two stages of adders 1441.

[0077] The input end of the first NOT gate 1411 is connected to the MSB, and the output end of the first NOT gate 1411 outputs the opposite data MSB_B of the MSB. The first input end of the first-stage third AND gate 1412 is connected to the weight adjustment control data adj<1>, the second input end of the first-stage third AND gate 1412 is connected to the MSB_B, and the output end of the first-stage third AND gate 1412 outputs the first-stage high-bit weight adjustment code value a1. The first input end of the second-stage third AND gate 1412 is connected to the weight adjustment control data adj<2>, the second input end of the second-stage third AND gate 1412 is connected to the MSB_B, and the output end of the second-stage third AND gate 1412 outputs the second-stage high-bit weight adjustment code value a2.

[0078] The input end of the second NOT gate 1421 is connected to the LSB, and the output end of the second NOT gate 1421 outputs the opposite data LSB_B of the LSB. The first input end of the first-stage fourth AND gate 1422 is connected to the weight adjustment control data adj<1>, the second input end of the first-stage fourth AND gate 1422 is connected to the LSB_B, and the output end of the first-stage fourth AND gate 1422 outputs the first-stage low-bit weight code value b1. The first input end of the second-stage fourth AND gate 1422 is connected to the weight adjustment control data adj<2>, the second input end of the second-stage fourth AND gate 1422 is connected to the LSB_B, and the output end of the second-stage fourth AND gate 1422 outputs the second-stage low-bit weight adjustment code value b2.

[0079] The first input of the first stage adder 1431 is connected to MSB<7:1>, the second input of the first stage adder 1431 is connected to 0, 0, 0, 0, 0, a2, 0; the output of the first stage adder outputs D0<7:1>. The first input of the second stage adder 1431 is connected to D0<7:1>, the second input of the second stage adder 1431 is connected to 0, 0, 0, 0, 0, 0, al; the output of the second stage adder 1431 outputs msb<7:1>.

[0080] The first input of the first stage adder 1441 is connected to LSB<7>, LSB<7:1>, the second input of the first stage adder 1441 is connected to 0, 0, 0, 0, 0, b2, 0; the output of the first stage adder outputs D1<7:1>, i.e. LSB<7:1> divided by 2 and summed with 0, 0, 0, 0, 0, b2, 0 for weight adjustment. The first input of the second stage adder 1441 is connected to D1<7:1>, the second input of the second stage adder 1441 is connected to 0, 0, 0, 0, 0, 0, bl; the output of the second stage adder 1441 outputs lsb<7:1>.

[0081] The first input of the output sum module 145 is connected to msb <m:1>, the second input of the output summation module 145 is connected to the lsb <m:1>; output sum module 145 is set to add the lsb <m:1>with msb <m:1>Full adder is performed to obtain PAM4.

[0082] In combination Figure 1 and Figure 4 The working principle of the multi-level output driving circuit is described with m=7 (7-bit digital mode) and n=2 (2-bit mode).

[0083] When adj<1:0> is 00 (i.e., no adjustment is made to the eye height), the eye diagram is the same as described in the 1-bit mode.

[0084] When adj<1:0> is not 00 (i.e., adjustment is made to the eye height), the following adjustment modes can be used.

[0085] When adj<1:0> is 01, the upper and lower eye weight code values are increased by 1, and the middle eye is unchanged.

[0086] When adj<1:0> is 10, the upper and lower eye weight code values are increased by 2, and the middle eye is unchanged.

[0087] When adj<1:0> is 11, the upper and lower eye weight code values are increased by 3, and the middle eye is unchanged.

[0088] In addition, similar to the 1-bit mode, in the 2-bit mode, co<7:1>+adj<1:0><42 needs to be satisfied to avoid code value overflow.

[0089] The following is a specific analysis of the case where co<7:1> is 38.

[0090] 1) When adj<1:0> = 00; co_polar takes a positive value: 0.

[0091] The C<7:1> and CB<7:1> output by the weight generation module 120 are 0100110 (38) and 1011010 (90), respectively; the MSB<7:1> and LSB<7:1> are 90 and 38, respectively; full adder operation is performed on the MSB<7:1> (taking a value of 90 or 38) and the LSB<7:1> (taking a value of 90 or 38) to obtain 45, 83, 121 four states, and H1=38, H2=38, H3=38.

[0092] Therefore, the three eyes are equal in size, and the relative eye height is 38 code values.

[0093] 2) When adj<1:0> = 01; co_polar takes a positive value: 0.

[0094] The C<7:1> and CB<7:1> outputted by the weight generating module 120 are 0100110 (38) and 1011010 (90) respectively; the MSB<7:1> and LSB<7:1> are 90 and 38 respectively; the MSB<7:1> and LSB<7:1> are transmitted to the weight adjusting and data output module 140, the MSB after inversion is summed with adj<1> to obtain a1, the MSB after inversion is summed with adj<2> to obtain a2, the LSB after inversion is summed with adj<1> to obtain b1, and the LSB after inversion is summed with adj<2> to obtain b2.

[0095] The MSB<7:1> and 0, 0, 0, 0, 0, a2, 0 are summed to obtain DO<7:1>, the DO<7:1> and 0, 0, 0, 0, 0, 0, a1 are summed to obtain msb<7:1>, the LSB<7:1> after division by 2 and 0, 0, 0, 0, 0, b2, 0 are summed to obtain D1<7:1>, and the D1<7:1> and 0, 0, 0, 0, 0, 0, b1 are summed to obtain lsb<7:1>. The msb<7:1> and lsb<7:1> are full added to obtain 46, 84, 123 four states, and H1=39, H2=38, H3=39.

[0096] Among them, compared with adj<1:0>=00, the middle two levels (46 and 84) increase the weight by 1, and the highest level (123) increases the weight by 2, that is, the weight code value of the upper and lower eyes increases by 1, and the middle eye remains unchanged.

[0097] 3) When adj<1:0>=10; co_polar takes a positive value: 0.

[0098] The C<7:1> and CB<7:1> outputted by the weight generating module 120 are 0100110 (38) and 1011010 (90) respectively; the MSB<7:1> and LSB<7:1> are 90 and 38 respectively; the MSB<7:1> and LSB<7:1> are transmitted to the weight adjusting and data output module 140, the MSB after inversion is summed with adj<1> to obtain a1, the MSB after inversion is summed with adj<2> to obtain a2, the LSB after inversion is summed with adj<1> to obtain b1, and the LSB after inversion is summed with adj<2> to obtain b2.

[0099] MSB<7:1> and 0,0,0,0,0,a2,0 are added to get D0<7:1>, D0<7:1> and 0,0,0,0,0,0,a1 are added to get msb<7:1>, LSB<7:1> is divided by 2, and 0,0,0,0,0,b2,0 are added to get D1<7:1>, D1<7:1> and 0,0,0,0,0,0,b1 are added to get lsb<7:1>. msb<7:1> and lsb<7:1> are full added to get 47, 85, 125 four states, and H1=40, H2=38, H3=40.

[0100] Among them, compared with adj<1:0>=00, the middle two levels (47 and 85) are added by 2 in weight, and the highest level (125) is added by 4 in weight, that is, the weight code value of the upper and lower eyes is increased by 2, and the middle eye is unchanged.

[0101] 4) When adj<1:0>=11; co_polar takes value positive: 0.

[0102] C<7:1> and CB<7:1> output by the weight generation module 120 are 0100110 (38) and 1011010 (90) respectively; MSB<7:1> and LSB<7:1> are 90 and 38 respectively; MSB<7:1> and LSB<7:1> are transmitted to the weight adjustment and data output module 140, MSB is added with adj<1> after being inverted to get a1, MSB is added with adj<2> after being inverted to get a2, LSB is added with adj<1> after being inverted to get b1, and LSB is added with adj<2> after being inverted to get b2.

[0103] MSB<7:1> and 0,0,0,0,0,a2,0 are added to get D0<7:1>, D0<7:1> and 0,0,0,0,0,0,a1 are added to get msb<7:1>, LSB<7:1> and 0,0,0,0,0,b2,0 are added to get D1<7:1>, D1<7:1> and 0,0,0,0,0,0,b1 are added to get lsb<7:1>. msb<7:1> and lsb<7:1> are full added to get 48, 86, 127 four states, and H1=41, H2=38, H3=41.

[0104] Among them, compared with adj<1:0>=00, the middle two levels (48 and 86) are added by 3 in weight, and the highest level (127) is added by 6 in weight, that is, the weight code value of the upper and lower eyes is increased by 3, and the middle eye is unchanged.

[0105] Therefore, by performing an AND operation between the MSB and the control bits 0, 0, 0, 0, 0, a2, a1 with weight adjustment code value information, performing an AND operation between the LSB divided by 2 and the control bits 0, 0, 0, 0, 0, b2, b1 with weight adjustment code value information, and finally obtaining the binary data signal msb<7:1> / lsb<7:1> with weight adjustment information, performing a full add operation between lsb<7:1> and msb<7:1>, and finally outputting the MSB+1 / 2*LSB signal with weight-adjustable code value, it can be seen from the above analysis that the embodiment of the application transmits the data signal in the form of binary, and the change of transmission level corresponding to one code value is small, so that more accurate fine adjustment of the eye diagram can be achieved. The 2bits weight adjustment mode structure provided in the embodiment of the application realizes the processing of reducing the middle eye diagram and increasing the upper and lower eye diagrams.

[0106] Figure 5 is a structural schematic diagram of an output summation module provided in the embodiment of the application. Referring to Figure 5 In an embodiment, the output summation module 145 is a full adder, and the output summation module 145 includes m-level adders 1451 and a third NOT gate 1452. Taking m=7 as an example, the addend input end of the first-level adder 1451 is connected to data A<1>, the addend input end of the first-level adder 1451 is connected to data B<1>, the carry input end of the first-level adder 1451 is connected to data TIEL, the sum output end of the first-level adder 1451 outputs data S<1>, and the carry output end of the first-level adder 1451 outputs data COUT1; the addend input end of the second-level adder 1451 is connected to data A<2>, the addend input end of the second-level adder 1451 is connected to data B<2>, the carry input end of the second-level adder 1451 is connected to data COUT1, the sum output end of the second-level adder 1451 outputs data S<2>, and the carry output end of the second-level adder 1451 outputs data COUT2; …; the addend input end of the sixth-level adder 1451 is connected to data A<6>, the addend input end of the sixth-level adder 1451 is connected to data B<6>, the carry input end of the sixth-level adder 1451 is connected to data COUT5, the sum output end of the sixth-level adder 1451 outputs data S<6>, and the carry output end of the sixth-level adder 1451 outputs data COUT6; the addend input end of the seventh-level adder 1451 is connected to data A<7>, the addend input end of the seventh-level adder 1451 is connected to data B<7>, the carry input end of the seventh-level adder 1451 is connected to data COUT6, the sum output end of the seventh-level adder 1451 outputs data S_B<7>, and the carry output end of the seventh-level adder 1451 outputs data COUT7; the input end of the third NOT gate 1452 is connected to S_B<7>, and the output end of the third NOT gate 1452 outputs S<7>, that is, the high bits of the obtained 7bits binary data are inverted to obtain PAM4.

[0107] Figure 6 is a structural schematic diagram of a weight generation module provided by an embodiment of the present application. Referring to Figure 6 In an embodiment, the weight generation module 120 comprises a complement generation submodule 121 and a weight selection submodule 122. A first input end of the complement generation submodule 121 is connected to the co <m:1>, a second input end of the complement generation submodule 121 is connected to 1; an output end of the complement generation submodule 121 outputs co <m:1>complement co_b of b <m:1>The control end of the weight selection submodule 122 accesses co_polar, and the first data input end of the weight selection submodule 122 accesses co <m:1>, a second data input end of the weight selection submodule 122 accesses co_b <m:1>; a first data output terminal of the weight selection sub-module 122 outputs C <m:1>, a second data output end of the weight selection sub-module 122 outputs CB <m:1>; wherein C <m:1>For co <m:1>or co_b <m:1>; CB <m:1>co_b <m:1>or co <m:1>co_polar control C <m:1>and CB <m:1>the position relationship of the two.

[0108] With continued reference to Figure 6 In an embodiment, the complement generation submodule 121 includes a fourth NOT gate 1211 and an adder 1212; the input end of the fourth NOT gate 1211 is connected to the co <m:1>, the output end of the fourth NOT gate 1211 outputs c_b <m:1>; first input of adder 1212 connected to c_b <m:1>The second input of the adder 1212 is connected to 1. The output of the adder 1212 outputs co_b <m:1>.

[0109] The weight selection sub-module 122 includes a fifth NOT gate 1221, a selector 1222 and a selector 1223. The input end of the fifth NOT gate 1221 is connected to co_polar, and the output end of the fifth NOT gate 1221 outputs co_polar_b. The control end of the selector 1222 is connected to co_polar, the first input end of the selector 1222 is connected to co_polar_b, and the output end of the selector 1222 outputs co_polar_b1. The control end of the selector 1223 is connected to co_polar, the first input end of the selector 1223 is connected to co_polar_b, and the output end of the selector 1223 outputs co_polar_b2. <m:1>, a second input of the selector 1222 is connected to co b <m:1>, the output of the selector 1222 outputs C <m:1>; the control end of the selector 1223 accesses co_polar_b, the first input end of the selector 1222 accesses co <m:1>, a second input of the selector 1222 is connected to co_b <m:1>, the output of the selector 1222 outputs CB <m:1>.

[0110] Exemplarily, m=7, an input end of the fourth NOT gate 1211 is connected to co<7:1>, and an output end of the fourth NOT gate 1211 outputs c_b<7:1>; a first input end of the adder 1212 is connected to c_b<7:1>, a second input end of the adder 1212 is connected to 0, 0, 0, 0, 0, 0, 1, and an output end of the adder 1212 outputs co_b<7:1>. A control end of the selector 1222 is connected to co_polar, a first input end of the selector 1222 is connected to co<7:1>, a second input end of the selector 1222 is connected to co_b<7:1>, and an output end of the selector 1222 outputs C<7:1>; a control end of the selector 1223 is connected to co_polar_b, a first input end of the selector 1222 is connected to co<7:1>, a second input end of the selector 1222 is connected to co_b<7:1>, and an output end of the selector 1222 outputs CB<7:1>.

[0111] In conclusion, the embodiment of the present application adopts the digital mode of the DAC to realize the weight adjustment, sets the weight adjustment and data output module in the multi-level output driving circuit to output the MSB of the data containing the weight information <m:1> / LSB <m:1>The weight adjustment and pulse amplitude modulation calculation are performed to achieve the adjustment purpose of the generated pulse amplitude modulation data level. Compared with adjusting the eye diagram by using an analog implementation, the embodiment of the application can not only realize the processing of reducing the middle eye diagram, but also realize the processing of increasing the upper and lower eye diagrams, and can more widely cope with the eye diagram RLM misadjustment problem caused by different transmission environments. In addition, the embodiment of the application transmits the data signal in the form of binary, and the change of the transmission level corresponding to one code value is small, so that more accurate fine adjustment of the eye diagram can be realized. In addition, the operation process in the principle of the embodiment of the application does not have a requirement on the transmission rate, the power consumption is determined by the to-be-transmitted signal rate, the adjustment process does not produce additional power consumption, and the calculation demand is small.

[0112] The embodiment of the application also provides a multi-level output driving method, which is suitable for the multi-level output driving circuit provided by any embodiment of the application. Figure 7 is a flowchart of a multi-level output driving method provided by the embodiment of the application. Referring to Figure 7 , the multi-level output driving method comprises the following steps:

[0113] S110, the signal selection module controls to select the to-be-transmitted signal of the corresponding channel according to the externally input signal.

[0114] S120, the weight generation module generates weight data according to the weight of the output eye diagram.

[0115] S130, the coefficient transmission module performs weight control on the to-be-transmitted signal according to the weight data to generate data containing weight information.

[0116] S140, the weight adjustment and data output module performs weight adjustment and pulse amplitude modulation calculation according to the weight adjustment control data, the to-be-transmitted signal and the data containing weight information to generate four-level pulse amplitude modulation data PAM4.

[0117] Among them, the embodiment of the application realizes the weight adjustment by using the digital way of DAC, and sets the weight adjustment and data output module in the multi-level output driving circuit to perform weight adjustment on the data MSB <m:1> / LSB <m:1>The weight adjustment and the pulse amplitude modulation calculation are performed, and the adjustment purpose of the generated pulse amplitude modulation data level is achieved. Compared with adjusting the eye diagram by using an analog implementation manner, the embodiment of the application can not only realize the processing of reducing the middle eye diagram, but also realize the processing of increasing the upper and lower eye diagrams, and can more widely cope with the eye diagram RLM misadjustment problem caused by different transmission environments. Moreover, the embodiment of the application transmits the data signal in a binary form, wherein one code value corresponds to a small change of the transmission level, and the eye diagram can be more accurately fine-adjusted. In addition, the operation process in the principle of the embodiment of the application does not have a requirement on the transmission rate, the power consumption is determined by the to-be-transmitted signal rate, the adjustment process does not generate additional power consumption, and the calculation demand is small.

[0118] In an embodiment, the to-be-transmitted signal includes a high-bit transmission signal MSB and a low-bit transmission signal LSB; the data including the weight information includes high-bit data MSB including the weight information <m:1>and low bit data LSBs including weight information <m:1>, m is a natural number, and m > 7, to convert the MSB and the LSB into higher bit binary data, and to improve the precision of signal transmission.

[0119] In one embodiment, the weight adjustment and data output module includes: a high-bit weight adjustment module, a low-bit weight adjustment module, a high-bit summation module, a low-bit summation module, and an output summation module; the method further includes:

[0120] The high-bit weight adjustment module adjusts the MSB according to the MSB and the weight adjustment control data adj <n:1>, generate high-bit weight adjustment code value; wherein n is a positive integer;

[0121] The low-bit weight adjustment module generates the LSB according to the LSB and the weight adjustment control data adj <n:1>, to generate low bit weight adjustment code values;

[0122] The high bit summation module recombines the high bit weight adjustment code values with 0 to obtain mbits high bit weight adjustment data; and recombines the MSB <m:1>summing the high bit weight adjustment data to obtain a high bit adjustment signal msb <m:1>;

[0123] The low bit summation module recombines the low bit weight adjustment code value with 0 to obtain the mbits low bit weight adjustment data; and recombines the LSB <m:1>summing the low bit weight adjustment data to obtain a low bit adjustment signal lsb <m:1>;

[0124] The output summation module will msb <m:1>and lsb <m:1>Summing, PAM4 is obtained.

[0125] In the above embodiments, the LSB division by 2 can be in addition to the LSB division by 2 <m:1>before weight adjustment, or after the LSBs <m:1>After weight adjustment is performed, i.e. lsb <m:1>may be LSB <m:1>Data after 2, also LSB <m:1>Data not excluded 2, specific needs according to the value of n to determine.

[0126] In an embodiment, n = 1; the high bit weight adjustment module includes a first AND gate, and the low bit weight adjustment module includes a second AND gate; the method further includes:

[0127] The first AND gate logically ANDs the weight adjustment control data adj and the MSB to obtain a high bit weight adjustment code value a;

[0128] The second AND gate logically ANDs the weight adjustment control data adj and the LSB to obtain a low bit weight adjustment code value b;

[0129] The high bit summation module logically ORs the MSB <m:1>and a full adder is performed to obtain msb <m:1>;

[0130] The low bit summation module sums the LSBs <m:1>and b is full adder, lsb <m:1>;

[0131] The output summation module sums the lsbs <m:1>after 2 with msb <m:1>PAM4 is obtained by performing a full adder summation.

[0132] In one embodiment, n = 1; the high-bit weight adjustment module includes a first AND gate, and the low-bit weight adjustment module includes a second AND gate; the method further includes:

[0133] The first AND gate logically ANDs the weight adjustment control data adj and the MSB to obtain a high-bit weight adjustment code value a;

[0134] The second AND gate logically ANDs the weight adjustment control data adj and the LSB to obtain a low-bit weight adjustment code value b;

[0135] The high-bit summation module logically ORs the MSB <m:1>and a full adder is performed to obtain msb <m:1>;

[0136] The low bit summation module sums the LSBs <m:1>after 2 with b full adder summing to get lsb <m:1>;

[0137] The output summation module sums the lsbs <m:1>with msb <m:1>A full add sum is performed to obtain PAM4.

[0138] It can be seen that for n = 1, the LSB divide-by-2 can be in place of the LSB <m:1>before weight adjustment is performed, or after the LSBs <m:1>The weight adjustment is performed after this is because for binary data, the lowest bit is 1, and in 1 bit mode, even if the LSB <m:1>After the weight adjustment, the LSB is divided by 2, and the weight adjustment bit is still 1, so the weight adjustment will not be affected by the division by 2.

[0139] In an embodiment, n≥2; the high-bit weight adjustment module comprises a first NOT gate, a first third AND gate, a i-th third AND gate, and an n-th third AND gate, i is a positive integer, and 1≤i≤n; the low-bit weight adjustment module comprises a second NOT gate, a first fourth AND gate, a i-th fourth AND gate, and an n-th fourth AND gate; the method further comprises:

[0140] The first NOT gate inverts the MSB to obtain the opposite data MSB_B of the MSB;

[0141] The first third AND gate performs logical AND operation on the weight adjustment control data adj<1> and the MSB_B to obtain the first high-bit weight adjustment code value a1;

[0142] The i-th third AND gate performs logical AND operation on the weight adjustment control data adj Logical AND with MSB_B, to get the i-th level high bit weight adjustment code value ai;

[0143] The n-th level third AND gate will get the weight adjustment control data adj <n>and the MSB_B, to obtain the n-level high-bit weight adjustment code value a(n);

[0144] The second NOT gate inverts the LSB to obtain the opposite data of the LSB, LSB_B;

[0145] The first fourth AND gate performs logical and between the weight adjustment control data adj<1> and the LSB_B to obtain the first-level low-bit weight adjustment code value b1;

[0146] The i-level fourth AND gate performs logical and between the weight adjustment control data adj Logical AND with LSB_B, to get the i-th level low bit weight adjustment code value bi;

[0147] The n-th level fourth AND gate will get the weight adjustment control data adj <n>and the LSB_B to obtain the n-th stage low bit weight adjustment code value b(n);

[0148] The high bit summation module will MSB <m:1>and an,..., ai,..., a1 are summed up by full adder to get msb <m:1>;

[0149] The low bit summation module sums the LSBs <m:1>after 2 and bn,...,bi,...,bl are summed up by full adder to get lsb <m:1>;

[0150] The sixth adder will msb <m:1>and lsb <m:1>A full adder sum is performed to obtain PAM4.

[0151] The embodiment of the present application sets that when n≥2, the LSB is divided by 2 in the calculation of the LSB <m:1>The weight adjustment is performed before the LSB adjustment, so that the low bit weight adjustment code values bn,..., bi,..., b1 do not change with the LSB <m:1>The deviation caused by the high weight adjustment code values an,..., ai,..., a1 not divided by 2.

[0152] In one embodiment, the signal selection module comprises a first data selector and a second data selector; the method further comprises:

[0153] The first data selector selects the MSB according to the high-bit selection control signal to output;

[0154] The second data selector selects the LSB according to the low-bit selection control signal to output.

[0155] In one embodiment, the multi-level output driving method further comprises:

[0156] The weight generation module generates the weight data co <m:1>and a weight polarity co_polar, to determine weight data; the weight data including a maximum weight code value C <m:1>and C <m:1>complement CB <m:1>.

[0157] In an embodiment, the weight generating module comprises a complement generating submodule and a weight selecting submodule; the multi-level output driving method further comprises:

[0158] The complement generating submodule generates co <m:1>after taking the complement of 1. Perform a full add operation to obtain co <m:1>co_b (two's complement) <m:1>;

[0159] The weight selection sub-module determines the output C <m:1>For co <m:1>, output CB <m:1>co_b <m:1>; or, determining the output C <m:1>co_b <m:1>, output CB <m:1>For co <m:1>.

[0160] In one embodiment, the coefficient transfer module includes a third data selector and a fourth data selector. The multi-level output driving method further includes:

[0161] The third data selector determines the output MSB according to the MSB <m:1>For C <m:1>or CB <m:1>;

[0162] The fourth data selector determines the LSB of the output according to the LSB <m:1>For C <m:1>or CB <m:1>.

[0163] It is to be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the application. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. In a claim, the word "a" or "an" preceding the commencement of the recitation of a list of elements or steps does not exclude the presence of more than one of such element or step. It is appreciated that features of the application that are, at this time, considered to be the most preferred can evolve. Therefore, the terms "the", "this", "previous" and the like in reference to a particular feature of the application should not be interpreted as excluding the existence of other features that are identical or similar thereto. Furthermore, the words "a" and "an" shall not include the word "quasi". < / n> < / n> < / m> < / m> < / n> < / n> < / m>

Claims

1. A multi-level output driver circuit, characterized by, The application relates to a multi-level output drive circuit, comprising: a signal selection module configured to select a to-be-transmitted signal of a corresponding channel according to an externally input signal; a weight generation module configured to generate weight data according to a weight of an output eye diagram; wherein the weight of the output eye diagram and the weight data are both multi-bit binary data; a coefficient transmission module configured to perform weight control on the to-be-transmitted signal according to the weight data, and generate data containing weight information; a weight adjustment and data output module configured to perform weight adjustment and pulse amplitude modulation calculation according to weight adjustment control data, the to-be-transmitted signal and the data containing weight information, and generate four-level pulse amplitude modulation data PAM4.

2. The multi-level output driver circuit of claim 1, wherein, The to-be-transmitted signal comprises high-bit transmission signals MSB and low-bit transmission signals LSB; The data including the weight information includes high bit data MSB including the weight information <m:1>and low bit data LSBs including weight information <m:1>m is a natural number, and m >= 7.

3. The multi-level output driver circuit of claim 2, wherein, The weight adjustment and data output module comprises: a high weight adjustment module configured to adjust the weight of the MSB according to the MSB and the weight adjustment control data adj <n:1>a high-bit weight adjustment module configured to generate a high-bit weight adjustment code value; wherein n is a positive integer; a low bit weight adjustment module configured to adjust the weight of the LSB according to the LSB and the weight adjustment control data adj <n:1>a low-bit weight adjustment module configured to generate a low-bit weight adjustment code value; a high-bit summation module configured to recombine the high-bit weight adjustment code value with 0 to obtain m bits high-bit weight adjustment data; and to recombine the MSB <m:1>summing the high bit weight adjustment data to obtain a high bit adjustment signal msb <m:1> ；< / m:1> a low bit summation module configured to recombine the low bit weight adjustment code value with 0 to obtain m bits low bit weight adjustment data; and to recombine the LSB <m:1>summing the low bit weight adjustment data to obtain a low bit adjustment signal lsb <m:1> ；< / m:1> an output summation module configured to sum the msb <m:1>and the lsb <m:1>a summing module configured to obtain the PAM4 through full-addition summation.

4. The multi-level output driver circuit of claim 3, wherein, n＝1； The high-bit weight adjustment module comprises a first AND gate, a first input end of the first AND gate is connected to weight adjustment control data adj, a second input end of the first AND gate is connected to the MSB, and an output end of the first AND gate outputs a high-bit weight adjustment code value a. The low-bit weight adjustment module comprises a second AND gate, a first input end of the second AND gate is connected to weight adjustment control data adj, a second input end of the second AND gate is connected to the LSB, and an output end of the second AND gate outputs a low-bit weight adjustment code value b.

5. The multi-level output drive circuit according to claim 4, wherein: a first input of the high-bit summation module is connected to the MSB <m:1>, a second input of the high bit sum module is connected to an output of the high bit sum module outputs the msb <m:1> ；< / m:1> a first input of the low bit sum module is connected to the LSB <m:1>, a second input of the low sum module is connected to an output of the low sum module outputs the lsbs <m:1> ；< / m:1> a first input of the output summation module is connected to the msb <m:1>, a second input of the output summing module is connected to the lsb <m:1>, the output summing module is configured to sum the lsbs <m:1>after 2 with the msb <m:1>a summing module configured to obtain the PAM4 through full-addition summation.

6. The multi-level output drive circuit according to claim 4, wherein: a first input of the high-bit summation module is connected to the MSB <m:1>, a second input of the high bit sum module is connected to an output of the high bit sum module outputs the msb <m:1> ；< / m:1> a first input of the low bit sum module is connected to the LSB <m>, LSB <m:1>, a second input of the low sum module is connected to The low sum module is configured to sum the LSB <m:1>after 2 and summed, at an output of the low sum module, the lsbs <m:1> ；< / m:1> < / m> a first input of the output summation module is connected to the msb <m:1>, a second input of the output summing module is connected to the lsb <m:1>, the output summing module is configured to sum the lsbs <m:1>with the msb <m:1>a summing module configured to obtain the PAM4 through full-addition summation.

7. The multi-level output driver circuit of claim 3, wherein, n≥2； The high-bit weight adjustment module comprises: a first NOT gate, an input end of the first NOT gate is connected to the MSB, and an output end of the first NOT gate outputs opposite data MSB_B of the MSB; a first-stage third AND gate, a first input end of the first-stage third AND gate is connected to the weight adjustment control data adj<1>, a second input end of the first-stage third AND gate is connected to the MSB_B, and an output end of the first-stage third AND gate outputs a first-stage high-bit weight adjustment code value a1; a first input of the i-th stage third AND gate is connected to the weight adjustment control data adj a i-stage third AND gate, a second input end of the i-stage third AND gate is connected to the MSB_B, and an output end of the i-stage third AND gate outputs an i-stage high-bit weight adjustment code value ai; wherein i is a positive integer, and 1 <= i <= n; an nth stage third AND gate, a first input terminal of the nth stage third AND gate being connected to the weight adjustment control data adj <n>a n-stage third AND gate, a second input end of the n-stage third AND gate is connected to the MSB_B, and an output end of the n-stage third AND gate outputs an n-stage high-bit weight adjustment code value a(n).< / n> The low-bit weight adjustment module comprises: a second NOT gate, an input end of the second NOT gate is connected to the LSB, and an output end of the second NOT gate outputs opposite data LSB_B of the LSB; a first input end of the first fourth AND gate is connected to the weight adjustment control data adj<1>, a second input end of the first fourth AND gate is connected to the LSB_B, and an output end of the first fourth AND gate outputs a first low bit weight adjustment code value b1; a fourth AND gate of stage i, a first input terminal of the fourth AND gate of stage i being connected to the weight adjustment control data adj a second input end of the i-th fourth AND gate is connected to the LSB_B, and an output end of the i-th fourth AND gate outputs an i-th low bit weight adjustment code value bi; wherein i is a positive integer, and 1≤i≤n; an nth stage fourth AND gate, a first input terminal of the nth stage fourth AND gate being connected to the weight adjustment control data adj <n>a second input end of the n-th fourth AND gate is connected to the LSB_B, and an output end of the n-th fourth AND gate outputs an n-th low bit weight adjustment code value b(n).< / n> 8. The multi-level output driving circuit according to claim 7, wherein, a first input of the high-bit summation module is connected to the MSB <m:1>, a second input of the high bit sum module is connected to an output of the high bit sum module outputs the msb <m:1> ；< / m:1> The first input terminal of the low bit summation module is connected to the LSB <m>, LSB <m:1>, a second input of the low sum module is connected to The low sum module is configured to sum the LSB <m:1>after 2 and summed, at an output of the low-bit summation module, the lsbs <m:1> ；< / m:1> < / m> a first input of the output summation module is connected to the msb <m:1>, a second input of the output sum module is connected to the lsb <m:1>; the output sum module is configured to sum the lsbs <m:1>with the msb <m:1>full adder summation is performed to obtain the PAM4.

9. The multi-level output driver circuit of claim 2, wherein, The signal selection module comprises: a first data selector, a control end of the first data selector is connected to a high bit selection control signal, a first data input end of the first data selector is connected to the MSB, a second data input end of the first data selector is connected to the LSB, and an output end of the first data selector outputs the MSB; a second data selector, a control end of the second data selector is connected to a low bit selection control signal, a first data input end of the second data selector is connected to the MSB, a second data input end of the second data selector is connected to the LSB, and an output end of the second data selector outputs the LSB.

10. The multi-level output driver circuit of claim 2, wherein, The weight generating module is configured to generate the initial weight data co <m:1>and a weight polarity co_polar, determining the weight data; the weight data including a maximum weight code value C <m:1>and said C <m:1>complement CB <m:1> 。< / m:1> 11. The multi-level output driver circuit of claim 10, wherein, The weight generation module comprises: a complement generation submodule, a first input terminal of the complement generation submodule being connected to the co <m:1>The second input end of the complement generation submodule is connected to the output end of the first input selection submodule The output end of the complement generation submodule outputs the co <m:1>co_b (two's complement) <m:1> ；< / m:1> The weight selection sub-module has a control end connected to the co_polar and a first data input end connected to the co_polar. <m:1>, a second data input end of the weight selection submodule is connected to the co_b <m:1>; the first data output terminal of the weight selection sub-module outputs the C <m:1>, a second data output terminal of the weight selection sub-module outputs the CB <m:1>; wherein the C <m:1>for the co <m:1>or the co_b <m:1>; the CB <m:1>co_b <m:1>or the co <m:1> 。< / m:1> 12. The multi-level output driver circuit of claim 10, wherein, The coefficient transfer module comprises: a third data selector, a control terminal of the third data selector accessing the MSB, a first data input terminal of the third data selector accessing the C <m:1>, a second data input of the third data selector is connected to the CB <m:1>; the output of the third data selector outputs the MSB <m:1>; wherein the MSB <m:1>For the C <m:1>or the CB <m:1> ；< / m:1> a fourth data selector, a control terminal of the fourth data selector accessing the LSB, a first data input terminal of the fourth data selector accessing the C <m:1>, a second data input of the fourth data selector is connected to the CB <m:1>; an output of the fourth data selector outputs the LSB <m:1>; wherein the LSB <m:1>For the C <m:1>or the CB <m:1> 。< / m:1> 13. A method of driving a multi-level output, characterized by, The method is applied to the signal selection module, the weight generation module, the coefficient transfer module, and the weight adjustment and data output module; the method comprises: The signal selection module controls selection of output of a to-be-transmitted signal of a corresponding channel according to an externally input signal; The weight generation module generates weight data according to a weight of an output eye diagram; wherein the weight of the output eye diagram and the weight data are both multi-bit binary data; The coefficient transfer module controls the to-be-transmitted signal according to the weight data to generate data containing weight information; The weight adjustment and data output module performs weight adjustment and pulse amplitude modulation calculation according to weight adjustment control data, the to-be-transmitted signal, and the data containing weight information to generate four-level pulse amplitude modulation data PAM4.

14. The multi-level output driving method according to claim 13, wherein the to-be-transmitted signal comprises a high bit transmission signal MSB and a low bit transmission signal LSB; The data including the weight information includes high bit data MSB including the weight information <m:1>and low bit data LSBs including weight information <m:1>m is a natural number, and m≥7.

15. The multi-level output driving method according to claim 14, wherein The weight adjustment and data output module comprises a high bit weight adjustment module, a low bit weight adjustment module, a high bit summation module, a low bit summation module, and an output summation module; the method further comprises: The high weight adjustment module adjusts the MSB according to the weight adjustment control data adj <n:1>generating a high bit weight adjustment code value; wherein n is a positive integer; The low bit weight adjustment module adjusts the weight of the LSB according to the LSB and the weight adjustment control data adj <n:1>generating a low bit weight adjustment code value; The high-bit summation module recombines the high-bit weight adjustment code value with 0 to obtain m bits high-bit weight adjustment data; and the MSB <m:1>summing the high bit weight adjustment data to obtain a high bit adjustment signal msb <m:1> ；< / m:1> The low-bit summation module reorganizes the low-bit weight adjustment code value and 0 to obtain m bits low-bit weight adjustment data; and reorganizes the LSB <m:1>summing the low bit weight adjustment data to obtain a low bit adjustment signal lsb <m:1> ；< / m:1> The output summation module sums the msb <m:1>and the lsb <m:1>summing to obtain the PAM4.

16. The multi-level output driving method according to claim 15, wherein n=1; the high bit weight adjustment module comprises a first AND gate, the low bit weight adjustment module comprises a second AND gate; the method further comprises: The first AND gate performs logical AND operation on the weight adjustment control data adj and the MSB to obtain the high-bit weight adjustment code value a. The second AND gate performs logical AND operation on the weight adjustment control data adj and the LSB to obtain the low-bit weight adjustment code value b. The high-bit summation module will sum the MSBs <m:1>and a full adder sum is performed to obtain the msb <m:1> ；< / m:1> The low bit summation module will sum the LSBs <m:1>and performing a full add sum to obtain the lsb <m:1> ；< / m:1> The output summation module sums the lsbs <m:1>after 2 with the msb <m:1>Full adder is performed to obtain the PAM4.< / m:1> 17. The multi-level output driving method according to claim 15, wherein n=1; the high-bit weight adjustment module includes a first AND gate, and the low-bit weight adjustment module includes a second AND gate; the method further includes: The first AND gate performs logical AND operation on the weight adjustment control data adj and the MSB to obtain the high-bit weight adjustment code value a. The second AND gate performs logical AND operation on the weight adjustment control data adj and the LSB to obtain the low-bit weight adjustment code value b. The high-bit summation module will sum the MSB <m:1>and a full adder sum is performed to obtain the msb <m:1> ；< / m:1> The low bit summation module will sum the LSBs <m:1>after 2 and performing a full add sum to obtain the lsb <m:1> ；< / m:1> The output summation module sums the lsbs <m:1>with the msb <m:1>Full adder is performed to obtain the PAM4.< / m:1> 18. The multi-level output driving method of claim 15, wherein, n≥2; the high-bit weight adjustment module includes a first NOT gate, a first third AND gate, an i-th third AND gate, and an n-th third AND gate, i is a positive integer, and 1≤i≤n; the low-bit weight adjustment module includes a second NOT gate, a first fourth AND gate, an i-th fourth AND gate, and an n-th fourth AND gate; the method further includes: The first NOT gate inverts the MSB to obtain the opposite data MSB_B of the MSB. The first third AND gate performs logical AND operation on the weight adjustment control data adj<1> and the MSB_B to obtain a first high-bit weight adjustment code value a1. the i-th stage third AND gate receives the weight adjustment control data adj The i-th third AND gate performs logical AND operation on the weight adjustment control data adj and the MSB_B to obtain an i-th high-bit weight adjustment code value ai. the nth stage third AND gate receives the weight adjustment control data adj <n>The n-th third AND gate performs logical AND operation on the weight adjustment control data adj<n> and the MSB_B to obtain an n-th high-bit weight adjustment code value a(n).< / n> The second NOT gate inverts the LSB to obtain the opposite data LSB_B of the LSB. The first fourth AND gate performs logical AND operation on the weight adjustment control data adj<1> and the LSB_B to obtain a first low-bit weight adjustment code value b1. the i-th stage fourth AND gate receives the weight adjustment control data adj The i-th fourth AND gate performs logical AND operation on the weight adjustment control data adj and the LSB_B to obtain an i-th low-bit weight adjustment code value bi. the nth stage fourth AND gate receives the weight adjustment control data adj <n>The n-th fourth AND gate performs logical AND operation on the weight adjustment control data adj<n> and the LSB_B to obtain an n-th low-bit weight adjustment code value b(n).< / n> The high-bit summation module will sum the MSB <m:1>and a full adder sum is performed to obtain the msb <m:1> ；< / m:1> The low bit summation module will sum the LSBs <m:1>after 2 and performing a full add sum to obtain the lsb <m:1> ；< / m:1> The output summation module sums the msb <m:1>and the lsb <m:1>Full adder is performed to obtain the PAM4.< / m:1> 19. The method of claim 14, wherein, The signal selection module includes a first data selector and a second data selector; the method further includes: The first data selector selects the MSB to be output according to a high-bit selection control signal. The second data selector selects the LSB to be output according to a low-bit selection control signal.

20. The method of claim 14, wherein, Further includes: The weight generation module generates the initial weight data co according to the initial weight data co <m:1>and a weight polarity co_polar, determining the weight data; the weight data including a maximum weight code value C <m:1>and said C <m:1>complement CB <m:1> 。< / m:1> 21. The multi-level output driving method according to claim 20, wherein The weight generation module includes a complement generation sub-module and a weight selection sub-module; the method further includes: The complement generation submodule generates the co <m:1>after negation and performing a full add operation to obtain the co <m:1>co_b (two's complement) <m:1> ；< / m:1> The weight selection sub-module determines the C <m:1>for the co <m:1>, the CB <m:1>co_b <m:1>; or, determining the C <m:1>co_b <m:1>, the CB <m:1>for the co <m:1> 。< / m:1> 22. The multi-level output driving method of claim 20, wherein The coefficient transfer module includes a third data selector and a fourth data selector; the method further includes: The third data selector determines the MSB of the output according to the MSB <m:1>For the C <m:1>or the CB <m:1> ；< / m:1> the fourth data selector determines the LSB of the output according to the LSB <m:1>For the C <m:1>or the CB <m:1> 。< / m:1>

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