HIGH-SPEED RECEIVER

Abstract

Device comprising the following: a first set of amplitude filters (210A) comprising input terminals for receiving a first input signal, wherein the first set of amplitude filters (210A) is configured to generate a first amplitude filter output signal comprising outputs of the first set of amplitude filters (210A), wherein the first amplitude filter output signal digitally indicates a level of the first input signal; a first speculative tap (220A) which includes input terminals coupled to output terminals of the first set of amplitude sieves (210A) for receiving the first amplitude sieve output signal, control terminals for receiving an output of a second speculative tap (220B) and output terminals for outputting an output of the first speculative tap (220A), wherein the first speculative tap (220A) is configured to select outputs of a subset of the first set of amplitude sieves (210A) based on the output of the second speculative tap (220B) received at the control terminals; a first decoder (230A) comprising input terminals coupled to the output terminals of the first speculative tap (220A), wherein the first decoder (230A) is configured to decode the selected outputs of the subset of the first set of amplitude sieves (210A), present in a first digital representation, into a second digital representation; and a first feedback generator comprising the following: Input terminals coupled to the output terminals of the first decoder (230A) and Output terminals coupled to the input terminals of the first set of amplitude filters (210A), wherein the first feedback generator is configured to generate a first feedback signal according to the decoded outputs of the subset of the first set of amplitude filters (210A) and outputs the first feedback signal at its output terminals.

Description

[0001] This disclosure relates generally to systems and methods for communication processes. In particular, this disclosure relates to systems and methods for improving the communication speed of a receiver based on a pulse-amplitude modulated signal.

[0002] The proliferation of communication technology enables multiple devices to communicate with each other. For example, two computer devices exchange content data (such as text, images, video, etc.). In one approach, content data is exchanged in an encoded format to improve bandwidth. For example, a sender encodes content data according to a pulse amplitude modulation (PAM) protocol and transmits the encoded data. A PAM protocol represents a data value according to the amplitude of a pulse. For example, a pulse amplitude of 100 mV represents a logical value '0', a pulse amplitude of 200 mV represents a logical value '1', a pulse amplitude of 300 mV represents a logical value '2', and a pulse amplitude of 400 mV represents a logical value '3'. Accordingly, a single pulse can transmit multiple bits of information, thereby improving communication bandwidth.

[0003] Communication via a PAM protocol presents challenges for receiver design. For example, a receiver detects the amplitude of a pulse of received data and decodes the received data to obtain content data. Sampling the amplitude of high-speed data (for example, over 50 Gbit / s) and decoding the data according to the sampled amplitude is a complex and challenging process. For instance, a signal received by the receiver is subject to distortion due to intersymbol interference (ISI). Specifically, energy in one symbol of a signal spreads to the adjacent symbol. In some implementations, the receiver incorporates circuitry to compensate for such distortion.However, the circuit arrangements used to compensate for the distortion caused by ISI reduce the performance (e.g., speed) of the receiver and consume additional hardware resources.

[0004] US 2016 / 261435 A1 describes a device comprising: a variable gain amplifier; a set of samplers for sampling data output by the amplifier according to a clock signal; and a clock data recovery circuit to adjust the phase of the clock signal such that the magnitude of a first post-cursor signal associated with the sampled data is substantially half the magnitude of a primary cursor tap associated with the sampled data.

[0005] In accordance with the present invention, a device with the features of claim 1 and a device with the features of claim 9 are provided. Advantageous embodiments are described in the dependent claims.

[0006] The first speculative take should expedite to include the following: a first set of multiplexers comprising input terminals coupled to output terminals of the first set of amplitude sieves, and a first set of latches comprising input terminals coupled to output terminals of the first set of multiplexers.

[0007] Conveniently, the first speculative tap does not include a decoder between the first set of multiplexers and the first set of latches.

[0008] The device should also expeditely include the following: a second set of amplitude filters comprising input terminals for receiving a second input signal, wherein the second set of amplitude filters is configured to generate the second amplitude filter output signal comprising outputs of the second set of amplitude filters, wherein the second amplitude filter output signal digitally indicates a level of the second input signal; a second speculative tap comprising input terminals coupled to output terminals of the second set of amplitude sieves, wherein the second speculative tap is configured to select outputs of a subset of the second set of amplitude sieves based on the first amplitude sieve output signal; a second decoder comprising input terminals coupled to output terminals of the second speculative tap, wherein the second decoder is configured to decode the selected outputs of the subset of the second set of amplitude sieves present in the first digital representation into the second digital representation; and a second feedback generator, comprising the following: Input terminals coupled with output terminals of the second decoder and Output terminals coupled to the input terminals of the second set of amplitude filters, wherein the second feedback generator is configured to generate a second feedback signal according to the decoded outputs of the subset of the second set of amplitude filters and outputs the second feedback signal at its output terminals.

[0009] Appropriately The first speculative tap is configured to select the outputs of the subset of the first set of amplitude sieves according to the selected outputs of the subset of the second set of amplitude sieves, and wherein the second speculative tap is configured to select the outputs of the subset of the second set of amplitude sieves according to the selected outputs of the subset of the first set of amplitude sieves.

[0010] The second speculative approach should expedite to include the following: a second set of multiplexers comprising input terminals coupled to output terminals of the second set of amplitude sieves, and a second set of latches comprising input terminals coupled to the output terminals of the second set of multiplexers.

[0011] Conveniently, the output terminals of the first set of multiplexers are directly coupled to the input terminals of the first set of latches, and wherein the output terminals of the second set of multiplexers are directly coupled to the input terminals of the second set of latches.

[0012] Conveniently, the output terminals of the first set of latches are directly coupled to the control terminals of the second set of multiplexers, and where the output terminals of the second set of latches are directly coupled to the control terminals of the first set of multiplexers.

[0013] Conveniently, each multiplexer of the first set of multiplexers is controlled by latches according to the outputs of the second set, and where each multiplexer of the second set of multiplexers is controlled by latches according to the outputs of the first set.

[0014] Conveniently, the first set of latches is clocked according to a clock signal, and where the second set of latches is clocked according to an inversion of the clock signal.

[0015] The device should also include, expediently, a first feedback tap, which includes the following: Input terminals coupled to the output terminals of the first decoder and Output terminals coupled to the input terminals of the second set of amplitude filters, wherein the first feedback tap is configured to generate a third feedback signal according to the decoded outputs of the subset of the first set of amplitude filters and outputs the third feedback signal at its output terminals, the third feedback signal being intended to modify the second input signal; and a second feedback tap, which includes the following: Input terminals coupled to the output terminals of the second decoder and Output terminals coupled to the input terminals of the second set of amplitude filters, wherein the second feedback tap is configured to generate a fourth feedback signal according to the decoded outputs of the subset of the second set of amplitude filters and outputs the fourth feedback signal at its output terminals, wherein the fourth feedback signal is intended to modify the first input signal.

[0016] Ideally, the first feedback generator includes the following: a single-ended-to-differential signal converter comprising the following: an input terminal coupled to a corresponding output terminal from the output terminals of the first decoder and Differential output terminals, wherein the single-ended-to-differential signal converter is configured to convert a single-ended signal at the input terminal of the single-ended-to-differential signal converter into differential signals and outputs the differential signals via the differential output terminals, wherein the differential signals are intended to modify the first input signal.

[0017] The first feedback generator conveniently also includes the following: A crossing point control unit coupled to the input terminal of the single-ended-to-differential signal converter and a control point of the single-ended-to-differential signal converter, wherein the crossing point control unit is configured to delay one from a pull-up or pull-down operation of a first signal from the differential signals without delaying the other from the pull-up or pull-down operation of the first signal.

[0018] The device should also expeditely include the following: a pull-up transistor coupled between one of the differential output terminals and the other of the differential output terminals.

[0019] A single-ended to differential signal converter conveniently includes the following: a P-transistor and an N-transistor connected in parallel between the input terminal of the single-ended-to-differential signal converter and one of the differential output terminals, wherein a gate electrode of the P-transistor is coupled to an output terminal of the crossover control unit and a gate electrode of the N-transistor is coupled to a supply terminal to which a supply voltage is supplied.

[0020] Advantageously, the first speculative tap includes a multiplexer to select one of the selected outputs of the subset of the first set of amplitude sieves according to a redundant number of bits of the second amplitude sieve output signal.

[0021] A single-ended to differential signal converter conveniently includes the following: a first transistor with a gate electrode controlled by the intersection point control unit and a second transistor with a gate electrode coupled to a supply terminal to which a supply voltage is supplied, wherein the first transistor and the second transistor are connected in parallel to each other.

[0022] The device is expediently a feedback tap. Brief description of the drawings

[0023] The various tasks, forms, features, and advantages of the disclosure become even clearer when viewed in conjunction with the detailed description and the accompanying drawings, in which identical reference symbols consistently denote corresponding elements. In the drawings, identical reference symbols generally indicate identical, functionally similar, and / or structurally similar elements. Fig. Figure 1 is a diagram illustrating an exemplary communication environment; Fig. Figure 2 is a diagram illustrating an exemplary receiver device; Fig. Figure 3 is a diagram illustrating exemplary PAM4 signals; Fig. Figure 4 is a diagram that depicts a set of amplitude sieves; Fig. Figure 5 is a diagram illustrating an example amplitude sieve; Fig.Figure 6 is a diagram illustrating an exemplary circuit of the first stage of a comparator; Fig. Figure 7 is a diagram illustrating an example sampling circuit; Fig. Figure 8 is a diagram illustrating an example regeneration circuit; Fig. Figure 9A is a timing diagram illustrating an example of the operation of a comparator; Fig. Figure 9B is a timing diagram illustrating an example of the operation of an SR latch; Fig. 9C is an eye diagram without a beat kickback compensation; Fig. 9D is an eye diagram with a beat-kickback balance; Fig. Figure 10 is a flowchart illustrating an exemplary process of sampling an input signal with clock kickback compensation; Fig. Figure 11 is a diagram illustrating an example of a speculative tap using a decoder; Fig. Figure 12 is a diagram illustrating an exemplary speculative take; Fig. Figure 13 is a diagram illustrating an example multiplexer; Fig. Figure 14 is a flowchart that illustrates an example of the operation of a receiver; Fig. Figure 15 is a diagram illustrating an example of a feedback tap; Fig. Figure 16 is a timing diagram showing an exemplary operation of the feedback tap of Fig. 15 depicts; Fig. Figure 17 is a diagram illustrating an exemplary feedback tap with an intersection point control unit; Fig. Figure 18 is a timing diagram showing an exemplary operation of the feedback tap of Fig. 17 depicts; Fig. Figure 19 is a flowchart illustrating an example of converting a single-ended signal into differential signals; Fig. Figure 20A is a block diagram illustrating an embodiment of a network environment with one or more network devices that communicate with one or more devices or stations; and Fig. 20B and Fig. Section 20C are block diagrams illustrating exemplary implementations of computer devices that are useful in conjunction with the methods and systems described in this document.

[0024] The details of various embodiments of the methods and systems are set out in the accompanying drawings and in the following description. Detailed description

[0025] The following descriptions from the sections of the specification and their respective contents may be helpful for reading the description of the various embodiments mentioned below: - Section A describes examples of a high-speed receiver; and - Section B describes a network environment and a computer environment that may be helpful for the practical implementation of the examples described in this document. A. High-speed receiver

[0026] The disclosure in the present document relates to various manifestations of systems (or devices), methods and non-volatile, computer-readable media for high-speed communication.

[0027] In one embodiment, a system comprises a set of amplitude filters configured to generate an amplitude filter output signal that digitally indicates the level of an input signal received by the set of amplitude filters. In some embodiments, the system comprises a speculative tap coupled to the set of amplitude filters, the speculative tap being configured to select bits of the amplitude filter output signal based on selected bits of a previous amplitude filter output signal. In some embodiments, the system comprises a decoder coupled to the speculative tap, the decoder being configured to decode the selected bits of the amplitude filter output signal, present in a first digital representation, into a second digital representation.In some embodiments, the system includes a feedback generator coupled to the decoder, the feedback generator being configured to generate a feedback signal according to the decoded bits of the amplitude filter output signal. In one embodiment, the feedback signal modifies a subsequent symbol of the input signal to reduce the distortion caused by the ISI.

[0028] Advantageously, in some embodiments, the operating speed of the system is improved by selecting bits of the amplitude-seal output signal based on selected bits of a previous amplitude-seal output signal. In one embodiment, a previous amplitude-seal output signal precedes the amplitude-seal output signal by one or more symbols. In some embodiments, the selected bits of the previous amplitude-seal output signal are received from the speculative tap coupled to the set of amplitude-seals or from another speculative tap coupled to another set of amplitude-seals.In some embodiments, the first set of amplitude filters is operated according to a clock signal, while the second set of amplitude filters is operated according to a clock signal that is 90 degrees out of phase or 180 degrees out of phase. Selecting bits of the amplitude filter output signal based on a previous amplitude filter output signal, rather than a decoded output from the set of amplitude filters, reduces a critical path delay of the set of amplitude filters in some embodiments, thus improving the system's operating speed.

[0029] In one embodiment, the speculative tap exploits the redundancy of bits in a control signal (or the earlier amplitude-separator output signal) to reduce a critical path delay. In some embodiments, the speculative tap includes a multiplexer that selects from a number of bits in the amplitude-separator output signal that is less than the total number of distinct values ​​that can be represented by the control signal (or the earlier amplitude-separator output signal). For example, the speculative tap includes a 4:1 multiplexer operating according to a 3-bit control signal that has eight distinct representable values.Although a 2-bit control signal is sufficient to control a 4:1 multiplexer by exploiting the redundancy of the control signal, in some embodiments the speculative tap is operated without a decoder between the speculative tap and a component (for example, the speculative tap or another speculative tap) that generates the control signal to reduce the critical path delay.

[0030] In one implementation, the speculative tap is controlled and outputs data in a differential representation to improve operating speed. In some embodiments, the speculative tap selects bits of the amplitude filter output signal based on selected bits of a previous amplitude filter output signal in a differential representation. Accordingly, any delay associated with generating an inverted signal of the amplitude filter output is eliminated, thus reducing a critical path delay of the set of amplitude filters.

[0031] In one embodiment, each amplitude filter includes an improved comparator with clock kickback compensation. In some embodiments, a comparator compares an input signal at an input terminal with a reference signal at a reference terminal according to a pulse of a clock signal, and it generates an output signal that indicates a level of the input signal according to the comparison. In some embodiments, the comparator includes, or is coupled to, a kickback suppression circuit that injects a delayed clock signal into the input terminal. In one embodiment, the delayed clock signal is delayed relative to the clock signal.Without a kickback suppression circuit, a pulse from a clock signal degrades the input signal, the output signal, or a combination of both in some embodiments of the comparator, for example, via parasitic coupling. By employing the kickback suppression circuit, which injects the delayed clock signal into the input terminal, the degradation caused by the parasitic coupling of the clock signal pulse is mitigated. Consequently, the comparator's sensitivity is improved in some embodiments. In one embodiment, the comparator's sensitivity corresponds to the smallest input amplitude that ensures reliable operation of an amplitude filter.

[0032] In one embodiment, each amplitude filter includes an improved SR latch coupled to the comparator. In some embodiments, the SR latch comprises a sampling circuit and a regeneration circuit. In some embodiments, the sampling circuit samples the comparator's output signal according to the pulse of the clock signal, and the regeneration circuit amplifies the sampled signal coming from the sampling circuit. In one embodiment, the SR latch is implemented as a CMOS (complementary metal oxide semiconductor) circuit arrangement, which performs faster sampling and amplification with reduced hardware resources (e.g., chip area) than conventional circuit arrangements (e.g., CMOS NOR circuit arrangements).

[0033] Although many embodiments disclosed in this document are described with regard to the PAM4 protocol, the general principles disclosed in this document can be applied to any communication protocol.

[0034] With reference to Fig. Figure 1 is a diagram illustrating an exemplary communication environment 100. In Fig.In Figure 1, the communication environment 100 comprises a communication device 110A and a communication device 110B, which are communicatively coupled to each other via a network 115. In some embodiments, the network 115 is a wired network, a wireless network, or a combination of the wired and wireless networks. In some embodiments, these components communicate with each other via the network 115 to exchange content data (for example, text, images, video, etc.). In some embodiments, the communication environment 100 comprises any number of communication devices 110.

[0035] In some embodiments, the communication device 110A comprises a transmitter 120 (also referred to in this document as "a transmitter circuit 120"), and the communication device 110B comprises a receiver 130 (also referred to in this document as "a receiver circuit 130"). In some embodiments, the transmitter 120 encodes content data according to a PAM protocol and transmits the content data over the network 115. In some embodiments, the receiver 130 receives the encoded data from the transmitter 120 of another communication device 110 and decodes the received data to obtain the content data.

[0036] With reference to Fig. Figure 2 is a schematic diagram illustrating an exemplary receiver device 200. In some embodiments, the receiver device 200 is designated as the receiver 130 of Fig.1 implemented. In some embodiments, the receiver device 200 comprises the amplitude filters 210A, 210B (also referred to in this document as "amplitude filter circuits 210"), the speculative taps 220A, 220B (also referred to in this document as "speculative tap circuits 220"), the decoders 230A, 230B (also referred to in this document as "decoder circuits 230"), the feedback generators 240A, 240B (also referred to in this document as "feedback generator circuits 240"), and the adders 270A, 270B. These components are operated together to receive an input signal 202 and generate the decoded signals 235A, 235B according to the input signal 202. In some embodiments, the input signal 202 is a PAM4 signal from another device (for example, the communication device 110).In some embodiments, the receiver device comprises 200 more, fewer, or different components than in . Fig. 2 shown.

[0037] In some embodiments, the receiver device 200 performs decision-feedback equalization. In one approach, the input signal 202 is modified by the feedback signals 242A, 245A, 242B, 245B from the feedback generators 240A, 240B. In some embodiments, the adder 270A receives the input signal 202 and the feedback signals 242A, 245B, and adds the feedback signals 242A, 245B to the input signal 202 to obtain a modified input signal 205A. In some embodiments, the adder 270B receives the input signal 202 and the feedback signals 242B, 245A, and adds the feedback signals 242B, 245A to the input signal 202 to obtain a modified input signal 205B. Without the feedback signals 242A, 245A, 242B, 245B, the input signal 202 received by the receiver device 200 is subject to distortion due to intersymbol interference (ISI).For example, energy in a previous symbol of the input signal 202 spreads to a subsequent symbol. In some embodiments, distortions due to a previous symbol of the input signal are predicted, and equalization is applied to a subsequent symbol of the input signal 202 according to the predicted distortions in order to obtain the modified input signals 205A, 205B with reduced distortions.

[0038] An amplitude filter set 210A is a circuit that receives the modified input signal 205A and generates an amplitude filter output signal 215A that indicates a level of the modified input signal 205A. In one configuration, the amplitude filter set 210A includes input terminals, a clock terminal, and output terminals. In this configuration, the amplitude filter set 210A receives the modified input signal 205A at the input terminals and a clock signal CLK at the clock terminal. In some embodiments, the amplitude filter set 210A generates the amplitude filter output signal 215A according to a pulse of the clock signal CLK and outputs the amplitude filter output signal 215A at the output terminals. In one example, the set of amplitude filters 210A, in response to a rising edge, a falling edge, a state "High" (or logical '1') or a state "Low" (orThe logic '0') of the clock signal CLK, the modified input signal 205A, and generates the amplitude filter output signal 215A, which indicates a voltage level of the sampled signal in a thermometer code. For example, the amplitude filter output signal 215A indicates the voltage level of the sampled signal in the form of 12 bits, because in a tap-type ISI, a PAM4 signal can assume one of twelve levels, as shown, for example, below with regard to . Fig. 3 is described. The set of amplitude filters 210A provides the speculative tap 220A with the amplitude filter output signal 215A. Detailed implementations and operations of the amplitude filters 210 are described below with regard to Fig. 2 to Fig. 10 described.

[0039] A speculative tap 220A is a circuit that receives the amplitude filter output signal 215A and selects bits from the amplitude filter output signal 215A. In one configuration, the speculative tap 220A comprises i) input terminals coupled to the output terminals of the set of amplitude filters 210A, ii) control terminals coupled to the output terminals of the speculative tap 220B, iii) a clock terminal, and iv) output terminals. In this configuration, the speculative tap 220A receives the amplitude filter output signal 215A at its input terminals, receives outputs from the speculative tap 220B at its control terminals, and receives the clock signal CLK at its clock terminal.In some embodiments, the speculative tap 220A selects outputs from a subset of the set of amplitude filters 210A, or it selects bits of the amplitude filter output signal 215A at the control terminals according to an output signal of the speculative tap 225B coming from the speculative tap 220B, and it outputs the selected outputs as the output signal of the speculative tap 225A at the output terminals. In one example, the amplitude filter output signal has twelve bits, and the output signal of the speculative tap 225A has three bits. In some embodiments, the speculative tap 220A, in response to a pulse of the clock signal CLK, stores the selected bits of the amplitude filter output signal 215A and makes the stored bits available to the decoder 230A and the speculative tap 220B.In some embodiments, the outputs of speculative tap 220B correspond to selected outputs of a subset of the set of amplitude filters 210B. In some embodiments, the set of amplitude filters 210A is operated according to the clock signal CLK, and the set of amplitude filters 210B is operated according to an inverted clock signal CLKB, such that the modified input signal 205A includes odd symbols and the modified input signal 205B includes an even symbol. Consequently, in one manifestation, the outputs of speculative tap 220B correspond to a symbol preceding the outputs of speculative tap 220A. In one manifestation, speculative tap 220A forms a feedback loop with speculative tap 220B without a decoder in the feedback loop. Detailed implementations and operations of the speculative tap 220 are described below with regard to . Fig. 11 to Fig. 14 described.

[0040] A decoder 230A is a circuit that decodes the output signal of the speculative tap 225A and generates a decoded signal 235A. In one configuration, the decoder 230A comprises i) input terminals coupled to the output terminals of the speculative tap 220A and ii) output terminals. In this configuration, the decoder 230A receives at its input terminals the selected outputs of the subset of the set of amplitude sieves 210A as the output signal of the speculative tap 225A. In some embodiments, the decoder 230A decodes the output signal of the speculative tap 225A to obtain a decoded signal 235A and outputs the decoded signal 235A at its output terminals. In one form, the decoder 230A decodes the output signal of the speculative tap 225A, which is present in a thermometer code, into a binary code in order to obtain the decoded signal 235A.For example, the decoder 230A decodes three bits of the output signal of the speculative tap 225A, which are present in the thermometer code, into two binary bits of the decoded signal 235A.

[0041] A feedback generator 240A is a circuit that receives the decoded signal 235A and generates the feedback signals 242A and 245A. In one configuration, the feedback generator 240A comprises i) input terminals coupled to the output terminals of the decoder 230A, ii) a clock terminal, and iii) output terminals coupled to the input terminals of the amplitude filters 210A and 210B. In this configuration, the feedback generator 240A receives the decoded signal 235A at its input terminals and the clock signal CLK at its clock terminal. In some embodiments, the feedback generator 240A generates the feedback signals 242A and 245A according to the decoded signal 235A and the clock signal CLK and outputs the feedback signals 242A and 245A at its output terminals.In one implementation, the feedback signal 242A modifies the input signal 202 to obtain the modified input signal 205A, and the feedback signal 245A modifies the input signal 202 to obtain the modified input signal 205B. In one embodiment, modifying the input signal 202 based on the feedback signals 242A and 245A allows for mitigation of distortion due to ISI. In some embodiments, the feedback generator 240A includes one or more taps, including a latch, a single-ended-to-differential signal converter, and an amplifier. Detailed implementations and operations of the feedback generator 240A are described below. Fig. 15 to Fig. 19 described.

[0042] In some embodiments, the adder 270B, the set of amplitude filters 210B, the speculative tap 220B, the decoder 230B, and the feedback generator 240B are configured and operated together according to the input signal 202, the modified input signal 205B, the amplitude filter output signal 215B, the output signal of the speculative tap 225B, the inverted clock signal CLKB, the decoded signal 235B, and the feedback signals 242B, 245B, in a similar manner to how the adder 270A, the set of amplitude filters 210A, the speculative tap 220A, the decoder 230A, and the feedback generator 240A are operated according to the input signal 202, the modified input signal 205A, the Amplitude filter output signal 215A, the output signal of the speculative tap 225A, the clock signal CLK, the decoded signal 235A and the feedback signals 242A, 245A.Therefore, for the sake of brevity, the repeated description of this is omitted in the present document.

[0043] Although the in Fig.In the device 200 shown in Figure 2, which uses a half-clock frequency architecture, wherein the adder 270A, the set of amplitude filters 210A, the speculative tap 220A, the decoder 230A and the feedback generator 240A are operated according to a clock signal CLK, and the adder 270B, the set of amplitude filters 210B, the speculative tap 220B, the decoder 230B and the feedback generator 240B are operated according to the inverted clock signal CLKB, the device 200 uses a different architecture in other embodiments. For example, the device 200 uses a full clock frequency architecture, with the adder 270B, the set of amplitude sieves 210B, the speculative tap 220B, the decoder 230B and the feedback generator 240B omitted or disabled, and the speculative tap 220A operated according to the previous output signal of the speculative tap 225A.As another example, the device 200 uses an architecture with a quarter of the clock frequency, employing additional adders, additional sets of amplitude sieves, additional speculative taps, additional decoders, and additional feedback generators.

[0044] With reference to Fig. Figure 3 illustrates a diagram depicting exemplary PAM4 signals. In some embodiments, an input signal 202 is represented as one of four available levels. In some embodiments, a preceding symbol of an input signal distorts a subsequent symbol of the input signal. By modeling the effect of a preceding signal as α, a modified input signal for a non-zero tap 1 is expressed according to the following equation: y(n)=x(n)+φx(n−1) where y(n) is the input signal 202 received by the device 200, x(n) is a signal transmitted by a transmitter (for example, the communication device 110A) at symbol n, x(n-1) is the signal transmitted by the transmitter at a previous symbol n-1, and α is a coefficient that models an effect (for example, ISI) of the previous symbol n-1 on symbol n. As in Fig. As shown in Figure 3, in some embodiments the total available number of levels of the input signal 202 is 16, while 12 thresholds are used to distinguish different levels for a given, previous symbol n-1.

[0045] With reference to Fig.Figure 4 illustrates a schematic diagram depicting a set of amplitude filters 400. In some embodiments, the set of amplitude filters 400 comprises the amplitude filters 410A, 410B...410L, each amplitude filter 410X having i) input terminals for receiving the input signals 405A, 405B, ii) reference terminals for receiving the reference signals 420XA, 420XB, iii) a clock terminal for receiving a clock signal 470, and iv) output terminals for outputting the bits 430XA, 430XB. In one example, L corresponds to the value 12 when using PAM4-DFE. In one manifestation, the input signals 405A, 405B are PAM4 signals, and each amplitude filter 410 generates the differential bits 430XA, 430XB of the amplitude filter output signals, which indicate whether, according to a pulse of the clock signal 470, a voltage difference of the input signals 405A, 405B is greater or less than a voltage difference of the reference signals 420XA, 420XB.In some embodiments, the set of amplitude screens 400 is implemented as the set of amplitude screens 210A or the set of amplitude screens 210B. In the case that the set of amplitude screens 400 is implemented as the set of amplitude screens 210A of . Fig. 2 is implemented, the input signals 405A, 405B correspond to the modified input signal 205A, for example in a differential representation, the clock signal 470 corresponds to the clock signal CLK, and a set of bits 430AA, 430BA, 430CA...430LA and a set of bits 430AB, 430BB, 430CB...430LB correspond to a differential representation of the amplitude filter output signal 215A of Fig. 2.

[0046] In some embodiments, the reference signals 420XA, 420XB are predefined according to a corresponding threshold value of the PAM4 signal. For example, a voltage difference 420AA, 420AB of an amplitude filter 410A corresponds to 2+3α, a voltage difference of the reference signals 420BA, 420BB of an amplitude filter 410B corresponds to 2+α, a voltage difference of the reference signals 420CA, 420CB of an amplitude filter 410C corresponds to 2-α, and a voltage difference of the reference signals 420DA, 420DB of an amplitude filter 410D corresponds to 2-3α. For example, a voltage difference 420EA, 420EB of an amplitude sieve 410E corresponds to 3a, a voltage difference of the reference signals 420FA, 420FB of an amplitude sieve 410F corresponds to α, a voltage difference of the reference signals 420GA, 420GB of an amplitude sieve 410G corresponds to -α, and a voltage difference of the reference signals 420HA, 420HB of an amplitude sieve 410H corresponds to -3α.For example, a voltage difference 420IA, 420IB of an amplitude sieve 410I corresponds to -2+3α, a voltage difference of the reference signals 420JA, 420JB of an amplitude sieve 410J corresponds to -2+α, a voltage difference of the reference signals 420KA, 420KB of an amplitude sieve 410K corresponds to -2-α, and a voltage difference of the reference signals 420LA, 420LB of an amplitude sieve 410L corresponds to -2-3α.

[0047] In some embodiments, a first set of bits 430AA, 430BA, 430CA...430LA indicates a voltage level of the input signal 405A in a digital representation, and a second set of bits 430AB, 430BB, 430CB...430LB indicates a voltage level of the input signal 405B in a digital representation. For example, if the voltage level of the input signal 405A corresponds to 1+3α, the first set of bits 430AA, 430BA, 430CA...430LA represents the value '0000 1111 1111' because the voltage difference between the input signals 405A and 405B is higher than a voltage difference corresponding to 3α, but lower than a voltage difference corresponding to 2-3α. If, in an analogous example, the voltage difference of the input signals 405A, 405B corresponds to 1-3α, the first set of bits represents 430AA, 430BA, 430CA...430LA represents the value ,0000 0001 1111', because the voltage difference of the input signals 405A, 405B is higher than a voltage difference corresponding to -3α, but smaller than a voltage difference corresponding to -α.

[0048] Although each amplitude sieve 410 is operated according to a voltage difference of reference signals, in other embodiments each amplitude sieve 410 is operated according to a corresponding, individual reference voltage.

[0049] With reference to Fig.Figure 5 illustrates a schematic diagram depicting an exemplary amplitude filter 500. In some embodiments, an amplitude filter 500 comprises a comparator 502 (also referred to in this document as "a comparator circuit 502") and an SR latch 520 (also referred to in this document as "an SR latch circuit 520"). In one embodiment, the comparator 502 comprises a first-stage circuit 510, a second-stage circuit 570, and a kickback suppression circuit 580. These components are operated together to receive the reference signals 515A, 515B, the input signals 505A, 505B, and a clock signal 550, and they generate the amplitude filter output signals 545A, 545B, which indicate whether the voltage difference of the input signals 505A, 505B exceeds a voltage difference of the reference signals 515A, 515B. In some embodiments, the amplitude filter 500 is designated as the amplitude filter 410 of Fig.4 implemented. In one embodiment, the amplitude filter 500 receives the input signals 505A, 505B with a reduced amplitude (for example, 150 mV) and generates the amplitude filter output signals 545A, 545B with a larger amplitude (for example, between 0 V and the supply voltage VDD) in a digital representation. In some embodiments, the input signals 505A, 505B correspond to the input signals 405A, 405B of Fig. 4, the clock signal 550 corresponds to the clock signal 470 from Fig. 4, the reference signals 515A, 515B correspond to the reference signals 420XA, 420XB, and the amplitude filter output signals 545A, 545B correspond to the differential bits 430XA, 430XB of Fig. 4.

[0050] The first-stage circuit 510 is a circuit that compares the input signals 505A, 505B with the reference signals 515A, 515B according to a pulse from the clock signal 550. In one configuration, the first-stage circuit 510 comprises i) input terminals to receive the input signals 505A, 505B, ii) reference terminals to receive the reference signals 515A, 515B, iii) a clock terminal to receive the clock signal 550, iv) a terminal for a delayed clock to receive the delayed clock signal 555, and v) output terminals to provide the output comparison signals 518A, 518B. In this configuration, the circuit of the first stage 510 performs a preliminary sampling of the input signals 505A, 505B with regard to the reference signals 515A, 515B.In some embodiments, the circuit of the first stage 510 compares a voltage difference of the input signals 505A, 505B with a voltage difference of the reference signals 515A, 515B at the reference terminals according to a pulse of the clock signal 550 and generates the output comparison signals 518A, 518B, which indicate whether the voltage difference of the input signals 505A, 505B exceeds the voltage difference of the reference signals 515A, 515B.

[0051] In some embodiments, the circuit of the first stage 510 is configured such that, in response to a state (for example, the state “Low”, logical ,0’ or 0 V) ​​of the clock signal 550, it resets voltages at the output terminals of the circuit of the first stage 510. In some embodiments, the circuit of the first stage 510 charges its output terminals in response to a state (for example, the "Low" state, logic '0' or 0 V) ​​of the clock signal 550. Furthermore, the circuit of the first stage 510 discharges its output terminals in response to a state (for example, the "High" state, logic '1' or VDD) of the clock signal 550 according to i) a first voltage difference between the input signals 505A, 505B and ii) a second voltage difference between the reference signals 515A, 515B at different rates.A detailed implementation and operation of the first stage 510 circuit are described below with regard to . Fig. 6 and Fig. 9A described.

[0052] In one embodiment, the kickback suppression circuit 580 performs clock kickback compensation. In some embodiments, the kickback suppression circuit 580 comprises i) an input terminal for receiving the clock signal 550 and ii) an output terminal coupled to the delayed clock terminal of the first-stage circuit 510. In some embodiments, the kickback suppression circuit 580 includes delay circuits that delay the clock signal 550 to obtain the delayed clock signal 555 and to feed the delayed clock signal 555 into the delayed clock terminal of the first-stage circuit 510. Without the kickback suppression circuit 580, a pulse of the clock signal 550 degrades the input signals, the output signals, or a combination of the input signals and the output signals of the first-stage circuit 510, for example, via parasitic coupling.By using the kickback suppression circuit 580, which feeds the delayed clock signal 555 into the circuit of the first stage 510, the degradation due to the parasitic coupling of the clock signal pulse is mitigated in some embodiments. Accordingly, the sensitivity of the circuit of the first stage 510 is improved via clock kickback compensation.

[0053] In some embodiments, the circuit of the second stage 570 comprises i) input terminals coupled to output terminals of the circuit of the first stage 510 and ii) output terminals. In some embodiments, the circuit of the second stage 570 performs amplification or regeneration of the output comparison signals 518A, 518B. In one embodiment, the circuit of the second stage 570 samples a voltage difference between the output comparison signals 518A, 518B and generates the comparator output signals 575A, 575B, which indicate which of the output comparison signals 518A, 518B is higher. In some embodiments, the comparator output signals 575A, 575B are pulses that fluctuate between 0 V and the supply voltage VDD, where 0 V corresponds to the logical value 0 and the supply voltage VDD corresponds to the logical value '1' (or the state 'High').In one configuration, the circuit of the second stage 570 generates the comparator output signals 575A, 575B according to the following table:. State of the comparator output signal 575A State of the comparator output signal 575B If the output comparison signals 518A and 518B are equal 0 0 If output comparison signal 518A > output comparison signal 518B (or the output comparison signal 518B discharges faster) 1 0 If output comparison signal 518B > output comparison signal 518A (or the output comparison signal 518A discharges faster) 0 1

[0054] Accordingly, in some embodiments, the circuit of the second stage 570 generates the comparator output signals 575A, 575B, which indicate whether the voltage difference of the input signals 505A, 505B exceeds the voltage difference of the reference signals 515A, 515B, and it outputs the comparator output signals 575A, 575B to the SR-latch 520.

[0055] In some embodiments, the SR-Latch 520 comprises a sampling circuit 530 and a regeneration circuit 540. In one configuration, the sampling circuit 530 includes i) input terminals coupled to the output terminals of the second-stage circuit 570, ii) a clock terminal, and iii) output terminals. In another configuration, the regeneration circuit 540 includes i) input terminals coupled to the output terminals of the sampling circuit 530 and ii) output terminals. In this configuration, the sampling circuit 530, in response to a pulse of the clock signal 550, samples a voltage difference between the comparator output signals 575A, 575B to obtain the sampled signals 535A, 535B, and outputs the sampled signals 535A, 535B at the output terminals.Furthermore, in this configuration, the regeneration circuit 540 amplifies the sampled signals 535A and 535B to obtain the amplitude filter output signals 545A and 545B and outputs these signals at the output terminals. In one embodiment, the SR-Latch 520 is implemented as a CMOS (Complete Metal Oxide Semiconductor) circuit, which performs faster sampling and amplification with reduced hardware resources than conventional circuits (for example, CMOS NOR circuits). A detailed implementation and operation of the SR-Latch 520 are described below. Fig. 7, Fig. 8 and Fig. 9B described.

[0056] With reference to Fig.Figure 6 illustrates a schematic diagram depicting an exemplary circuit of the first stage 600 of a comparator. In some embodiments, the circuit of the first stage 600 is the same as the circuit of the first stage 510 of Fig.5 implemented. In some embodiments, the first-stage 600 circuit includes transistors Ta1, Ta2, Ta3, Ta4, Ta5, Ta6, Ta7, Ta8. In some embodiments, the first-stage 600 circuit includes or is coupled to capacitors C1, C2, C3, C4. In some embodiments, capacitors C1, C2, C3, C4 are implemented as MOS (Metal Oxide Semiconductor) or MOM (Metal Oxide Metal) capacitors.In some embodiments, capacitors C1, C2, C3, and C4 are implemented as part of the kickback suppression circuit 580, or they are coupled between the first-stage circuit 600 of a comparator and the kickback suppression circuit 580. These components operate together to receive the input signals 505A and 505B, a clock signal 550, and a delayed clock signal 555; to compare the input signals 505A and 505B with the reference signals 515A and 515B; and to generate the comparison signals 518A and 518B based on the comparison and a pulse of the clock signal 550. In some embodiments, the delayed clock signal 555 is injected to perform clock kickback compensation. In other embodiments, the first-stage circuit 600 of a comparator includes more, fewer, or different components than shown in [reference missing]. Fig.Figure 6 shows that in some embodiments, transistors Ta1, Ta2, Ta3, Ta4, Ta5, Ta6 are N-type transistors (for example, NMOS) and transistors Ta7, Ta8 are P-type transistors (for example, PMOS). In other embodiments, transistors Ta1, Ta2, Ta3, Ta4, Ta5, Ta6, Ta7, Ta8 are implemented with different types of transistors than shown in Figure 6. Fig. 6 shown.

[0057] In one configuration, transistor Ta1 comprises i) a gate electrode, ii) a source electrode, and iii) a drain electrode. In another configuration, transistor Ta2 comprises i) a gate electrode, ii) a source electrode coupled to the source electrode of Ta1, and iii) a drain electrode. In another configuration, transistor Ta3 comprises i) a gate electrode, ii) a source electrode, and iii) a drain electrode coupled to the drain electrode of transistor Ta2. In another configuration, transistor Ta4 comprises i) a gate electrode, ii) a source electrode coupled to the source electrode of transistor Ta3, and iii) a drain electrode coupled to the drain electrode of transistor Ta1.In one configuration, transistor Ta5 comprises i) a gate electrode, ii) a source electrode coupled to a first supply terminal (for example, a ground terminal (GND)), and iii) a drain electrode coupled to the source electrodes of transistors Ta1 and Ta2. In one configuration, transistor Ta6 comprises i) a gate electrode, ii) a source electrode coupled to the first supply terminal, and iii) a drain electrode coupled to the source electrodes of transistors Ta3 and Ta4. In one configuration, transistor Ta7 comprises i) a gate electrode, ii) a source electrode coupled to a second supply terminal (for example, a VDD terminal), and iii) a drain electrode coupled to the drain electrodes of transistors Ta2 and Ta3.In one configuration, transistor Ta8 comprises i) a gate electrode coupled to the gate electrode of transistor Ta7, ii) a source electrode coupled to the second supply terminal, and iii) a drain electrode coupled to the drain electrodes of transistors Ta1 and Ta4. In some embodiments, the drain electrodes of transistors Ta1, Ta4, and Ta8 are coupled to an output terminal O1 of the first-stage 600 circuit, and the drain electrodes of transistors Ta2, Ta3, and Ta7 are coupled to an output terminal O2 of the first-stage 600 circuit.

[0058] In this configuration, transistor Ta1 receives the input signal 505A at its gate electrode, and transistor Ta3 receives the input signal 505B at its gate electrode. Additionally, transistor Ta2 receives the reference signal 515A at its gate electrode, and transistor Ta4 receives the reference signal 515B at its gate electrode. Furthermore, transistors Ta5, Ta6, Ta7, and Ta8 receive the clock signal 550 at their gate electrodes. In one embodiment, the circuit of the first stage 600, in response to the clock signal 550 being in a "low" state (for example, logic '0' or 0 V), resets the voltages at the output terminals O1 and O2. In some embodiments, the circuit of the first stage 600, in response to the clock signal 550 being in a "low" state (for example, logic '0' or 0 V), charges the output terminals O1 and O2.In one approach, in response to a "Low" state (for example, logic '0' or 0V) of the clock signal 550, transistors Ta7 and Ta8 are activated, and transistors Ta5 and Ta6 are deactivated; consequently, the voltages at output terminals O1 and O2 are increased, for example, to a supply voltage VDD. In another approach, in response to a "High" state (for example, logic '1' or VDD) of the clock signal 550, transistors Ta7 and Ta8 are deactivated, and transistors Ta5 and Ta6 are activated; consequently, the voltages at output terminals O1 and O2 are decreased, for example, to 0V. In yet another approach, the discharge rate changes according to the input signals 505A and 505B with respect to the reference signals 515A and 515B. For example, if the voltage difference between the input signals 505A, 505B is higher than the voltage difference between the reference signals 515A, 515B, then the output terminal O1 will discharge faster than the output terminal O2.

[0059] In one manifestation, a pulse of the clock signal 550 degrades the input signal, the output signal, or a combination of the input and output signals of the first-stage circuit 600, for example, via parasitic coupling. For instance, in one manifestation, the clock signal 550 applied to the gate electrodes of transistors Ta5, Ta6, Ta7, and Ta8 propagates via parasitic capacitors (e.g., Cgs or Cgd) of transistors Ta1 to Ta8, thereby degrading the sensitivity of the first-stage circuit 600.

[0060] In some embodiments, the degradation due to the parasitic coupling of the clock signal 550 is mitigated by injecting the delayed clock signal 555 at the input terminals or at the gate electrodes of transistors Ta1, Ta2, Ta3, Ta4. In some embodiments, the first-stage circuit 600 includes or is coupled to capacitors C1, C2, C3, C4 to inject the delayed clock signal 555. In some embodiments, capacitors C1, C2, C3, C4 have substantially the same capacitance. In one implementation, a first electrode of capacitor C1 is coupled to the gate electrode of transistor Ta1, and a second electrode of capacitor C1 is coupled to the output terminal of the kickback suppression circuit 580.In one implementation, the first electrode of capacitor C2 is coupled to the gate electrode of transistor Ta3, and the second electrode of capacitor C2 is coupled to the output terminal of kickback suppression circuit 580. Similarly, in another implementation, the first electrode of capacitor C3 is coupled to the gate electrode of transistor Ta2, and the second electrode of capacitor C3 is coupled to the output terminal of kickback suppression circuit 580. Furthermore, in another implementation, the first electrode of capacitor C4 is coupled to the gate electrode of transistor Ta4, and the second electrode of capacitor C4 is coupled to the output terminal of kickback suppression circuit 580. In this configuration, the delayed clock signal 555 is supplied via capacitors C1, C2, C3, and C4.In one approach, the delayed clock signal 555 is delayed relative to the clock signal 550 by a time delay for the clock signal 550, in order to propagate to the source electrodes, drain electrodes or a combination of the source electrodes and the drain electrodes of the transistors Ta1, Ta2, Ta3, Ta4 via parasitic capacitors in such a way that the transistors Ta1, Ta2, Ta3, Ta4 are conducting or discharging according to the input signals 505A, 505B with reduced influence from the clock signal 550.

[0061] In some embodiments, the input impedances at the input terminals of the first stage 600 circuit (or at the gate electrodes of transistors Ta1, Ta2, Ta3, Ta4) are matched to ensure that the delayed clock signal 555 is supplied simultaneously to the input terminals of the first stage 600 circuit.

[0062] With reference to Fig.Figure 7 is a diagram illustrating an exemplary sampling circuit 700. In some embodiments, the sampling circuit 700 is referred to as the sampling circuit 530 of Fig. 5 implemented. In some embodiments, the sampling circuit 700 comprises transistors Tbl, Tb2, Tb3, Tb4, Tb5, Tb6, Tb7, Tb8, and Tsw. These components are operated together to receive the comparator output signals 575A and 575B and a clock signal 550, and they amplify a voltage difference of the comparator output signals 575A and 575B to generate the sampled signals 535A and 535B. In other embodiments, the sampling circuit 700 comprises more, fewer, or different components than described in Figure 5. Fig.Figure 7 shows that in some embodiments, transistors Tb1, Tb2, Tb3, Tb4, and Tsw are N-type transistors (for example, NMOS), and transistors Tb5, Tb6, Tb7, and Tb8 are P-type transistors (for example, PMOS). In other embodiments, transistors Tb1, Tb2, Tb3, Tb4, Tb5, Tb6, Tb7, Tb8, and Tsw are implemented with different types of transistors than those shown in Figure 7. Fig. 7 shown.

[0063] In one configuration, transistor Tb1 comprises i) a gate electrode coupled to a first input terminal of the sampling circuit 700, ii) a source electrode coupled to the first supply terminal (for example, the GND terminal), and iii) a drain electrode. In one configuration, transistor Tb2 comprises i) a gate electrode coupled to a second input terminal of the sampling circuit 700, ii) a source electrode coupled to the first supply terminal, and iii) a drain electrode. In one configuration, transistor Tb3 comprises i) a gate electrode coupled to the drain electrode of transistor Tb2, ii) a source electrode, and iii) a drain electrode coupled to the drain electrode of transistor Tb1. In one configuration, transistor Tb4 comprises i) a gate electrode coupled to the drain electrode of transistor Tb1, ii) a source electrode coupled to the source electrode of transistor Tb3, and iii) a.In one configuration, transistor Tb5 comprises i) a gate electrode, ii) a source electrode coupled to a second supply terminal (for example, a VDD terminal), and iii) a drain electrode coupled to the drain electrode of transistor Tb1. In one configuration, transistor Tb6 comprises i) a gate electrode, ii) a source electrode coupled to the second supply terminal, and iii) a drain electrode coupled to the drain electrode of transistor Tb2. In one configuration, transistor Tb7 comprises i) a gate electrode coupled to the drain electrode of transistor Tb2, ii) a source electrode coupled to the second supply terminal, and iii) a drain electrode coupled to the drain electrode of transistor Tb1.In one configuration, transistor Tb8 comprises i) a gate electrode coupled to the drain electrode of transistor Tb1, ii) a source electrode coupled to the second supply terminal, and iii) a drain electrode coupled to the drain electrode of transistor Tb2. In another configuration, transistor Tsw comprises i) a gate electrode, ii) a source electrode coupled to the first supply terminal, and iii) a drain electrode coupled to the source electrodes of transistors Tb3 and Tb4. In some embodiments, the drain electrodes of transistors Tb2, Tb4, Tb6, and Tb8 are coupled to an output terminal O3 of the sampling circuit 700, and the drain electrodes of transistors Tb1, Tb3, Tb5, and Tb7 are coupled to an output terminal O4 of the sampling circuit 700.

[0064] In this configuration, transistors Tb3, Tb4, Tb7, and Tb8 form cross-coupled transistors 710, the strength of which is increased or decreased according to the switching transistor Tsw. In one example, transistor Tb1 receives the comparator output signal 575A at its gate electrode, and transistor Tb2 receives the comparator output signal 575B at its gate electrode. Additionally, transistors Tb5, Tb6, and Tsw receive the clock signal 550 at their gate electrodes.

[0065] In one embodiment, the sampling circuit 700, in response to a "Low" state (for example, logic '0' or 0 V) ​​of the clock signal 550, resets the voltages at the output terminals O3, O4. In some embodiments, the sampling circuit 700, in response to a "Low" state (for example, logic '0' or 0 V) ​​of the clock signal 550, charges the output terminals O3, O4. In one approach, in response to a "Low" state (for example, logic '0' or 0 V) ​​of the clock signal 550, transistors Tb5, Tb6 are activated, and no current flows through transistors Tb3, Tb4; consequently, the strength of the regeneration by means of the cross-coupled transistors 710 is reduced. In another approach, in response to a "High" state (for example, logic '1' or 0 V) ​​of the clock signal 550, the voltages at the output terminals O3, O4 are set to 0.When the clock signal 550 is switched off (VDD), transistors Tb5 and Tb6 are deactivated, and current flows either through one of transistors Tb3 or Tb4, or through a combination of transistors Tb3 and Tb4. Consequently, the strength of the regeneration via the cross-coupled transistors 710 is increased. In one configuration, in response to a pulse of the clock signal 550 being in the "high" state, a voltage difference between the comparator output signals 575A and 575B is sampled, and the sampled voltage difference is amplified. In another configuration, the sampling circuit 700, in response to the clock signal 550 being in the "high" state, performs sampling by discharging the output terminals O3 and O4 according to the comparator output signals 575A and 575B at different rates.For example, if the voltage of comparator output signal 575A is higher than the voltage of comparator output signal 575B, then output terminal O4 will discharge faster than output terminal O3, so that the voltage of the sampled signal 535A will be higher than the voltage of the sampled signal 535B.

[0066] With reference to Fig. Figure 8 is a schematic diagram illustrating an exemplary regeneration circuit 800. In some embodiments, the regeneration circuit 800 is referred to as the regeneration circuit 540 of Fig.5 implemented. In some embodiments, the regeneration circuit 800 comprises transistors Tc1, Tc2, Tc3, Tc4 and inverters I1, I2, I3, I4. These components are operated together to receive the sampled signals 535A, 535B, and they amplify a voltage difference of the sampled signals 535A, 535B to generate the amplitude-sweeping output signals 545A, 545B. In other embodiments, the regeneration circuit 800 comprises more, fewer, or different components than described in Figure 5. Fig. Figure 8 shows that in some embodiments, transistors Tc2 and Tc4 are N-type transistors (for example, NMOS) and transistors Tc1 and Tc3 are P-type transistors (for example, PMOS). In other embodiments, transistors Tc1, Tc2, Tc3, and Tc4 are implemented using different types of transistors than those shown in Figure 8. Fig. 8 shown.

[0067] In one configuration, transistor Tc1 comprises i) a gate electrode coupled to output terminal O3 of the sampling circuit 700, ii) a source electrode coupled to the second supply terminal (for example, the VDD terminal), and iii) a drain electrode. In another configuration, transistor Tc3 comprises i) a gate electrode coupled to output terminal O4 of the sampling circuit 700, ii) a source electrode coupled to the second supply terminal, and iii) a drain electrode. In another configuration, inverter I1 comprises an input terminal coupled to output terminal O4 of the sampling circuit 700, and inverter I2 comprises an input terminal coupled to output terminal O3 of the sampling circuit 700.In one configuration, transistor Tc2 comprises i) a gate electrode coupled to the output terminal of inverter I1, ii) a source electrode coupled to the first supply terminal (for example, the GND terminal), and iii) a drain electrode coupled to the drain electrode of transistor Tc1. In another configuration, transistor Tc4 comprises i) a gate electrode coupled to the output terminal of inverter I2, ii) a source electrode coupled to the first supply terminal, and iii) a drain electrode coupled to the drain electrode of transistor Tc3. In another configuration, inverters I3 and I4 form cross-coupled inverters between the output terminals O5 and O6 of regeneration circuit 800.

[0068] In some embodiments, transistor Tc1 receives the sampled signal 535A at its gate electrode, and transistor Tc3 receives the sampled signal 535B at its gate electrode. In some embodiments, inverter I2 receives the sampled signal 535A at its input terminal, and inverter I1 receives the sampled signal 535B at its input terminal. Furthermore, in some embodiments, transistor Tc2 receives an inverted sampled signal 870B at its gate electrode, with an inverted phase of the sampled signal 535B, and transistor Tc4 receives an inverted sampled signal 870A at its gate electrode, with an inverted phase of the sampled signal 535A.

[0069] In one configuration, transistors Tc1, Tc2, Tc3, and Tc4 receive the sampled signals from the sampling circuit 700 and amplify the received signals via positive feedback using the cross-coupled inverters I3 and I4. In another approach, the regeneration circuit 800 holds the voltages at output terminals O5 and O6 while the clock signal 550 is in a "low" state, so that the voltage difference at output terminals O3 and O4 is not strong enough to overdrive the voltages held at output terminals O5 and O6 by the cross-coupled inverters I3 and I4.In one approach, the regeneration circuit 800 modifies the voltages at output terminals O5, O6 according to the voltages at output terminals O3, O4 of the sampling circuit 700, while the clock signal 550 is in a "high" state, such that a voltage difference at output terminals O3, O4 is large enough to overdrive the voltages held at output terminals O5, O6 by the cross-coupled inverters I3, I4. Although the comparator output signals 575A, 575B are not fully differential, inverters I1, I2 allow the regeneration circuit 800 to operate with the inverted sampled signals 870A, 870B.

[0070] In one embodiment, the sampling circuit 700 and the regeneration circuit 800 are implemented as CMOS (Complete Metal Oxide Semiconductor) circuit arrangements, which perform faster sampling and amplification with a smaller form factor than conventional circuit arrangements (for example, CML (Current Mode Logic) or CMOS NOR circuit arrangements).

[0071] With reference to Fig. Figure 9A is a timing diagram illustrating an exemplary operation of the circuit of the first stage 510 of the comparator 502 of Fig.Figure 5 illustrates this. In one example, the first-stage circuit 510, in response to a "low" state of the clock signal 550, charges its output terminals so that the reference signals 518A and 518B are at voltage VDD. In response to the clock signal 550 being in a "high" state, the first-stage circuit 510 discharges its output terminals according to the input signals 505A and 505B at different rates. For example, if the voltage of input signal 505A at time t1 is lower than the voltage of input signal 505B, then the voltage of reference signal 518B will be lower than the voltage of reference signal 518A because the first-stage circuit 510 discharges output terminal O2 faster than output terminal O1.For example, if the voltage of input signal 505A at time t2 is higher than the voltage of input signal 505B, then the voltage of comparison signal 518B will be higher than the voltage of comparison signal 518A because the circuit of the first stage 510 discharges the output terminal O1 faster than the output terminal O2.

[0072] In one example, the peak-to-peak voltage of each of the input signals 505A, 505B is 150 mV, and the peak-to-peak voltage of each of the comparison signals 518A, 518B, the clock signal 550 and the delayed clock signal 555 is 800 mV (or VDD).

[0073] With reference to Fig.Figure 9B illustrates a timing diagram depicting an example operation of an SR-Latch 520. In one example, the SR-Latch 520 samples the comparator output signals 575A and 575B in response to the clock signal and amplifies the sampled signals to obtain the amplitude filter output signals 545A and 545B. In another example, the SR-Latch 520 samples the comparator output signals 575A and 575B in response to the clock signal being in a "high" state and amplifies the sampled signals. In response to the clock signal being in a "low" state, the SR-Latch 520 maintains the voltages of the amplitude filter output signals 545A and 545B.For example, in response to the clock signal 550 being in the "high" state, the voltage of the comparator output signal 575B at time t3 is higher than the voltage of the comparator output signal 575A. Consequently, the SR latch 520 generates the amplitude filter output signal 545A with a higher voltage than that of the amplitude filter output signal 545B. The SR latch 520 maintains the amplitude filter output signals 545A and 545B until a pulse of the comparator output signal 575A is detected. For example, in response to the clock signal 550 being in the "High" state, the voltage of the comparator output signal 575B at time t4 is lower than the voltage of the comparator output signal 575A; consequently, the SR latch 520 generates the amplitude filter output signal 545A with a lower voltage than that of the amplitude filter output signal 545B.

[0074] In one example, the peak-to-peak voltage of each of the clock signal 550 and the amplitude filter output signals 545A, 545B is 800 mV (or VDD).

[0075] With reference to Fig. 9C illustrates an exemplary eye diagram without a beat-kickback balance, with reference to Fig. Figure 9D illustrates an example eye diagram with clock kickback compensation. In one example, a delayed clock signal 555 is used to perform clock kickback compensation. Without clock kickback compensation, a pulse of the clock signal 550 degrades the input signal of the comparator 502, for example via parasitic coupling, as shown in Figure 9D. Fig.Figure 9C shows that by injecting the delayed clock signal 555, distortions propagated via a parasitic capacitance due to a pulse of the clock signal 550 are reduced. Consequently, an eyepiece 990 with clock kickback compensation is improved compared to an eyepiece 980 without clock kickback compensation.

[0076] With reference to Fig. Figure 10 illustrates a flowchart depicting an exemplary process 1000 of sampling an input signal with clock kickback compensation. In some embodiments, the process 1000 is modified by means of the amplitude filter 500. Fig. 5. In some embodiments, process 1000 is performed using other entities. In some embodiments, process 1000 includes more, fewer, or different steps than in Fig. 10 shown.

[0077] In some embodiments, the amplitude filter 500 receives an input signal at 1010. In some embodiments, the input signal originates from another communication device 110. In some embodiments, the input signal conforms to a PAM4 protocol. In some embodiments, a feedback signal is added to the input signal to reduce the ISI of an adjacent symbol.

[0078] In some embodiments, the amplitude filter 500 at 1020 compares the modified input signal with a threshold value (for example, a reference signal voltage). In some embodiments, the amplitude filter 500 receives a clock signal and, in response to a pulse (for example, rising edge, falling edge, "high" state, or "low" state) of the clock signal, compares the modified input signal with the threshold value. In some embodiments, the amplitude filter 500, in response to a "low" state of the clock signal, resets voltages at intermediate terminals (for example, the output terminals O1, O2 of the first-stage circuit 600). In some embodiments, the amplitude filter 500, in response to a "low" state of the clock signal, charges the intermediate terminals (for example, the output terminals O1, O2 of the first-stage circuit 600).In some embodiments, the amplitude filter 500 detects a difference between the differential input signals or PAM4 input signals and the threshold value in response to a "High" state of the clock signal.

[0079] In some embodiments, the amplitude filter 500 at 1030 injects a delayed clock signal to modify the input signal. In some embodiments, the amplitude filter 500 delays the clock signal by an amount corresponding to a time delay so that the clock signal reaches transistors (for example, transistors Ta1, Ta2, Ta3, Ta4 of Fig. 6.) Accordingly, in some embodiments, distortions due to the propagation of the clock signal via parasitic capacitances of the transistors are reduced.

[0080] In some embodiments, the amplitude filter 500 generates a comparison signal of the input signal at 1040 at the intermediate terminals (for example, the output terminals O1, O2 of the first-stage circuit 600). In some embodiments, the amplitude filter 500 discharges the intermediate terminals in response to the "high" state of the clock signal according to the voltage difference between the differential input signals or PAM4 input signals relative to the threshold value. In some embodiments, with the differential PAM4 input signals, an output terminal connected to one input signal with a higher voltage than the other discharges faster than the other terminal connected to the other input signal. Consequently, the comparison signal indicates a level of the differential PAM4 input signals during discharge by means of a voltage difference.

[0081] The amplitude filter 500 samples the comparison signal at 1050 according to a first state of the clock signal 550. In some embodiments, the amplitude filter 500 detects a voltage difference at the intermediate terminals, for example due to different discharge rates, and amplifies the sampled signal or the sampled voltage difference at 1060.

[0082] With reference to Fig.Figure 11 illustrates a schematic diagram depicting an exemplary speculative tap 1100 with a decoder 1120. In one implementation, the speculative tap 1100 is implemented to replace the speculative tap 220 and the decoder 230. In this implementation, the speculative tap 1100 comprises the 4:1 multiplexers 1110A, 1110B, 1110C, the 3-bit thermometer-to-2-bit binary decoder 1120, the two-bit latch 1130, and the two-bit inverter INV. In this implementation, these components are operated together to receive the bits d0, d1, d2...d11 of an amplitude-sweeping output signal and generate a decoded signal 1125. In one implementation, bits d0, d1, d2...d11 correspond to the output bits 430LA, 430KA...430BA, 430AA of Fig. 4, or they each correspond to the output bits 430LB, 430KB...430BB, 430AB of Fig. 4.

[0083] In one implementation, each multiplexer 1110 comprises i) four input terminals (1 1, 10, 01, 00) coupled to the output terminals of corresponding amplitude filters, ii) two-bit control terminals Sel(1:0), iii) inverted two-bit control terminals Selb(1:0) and iv) one output terminal. In one implementation, the two-bit control inputs Sel(1:0) of multiplexers 1110A, 1110B, 1110C are coupled to output inputs of the two-bit latch 1130, and the inverted two-bit control inputs Selb(1:0) of multiplexers 1110A, 1110B, 1110C are coupled to output inputs of the two-bit inverter INV, with the input inputs of the two-bit inverter INV being coupled to output inputs of the two-bit latch 1130. Output inputs of multiplexers 1110A, 1110B, 1110C are coupled to input inputs of decoder 1120, and output inputs of decoder 1120 are coupled to input inputs of the two-bit latch 1130.The two-bit latch 1130 includes clock input terminals to receive the clock signal 1170.

[0084] In one implementation, each of the multiplexers 1110A, 1110B, 1110C receives corresponding four bits of amplitude filter output signals at its input terminals and selects one bit from the received bits of the amplitude filter output signals at its control terminals according to the two-bit control signal 1135, and the inverted two-bit control signal 1138 at its inverted control terminals. In another implementation, the multiplexers 1110A, 1110B, 1110C select bits according to a previous symbol. Assuming that the previous symbol corresponds to the value '3' of the PAM4 signal in Fig.If 3 corresponds to the input signal, the multiplexers 1110A, 1110B, and 1110C output bits d11, d7, and d3 of the amplitude filter output signal, which indicate a voltage level of the input signal with respect to three reference voltages associated with 2+3α, 3α, and -2+3α. In one implementation, the decoder 1120 receives a subset of the amplitude filter output signals 1115 selected by the multiplexers 1110 at the input terminals, decodes the three bits present in the thermometer code into two-bit binary code, and outputs the decoded two-bit signal 1125 at the output terminals. In one implementation, the two-bit latch 1130 receives the decoded two-bit signal 1125 at its input terminals, stores the received bits, and, in response to a pulse of the clock signal 1170 at the clock terminal, outputs the previously stored bits at the output terminals as a control signal 1135.In one implementation, the two-bit inverter INV receives the two-bit control signal 1135 and inverts the phase of the control signal 1135 to generate the inverted control signal 1138.

[0085] In this implementation, the speculative tap 1100 experiences a delay in the feedback path 1180. For example, the feedback path 1180 includes the multiplexer 1110, the decoder 1120, the latch 1130, and the inverter INV. In this implementation, the delay in the feedback path 1180 reduces the operating speed of the receiver.

[0086] With reference to Fig.Figure 12 illustrates a schematic diagram depicting an example of an improved speculative tap 1200. In some embodiments, the speculative tap 1200 comprises the multiplexers 1210A, 1210B, 1210C, 1260A, 1260B, 1260C and the three-bit latches 1230A, 1230B. In some embodiments, the speculative tap 1200 is the speculative tap 220A or 220B of Fig.2 implemented. In some embodiments, the speculative tap 1200 is implemented to process differential PAM4 signals, wherein the output terminals of the multiplexers 1210 are directly coupled to the input terminals of the corresponding latches 1230, without any decoder or inverter in between, and the output terminals of the latches 1230 are directly coupled to the control terminals of the corresponding multiplexers 1210. In some embodiments, bits d0, d1, d2...d11 correspond to output bits 430LA, 430KA...430BA, 430AA of Fig. 4, and the bits d0b, d1b...d11b each correspond to the output bits 430LB, 430KB...430BB, 430AB of Fig. 4.

[0087] In some embodiments, each multiplexer 1210 comprises i) four input terminals (for example, 111, 011, 001, 000) coupled to output terminals of corresponding amplitude filters, ii) three-bit control terminals Sel(2:0), iii) inverted three-bit control terminals Selb(2:0), and iv) one output terminal. In some embodiments, the output terminals of the multiplexers 1210A, 1210B, and 1210C are directly coupled to input terminals of the three-bit latch 1230A. In some embodiments, the three-bit control terminals Sel(2:0) of the multiplexers 1210A, 1210B, 1210C are directly coupled to output terminals of the three-bit latch 1230A, and the inverted three-bit control terminals Selb(2:0) of the multiplexers 1210A, 1210B, 1210C are directly coupled to output terminals of the three-bit latch 1230B.Similarly, in some embodiments, the output terminals of the multiplexers 1260A, 1260B, 1260C are directly coupled to input terminals of the three-bit latch 1230B. In some embodiments, the three-bit control terminals Sel(2:0) of the multiplexers 1260A, 1260B, 1260C are directly coupled to output terminals of the three-bit latch 1230A, and the inverted three-bit control terminals Selb(2:0) of the multiplexers 1260A, 1260B, 1260C are directly coupled to output terminals of the three-bit latch 1230B.

[0088] In some embodiments, each of the multiplexers 1210A, 1210B, 1210C receives corresponding four bits of the amplitude filter output signal (for example, bits 430LA, 430KA...430BA, 430AA) at its input terminals and selects one bit from the received bits of the amplitude filter output signals according to the three-bit control signal 1240A at the control terminals and the inverted three-bit control signal 1240B at the inverted control terminals. Analogously, in some embodiments, each of the multiplexers 1260A, 1260B, 1260C receives corresponding four bits of the amplitude filter output signal (for example, the bits 430LB, 430KB...430BB, 430AB) at the input terminals, and selects one bit of the received bits of the amplitude filter output signals according to the three-bit control signal 1240A at the control terminals and the inverted three-bit control signal 1240B at the inverted control terminals.In one manifestation, the input signals received by the set of multiplexers 1210A, 1210B, 1210C and those received by the set of multiplexers 1260A, 1260B, 1260C are differential signals. For example, bit d11 received by multiplexer 1210A has an inverted phase compared to bit d11b received by multiplexer 1260A.

[0089] In some embodiments, the three-bit latch 1230A receives the multiplexer output signal 1280A, including selected bits of the amplitude filter output signal, at its input terminals, stores the received bits, and, in response to a pulse of the clock signal 1270 at the clock terminal, outputs the previously stored bits at the output terminals as a three-bit control signal 1240A. Similarly, in some embodiments, the three-bit latch 1230B receives the multiplexer output signal 1280B, including selected bits of the amplitude filter output signal, at its input terminals, stores the received bits, and, in response to a pulse of the clock signal 1270 at the clock terminal, outputs the previously stored bits at the output terminals as an inverted three-bit control signal 1240B.In some embodiments, the control signal 1240A, the inverted control signal 1240B or a combination of the signals 1240A, 1240B are provided to the decoder 230 as the output signal of the speculative tap 225.

[0090] Advantageously, the speculative tap 1200 improves the operating speed by omitting the inverter and a decoder in the feedback path 1290. For example, the operating speed of the speculative tap 1200 compared to the speculative tap 1100 is Fig. 11 improved by 40%.

[0091] With reference to Fig. Figure 13 illustrates a schematic diagram depicting an exemplary multiplexer 1300. In some embodiments, the multiplexer 1300 is one of the multiplexers 1210A, 1201B, 1210C, 1260A, 1260B, 1260C from Fig.12 implemented. In some embodiments, the multiplexer 1300 comprises the 2:1 multiplexers 1310, 1320, and 1330. These components are operated together to perform 4:1 multiplexing. In some embodiments, the multiplexer 1300 comprises more, fewer, or different components than in Fig. 13 shown.

[0092] In some embodiments, the multiplexer 1310 comprises i) a first input port coupled to input port In3 of the multiplexer 1300, ii) a second input port coupled to input port In2 of the multiplexer 1300, iii) a control port coupled to port Sel(2), iv) an inverted control port coupled to port Selb(2), and v) an output port. In some embodiments, the multiplexer 1320 comprises i) a first input port coupled to input port In1 of the multiplexer 1300, ii) a second input port coupled to input port In0 of the multiplexer 1300, iii) a control port coupled to port Sel(0), iv) an inverted control port coupled to port Selb(0), and v) an output port.In some embodiments, the multiplexer 1330 comprises i) an input port coupled to an output port of the multiplexer 1310, ii) a second input port coupled to an output port of the multiplexer 1320, iii) a control port coupled to the port Sel(1), iv) an inverted control port coupled to the port Selb(1), and v) an output port coupled to an output port OUT_MUX of the multiplexer 1300.

[0093] In one configuration, the Multiplexer 1300 selects one of the signals received at inputs In0, In1, In2, In3 based on the control signals received at terminals Sel<2:0> and Selb<2:0>, and outputs the selected signal at output terminal OUT_MUX. In one appearance mode, the Multiplexer 1300 selects a signal as shown in the table below. Sel<2:0> 111 110 101 100 011 010 001 000 OUT IN3 IN3 IN1 IN0 IN2 IN2 IN1 IN0

[0094] Because it is possible to operate the multiplexer 1300 according to three-bit control signals with redundancy, instead of two-bit control signals, the multiplexers 1210A, 1210B, 1210C, 1260A, 1260B, and 1260C are operated according to direct outputs from the latches 1230A and 1230B without any decoder. Consequently, in some embodiments, the operating speed of the device 200 is improved.

[0095] With reference to Fig. Figure 14 illustrates a flowchart depicting an exemplary process 1400 of receiving signals by means of a receiver. In some embodiments, the process 1400 is carried out by means of the receiver device 200. Fig. 2. In some embodiments, process 1400 is performed using other entities. In some embodiments, process 1400 includes more, fewer, or different steps than in Fig. 14 shown.

[0096] In some embodiments, the device 200 receives an input signal at 1410. In some embodiments, the input signal originates from another communication device 110. In some embodiments, the input signal conforms to a PAM4 protocol. In some embodiments, a feedback signal is added to the input signal to reduce the ISI of an adjacent symbol.

[0097] In some embodiments, the device 200 at 1420 generates an amplitude filter output signal that digitally indicates the level of the input signal. In one example, the amplitude filter output signal indicates the level of the input signal in a thermometer code. For example, if in Fig. 4. If the voltage level of the input signal corresponds to the value 1+3α, the first set of bits 430AA, 430BA, 430CA...430LA represents the value ,0000 1111 1111'.

[0098] In some embodiments, the device 200 at 1430 selects a number of bits of the amplitude filter output signal based on selected bits of an earlier amplitude filter output signal. In one embodiment, an earlier amplitude filter output signal precedes the amplitude filter output signal by one or more symbols. Selecting the number of bits of the amplitude filter output signal based on the selected bits of the earlier amplitude filter output signal without a decoder improves the operating speed of the device 200.

[0099] In some embodiments, the device 200 decodes the selected bits of the amplitude filter output signal, which are present in a first digital representation, into a second digital representation. In some embodiments, the device 200 decodes the selected bits of the amplitude filter output signal, which are present in a thermometer code, into a binary code.

[0100] In some embodiments, the device generates a feedback signal at 200 at 1450 according to the decoded bits of the amplitude filter output signal. In some embodiments, the feedback signal is added to a subsequent symbol of the input signal to reduce the ISI.

[0101] With reference to Fig.Figure 15 illustrates a schematic diagram depicting an exemplary feedback tap 1500. In one implementation, the feedback tap 1500 comprises a latch 1505, a single-ended-to-differential signal converter 1510, and an amplifier 1550. In this implementation, the single-ended-to-differential signal converter 1510 receives a latch output signal 1515 from the latch 1505 and converts the latch output signal 1515 into the differential signals 1535A and 1535B. In this implementation, the amplifier 1550 amplifies the differential signals 1535A and 1535B to obtain the feedback signals 1565A and 1565B. In one implementation, the feedback tap 1500 is part of the feedback generator 240A or the feedback generator 240B. In one example, the feedback signals 1565A and 1565B are parts of the feedback signal 242A, the feedback signal 245A, the feedback signal 242B, or the feedback signal 245B.

[0102] In one implementation, the latch 1505 comprises an input terminal coupled to an output terminal of a latch in a preceding tap and a clock terminal to receive a clock signal. In this implementation, the latch receives and stores a signal, for example, in response to a "high" state of the clock signal at the input terminal, and maintains the stored signal at the output terminal, for example, in response to a "low" state of the clock signal. In one implementation, the latch 1505 of a first tap is omitted because the feedback tap 1500 shares the latch 1230A or 1230B of the speculative tap 1200.

[0103] In one implementation, the single-ended-to-differential signal converter 1510 comprises i) an input terminal coupled to the output terminal of the latch 1505, ii) a first output terminal, and iii) a second output terminal. In one implementation, an input terminal of the single-ended-to-differential signal converter 1510 of a first tap is coupled to a one-bit output terminal of the decoder 230A or the decoder 230B. In one implementation, the single-ended-to-differential signal converter 1510 comprises a P-transistor Td1 and an N-transistor Td2 coupled together in a transfer-gate topology.In one implementation, a gate electrode of the P-transistor Td1 is coupled to a first supply terminal, to which a first supply voltage (for example, 0 V) ​​is supplied, and a gate electrode of the N-transistor Td3 is coupled to a second supply terminal, to which a second supply voltage (for example, VDD) is supplied. In another implementation, transistors Td1 and Td2 have coupled drain and source electrodes between the input terminal of the single-ended-to-differential signal converter 1510 and the first output terminal of the single-ended-to-differential signal converter 1510. Furthermore, in an implementation of the single-ended-to-differential signal converter 1510, an inverter I15 comprises i) an input terminal coupled to the input terminal of the single-ended-to-differential signal converter 1510 and ii) an output terminal coupled to the second output terminal of the single-ended-to-differential signal converter 1510.In one implementation, the transmission gate formed by transistors Tdl, Td2 delays the latch output signal 1515 (or one bit of the decoded signal 235A or 235B) to obtain a phase-in-phase signal 1535A without inverting a phase, and the inverter I15 inverts the phase of the latch output signal 1515 to obtain a signal with inverted phase 1535B.

[0104] In one implementation, the amplifier 1550 includes input terminals coupled to the output terminals of the single-ended-to-differential signal converter 1510. In this implementation, the amplifier 1550 receives the differential signals 1535A and 1535B at its input terminals and amplifies these differential signals to obtain the feedback signals 1565A and 1565B.

[0105] With reference to Fig. Figure 16 illustrates a timing diagram showing an example of the operation of the feedback tap 1500. Fig. 15. In one implementation, the crossing points P1, P2 of signals 1535A, 1535B are not aligned. These misaligned crossing points P1, P2 distort an eye diagram and degrade sensitivity. However, the single-ended-to-differential signal converter 1510 does not allow independent control of a single crossing point. This means that changing the delay of the transmission gate or inverter I15 changes the crossing points P1, P2 together. Consequently, it is difficult to align a crossing point with the single-ended-to-differential signal converter 1510.

[0106] With reference to Fig.Figure 17 illustrates a schematic diagram depicting an exemplary feedback tap 1700 with a crossover control unit 1720. In some embodiments, the feedback tap 1700 is similar to the feedback tap 1500, except that the feedback tap 1700 includes a crossover control unit 1720 and, instead of the single-ended-to-differential signal converter 1510, includes a single-ended-to-differential signal converter 1710. In some embodiments, the crossover control unit 1720 is coupled between the input terminal of the single-ended-to-differential signal converter 1710 and a gate electrode of transistor Td1 of the single-ended-to-differential signal converter 1710.In some embodiments, the single-ended-to-differential signal converter 1710 is similar to the single-ended-to-differential signal converter 1510, except that a gate electrode of transistor Td1 is coupled to the output terminal of the crossover control unit 1720, a transistor Td3 has been added, and the single-ended-to-differential signal converter 1710 generates the differential signals 1735A and 1735B. Therefore, for the sake of brevity, its repeated description is omitted in this document.

[0107] In one embodiment, the crossover control unit 1720 comprises i) an input terminal coupled to the input terminal of the single-ended-to-differential signal converter 1710 and ii) an output terminal coupled to the gate electrode of transistor Td1. In this configuration, the crossover control unit 1720 receives the latch output signal 1515 (or a bit of the decoded signal 235A or 235B) at the input terminal, delays the latch output signal 1515 (or a bit of the decoded signal 235A or 235B) to obtain a delay control signal 1725, and outputs the delay control signal 1725 at the output terminal. In some embodiments, the delay amount is predetermined or adjustable by means of the crossover control unit 1720.

[0108] In one configuration, transistor Td3 comprises a gate electrode coupled to the output terminal of inverter 115, a drain electrode coupled to transistors Td1 and Td2, and a source electrode coupled to the second supply terminal, where the second supply voltage (for example, VDD) is supplied. Thus, transistor Td3 performs a pull-up operation when signal 1735B is in a "low" state (for example, 0 V).

[0109] In some embodiments, the crossing point control unit 1720 allows the adjustment of a pull-down operation for signal 1735A without interfering with the pull-up operation for signal 1735A. In one example, when the voltage of the latch output signal 1515 (or a bit of the decoded signal 235A or 235B) drops, transistor Td1 is switched off until the voltage of the latch output signal 1515 (or a bit of the decoded signal 235A or 235B) falls below a voltage VDD from which a threshold value of transistor Td1 is subtracted. Consequently, in some embodiments, a falling edge of signal 1735A is delayed without modifying a rising edge of signal 1735A.

[0110] Although the intersection point control unit 1720 and the single-ended-to-differential signal converter 1710 are configured to allow the adjustment of a pull-down operation for signal 1735A without interfering with the pull-up operation for signal 1735A, in some embodiments the intersection point control unit 1720 and the single-ended-to-differential signal converter 1710 are configured differently than described in Fig.Figure 17 shows how to adjust the pull-up operation for signal 1735A without interfering with the pull-down operation for signal 1735A. For example, in some embodiments, an output terminal of the junction control unit 1720 is coupled to a gate electrode of transistor Td2 instead of transistor Td1, a gate electrode of transistor Td1 is coupled to the first supply terminal where the first supply voltage (for example, 0 V or GND) is supplied, and transistor Td3 is configured to perform a pull-down operation instead of a pull-up operation.

[0111] With reference to Fig. Figure 18 illustrates a timing diagram showing an exemplary operation of the feedback tap 1700. Fig. 17 depicts. As in Fig.As shown in Figure 18, the crossing point control unit 1720 enables the independent control of a pull-down operation such that the crossing points P3, P4 of signals 1735A, 1735B are controlled in comparison to the crossing points P1, P2 of signals 1535A, 1535B. Fig. 16 are better aligned. Consequently, in some embodiments, the sensitivity of the receiver device 200 is improved.

[0112] With reference to Fig. Figure 19 illustrates a flowchart depicting an exemplary process 1900 of converting a single-ended signal into differential signals. In some embodiments, the process 1900 is implemented using the feedback tap 1700. Fig. 17. In some embodiments, process 1900 is carried out using other entities (for example, other single-ended-to-differential signal converters). In some embodiments, process 1900 includes more, fewer, or different steps than in Fig. 19 shown.

[0113] In some embodiments, the feedback tap 1700 at 1910 receives an input signal applied to an input of a single-ended-to-differential signal converter. In some embodiments, the input signal is an output of the latch 1505, a one-bit output of the decoder 230, or another circuit arrangement.

[0114] In some embodiments, the feedback tap 1700 at 1920 generates a crossing point control signal according to the received input signal. In one approach, the feedback tap 1700 delays the input signal to obtain the crossing point control signal. In some embodiments, the delay amount is predetermined or adjustable.

[0115] In some embodiments, the feedback tap 1700 at 1930 applies the crossover control signal to a single-ended-to-differential signal converter and, at 1940, converts the input signal into the differential signals according to the crossover control signal. In one approach, the single-ended-to-differential signal converter comprises a transmission gate with i) a P-transistor with one gate electrode to receive the crossover control signal and ii) an N-transistor with one gate electrode to which a supply voltage (for example, VDD) is applied. In some embodiments, by applying the crossover control signal only to the P-transistor, but not to the N-transistor, a falling edge of a signal is matched to the differential signals without altering a rising edge of the signal.

[0116] Although one or more latches for timing circuits are implemented in various embodiments disclosed in this document, some embodiments implement one or more flip-flops to replace the functionality of the latches. In some embodiments, a flip-flop is implemented across two or more latches.

[0117] In some embodiments, a signal comprises multiple bits. In some embodiments, two or more one-bit signals constitute the two-bit or more-bit signal. Similarly, in some embodiments, two or more one-bit components constitute a two-bit or more-bit component. For example, three one-bit latches constitute a three-bit latch. In another example, twelve one-bit output terminals constitute a twelve-bit output terminal.

[0118] Several embodiments disclosed in this document relate to a high-speed communication device. In some embodiments, the device includes a first set of amplitude filters with input terminals for receiving a first input signal. In some embodiments, the first set of amplitude filters is configured to generate a first amplitude filter output signal that includes outputs of the first set of amplitude filters. In some embodiments, the first amplitude filter output signal digitally indicates a level of the first input signal. In some embodiments, the device includes a first speculative tap with input terminals coupled to output terminals of the first set of amplitude filters.In some embodiments, the first speculative tap is configured to select outputs from a subset of the first set of amplitude filters based on a second amplitude filter output signal. In some embodiments, the device includes a first decoder with input terminals coupled to output terminals of the first speculative tap. In some embodiments, the first decoder is configured to decode the selected outputs of the subset of the first set of amplitude filters, present in a first digital representation, into a second digital representation. In some embodiments, the device includes a first feedback generator with input terminals coupled to output terminals of the first decoder and with output terminals coupled to the input terminals of the first set of amplitude filters.In some embodiments, the first feedback generator is configured to generate a first feedback signal according to the decoded outputs of the subset of the first set of amplitude filters shown in the second illustration, and to output the first feedback signal at its output terminals. In some embodiments, the first feedback signal modifies the first input signal.

[0119] In some embodiments, the first speculative tap comprises a first set of multiplexers, which include input terminals coupled to output terminals of the first set of amplitude sieves, and a first set of latches, which include input terminals coupled to output terminals of the first set of multiplexers.

[0120] In some embodiments, the first speculative tap does not include a decoder between the first set of multiplexers and the first set of latches.

[0121] In some embodiments, the device further comprises a second set of amplitude filters, which include input terminals for receiving a second input signal. In some embodiments, the second set of amplitude filters is configured to generate the second amplitude filter output signal, which includes outputs of the second set of amplitude filters. In some embodiments, the second amplitude filter output signal digitally indicates a level of the second input signal. In some embodiments, the device further comprises a second speculative tap, which includes input terminals coupled to output terminals of the second set of amplitude filters. In some embodiments, the second speculative tap is configured to select outputs of a subset of the second set of amplitude filters based on the first amplitude filter output signal.In some embodiments, the device further comprises a second decoder with input terminals coupled to the output terminals of the second speculative tap. In some embodiments, the second decoder is configured to decode the selected outputs of the subset of the second set of amplitude filters present in the first digital representation into the second digital representation. In some embodiments, the device further comprises a second feedback generator with input terminals coupled to the output terminals of the second decoder and with output terminals coupled to the input terminals of the second set of amplitude filters.In some embodiments, the second feedback generator is configured to generate a second feedback signal according to the decoded outputs of the subset of the second set of amplitude filters shown in the second illustration, and to output this second feedback signal at its output terminals. In some embodiments, the second feedback signal modifies the second input signal.

[0122] In some embodiments, the first speculative tap is configured to select the outputs of the subset of the first set of amplitude sieves according to the selected outputs of the subset of the second set of amplitude sieves. In some embodiments, the second speculative tap is configured to select the outputs of the subset of the second set of amplitude sieves according to the selected outputs of the subset of the first set of amplitude sieves.

[0123] In some embodiments, the second speculative tap includes a second set of multiplexers comprising input terminals coupled to output terminals of the second set of amplitude sieves, and a second set of latches comprising input terminals coupled to output terminals of the second set of multiplexers.

[0124] In some embodiments, the output terminals of the first set of multiplexers are directly coupled to the input terminals of the first set of latches. In some embodiments, the output terminals of the second set of multiplexers are directly coupled to the input terminals of the second set of latches. In some embodiments, the output terminals of the first set of latches are directly coupled to the control terminals of the second set of multiplexers. In some embodiments, the output terminals of the second set of latches are directly coupled to the control terminals of the first set of multiplexers.

[0125] In some embodiments, each multiplexer of the first set of multiplexers is controlled according to outputs of the second set of latches, and each multiplexer of the second set of multiplexers is controlled according to outputs of the first set of latches.

[0126] In some embodiments, the first set of latches is clocked according to a clock signal, and the second set of latches is clocked according to an inversion of the clock signal.

[0127] In some embodiments, the device comprises a first feedback tap with input terminals coupled to the output terminals of the first decoder and output terminals coupled to the input terminals of the second set of amplitude filters. In some embodiments, the first feedback tap is configured to generate a third feedback signal according to the decoded outputs of the subset of the first set of amplitude filters and outputs the third feedback signal at its output terminals. In some embodiments, the third feedback signal modifies the second input signal.In some embodiments, the device includes a second feedback tap with input terminals coupled to the output terminals of the second decoder and output terminals coupled to the input terminals of the first set of amplitude filters. In some embodiments, the second feedback tap is configured to generate a fourth feedback signal according to the decoded outputs of the subset of the second set of amplitude filters and outputs the fourth feedback signal at its output terminals. In some embodiments, the fourth feedback signal modifies the first input signal.

[0128] In some embodiments, the first feedback generator comprises a single-ended-to-differential signal converter with i) an input terminal coupled to a corresponding output terminal of the output terminals of the first decoder and ii) differential output terminals. In some embodiments, the single-ended-to-differential signal converter is configured to convert a single-ended signal at the input terminal of the single-ended-to-differential signal converter into differential signals and output the differential signals via the differential output terminals. In some embodiments, the differential signals modify the first input signal.

[0129] In some embodiments, the first feedback generator further comprises a crossover control unit coupled to the input terminal of the single-ended-to-differential signal converter and to a control terminal of the single-ended-to-differential signal converter. In some embodiments, the crossover control unit is configured to delay one of the differential signals from a pull-up or pull-down operation for a first signal without delaying the other of the first signal from the pull-up or pull-down operation.

[0130] In some embodiments, the intersection point control unit includes delay circuits.

[0131] In some embodiments, the device includes a pull-up transistor coupled between one of the differential output terminals and the other of the differential output terminals.

[0132] In some embodiments, the single-ended-to-differential signal converter comprises a P-transistor and an N-transistor connected in parallel between the input terminal of the single-ended-to-differential signal converter and one of the differential output terminals. In some embodiments, a gate electrode of the P-transistor is coupled to an output terminal of the crossover control unit. In some embodiments, a gate electrode of the N-transistor is coupled to a supply terminal to which a supply voltage is provided.

[0133] In some embodiments, the input signal conforms to a PAM4 protocol (Pulse Amplitude Modulated).

[0134] In some embodiments, the first speculative tap includes a multiplexer for selecting one of the selected outputs of the subset of the first set of amplitude filters according to a redundant number of bits of the second amplitude filter output signal.

[0135] Several embodiments disclosed in this document relate to a device for high-speed communication. In some embodiments, the device comprises a latch and a single-ended-to-differential signal converter coupled to the latch. In some embodiments, the single-ended-to-differential signal converter is configured to convert a single-ended signal from the latch into differential signals. In some embodiments, the device comprises a crossover control unit coupled between the latch and the single-ended-to-differential signal converter. In some embodiments, the crossover control unit is configured to delay one of the differential signals from a pull-up or pull-down operation for a first signal without delaying the other from the pull-up or pull-down operation for the first signal.

[0136] In some embodiments, the single-ended-to-differential signal converter comprises a first transistor with a gate electrode controlled by the crossover control unit and a second transistor with a gate electrode coupled to a supply terminal to which a supply voltage is applied. In some embodiments, the first and second transistors are connected in parallel.

[0137] In some embodiments, the device is a feedback tap.

[0138] Several embodiments disclosed in this document relate to high-speed communication. In some embodiments, the device includes a set of amplitude filters configured to generate an amplitude filter output signal that digitally indicates the level of an input signal received by the set of amplitude filters. In some embodiments, the device includes a speculative tap coupled to the set of amplitude filters. In some embodiments, the speculative tap is configured to select bits of the amplitude filter output signal based on a previous amplitude filter output signal. In some embodiments, the speculative tap includes a multiplexer to select a bit from the selected bits of the previous amplitude filter output signal according to a redundant number of bits.In some embodiments, the device includes a decoder coupled to the speculative tap. In some embodiments, the decoder is configured to decode the selected bits of the amplitude filter output signal, present in a first digital representation, into a second digital representation. In some embodiments, the device includes a feedback generator coupled to the decoder. In some embodiments, the feedback generator is configured to generate a feedback signal according to the decoded bits of the amplitude filter output signal. In some embodiments, the feedback signal modifies the input signal.

[0139] Several embodiments disclosed in this document relate to a device for high-speed communication. In some embodiments, the device comprises a comparator with a first input terminal for receiving a first input signal, a reference terminal for receiving a reference signal, and a clock terminal for receiving a clock signal. In some embodiments, the comparator is configured to compare the first input signal with the reference signal according to a pulse of the clock signal. In some embodiments, the device includes a kickback suppression circuit coupled to the first input terminal of the comparator. In some embodiments, the kickback suppression circuit is configured to inject a delayed clock signal into the first input terminal of the comparator.In some embodiments, the delayed clock signal is delayed relative to the clock signal.

[0140] In some embodiments, the comparator is configured to reset a voltage at an output terminal of the comparator in response to a first state of the clock signal, and to change the voltage at the output terminal of the comparator in response to a second state of the clock signal, according to the comparison of the first input signal with the reference signal.

[0141] In some embodiments, the comparator is configured to charge an output terminal of the comparator in response to a first state of the clock signal and to discharge the output terminal of the comparator in response to a second state of the clock signal according to the comparison of the first input signal with the reference signal.

[0142] In some embodiments, the comparator further comprises a first capacitor coupled between the first input terminal of the comparator and the kickback suppression circuit. In some embodiments, the kickback suppression circuit is configured to feed the delayed clock signal into the first input terminal via the first capacitor.

[0143] In some embodiments, the first capacitor is a MOS capacitor (Metal Oxide Semiconductor) or a MOM capacitor (Metal Oxide Metal).

[0144] In some embodiments, the comparator further includes a second input terminal to receive a second input signal. In some embodiments, the comparator is configured to charge one output terminal and another output terminal of the comparator in response to a first state of the clock signal, and to discharge the output terminal and the other output terminal of the comparator at different rates in response to a second state of the clock signal, according to i) a first difference between the first input signal and the reference signal and ii) a second difference between the second input signal and the reference signal.

[0145] In some embodiments, the kickback suppression circuit is configured to feed the delayed clock signal into the second input terminal of the comparator.

[0146] In some embodiments, the kickback suppression circuit is configured to feed the delayed clock signal into the comparator's reference terminal.

[0147] In some embodiments, the input impedances of the first input terminal, the second input terminal, and the reference terminal are matched to each other.

[0148] In some embodiments, the comparator further comprises a first transistor with i) a source electrode, ii) a gate electrode coupled to the first input terminal, and iii) a drain electrode. In some embodiments, the comparator further comprises a second transistor with i) a source electrode coupled to the source electrode of the first transistor, ii) a gate electrode coupled to the reference terminal, and iii) a drain electrode. In some embodiments, the comparator further comprises a third transistor with i) a source electrode, ii) a gate electrode coupled to the second input terminal, and iii) a drain electrode coupled to the drain electrode of the second transistor.In some embodiments, the comparator further comprises a fourth transistor with i) a source electrode coupled to the source electrode of the third transistor, ii) a gate electrode coupled to the reference terminal, and iii) a drain electrode coupled to the drain electrode of the first transistor.

[0149] In some embodiments, the comparator further comprises a fifth transistor with i) a gate electrode coupled to the clock terminal and ii) a drain electrode coupled to the source electrode of the first transistor and the source electrode of the second transistor. In some embodiments, the comparator further comprises a sixth transistor with i) a gate electrode coupled to the clock terminal and ii) a drain electrode coupled to the source electrode of the third transistor and the source electrode of the fourth transistor.

[0150] In some embodiments, the comparator further comprises a seventh transistor with i) a gate electrode coupled to the clock terminal and ii) a drain electrode coupled to the drain electrode of the second transistor and the drain electrode of the third transistor. In some embodiments, the comparator further comprises an eighth transistor with i) a gate electrode coupled to the clock terminal and ii) a drain electrode coupled to the drain electrode of the first transistor and the drain electrode of the fourth transistor.

[0151] In some embodiments, the device further comprises an SR latch configured to amplify a voltage difference between a first and second output terminal of the comparator. In some embodiments, the SR latch includes a sampling circuit coupled to the first and second output terminals of the comparator. In some embodiments, the sampling circuit is configured to sample the voltage difference between the first and second output terminals of the comparator according to the clock signal. In some embodiments, the SR latch includes a regeneration circuit coupled to a first and second output terminal of the sampling circuit. In some embodiments, the regeneration circuit amplifies the sampled voltage difference coming from the sampling circuit.

[0152] In some embodiments, the sampling circuit comprises cross-coupled transistors connected to the first and second output terminals of the sampling circuit, and a switching transistor connected in series with the cross-coupled transistors. In some embodiments, the switching transistor is configured to enable or disable current flow through the cross-coupled transistors according to the clock signal.

[0153] In some embodiments, the sampling circuit further comprises a first transistor with i) a gate electrode coupled to the first output terminal of the comparator and ii) a drain electrode coupled to the second output terminal of the sampling circuit and the cross-coupled transistors. In some embodiments, the sampling circuit further comprises a second transistor with i) a gate electrode coupled to the second output terminal of the comparator and ii) a drain electrode coupled to the first output terminal of the sampling circuit and the cross-coupled transistors.

[0154] In some embodiments, the regeneration circuit further comprises a first transistor and a second transistor coupled to each other at a first output terminal of the regeneration circuit. In some embodiments, the regeneration circuit further comprises a third transistor and a fourth transistor coupled to each other at a second output terminal of the regeneration circuit. In some embodiments, the first transistor is controlled by a voltage at the first output terminal of the sampling circuit. In some embodiments, the fourth transistor is controlled by an inverse of the voltage at the first output terminal of the sampling circuit. In some embodiments, the third transistor is controlled by a voltage at the second output terminal of the sampling circuit.In some embodiments, the second transistor is controlled according to the inverse of the voltage at the second output terminal of the sampling circuit. In some embodiments, the regeneration circuit further comprises cross-coupled inverters coupled between the first output terminal and the second output terminal of the regeneration circuit.

[0155] In some embodiments, the device is an amplitude filter circuit.

[0156] Several embodiments disclosed in this document relate to a device for high-speed communication. In some embodiments, the device comprises a sampling circuit configured to sample a voltage difference at input terminals of the sampling circuit in accordance with a clock signal. In some embodiments, the device comprises a regeneration circuit coupled to output terminals of the sampling circuit. In some embodiments, the regeneration circuit is configured to amplify the sampled voltage difference. In some embodiments, the regeneration circuit comprises a first transistor and a second transistor coupled to each other at a first output terminal of the regeneration circuit.In some embodiments, the regeneration circuit comprises a third transistor and a fourth transistor, which are coupled to each other at a second output terminal of the regeneration circuit. In some embodiments, the first transistor is controlled by a voltage at a first output terminal of the sampling circuit. In some embodiments, the fourth transistor is controlled by an inverse of the voltage at the first output terminal of the sampling circuit. In some embodiments, the third transistor is controlled by a voltage at a second output terminal of the sampling circuit. In some embodiments, the second transistor is controlled by an inverse of the voltage at the second output terminal of the sampling circuit.In some embodiments, the voltage at the first output terminal of the sampling circuit differs from the reciprocal of the voltage at the second output terminal of the sampling circuit.

[0157] In some embodiments, the regeneration circuit further comprises a first inverter coupled between the first output terminal of the regeneration circuit and a gate electrode of the fourth transistor, and a second inverter coupled between the second output terminal of the regeneration circuit and a gate electrode of the second transistor.

[0158] In some embodiments, the device is a latch circuit.

[0159] Several embodiments disclosed in this document relate to a device. In some embodiments, the device comprises a first-stage circuit configured to discharge, in response to a clock signal, output terminals of the first-stage circuit according to a voltage difference of input signals at different discharge rates. In some embodiments, the device comprises a second-stage circuit coupled to the first-stage circuit. In some embodiments, the second-stage circuit is configured to sample voltages at the output terminals of the first-stage circuit according to the different discharge rates and to generate a first pulse signal and a second pulse signal according to the sampled voltages.In some embodiments, the first and second pulse signals indicate which output terminal of the first-stage circuit discharges faster. In some embodiments, the device includes a sampling circuit coupled to the second-stage circuit. In some embodiments, the sampling circuit is configured to generate an output signal in response to a first state of the clock signal, based on a voltage difference between the first and second pulse signals, and to maintain the output signal in response to a second state of the clock signal. In some embodiments, the device includes a regeneration circuit coupled to the sampling circuit and configured to amplify the output signal.

[0160] Several embodiments disclosed in this document relate to a device for high-speed communication. In some embodiments, the device includes a comparator configured to compare an input signal at an input terminal with a reference signal at a reference terminal according to a pulse of a clock signal at a clock terminal, and, based on the comparison, to generate an output signal indicating the level of the input signal. In some embodiments, the device includes a kickback suppression circuit coupled to the comparator. In some embodiments, the kickback suppression circuit is configured to inject a delayed clock signal into the input terminal. In some embodiments, the delayed clock signal is delayed relative to the clock signal. B. Computer and network environment

[0161] After discussing specific implementation examples of the present solution, it may be helpful to describe aspects of the operating environment and the associated system components (e.g., hardware elements) in connection with the methods and systems described in this document. With reference to Fig. Figure 20A shows an embodiment of a network environment. In short, the network environment comprises a communication system that includes one or more network devices 2006, one or more communication devices 2002, and a node 2092. The communication devices 2002 may include, for example, laptop computers 2002, tablets 2002, PCs 2002, and / or mobile phone devices 2002. In some embodiments, the device 2002, the network device 2006, the node 2092, or any combination thereof is referred to as the communication device 110. Fig.1 implemented. The details of an exemplary embodiment of a respective communication device and / or network device are provided with reference to Fig. 20B and Fig. Section 20C describes this in more detail. The network environment can be an ad-hoc network environment, a network environment with infrastructure, a subnet environment, etc.

[0162] The Network Devices 2006 can be operatively connected to the Node 2092 via local area network connections. The Node 2092, which may include a router, gateway, switch, bridge, modem, system control unit, appliance, etc., can provide a local area network connection for the communication system. Each of the Network Devices 2006 can include an attached antenna or antenna array to communicate with the Communication Devices 2002 within its range. The Communication Devices 2002 can register with a specific Network Device 2006 to receive services from the communication system (for example, via a SU-MIMO or MU-MIMO configuration (Single-User Multiple-Input and Multiple-Output or Multi-User Multiple-Input and Multiple-Output, respectively)).In direct connections (for example, in point-to-point communication), some communication devices can communicate directly over an allocated channel and an allocated communication protocol. Some of the communication devices can be mobile or relatively static with respect to the network device.

[0163] In some embodiments, a network device 2006 comprises a device or module (including a combination of hardware and software) that allows communication devices 2002 to connect to a wired network using WiFi or other standards. A network device 2006 may be configured, designed, and / or constructed to operate in a wireless local area network (WLAN). In some embodiments, a network device 2006 may connect to a router as a standalone device (for example, via a wired network). In other embodiments, a network device may be a component of a router. A network device 2006 may provide access to a network for multiple devices 2002.A Network Device 2006 can, for example, connect to Devices 2002 via a wired Ethernet connection, a wireless WiFi connection, or both. A Network Device 2006 can be built and / or configured to support a standard for sending and receiving data using one or more radio frequencies. These standards and the frequencies they use may be defined by the IEEE (for example, IEEE 802.11 standards). A Network Device can be configured and / or used to support public internet hotspots and / or an internal network to extend the network's WiFi signal range.

[0164] In some embodiments, the network devices 2006 (for example, in homes or buildings) can be used for wireless networks (for example, IEEE 802.11, Bluetooth, ZigBee, any other types of radio frequency-based network protocols and / or variants thereof). Each of the communication devices 2002 may include and / or be coupled with a built-in radio device. Such communication devices 2002 and / or network devices 2006 can be operated according to the various manifestations of the disclosure as set forth in this document to achieve an improvement in performance, a reduction in cost and / or size, and / or an improvement in broadband applications.Any communication device 2002 can have the capability to function as a client node that wants to access resources (for example, data and a connection to network nodes, such as servers) via one or more network devices 2006.

[0165] The network connections can comprise any type and / or form of network or network, and they can include any of the following: a point-to-point network, a broadcast network, a telecommunications network, a data communications network, and a computer network. The network topology can be a bus, star, or ring topology. The network can have any such network topology known to those skilled in the art with normal knowledge in this field and capable of supporting the operations described in this document. In some embodiments, different types of data can be transmitted over different protocols. In other embodiments, the same types of data can be transmitted over different protocols.

[0166] The Node 2092, the Communication Device(s) 2002 and Network Device(s) 2006 can be provided as any type and form of computer device, such as a computer, network device or appliance, capable of communicating in any type and form of network and performing the operations described in this document, or being executed as such. Fig. 20B and Fig. Section 20C depicts block diagrams of a computer device 2000, which is helpful in carrying out an embodiment of the node 2092, the communication devices 2002, or the network device 2006. As shown in Fig. 20B and Fig. As shown in Figure 20C, each computer device 2000 comprises a central processing unit (CPU) 2021 and a main memory unit 2022. As shown in Fig.As shown in Figure 20B, a computer device 2000 can include a storage device 2028, an installation device 2016, a network interface 2018, an I / O control unit 2023, display devices 2024a to 2024n, a keyboard 2026, and a pointing device 2027, such as a mouse. The storage device 2028 can include, but is not limited to, an operating system and / or software. As shown in Fig. As shown in Figure 20C, each computer device 2000 may also include additional optional elements, such as a memory port 2003, a bridge 2070, one or more input / output devices 2030a to 2030n (generally referred to by reference 2030) and a cache memory 2040 associated with the central processing unit 2021.

[0167] The central processing unit 2021 is any logic circuit arrangement that responds to and processes instructions retrieved from the main memory unit 2022. In many embodiments, the central processing unit 2021 is provided by means of a microprocessor unit, such as those manufactured by Intel Corporation of Santa Clara, California (USA); those manufactured by International Business Machines of White Plains, New York (USA); or those manufactured by Advanced Micro Devices of Sunnyvale, California (USA). The computer device 2000 can be based on any of these processors or on any other processor capable of operating as described in this document.

[0168] The main memory unit 2022 can consist of one or more memory chips capable of storing data and allowing direct access to any memory location by the microprocessor 2021, such as any type or variant of SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FRAM (Ferroelectric RAM), NAND flash memory, NOR flash memory, and SSD (Solid State Drives). The main memory 2022 can be based on any of the memory chips described above or on any other available memory chips capable of operating as described in this document. In the Fig.In the embodiment shown in Figure 20B, the processor 2021 communicates with the main memory 2022 via a system bus 2050 (this is described in more detail below). Fig. Figure 20C depicts an embodiment of a computer device 2000 in which the processor communicates directly with the main memory 2022 via a memory port 2003. Fig. For example, in the case of 20C, the main memory in 2022 could be DRDRAM.

[0169] Fig.Figure 20C illustrates an embodiment in which the main processor 2021 communicates directly with the cache memory 2040 via a secondary bus, sometimes also referred to as a backside bus. In other embodiments, the main processor 2021 communicates with the cache memory 2040 using the system bus 2050. The cache memory 2040 typically has a shorter response time than the main memory 2022 and is implemented, for example, using SRAM, BSRAM, or EDRAM. In the embodiment shown in Fig.In the embodiment shown in Figure 20C, the processor 2021 communicates with various I / O devices 2030 via a local system bus 2050. Different buses can be used to connect the central processing unit 2021 to any of the I / O devices 2030, for example, a VESA VL bus, an ISA bus, an EISA bus, an MCA bus (MicroChannel Architecture), a PCI bus, a PCI-X bus, a PCI Express bus, or a NuBus. In embodiments where the I / O device is a video display device 2024, the processor 2021 can use an AGP (Advanced Graphics Port) to communicate with the display device 2024. Fig. Figure 20C represents an embodiment of a Computer 2000 in which the main processor 2021 can communicate directly with the I / O device 2030b, for example via HYPERTRANSPORT, RA-PIDIO or INFINIBAND communication technology. Fig.Figure 20C also shows an embodiment in which local buses and direct communication are mixed: The processor 2021 communicates with the I / O device 2030a using a local interconnect bus, while it communicates directly with the I / O device 2030b.

[0170] The Computer Device 2000 can contain a wide variety of I / O devices 2030a to 2030n. Input devices include keyboards, mice, trackpads, trackballs, microphones, dial devices, touchpads, touchscreens, and drawing tablets. Output devices include video display devices, speakers, inkjet printers, laser printers, projectors, and sublimation printers. The I / O devices can be configured as described in Fig.As shown in Figure 20B, the computer device 2000 can be controlled by means of an I / O control unit 2023. The I / O control unit can control one or more I / O devices, such as a keyboard 2026 and a pointing device 2027, for example, a mouse or an optical pen. Furthermore, an I / O device can also provide memory and / or an installation medium 216 for the computer device 2000. In further embodiments, the computer device 2000 can provide USB ports (not shown) to accommodate handheld USB storage devices, such as the USB flash drive series manufactured by Twintech Industry, Inc. of Los Alamitos, California (USA).

[0171] With further reference to Fig.20B The computer device 2000 can support any suitable installation device 2016, such as a disk drive, a CD-ROM drive, a CD-R / RW drive, a DVD-ROM drive, a flash memory drive, tape drives of various formats, a USB device, a hard disk drive, a network interface, or any other device suitable for installing software and programs. The computer device 2000 can also include a storage device, such as one or more hard disk drives or RAIDs (Redundant Arrays of Independent Disks), for storing an operating system and other related software and for storing application software programs, such as any program or software 2020 for implementing the systems and procedures described in this document (for example, configured and / or designed for them).Optionally, any of the 2016 installation devices could also be used as storage devices. Additionally, the operating system and software could be run from a bootable medium.

[0172] Furthermore, the computer device 2000 may include a network interface 2018 for forming an interface with the network 2004 via a variety of connections, including, but not limited to, standard telephone lines, LAN or WAN connections (for example, 802.11, T1, T3, 56 Kbit / s, X.25, SNA, DECNET), broadband connections (for example, ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet-over-SONET), wireless connections, or some combination of any or all of the above. Connections can be established using a variety of communication protocols (for example, TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, FDDI (Fiber Distributed Data Interface), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax and asynchronous direct connections).In one embodiment, the computer device 2000 communicates with other computer devices 2000 via any type and / or form of gateway or tunneling protocol, such as SSL (Secure Socket Layer) or TLS (Transport Layer Security). The network interface 2018 may include a built-in network adapter, a network interface card, a PCMCIA network card, a CardBus network adapter, a wireless network adapter, a USB network adapter, a modem, or any other device suitable for providing an interface between the computer device 2000 and any other type of network capable of communication and performing the operations described in this document.

[0173] In some embodiments, the computer device 2000 may include or be connected to one or more display devices 2024a to 2024n. In such a way, any of the I / O devices 2030a to 2030n and / or the I / O control unit 2023 may include any type and / or form of suitable hardware, software, or a combination of hardware and software to support, enable, or provide for the connection and use of the display device(s) 2024a to 2024n by the computer device 2000. For example, the computer device 2000 may include any type and / or form of video adapter, video card, driver, and / or library to interface with, communicate with, connect to, or otherwise use the display device(s) 2024a to 2024n. In one embodiment, a video adapter may include multiple ports to interface with the display device(s).to form the display device(s) 2024a to 2024n. In other embodiments, the computer device 2000 may comprise multiple video adapters, each video adapter being connected to the display device(s) 2024a to 2024n. In some embodiments, any part of the operating system of the computer device 2000 may be configured to use multiple display devices 2024a to 2024n. A person skilled in the art with normal knowledge in the field will recognize and understand the various possibilities and embodiments by which a computer device 2000 can be configured to have one or more display devices 2024a to 2024n.

[0174] In other embodiments, an I / O device 2030 can be a bridge between the system bus 2050 and an external communication bus, such as a USB bus, an Apple Desktop bus, a serial RS-232 connection, a SCSI bus, a FireWire bus, a FireWire 800 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an ATM bus (Asynchronous Transfer Mode), a FibreChannel bus, a SAS bus (Serial Attached SCSI (Small Computer System Interface)), a USB connection or an HDMI bus.

[0175] A computer device 2000 of the type used in Fig. 20B and Fig.The computer device shown in Figure 20C can be operated under the control of an operating system that manages task scheduling and access to system resources. The Computer Device 2000 can run any operating system, such as any version of Microsoft Windows, the various releases of Unix and Linux, any version of Mac OS for Macintosh computers, any embedded operating system, any real-time operating system, any open-source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on the computer device and performing the operations described in this document. Typical operating systems include, but are not limited to, Android, manufactured by Google Inc.; WINDOWS 7 and 8, manufactured by Microsoft Corporation of Redmond, Washington (USA); MAC OS, manufactured by Apple Computer of Cupertino, California (USA); WebOS, manufactured by Research In Motion (RIM); OS / 2, manufactured by International Business Machines of Armonk, New York (USA); and Linux, a freely available operating system distributed by Caldera Corp. of Salt Lake City, Utah (USA), or any type and / or form of Unix operating system, as well as others.

[0176] The Computer System 2000 can be any workstation, telephone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunications device, media player, gaming system, mobile computing device, or any other type and / or form of computer, telecommunications, or media device capable of communication. The Computer System 2000 must have sufficient processing power and memory capacity to perform the operations described in this document.

[0177] In some embodiments, the Computer Device 2000 may include various processors, operating systems, and input devices consistent with the device. For example, in one embodiment, the Computer Device 2000 may be a smartphone, a mobile device, a tablet, or a digital personal assistant. In still other embodiments, the Computer Device 2000 may be an Android-based mobile device, an iPhone smartphone manufactured by Apple Computer of Cupertino, California (USA), or a handheld device or smartphone based on Blackberry or WebOS, such as the devices manufactured by Research In Motion Limited.Furthermore, the computer device 2000 can be any workstation, any desktop computer, any laptop or notebook computer, any server, any handheld computer, any mobile phone, any other computer, or any other form of computer or telecommunications device capable of communication and possessing sufficient processing power and memory capacity to perform the operations described in this document.

[0178] Although the disclosure may refer to one or more “users”, such “users” may refer to devices associated with a user or users, for example, consistent with the terms “user” and “multi-user”, which are typically used, for example, in the context of a MU-MIMO (Multi-User Multiple-Input and Multiple-Output) environment.

[0179] Although examples of the communication systems described above may include devices and network devices that can be operated according to the PAM4-DFE protocol, it should be understood that embodiments of the described systems and procedures may be operated according to other standards.

[0180] It should be noted that in certain passages of this disclosure, reference may be made to terms such as "first" and "second" in connection with devices, a mode of operation, transmission chains, antennas, etc., to identify these elements or to distinguish one of these elements from another or from others. It is not intended that these terms merely relate units (for example, a first device and a second device) to one another temporally or according to a sequence, although these units may in some cases involve such a relationship. Nor do these terms limit the number of possible units (for example, devices) that may be operated within a system or environment.

[0181] It should be understood that the systems described above can include several or all of these components, and that these components can be located either on a standalone machine or, in some embodiments, on multiple machines in a distributed system. Additionally, the systems and methods described above can be implemented as one or more computer-readable programs or executable instructions on or in one or more products. The product can be a floppy disk, a hard disk, a CD-ROM, a flash memory card, a PROM, a RAM, a ROM, or a magnetic tape. Generally, the computer-readable programs can be implemented in any programming language, such as LISP, PERL, C, C++, C#, PROLOG, or in any bytecode language, such as JAVA.The software programs or executable instructions can be stored in or on one or more products as object code.

Claims

[1] Device comprising the following: a first set of amplitude filters (210A) comprising input terminals for receiving a first input signal, wherein the first set of amplitude filters (210A) is configured to generate a first amplitude filter output signal comprising outputs of the first set of amplitude filters (210A), wherein the first amplitude filter output signal digitally indicates a level of the first input signal; a first speculative tap (220A) which includes input terminals coupled to output terminals of the first set of amplitude sieves (210A) for receiving the first amplitude sieve output signal, control terminals for receiving an output of a second speculative tap (220B) and output terminals for outputting an output of the first speculative tap (220A), wherein the first speculative tap (220A) is configured to select outputs of a subset of the first set of amplitude sieves (210A) based on the output of the second speculative tap (220B) received at the control terminals; a first decoder (230A) comprising input terminals coupled to the output terminals of the first speculative tap (220A), wherein the first decoder (230A) is configured to decode the selected outputs of the subset of the first set of amplitude sieves (210A), present in a first digital representation, into a second digital representation; and a first feedback generator comprising the following: Input terminals coupled to the output terminals of the first decoder (230A) and Output terminals coupled to the input terminals of the first set of amplitude filters (210A), wherein the first feedback generator is configured to generate a first feedback signal according to the decoded outputs of the subset of the first set of amplitude filters (210A) and outputs the first feedback signal at its output terminals. [2] Device according to claim 1, wherein the first speculative tap (220A) comprises: a first set of multiplexers comprising input terminals coupled to output terminals of the first set of amplitude sieves (210A), and a first set of latches comprising input terminals coupled to output terminals of the first set of multiplexers. [3] Device according to claim 2, wherein the first speculative tap (220A) does not include a decoder between the first set of multiplexers and the first set of latches. [4] Device according to claim 2, further comprising: a second set of amplitude filters (210B) comprising input terminals for receiving a second input signal, wherein the second set of amplitude filters (210B) is configured to generate the second amplitude filter output signal, which comprises outputs of the second set of amplitude filters (210B), wherein the second amplitude filter output signal digitally indicates a level of the second input signal; a second speculative tap (220B) comprising input terminals coupled to output terminals of the second set of amplitude sieves (210B), wherein the second speculative tap (220B) is configured to select outputs of a subset of the second set of amplitude sieves (210B) based on the first amplitude sieve output signal; a second decoder (230B) comprising input terminals coupled to output terminals of the second speculative tap (220B), wherein the second decoder (230B) is configured to decode the selected outputs of the subset of the second set of amplitude sieves (210B) present in the first digital representation into the second digital representation; and a second feedback generator, comprising the following: Input terminals coupled with output terminals of the second decoder (230B) and Output terminals coupled to the input terminals of the second set of amplitude sieves (210B), wherein the second feedback generator is configured to generate a second feedback signal according to the decoded outputs of the subset of the second set of amplitude sieves (210B) and output the second feedback signal at its output terminals. [5] Device according to claim 4, wherein the first speculative tap (220A) is configured to select the outputs of the subset of the first set of amplitude sieves (210A) according to the selected outputs of the subset of the second set of amplitude sieves (210B), and wherein the second speculative tap (220B) is configured to select the outputs of the subset of the second set of amplitude sieves (210B) according to the selected outputs of the subset of the first set of amplitude sieves (210A). [6] Device according to claim 4, wherein the second speculative tap (220B) comprises: a second set of multiplexers comprising input terminals coupled to output terminals of the second set of amplitude sieves (210B), and a second set of latches comprising input terminals coupled to the output terminals of the second set of multiplexers. [7] Device according to claim 6, where the output terminals of the first The set of multiplexers are directly coupled to the input terminals of the first set of latches and wherein the output terminals of the second set of multiplexers are directly coupled to the input terminals of the second set of latches. [8] Device according to claim 7, where the output terminals of the first set of latches are directly coupled to the control terminals of the second set of multiplexers and where the output terminals of the second set of latches are directly coupled to the control terminals of the first set of multiplexers. [9] Device comprising the following: a first set of amplitude filters (210A) configured to generate a first amplitude filter output signal that digitally indicates a level of a first input signal received by means of the first set of amplitude filters (210A); a second set of amplitude filters (210B) configured to generate a second amplitude filter output signal that digitally indicates a level of a second input signal received by means of the second set of amplitude filters (210B); a first speculative tap (220A) coupled with the first set of amplitude sieves (210A), a second speculative tap (220B) coupled with the second set of amplitude sieves (210B), wherein the first speculative tap (220A) is configured to select bits of the first amplitude filter output signal based on an output of the second speculative tap (220B); wherein the second speculative tap (220B) is configured to select bits of the second amplitude filter output signal based on an output of the first speculative tap (220A), and a decoder (230A) coupled to the first speculative tap (220A), wherein the decoder (230A) is configured to decode the selected bits of the first amplitude filter output signal, which are present in a first digital representation, into a second digital representation. [10] Device according to claim 9, wherein the first set of amplitude sieves (210A) is operated according to a clock signal and the second set of amplitude sieves (210B) is operated according to an inverted clock signal.

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