Image sensing device and method of operating the same

Abstract

The present application relates to an image sensing device and an operation method thereof. An image sensing device includes: a first sampling circuit adapted to sample a reference ramp signal as a ramp signal; a switch circuit adapted to sequentially output a first pixel signal and a second pixel signal to a common node based on a first control signal and a second control signal; a second sampling circuit adapted to sample the first pixel signal and the second pixel signal sequentially output through the common node as measurement signals; a comparison circuit adapted to compare the ramp signal with the measurement signals and generate a comparison signal corresponding to the comparison result; and a counting circuit adapted to generate a counting signal corresponding to the voltage level of the measurement signal based on the comparison signal and a clock signal.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to semiconductor design technologies, and more particularly, to an image sensing device and an operating method thereof. Background Art

[0002] An image sensing device is a device for capturing an image by utilizing the property of a semiconductor to react to light. Image sensing devices can be roughly classified into charge-coupled device (CCD) image sensing devices and complementary metal-oxide-semiconductor (CMOS) image sensing devices. Recently, CMOS image sensing devices have been widely used because they allow both analog control circuits and digital control circuits to be directly implemented on a single integrated circuit (IC). Summary of the Invention

[0003] Various embodiments of the present disclosure relate to an image sensing device capable of converting a plurality of pixel signals through a single analog-to-digital (A / D) conversion operation and an operating method of the image sensing device.

[0004] According to one embodiment, an image sensing device may include: a first sampling circuit adapted to sample a reference ramp signal as a ramp signal; a switch circuit adapted to sequentially output a first pixel signal and a second pixel signal to a common node based on a first control signal and a second control signal; a second sampling circuit adapted to sample the first pixel signal and the second pixel signal sequentially output through the common node as a measurement signal; a comparison circuit adapted to compare the ramp signal with the measurement signal and generate a comparison signal corresponding to the comparison result; and a counting circuit adapted to generate a count signal corresponding to the voltage level of the measurement signal based on the comparison signal and a clock signal.

[0005] The measurement signal may have a voltage level corresponding to a voltage level difference between the first pixel signal and the second pixel signal.

[0006] According to another embodiment, an image sensing device may include: a first sampling circuit adapted to sample a first reference ramp signal as a first ramp signal; a second sampling circuit adapted to sample a second reference ramp signal as a second ramp signal; a first switching circuit adapted to output a first pixel signal and a second pixel signal to a first common node according to a first order based on a first control signal and a second control signal; a third sampling circuit adapted to sample the first pixel signal and the second pixel signal output through the first common node as a first measurement signal; a second switching circuit adapted to output the first pixel signal and the second pixel signal to a second common node according to a second order opposite to the first order based on a third control signal and a fourth control signal; a fourth sampling circuit adapted to sample the first pixel signal and the second pixel signal output through the second common node as a second measurement signal; a comparison circuit adapted to simultaneously compare the first ramp signal with the first measurement signal and the second ramp signal with the second measurement signal, and generate a comparison signal corresponding to the comparison result; and a counting circuit adapted to generate a counting signal corresponding to the voltage level of the first measurement signal and the voltage level of the second measurement signal based on the comparison signal and a clock signal.

[0007] The first measurement signal may have a first voltage level obtained by subtracting the voltage level of the first pixel signal from the voltage level of the second pixel signal, and the second measurement signal may have a second voltage level obtained by subtracting the voltage level of the second pixel signal from the voltage level of the first pixel signal.

[0008] According to another embodiment, an image sensing device may include: a pair of pixels adapted to generate a first pixel signal and a second pixel signal; and a signal converter adapted to generate a depth information signal corresponding to a voltage level difference between the first pixel signal and the second pixel signal through a single analog-to-digital conversion operation.

[0009] According to another embodiment, an operation method of an image sensing device may include: sampling a reference ramp signal as a ramp signal; sequentially sampling a pair of pixel signals indicating the depth from an object as measurement signals; generating a comparison signal corresponding to a voltage difference between the pair of pixel signals based on the ramp signal and the measurement signals; and generating a depth information signal based on the comparison signal. Description of the Drawings

[0010] Figure 1 is a block diagram illustrating an image sensing device according to an embodiment.

[0011] Figure 2 illustrates Figure 1 a circuit diagram of a pair of pixels of the pixel array shown.

[0012] Figure 3illustrates Figure 1 A block diagram of an example of the signal converter shown.

[0013] Figure 4 illustrates Figure 3 A circuit diagram of the first sampling circuit, the second sampling circuit, the switch circuit, and the comparison circuit shown.

[0014] Figure 5 illustrates Figure 1 A block diagram of another example of the signal converter shown.

[0015] Figure 6 illustrates Figure 5 A circuit diagram of the first sampling circuit, the second sampling circuit, the third sampling circuit, the fourth sampling circuit, the first switch circuit, the second switch circuit, and the comparison circuit shown.

[0016] Figures 7 to 12 illustrates Figure 1 A timing diagram of the operation of the image sensing device shown. Detailed implementation

[0017] The following describes various embodiments of the present disclosure with reference to the accompanying drawings to describe the present disclosure in detail so that those of ordinary skill in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure.

[0018] It will be understood that when an element is referred to as "connected to" or "coupled to" another element, the element can be directly connected to or coupled to the other element, or electrically connected to or coupled to the other element in the case where one or more elements are interposed therebetween. Additionally, it will also be understood that unless otherwise mentioned, when the terms "comprise," "comprised of," "include," and "included of" are used in this specification, they do not exclude the presence of one or more other elements, but may further include or have one or more other elements. Throughout the description in the specification, some components are described in the singular form, but the present disclosure is not limited thereto, and it will be understood that these components can be formed into multiple.

[0019] Figure 1 A block diagram illustrating the image sensing device 100 according to one embodiment.

[0020] Referring to Figure 1 , the image sensing device 100 can generate a depth information signal DOUT indicating the depth from the object 200 using the time-of-flight (TOF) method. For example, the image sensing device 100 can generate the depth information signal DOUT by detecting the phase difference between the first optical signal MS output to the object 200 and the second optical signal RS reflected from the object 200.

[0021] The image sensing device 100 may include a light emitter 110, a row controller 130, a phase controller 140, a pixel array 150, a ramp signal generator 160, and a signal converter 170.

[0022] The light emitter 110 may output a first light signal MS to the object 200. For example, the first light signal MS may be a periodic signal that flips periodically. The first light signal MS may be reflected from the object 200 and received by the pixel array 150 as a second light signal RS.

[0023] The row controller 130 may generate a plurality of row control signals CTRL for controlling the pixel array 150 for each row. For example, the row controller 130 may generate a first row control signal for controlling the pixels arranged in the first row of the pixel array 150, and generate an nth row control signal for controlling the pixels arranged in the nth row of the pixel array 150, where "n" is a natural number greater than 2.

[0024] The phase controller 140 may generate a first control signal MIXA and a second control signal MIXB having different phases. For example, the first control signal MIXA and the second control signal MIXB may have a phase difference of 180 degrees. The first control signal MIXA and the second control signal MIXB may have the same period as the first light signal MS, and either the first control signal MIXA or the second control signal MIXB may have the same phase as the first light signal MS.

[0025] The pixel array 150 may receive the second light signal RS, the plurality of row control signals CTRL, and the first control signal MIXA and the second control signal MIXB, and generate a plurality of pixel signals VPX. The pixel array 150 may receive background light together with the second light signal RS. The pixel array 150 may include at least a pair of pixels for measuring the depth from the object 200. For example, a pair of pixels may be selected based on the plurality of row control signals CTRL, and the pair of pixels generates a first pixel signal VPXA and a second pixel signal VPXB based on the first control signal MIXA and the second control signal MIXB and the second light signal RS. The first control signal MIXA and the second control signal MIXB may be signals having a phase difference of 180 degrees. Refer to Figure 2 A more detailed description of the pair of pixels will be given.

[0026] The ramp signal generator 160 may generate at least one reference ramp signal. According to one example, the ramp signal generator 160 may generate a reference ramp signal VRAMPI. According to another example, the ramp signal generator 160 may generate a first reference ramp signal VRAMPI and a second reference ramp signal VRAMPII. The first reference ramp signal VRAMPI and the second reference ramp signal VRAMPII may ramp in opposite directions within the same ramp range.

[0027] The signal converter 170 may generate a depth information signal DOUT based on at least one reference ramp signal and a plurality of pixel signals VPX. For example, the signal converter 170 may generate a depth information signal DOUT corresponding to the voltage level difference between a first pixel signal VPXA and a second pixel signal VPXB through a single analog-to-digital (A / D) conversion operation.

[0028] Figure 2 is an example of a circuit diagram of a pair of pixels referred to in the Figure 1 description.

[0029] Referring to Figure 2 , the pair of pixels may include a first pixel TAPA and a second pixel TAPB. The pair of pixels receiving control signals MIXA and MIXB are adapted to generate a first pixel signal and a second pixel signal indicating the depth from an object.

[0030] The first pixel TAPA may generate a first pixel signal VPXA based on a reset signal RX, a transmission signal TX, a selection signal SX, and a first control signal MIXA. The reset signal RX, the transmission signal TX, and the selection signal SX may be signals included in the above-mentioned plurality of row control signals CTRL. For example, the first pixel TAPA may include a first sensing circuit P1, a first transmission circuit TT1, a first charge storage circuit PC1, a first reset circuit RT1, a first driving circuit DT1, and a first selection circuit ST1.

[0031] The first sensing circuit P1 may be coupled between the first transmission circuit TT1 and a low voltage terminal. The first sensing circuit P1 may generate a first charge corresponding to a second optical signal RS and background light based on the first control signal MIXA. For example, the first sensing circuit P1 may include a photodiode.

[0032] The first transmission circuit TT1 may be coupled between a first floating diffusion node FD1 and the first sensing circuit P1. The first transmission circuit TT1 may couple the first reset circuit RT1 to the first charge storage circuit PC1 when the first sensing circuit P1 is reset, or transmit the first charge generated by the first sensing circuit P1 to the first charge storage circuit PC1 based on the transmission signal TX. For example, the first transmission circuit TT1 may include an NMOS transistor.

[0033] The first charge storage circuit PC1 can be connected between the first floating diffusion node FD1 and the low-voltage terminal. For example, the first charge storage circuit PC1 can be a parasitic capacitor.

[0034] The first reset circuit RT1 can be connected between the first high-voltage terminal and the first sensing circuit P1. The first reset circuit RT1 can reset the first sensing circuit P1 and the first charge storage circuit PC1 based on the reset signal RX. For example, the first reset circuit RT1 can include an NMOS transistor.

[0035] The first driving circuit DT1 can be connected between the second high-voltage terminal and the first selection circuit ST1. The second high-voltage terminal can be the same as or different from the first high-voltage terminal. The first driving circuit DT1 can drive the first column line COL1 with a high voltage provided through the second high-voltage terminal based on the voltage applied to the first floating diffusion node FD1. For example, the first driving circuit DT1 can include an NMOS transistor.

[0036] The first selection circuit ST1 can be connected between the first driving circuit DT1 and the first column line COL1. The first selection circuit ST1 can selectively connect the first driving circuit DT1 to the first column line COL1 based on the selection signal SX. For example, the first selection circuit ST1 can include an NMOS transistor.

[0037] The second pixel TAPB can generate a second pixel signal VPXB based on the reset signal RX, the transmission signal TX, the selection signal SX, and the second control signal MIXB. For example, the second pixel TAPB can include a second sensing circuit P2, a second transmission circuit TT2, a second charge storage circuit PC2, a second reset circuit RT2, a second driving circuit DT2, and a second selection circuit ST2.

[0038] The second sensing circuit P2 can be connected between the second transmission circuit TT2 and the low-voltage terminal. The second sensing circuit P2 can generate a second charge corresponding to the second optical signal RS and the background light based on the second control signal MIXB. For example, the second sensing circuit P2 can include a photodiode.

[0039] The second transmission circuit TT2 can be connected between the second floating diffusion node FD2 and the second sensing circuit P2. The second transmission circuit TT2 can connect the second reset circuit RT2 to the second charge storage circuit PC2 when the second sensing circuit P2 is reset, or transmit the second charge generated by the second sensing circuit P2 to the second charge storage circuit PC2 based on the transmission signal TX. For example, the second transmission circuit TT2 can include an NMOS transistor.

[0040] The second charge storage circuit PC2 can be connected between the second floating diffusion node FD2 and the low-voltage terminal. For example, the second charge storage circuit PC2 can be a parasitic capacitor.

[0041] The second reset circuit RT2 can be connected between the first high-voltage terminal and the second sensing circuit P2. The second reset circuit RT2 can reset the second sensing circuit P2 and the second charge storage circuit PC2 based on the reset signal RX. For example, the second reset circuit RT2 can include an NMOS transistor.

[0042] The second drive circuit DT2 can be connected between the second high-voltage terminal and the second selection circuit ST2. The second drive circuit DT2 can drive the second column line COL2 using the high voltage provided through the second high-voltage terminal based on the voltage applied to the second floating diffusion node FD2. For example, the second drive circuit DT2 can include an NMOS transistor.

[0043] The second selection circuit ST2 can be connected between the second drive circuit DT2 and the second column line COL2. The second selection circuit ST2 can selectively connect the second drive circuit DT2 to the second column line COL2 based on the selection signal SX. For example, the second selection circuit ST2 can include an NMOS transistor.

[0044] Figure 3 is an illustration of Figure 1 a block diagram of an example of the signal converter 170 shown in Figure 3 Only the configuration corresponding to a pair of pixels is illustrated.

[0045] Referring to Figure 3 , the signal converter 170 can include a first sampling circuit C0, a switch circuit SC, a second sampling circuit C1, a comparison circuit 171, and a counting circuit 173.

[0046] The first sampling circuit C0 can sample the reference ramp signal VRAMPI and generate a ramp signal VREFP. For example, the first sampling circuit C0 can include a capacitor.

[0047] The switch circuit SC can sequentially output the first pixel signal VPXA and the second pixel signal VPXB to the common node CN as the pixel signal VIN based on the first control signal SW0_A and the second control signal SW0_B.

[0048] The second sampling circuit C1 can sample the pixel signal VIN sequentially output through the common node CN and output the sampled pixel signal as the measurement signal VINN. For example, the second sampling circuit C1 can include a capacitor.

[0049] The comparison circuit 171 may have a 2-input / 2-output structure. For example, the comparison circuit 171 may have a non-inverting (+) input terminal that receives the ramp signal VREFP, an inverting (-) input terminal that receives the measurement signal VINN, and an output terminal that outputs the comparison signal VOUTP. This embodiment describes that the comparison circuit 171 has a first output terminal and a second output terminal, but an example where the comparison signal VOUTP is output through the first output terminal among the first output terminal and the second output terminal.

[0050] The comparison circuit 171 may compare the ramp signal VREFP with the measurement signal VINN and output a comparison signal VOUTP corresponding to the comparison result. For example, the comparison circuit 171 may generate a comparison signal VOUTP corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB through a single comparison operation.

[0051] The counting circuit 173 may generate a count signal corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB based on the comparison signal VOUTP and the clock signal CLK as the depth information signal DOUT.

[0052] Figure 4 is illustrated Figure 3 The circuit diagram of the first sampling circuit C0, the switch circuit SC, the second sampling circuit C1, and the comparison circuit 171 shown.

[0053] Referring to Figure 4 , the first sampling circuit C0 may output a ramp signal VREFP having the same waveform as the reference ramp signal VRAMPI to the non-inverting (+) input terminal of the comparison circuit 171 during a single rolling readout period CC.

[0054] The switch circuit SC may include a first switch element S0 and a second switch element S1. The first switch element S0 may output one of the first pixel signal VPXA and the second pixel signal VPXB (i.e., VPXA) to the common node CN during the transition period RR of a single rolling readout period CC based on the first control signal SW_A. For example, the first switch element S0 may output the first pixel signal VPXA to the common node CN during the transition period RR. The second switch element S1 may output the other pixel signal of the first pixel signal VPXA and the second pixel signal VPXB (i.e., VPXB) to the common node CN during the auto-zero period ZZ of a single rolling readout period CC based on the second control signal SW_B. For example, the second switch element S1 may output the second pixel signal VPXB to the common node CN during the auto-zero period ZZ.

[0055] The second sampling circuit C1 can generate a measurement signal VINN corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB according to the first pixel signal VPXA and the second pixel signal VPXB sequentially input during a single rolling readout period CC.

[0056] The comparison circuit 171 can include a current supply circuit CL, an input circuit IN, a sink circuit CS, a third switching element S2, and a fourth switching element S3.

[0057] The current supply circuit CL can be connected between a high-voltage terminal and a pair of output terminals NN and PP.

[0058] The input circuit IN can be connected between the pair of output terminals NN and PP and the node CCN. The input circuit IN can receive the measurement signal VINN and the ramp signal VREFP. For example, the input circuit IN can include a first input element and a second input element. The first input element can be connected between the first output terminal PP among the pair of output terminals NN and PP and the node CCN, and receive the measurement signal VINN. The second input element can be connected between the second output terminal NN among the pair of output terminals NN and PP and the node CCN, and receive the ramp signal VREFP.

[0059] The sink circuit CS can be connected between the node CCN and the low-voltage terminal.

[0060] The third switching element S2 can be connected between the non-inverting (+) input terminal and the second output terminal NN. The third switching element S2 can pre-charge the non-inverting (+) input terminal to a predetermined voltage level VAZ during the auto-zero period ZZ based on a third control signal SW_AZ. The predetermined voltage level VAZ can correspond to the gate-source voltage Vgs of the diode-connected PMOS transistor included in the current supply circuit CL.

[0061] The fourth switching element S3 can be connected between the inverting (-) input terminal and the first output terminal PP. The fourth switching element S3 can pre-charge the inverting (-) input terminal to a predetermined voltage level VAZ during the auto-zero period ZZ based on the third control signal SW_AZ.

[0062] Figure 5 is illustrated Figure 1 Another example block diagram of the signal converter 170 shown.

[0063] Refer to Figure 5 , the signal converter 170 can include a first sampling circuit C0, a first switching circuit SC0, a second sampling circuit C1, a second switching circuit SC1, a third sampling circuit C2, a fourth sampling circuit C3, a comparison circuit 171, and a counting circuit 173.

[0064] The first sampling circuit C0 can sample the first reference ramp signal VRAMPI and generate a first ramp signal VREFP. For example, the first sampling circuit C0 can include a capacitor.

[0065] The first switch circuit SC0 can output a first pixel signal VPXA and a second pixel signal VPXB to the first common node CN0 based on a first control signal SW0_A and a second control signal SW0_B according to a first order. For example, the first switch circuit SC0 can output the second pixel signal VPXB to the first common node CN0 and then output the first pixel signal VPXA to the first common node CN0 in sequence.

[0066] The second sampling circuit C1 can sample the pixel signal VIN<0> output through the first common node CN0 according to the first order and output the sampled pixel signal as a first measurement signal VINN. For example, the second sampling circuit C1 can include a capacitor.

[0067] The second switch circuit SC1 can output a first pixel signal VPXA and a second pixel signal VPXB to the second common node CN1 based on a third control signal SW1_A and a fourth control signal SW1_B according to a second order opposite to the first order. For example, the second switch circuit SC1 can output the first pixel signal VPXA to the second common node CN1 and then output the second pixel signal VPXB to the second common node CN1 in sequence.

[0068] The third sampling circuit C2 can sample the pixel signal VIN<1> output through the second common node CN1 according to the second order and output the sampled pixel signal as a second measurement signal VINP. For example, the third sampling circuit C2 can include a capacitor.

[0069] The fourth sampling circuit C3 can sample the second reference ramp signal VRAMPII and generate a second ramp signal VREFN. The second reference ramp signal VRAMPII can ramp in a direction opposite to that of the first reference ramp signal VRAMPI. For example, the fourth sampling circuit C3 can include a capacitor.

[0070] The comparison circuit 171 may have a 4-input / 2-output structure. For example, the comparison circuit 171 may have a first non-inverting (+) input terminal for receiving a first ramp signal VREFP, a first inverting (-) input terminal for receiving a first measurement signal VINN, a second non-inverting (+) input terminal for receiving a second measurement signal VINP, a second inverting (-) input terminal for receiving a second ramp signal VREFN, and an output terminal for outputting a comparison signal VOUTP. This embodiment describes that the comparison circuit 171 has a first output terminal and a second output terminal, but an example of outputting the comparison signal VOUTP through the first output terminal among the first output terminal and the second output terminal is given.

[0071] The comparison circuit 171 can simultaneously compare the first ramp signal VREFP with the first measurement signal VINN and the second ramp signal VREFN with the second measurement signal VINP, and output a comparison signal VOUTP corresponding to the comparison result. For example, the comparison circuit 171 can generate a comparison signal VOUTP corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB through a single comparison operation.

[0072] The counting circuit 173 can generate a count signal corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB as a depth information signal DOUT based on the comparison signal VOUTP and the clock signal CLK.

[0073] Figure 6 is an illustration of Figure 5 the circuit diagrams of the first sampling circuit C0, the second sampling circuit C1, the third sampling circuit C2, the fourth sampling circuit C3, the first switch circuit SC0, the second switch circuit SC1, and the comparison circuit 171 shown.

[0074] Referring to Figure 6 , during a single rolling readout period CC, the first sampling circuit C0 can output a first ramp signal VREFP having the same waveform as the first reference ramp signal VRAMPI to the first non-inverting (+) input terminal of the comparison circuit 171.

[0075] The first switching circuit SC0 may include a first switching element S0 and a second switching element S1. The first switching element S0 may output either the first pixel signal VPXA or the second pixel signal VPXB to the first common node CN0 during the transition period RR of a single rolling readout period CC based on the first control signal SW0_A. For example, the first switching element S0 may output the first pixel signal VPXA to the first common node CN0 during the transition period RR. The second switching element S1 may output the other one of the first pixel signal VPXA and the second pixel signal VPXB to the first common node CN0 during the auto-zero period ZZ of a single rolling readout period CC based on the second control signal SW0_B. For example, the second switching element S1 may output the second pixel signal VPXB to the first common node CN0 during the auto-zero period ZZ.

[0076] The second sampling circuit C1 may output a first measurement signal VINN corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB to the first inverting (-) input terminal of the comparison circuit 171 during a single rolling readout period CC according to the first pixel signal VPXA and the second pixel signal VPXB input in the first order. That is, the second sampling circuit C1 may generate a first measurement signal VINN having a voltage level obtained by subtracting the voltage level of the first pixel signal VPXA from the voltage level of the second pixel signal VPXB.

[0077] The second switching circuit SC1 may include a third switching element S2 and a fourth switching element S3. The third switching element S2 may output either the first pixel signal VPXA or the second pixel signal VPXB to the second common node CN1 during the auto-zero period ZZ of a single rolling readout period CC based on the third control signal SW1_A. The third control signal SW1_A may be the same signal as the second control signal SW0_B. For example, the third switching element S2 may output the first pixel signal VPXA to the second common node CN1 during the auto-zero period ZZ. The fourth switching element S3 may output the other one of the first pixel signal VPXA and the second pixel signal VPXB to the second common node CN1 during the transition period RR of a single rolling readout period CC based on the fourth control signal SW1_B. The fourth control signal SW1_B may be the same signal as the first control signal SW0_A. For example, the fourth switching element S3 may output the second pixel signal VPXB to the second common node CN1 during the transition period RR.

[0078] The third sampling circuit C2 can output a second measurement signal VINP corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB to the second non-inverting (+) input terminal of the comparison circuit 171 during a single rolling readout period CC according to the first pixel signal VPXA and the second pixel signal VPXB input in the second order. That is to say, the third sampling circuit C2 can generate a second measurement signal VINP, and the second measurement signal VINP has a voltage level obtained by subtracting the voltage level of the second pixel signal VPXB from the voltage level of the first pixel signal VPXA.

[0079] The fourth sampling circuit C3 can output a second ramp signal VREFN having the same waveform as the second reference ramp signal VRAMPII to the second inverting (-) input terminal of the comparison circuit 171 during a single rolling readout period CC.

[0080] The comparison circuit 171 can include a current supply circuit CL, a first input circuit IN0, a first sink circuit CS0, a fifth switching element S4, a second input circuit IN1, a second sink circuit CS1, and a sixth switching element S5.

[0081] The current supply circuit CL can be connected between the high-voltage terminal and a pair of output terminals NN and PP.

[0082] The first input circuit IN0 can be connected between the pair of output terminals NN and PP and the first node CCN0. The first input circuit IN0 can receive the first measurement signal VINN and the first ramp signal VREFP. For example, the first input circuit IN0 can include a first input element and a second input element. The first input element can be connected between the first output terminal PP of the pair of output terminals NN and PP and the first node and receive the first measurement signal VINN. The second input element can be connected between the second output terminal NN of the pair of output terminals NN and PP and the first node and receive the first ramp signal VREFP.

[0083] The first sink circuit CS0 can be connected between the first node and the low-voltage terminal.

[0084] The fifth switching element S4 can be connected between the first non-inverting (+) input terminal and the second output terminal NN. The fifth switching element S4 can pre-charge the first non-inverting (+) input terminal to a predetermined voltage level VAZ during the auto-zero period ZZ based on the fifth control signal SW_AZ. The predetermined voltage level VAZ can correspond to the gate-source voltage Vgs of the diode-connected PMOS transistor included in the current supply circuit CL.

[0085] The second input circuit IN1 can be connected between a pair of output terminals NN and PP and a second node CCN1. The second input circuit IN1 can receive a second measurement signal VINP and a second ramp signal VREFN. For example, the second input circuit IN1 can include a third input element and a fourth input element. The third input element can be connected between the first output terminal PP of the pair of output terminals NN and PP and the second node, and receive the second ramp signal VREFN. The fourth input element can be connected between the second output terminal NN of the pair of output terminals NN and PP and the second node, and receive the second measurement signal VINP.

[0086] The second sinking circuit CS1 can be connected between the second node and the low voltage terminal.

[0087] The sixth switching element S5 can be connected between the second inverting (-) input terminal and the first output terminal PP. The sixth switching element S5 can pre-charge the second inverting (-) input terminal to a predetermined voltage level VAZ during the auto-zero period ZZ based on the fifth control signal SW_AZ.

[0088] Hereinafter, refer to Figures 7 to 12 Describe the operation of the image sensing device 100 according to the present embodiment having the above configuration.

[0089] First, refer to Figures 7 to 9 Describe the operation of the image sensing device 100 according to an example.

[0090] Figure 7 is a timing diagram illustrating a case where the voltage (hereinafter referred to as "first voltage VFD1") applied to the first floating diffusion node FD1 is higher than the voltage (hereinafter referred to as "second voltage VFD2") applied to the second floating diffusion node FD2.

[0091] Refer to Figure 7 , during the reset period AA, the first voltage VFD1 and the second voltage VFD2 can have a reset level VRST. The reset level VRST can correspond to the high voltage provided through the first high voltage terminal. The voltage level of the first voltage VFD1 can change to a first target level during the integration time BB, and the voltage level of the second voltage VFD2 can change to a second target level during the integration time BB. During a single rolling readout period CC, the first voltage VFD1 and the second voltage VFD2 can be read out as a first pixel signal VPXA and a second pixel signal VPXB, respectively. In this case, the change amount ΔVFD1 of the voltage level of the first voltage VFD1 can be smaller than the change amount ΔVFD2 of the voltage level of the second voltage VFD2.

[0092] Figure 8 is an illustration of the image sensing device 100 according toFigure 7 A timing diagram of an operation example of a single rolling readout period CC shown. It can be seen that Figure 8 illustrates including Figure 3 and Figure 4 A timing diagram of the operation of the image sensing device 100 including the circuit shown.

[0093] Referring to Figure 8 , during the auto - zero period ZZ, the switch circuit SC can output the second pixel signal VPXB to the common node CN based on the second control signal SW_B. During the conversion period RR, the switch circuit SC can output the first pixel signal VPXA to the common node CN based on the first control signal SW_A. The pixel signal VIN generated through the common node CN can have a voltage level corresponding to the second pixel signal VPXB during the auto - zero period ZZ, and have a voltage level corresponding to the first pixel signal VPXA during the conversion period RR. The measurement signal VINN can have a voltage level corresponding to the predetermined voltage VAZ during the auto - zero period ZZ, and during the conversion period RR, have the voltage level to which the predetermined voltage VAZ, the voltage level of the second pixel signal VPXB, and the voltage level of the first pixel signal VPXA are applied, that is, VAZ+(VPXA - VPXB).

[0094] The comparison circuit 171 can compare the ramp signal VREFP with the measurement signal VINN during the conversion period RR, and allow the comparison signal VOUTP to transition at the time VT1 when the ramp signal VREFP and the measurement signal VINN have the same voltage level, as the comparison result.

[0095] The counting circuit 173 can generate a count signal corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB based on the comparison signal VOUTP and the clock signal CLK, as the depth information signal DOUT.

[0096] Figure 9 illustrates another example of the operation of the image sensing device 100 according to Figure 7 the single rolling readout period CC shown. It can be seen that Figure 9 illustrates including Figure 5 and Figure 6 A timing diagram of the operation of the image sensing device 100 including the circuit shown.

[0097] Referring to Figure 9, during the auto - zero period ZZ, the first switch circuit SC0 can output the second pixel signal VPXB to the first common node CN0 based on the second control signal SW0_B. During the conversion period RR, the first switch circuit SC0 can output the first pixel signal VPXA to the first common node CN0 based on the first control signal SW0_A. The pixel signal VIN<0> generated through the first common node CN0 can have a voltage level corresponding to the second pixel signal VPXB during the auto - zero period ZZ, and have a voltage level corresponding to the first pixel signal VPXA during the conversion period RR. The first measurement signal VINN can have a voltage level corresponding to the predetermined voltage VAZ during the auto - zero period ZZ, and have the voltage level to which the predetermined voltage VAZ, the voltage level of the second pixel signal VPXB, and the voltage level of the first pixel signal VPXA are applied during the conversion period RR, that is, VAZ+(VPXA - VPXB).

[0098] During the auto - zero period ZZ, the second switch circuit SC1 can output the first pixel signal VPXA to the second common node CN1 based on the third control signal SW1_A. During the conversion period RR, the second switch circuit SC1 can output the second pixel signal VPXB to the second common node CN1 based on the fourth control signal SW1_B. The pixel signal VIN<1> generated through the second common node CN1 can have a voltage level corresponding to the first pixel signal VPXA during the auto - zero period ZZ, and have a voltage level corresponding to the second pixel signal VPXB during the conversion period RR. The second measurement signal VINP can have a voltage level corresponding to the predetermined voltage VAZ during the auto - zero period ZZ, and have the voltage level to which the predetermined voltage VAZ, the voltage level of the first pixel signal VPXA, and the voltage level of the second pixel signal VPXB are applied during the conversion period RR, that is, VAZ+(VPXB - VPXA).

[0099] The comparison circuit 171 can generate a comparison signal VOUTP during the conversion period RR based on the first ramp signal VREFP, the second ramp signal VREFN, the first measurement signal VINN, and the second measurement signal VINP. The comparison signal VOUTP can transition at a time VT11 when the first ramp signal VREFP and the first measurement signal VINN have the same voltage level and the second ramp signal VREFN and the second measurement signal VINP have the same voltage level. For example, the comparison circuit 171 can compare the dual - ramp signal (i.e., VREFP - VREFN) with the dual - measurement signal (i.e., 2×(VPXA - VPXB)) and generate a comparison signal VOUTP corresponding to the comparison result. Since the dual - measurement signal (i.e., 2×(VPXA - VPXB)) is used to generate the comparison signal VOUTP, so compared withFigure 3 and Figure 4 Compared with the comparison signal VOUTP shown, the signal-to-noise ratio (SNR) of the comparison signal VOUTP can be improved.

[0100] The counting circuit 173 can generate a counting signal corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB based on the comparison signal VOUTP and the clock signal CLK, as the depth information signal DOUT.

[0101] Next, refer to Figures 10 to 12 The operation of the image sensing device 100 will be described according to another example.

[0102] Figure 10 is a timing diagram illustrating a case where the voltage level of the first voltage VFD1 is lower than the voltage level of the second voltage VFD2.

[0103] Refer to Figure 10 , during the reset period AA, the first voltage VFD1 and the second voltage VFD2 can have a reset level VRST. The voltage level of the first voltage VFD1 can be changed to a third target level during the integration time BB, and the voltage level of the second voltage VFD2 can be changed to a fourth target level during the integration time BB. During a single rolling readout period CC, the first voltage VFD1 and the second voltage VFD2 can be read out as the first pixel signal VPXA and the second pixel signal VPXB, respectively. In this case, the change amount ΔVFD1 of the voltage level of the first voltage VFD1 can be greater than the change amount ΔVFD2 of the voltage level of the second voltage VFD2.

[0104] Figure 11 is a timing diagram illustrating an operation example of the image sensing device 100 according to Figure 10 the single rolling readout period CC shown. It can be seen that Figure 11 is a timing diagram illustrating an operation of the image sensing device 100 including Figure 3 and Figure 4 the circuits shown.

[0105] Refer to Figure 11, during the auto - zero period ZZ, the switch circuit SC can output a second pixel signal VPXB to the common node CN based on the second control signal SW_B. During the conversion period RR, the switch circuit SC can output a first pixel signal VPXA to the common node CN based on the first control signal SW_A. The pixel signal VIN generated through the common node CN can have a voltage level corresponding to the second pixel signal VPXB during the auto - zero period ZZ and a voltage level corresponding to the first pixel signal VPXA during the conversion period RR. Thus, through the second sampling circuit C1, the measurement signal VINN can have a predetermined voltage VAZ and the voltage level to which the voltage level of the second pixel signal VPXB is applied, e.g., VAZ - VPXB, during the auto - zero period ZZ, and can have a predetermined voltage VAZ, the voltage level of the second pixel signal VPXB, and the voltage level to which the voltage level of the first pixel signal VPXA is applied, e.g., VAZ - VPXB+VPXA, during the conversion period RR.

[0106] The comparison circuit 171 can compare the ramp signal VREFP and the measurement signal VINN during the conversion period RR and allow the comparison signal VOUTP to transition at the time VT2 when the ramp signal VREFP and the measurement signal VINN have the same voltage level, as the comparison result.

[0107] The counting circuit 173 can generate a count signal corresponding to the voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB based on the comparison signal VOUTP and the clock signal CLK as the depth information signal DOUT.

[0108] Figure 12 is an example showing the operation of the image sensing device 100 according to Figure 10 a single rolling readout period CC as shown. It can be seen that Figure 12 is an example showing the operation of the image sensing device 100 including Figure 5 and Figure 6 the circuits as shown.

[0109] Referring to Figure 12, during the auto - zero period ZZ, the first switch circuit SC0 can output a second pixel signal VPXB to the first common node CN0 based on the second control signal SW0_B. During the conversion period RR, the first switch circuit SC0 can output a first pixel signal VPXA to the first common node CN0 based on the first control signal SW0_A. The pixel signal VIN<0> generated through the first common node CN0 can have a voltage level corresponding to the second pixel signal VPXB during the auto - zero period ZZ, and a voltage level corresponding to the first pixel signal VPXA during the conversion period RR. Thus, through the second sampling circuit C1, the first measurement signal VINN can have a predetermined voltage VAZ and the voltage level to which the voltage level of the second pixel signal VPXB is applied, for example, VAZ - VPXB, during the auto - zero period ZZ, and have a predetermined voltage VAZ, the voltage level of the second pixel signal VPXB, and the voltage level to which the voltage level of the first pixel signal VPXA is applied, for example, VAZ - VPXB+VPXA, during the conversion period RR.

[0110] During the auto - zero period ZZ, the second switch circuit SC1 can output a first pixel signal VPXA to the second common node CN1 based on the third control signal SW1_A. During the conversion period RR, the second switch circuit SC1 can output a second pixel signal VPXB to the second common node CN1 based on the fourth control signal SW1_B. The pixel signal VIN<1> generated through the second common node CN1 can have a voltage level corresponding to the first pixel signal VPXA during the auto - zero period ZZ, and a voltage level corresponding to the second pixel signal VPXB during the conversion period RR. Thus, through the third sampling circuit C2, the second measurement signal VINP can have a predetermined voltage VAZ and the voltage level to which the voltage level of the first pixel signal VPXA is applied, for example, VAZ - VPXA, during the auto - zero period ZZ, and have a predetermined voltage VAZ, the voltage level of the first pixel signal VPXA, and the voltage level to which the voltage level of the second pixel signal VPXB is applied, for example, VAZ - VPXA+VPXB, during the conversion period RR.

[0111] The comparison circuit 171 can compare the first ramp signal VREFP and the second ramp signal VREFN with the first measurement signal VINN and the second measurement signal VINP respectively during the conversion period RR, and allow the comparison signal VOUTP to transition at the time VT22 when the first ramp signal VREFP and the first measurement signal VINN have the same voltage level and the second ramp signal VREFN and the second measurement signal VINP have the same voltage level, as the comparison result.

[0112] The counting circuit 173 may generate a count signal corresponding to a voltage level difference between the first pixel signal VPXA and the second pixel signal VPXB based on the comparison signal VOUTP and the clock signal CLK as the depth information signal DOUT.

[0113] According to an embodiment of the present disclosure, a single analog-to-digital (A / D) conversion operation may be performed on the first pixel signal and the second pixel signal, and as a result of the single A / D conversion operation, a depth information signal of a voltage level difference between the first pixel signal and the second pixel signal may be obtained. In addition, since the voltage level difference between the first pixel signal and the second pixel signal is used during the single A / D conversion operation, background light reflected in each of the first pixel signal and the second pixel signal may be canceled out.

[0114] According to an embodiment of the present disclosure, a plurality of pixel signals are converted through a single analog-to-digital (A / D) conversion operation, thereby reducing an occupied area of a circuit (i.e., a signal converter) related to the A / D conversion operation and reducing time and power consumption during the A / D conversion operation.

[0115] Although the present disclosure has been illustrated and described with reference to specific embodiments, the disclosed embodiments are provided for description only and are not intended to be limiting. In addition, it should be noted that, as will be recognized by those skilled in the art from the present disclosure, the present disclosure may be implemented in various ways by substitutions, changes, and modifications falling within the scope of the appended claims.

[0116] Cross-reference to related applications

[0117] This application claims priority to Korean Patent Application No. 10-2021-0047962, filed on April 13, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensing device, the image sensing device comprising: A first sampling circuit that samples a reference ramp signal into a ramp signal; A switching circuit that sequentially outputs a first pixel signal and a second pixel signal to a common node based on a first control signal and a second control signal; A second sampling circuit that samples the first pixel signal and the second pixel signal sequentially output through the common node into a measurement signal; A comparison circuit that compares the ramp signal with the measurement signal and generates a comparison signal corresponding to the comparison result; And A counting circuit that generates a count signal corresponding to the voltage level of the measurement signal based on the comparison signal and a clock signal.

2. The image sensing device according to claim 1, wherein, The measurement signal has a voltage level corresponding to the voltage level difference between the first pixel signal and the second pixel signal.

3. The image sensing device according to claim 1, wherein, The switching circuit includes: A first switching element that outputs either the first pixel signal or the second pixel signal to the common node based on the first control signal during an auto-zero period of a single rolling readout period; and A second switching element that outputs the other of the first pixel signal and the second pixel signal to the common node based on the second control signal during a conversion period of the single rolling readout period.

4. The image sensing device according to claim 1, wherein, The comparison circuit includes: A non-inverting input terminal that receives the ramp signal; An inverting input terminal that receives the measurement signal; and An output terminal that outputs the comparison signal.

5. The image sensing device according to claim 1, the image sensing device further comprising a pair of pixels, the pair of pixels generating the first pixel signal and the second pixel signal indicating the depth from an object.

6. An image sensing device, the image sensing device comprising: A first sampling circuit that samples a first reference ramp signal into a first ramp signal; A second sampling circuit that samples a second reference ramp signal into a second ramp signal; A first switching circuit that outputs a first pixel signal and a second pixel signal to a first common node according to a first order based on a first control signal and a second control signal; A third sampling circuit that samples the first pixel signal and the second pixel signal output through the first common node into a first measurement signal; A second switching circuit that outputs the first pixel signal and the second pixel signal to a second common node according to a second order opposite to the first order based on a third control signal and a fourth control signal; A fourth sampling circuit that samples the first pixel signal and the second pixel signal output through the second common node into a second measurement signal; A comparison circuit that simultaneously compares the first ramp signal with the first measurement signal and the second ramp signal with the second measurement signal and generates a comparison signal corresponding to the comparison result; And A counting circuit that generates a count signal corresponding to the voltage level of the first measurement signal and the voltage level of the second measurement signal based on the comparison signal and a clock signal.

7. The image sensing device according to claim 6, wherein, The first measurement signal has a first voltage level obtained by subtracting the voltage level of the first pixel signal from the voltage level of the second pixel signal, and Wherein, the second measurement signal has a second voltage level obtained by subtracting the voltage level of the second pixel signal from the voltage level of the first pixel signal.

8. The image sensing device according to claim 6, wherein, The first switching circuit includes: A first switching element that outputs either the first pixel signal or the second pixel signal to the first common node during an auto-zero period of a single rolling readout period based on the first control signal; and A second switching element that outputs the other of the first pixel signal and the second pixel signal to the first common node during a conversion period of the single rolling readout period based on the second control signal, and Wherein, the second switching circuit includes: A third switching element that outputs the other of the first pixel signal and the second pixel signal to the second common node during the auto-zero period of the single rolling readout period based on the third control signal; and A fourth switching element that outputs either of the first pixel signal and the second pixel signal to the second common node during the conversion period of the single rolling readout period based on the fourth control signal.

9. The image sensing device according to claim 6, wherein, The comparison circuit includes: A first non-inverting input terminal that receives the first ramp signal; A first inverting input terminal that receives the first measurement signal; A second non-inverting input terminal that receives the second measurement signal; A second inverting input terminal that receives the second ramp signal; and An output terminal that outputs the comparison signal.

10. The image sensing device according to claim 6, wherein, The first ramp signal and the second ramp signal ramp in opposite directions within the same ramp range.

11. The image sensing device according to claim 6, the image sensing device further comprising a pair of pixels that generate the first pixel signal and the second pixel signal indicating the depth from the object.

12. An image sensing device, the image sensing device comprising: A pair of pixels that generate a first pixel signal and a second pixel signal; And A signal converter that generates a depth information signal through a single analog-to-digital conversion operation, the depth information signal corresponding to a voltage level difference between the first pixel signal and the second pixel signal, wherein the single analog-to-digital conversion operation compares at least one reference ramp signal with a signal corresponding to the voltage level difference between the first pixel signal and the second pixel signal.

13. The image sensing device according to claim 12, wherein, The signal converter includes: A first sampling circuit that samples a reference ramp signal as a ramp signal; A switching circuit that sequentially outputs a first pixel signal and a second pixel signal to a common node based on a first control signal and a second control signal; A second sampling circuit that samples the first pixel signal and the second pixel signal sequentially output through the common node as measurement signals; A comparison circuit that compares the ramp signal with the measurement signals and generates a comparison signal corresponding to the comparison result; and A counting circuit that generates a counting signal corresponding to the voltage level of the measurement signal as a depth information signal based on the comparison signal and a clock signal.

14. The image sensing device according to claim 13, wherein, The measurement signal has a voltage level corresponding to the voltage level difference between the first pixel signal and the second pixel signal.

15. The image sensing device according to claim 13, wherein, The switch circuit includes: A first switch element that outputs either the first pixel signal or the second pixel signal to the common node during an auto-zero period of a single rolling readout period based on the first control signal; and A second switch element that outputs the other of the first pixel signal and the second pixel signal to the common node during a conversion period of the single rolling readout period based on the second control signal.

16. The image sensing device according to claim 13, wherein, The comparison circuit includes: A non-inverting input terminal that receives the ramp signal; An inverting input terminal that receives the measurement signal; and An output terminal that outputs the comparison signal.

17. The image sensing device according to claim 12, wherein, The signal converter includes: A first sampling circuit that samples a first reference ramp signal as a first ramp signal; A second sampling circuit that samples a second reference ramp signal as a second ramp signal; A first switch circuit that outputs the first pixel signal and the second pixel signal to a first common node according to a first order based on a first control signal and a second control signal; A third sampling circuit that samples the first pixel signal and the second pixel signal output through the first common node as a first measurement signal; A second switch circuit that outputs the first pixel signal and the second pixel signal to a second common node according to a second order opposite to the first order based on a third control signal and a fourth control signal; A fourth sampling circuit that samples the first pixel signal and the second pixel signal output through the second common node as a second measurement signal; A comparison circuit that simultaneously compares the first ramp signal and the second ramp signal with the first measurement signal and the second measurement signal and generates a comparison signal corresponding to the comparison result; and A counting circuit that generates a count signal corresponding to the voltage level of the first measurement signal and the voltage level of the second measurement signal as the depth information signal based on the comparison signal and a clock signal.

18. The image sensing device according to claim 17, wherein, The first measurement signal has a first voltage level obtained by subtracting the voltage level of the first pixel signal from the voltage level of the second pixel signal, and wherein the second measurement signal has a second voltage level obtained by subtracting the voltage level of the second pixel signal from the voltage level of the first pixel signal.

19. The image sensing device according to claim 17, wherein, The first switch circuit includes: A first switch element that outputs either the first pixel signal or the second pixel signal to the first common node during an auto-zero period of a single rolling readout period based on the first control signal; and a second switching element that outputs, based on the second control signal, the other one of the first pixel signal and the second pixel signal to the first common node during a conversion period of the single rolling readout period, and wherein the second switching circuit includes: a third switching element that outputs, based on the third control signal, the other one of the first pixel signal and the second pixel signal to the second common node during an auto-zero period of the single rolling readout period; and a fourth switching element that outputs, based on the fourth control signal, any one of the first pixel signal and the second pixel signal to the second common node during a conversion period of the single rolling readout period.

20. The image sensing device according to claim 17, wherein, The comparison circuit includes: a first non-inverting input terminal that receives the first ramp signal; a first inverting input terminal that receives the first measurement signal; a second non-inverting input terminal that receives the second measurement signal; a second inverting input terminal that receives the second ramp signal; and an output terminal that outputs the comparison signal.

21. The image sensing device according to claim 17, wherein, The first ramp signal and the second ramp signal ramp in opposite directions within the same ramp range.

22. An operation method of an image sensing device, the operation method comprising the following steps: Sampling a reference ramp signal as a ramp signal; Sequentially sampling a pair of pixel signals indicating a depth from an object as measurement signals; Generating a comparison signal corresponding to a voltage difference between the pair of pixel signals based on the ramp signal and the measurement signal; and Generating a depth information signal based on the comparison signal.

Images