Data verification platform and data verification method thereof, and computer readable storage medium

Abstract

The application provides a data verification platform and a data verification method and a computer readable storage medium thereof, the data verification platform comprises at least two groups of extension modules and a master control module connected with the extension modules; the extension module is used for receiving the data of the project to be verified and verifying the data of the project to be verified; the master control module is used for compiling a basic data file related to the data of the project to be verified and detecting the running state of the extension module; when it is detected that the extension module which has verified the data of the project to be verified is in an occupied state and another group of extension modules in an idle state exist, the environment configuration variable in the basic data file is modified; the basic data file is mapped to another group of extension modules according to the modified environment configuration variable. Through the application, the FPGA resource can be used efficiently, and the user can be provided with the ability and flexibility of sharing the entire FPGA prototype / simulation system without waiting for the specific hardware to be released before the work is performed.

Description

Technical Field

[0001] This invention belongs to the field of chip testing technology, and relates to a data verification method, particularly a data verification platform and its data verification method, and a computer-readable storage medium. Background Technology

[0002] FPGA-based prototyping / simulation systems play a crucial role in verifying the system validity of ASICs and other system-level verifications. As the number of logic gates used in ASIC designs increases, a single prototyping or simulation system may utilize multiple FPGAs to meet the user's design requirements.

[0003] Large-scale prototype or simulation systems deploying multiple FPGAs can be used for final system-level verification of ASICs. However, before reaching this stage, users may use such systems more often for single-IP verification. Single-IP verification only requires a small portion of the FPGA's capacity and must wait for specific hardware to be released before data processing can begin, resulting in low FPGA resource utilization efficiency and low flexibility.

[0004] Therefore, how to provide a data verification platform and its data verification method, as well as a computer-readable storage medium, to solve the shortcomings of existing technologies, such as the need to wait for specific hardware to be released before data operations can be performed and the inability to efficiently utilize FPGA resources, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a data verification platform and its data verification method, as well as a computer-readable storage medium, to solve the problem that the prior art requires waiting for specific hardware to be released before data operations can be performed, and cannot efficiently utilize FPGA resources.

[0006] To achieve the above and other related objectives, the present invention provides a data verification platform, comprising at least two sets of extension modules and a main control module connected to the extension modules; the extension modules are used to receive the data to be verified and verify the data; the main control module is used to compile a basic data file related to the data to be verified and to detect the running status of the extension modules; and when it is detected that an extension module that has verified the data to be verified is in an occupied state, and there is another set of extension modules in an idle state, the environment configuration variables in the basic data file are modified; the basic data file is mapped to the other set of extension modules according to the modified environment configuration variables; the basic data file includes environment configuration variables used to characterize the data verification address; the running status of the extension modules includes an occupied state and an idle state.

[0007] In one embodiment of the present invention, the expansion module includes at least one FPGA; or the expansion module includes at least two cascaded expansion units and a control unit connected to each expansion unit; wherein the expansion unit includes a plurality of cascaded FPGAs; and the environmental configuration variables include the physical location ID of the FPGA and / or the physical location ID of the control unit.

[0008] In one embodiment of the present invention, the main control module is further configured to assign a physical location ID to each of the control units.

[0009] In another aspect, the present invention provides a data verification method based on a data verification platform, wherein the data verification platform includes at least two cascaded extension modules and a main control module connected to the extension modules; the data verification method includes: when at least one set of extension modules receives the data to be verified, verifying the data to be verified, and the main control module compiling a basic data file related to the data to be verified; the basic data file includes environment configuration variables for characterizing the data verification address; when the main control module detects that the extension module that has verified the data to be verified is in an occupied state, and there is another set of extension modules in an idle state, modifying the environment configuration variables in the basic data file; mapping the basic data file to the other set of extension modules according to the modified environment configuration variables, so that the other set of extension modules can verify the data to be verified.

[0010] In one embodiment of the present invention, the step of compiling the basic data file related to the project data to be verified includes: compiling the code related to the project data to be verified, setting constraints, synthesizing RTL code, generating netlist files, and placement and routing.

[0011] In one embodiment of the present invention, when each group of expansion modules includes at least one FPGA, the environment configuration variable includes the physical location ID of the FPGA.

[0012] In one embodiment of the present invention, when at least one FPGA forms a project running group, and the environment configuration variable includes the physical location ID of the FPGA, the data verification method includes: when the project running group receives the project data to be verified, verifying the project data to be verified, and the main control module compiling a basic data file related to the project data to be verified; when the main control module detects that the project running group that has verified the project data to be verified is in an occupied state, detecting whether there is an FPGA in an idle state; if so, combining the FPGAs in the idle state into another project running group; modifying the physical location ID of the FPGA in the project running group that has verified the project data to be verified in the basic data file to the physical location ID of the FPGA in the other project running group; mapping the basic data file to the other project running group according to the physical location ID of the FPGA in the other project running group, so that the other project running group can verify the project data to be verified; wherein, the number of FPGAs in the other project running group is consistent with the number of FPGAs in the project running group that has verified the project data to be verified.

[0013] In one embodiment of the present invention, each set of expansion modules includes at least two cascaded expansion units and a control unit connected to each expansion unit, wherein the expansion unit includes at least two cascaded FPGAs; each control unit is connected to the main control unit; each control unit has a physical location ID assigned to the main control module; and the environmental variables include the physical location ID of the control unit.

[0014] In one embodiment of the present invention, when at least one extended unit forms a project running group, and the environment variable includes the physical location ID of the control unit, the data verification method includes: when the project running group receives the project data to be verified, verifying the project data to be verified, and the main control module compiling a basic data file related to the project data to be verified; when the main control module detects that the project running group that has verified the project data to be verified is in an occupied state, detecting whether there are any extended units in an idle state; if so, combining the extended units in the idle state into another project running group; the main control module modifying the physical location ID of the control unit in the project running group that has verified the project data to be verified in the basic data file to the physical location ID of the control unit in the other project running group; mapping the basic data file to the other project running group according to the physical location ID of the control unit in the other project running group, so that the other project running group can verify the project data to be verified; wherein, the number of extended units in the other project running group is the same as the number of extended units in the project running group that has verified the project data to be verified.

[0015] The final aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data verification method based on the data verification platform.

[0016] As described above, the data verification platform, data verification method, and computer-readable storage medium of the present invention have the following beneficial effects:

[0017] This invention allows "design" or "data" to be independent of specific hardware, enabling the mapping of relevant designs and data onto any available hardware resources on demand for necessary IP core verification. Decoupling verification data from hardware allows multiple users to simultaneously verify multiple IP cores without waiting for specific hardware to be released before starting work. This provides users with the ability and flexibility to share the entire FPGA prototype / simulation system, enabling efficient use of FPGA resources. Attached Figure Description

[0018] Figure 1 The diagram shown is a schematic representation of the principle structure of the data verification platform of the present invention in one embodiment.

[0019] Figure 2A The diagram shown is a schematic representation of an embodiment of the data verification platform of the present invention.

[0020] Figure 2B The diagram shown is a schematic diagram of another embodiment of the data verification platform of the present invention.

[0021] Figure 3 The diagram shows a flowchart of the data verification method based on the data verification platform of the present invention.

[0022] Component designation explanation

[0023] 1. Data Verification Platform

[0024] 11. Extension Modules

[0025] 12 Main Control Module

[0026] 111 FPGA

[0027] 112 expansion units

[0028] 113 Control Unit

[0029] Steps S31 to S33 Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0031] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] Example 1

[0033] This embodiment provides a data verification platform, including at least two sets of expansion modules and a main control module connected to the expansion modules;

[0034] The extended module is used to receive the data of the project to be verified and to verify the data of the project to be verified.

[0035] The main control module is used to compile the basic data file related to the data to be verified and to detect the running status of the extended modules; and when it is detected that the extended module that has verified the data to be verified is in an occupied state, and there is another set of extended modules in an idle state, the environment configuration variables in the basic data file are modified; the basic data file is mapped to the other set of extended modules according to the modified environment configuration variables; the basic data file includes environment configuration variables used to represent the data verification address; the running status of the extended module includes occupied state and idle state.

[0036] The data verification platform provided in this embodiment will be described in detail below with reference to the illustrations. The data verification platform described in this embodiment supports portable databases. After an extension module in this data verification platform is designed to verify project data, the project data can be mapped to another extension module without recompiling once the extension module is in use.

[0037] Please see Figure 1 The diagram shows the principle structure of a data verification platform in one embodiment. Figure 1 As shown, the data verification platform 1 described in this embodiment includes at least two sets of expansion modules 11 and a main control module 12 connected to the expansion modules 11.

[0038] The expansion module 11 is used to receive the data to be verified and to verify the data. In this embodiment, the data to be verified includes the circuit logic, clock function, etc., of the chip. Verifying the data to be verified refers to simulating the circuit logic, clock function, etc., of the analog / simulated circuit chip.

[0039] The main control module 12 is used to compile the basic data file related to the data to be verified and to detect the running status of the extension module 11; and when it is detected that the extension module 11 that has verified the data to be verified is occupied and there is another set of extension modules in an idle state, the environment configuration variables in the basic data file are modified; and the basic data file is mapped to the other set of extension modules 11 according to the modified environment configuration variables.

[0040] In this embodiment, the main control module 12 compiles the basic data files related to the project data to be verified, including compiling the code related to the project data to be verified, setting constraints, synthesizing RTL code, generating netlist files, and placement and routing.

[0041] After the other set of extended modules 11 receives the basic data file related to the data to be verified, it continues to verify the data to be verified.

[0042] Please see Figure 2A The diagram shows an implementation structure of a data verification platform. Figure 2A As shown, the expansion module 11 includes at least one FPGA 111.

[0043] When the expansion module 11 includes at least one FPGA 111, at least one FPGA forms a project running group, and the environment configuration variable includes the physical location ID of the FPGA, when the project running group receives the project data to be verified, it verifies the project data to be verified, and the main control module compiles the basic data file related to the project data to be verified.

[0044] When the main control module 12 detects that the project running group that has verified the project data to be verified is in an occupied state, it checks whether there is an FPGA in an idle state; if so, it combines the FPGAs in the idle state into another project running group; it modifies the physical location ID of the FPGA in the project running group that has verified the project data to be verified in the basic data file to the physical location ID of FPGA111 in the other project running group; it maps the basic data file to FPGA111 in the other project running group according to the physical location ID of FPGA111 in the other project running group, so that the other project running group can verify the project data to be verified.

[0045] In this embodiment, the number of FPGAs in the other project run group is the same as the number of FPGAs in the project run group where the data of the project to be verified has been verified.

[0046] For example, when the expansion module 11 includes FPGAs 111A and 111B,

[0047] When the FPGA111A receives the circuit logic of the chip, it simulates the circuit logic of the chip, and the main control module compiles the basic data file related to the circuit logic of the chip.

[0048] When the main control module 12 detects that FPGA 11A, which has simulated the circuit logic of the chip, is in an occupied state, it checks whether there is an FPGA 11B in an idle state. If so, it combines the idle FPGA 11B into another project running group; it modifies the physical location ID of FPGA 11A, which has simulated the circuit logic of the chip in the basic data file, to the physical location ID of FPGA 11B; it maps the basic data file to FPGA 11B according to the physical location ID of FPGA 11B, so that FPGA 11B can continue to simulate the circuit logic of the chip.

[0049] Please see Figure 2B This is a schematic diagram of another implementation structure of the data verification platform. For example... Figure 2B As shown, the expansion module 11 includes at least two cascaded expansion units 112 (each expansion unit 112 includes several cascaded FPGAs) and a control unit 113 connected to each expansion unit. Each control unit 113 has a physical location ID assigned to the main control module 12. The environmental configuration variable includes the physical location ID of the control unit.

[0050] When at least one extended unit constitutes a project run group, and the environment variable includes the physical location ID of the control unit, the data verification method includes:

[0051] When the project operation group receives the project data to be verified, it verifies the project data to be verified, and the main control module 12 compiles the basic data file related to the project data to be verified.

[0052] When the main control module 12 detects that the project run group that has verified the project data to be verified is in an occupied state, it checks whether there are any idle expansion units. If so, it combines the idle expansion units into another project run group. The main control module 12 modifies the physical location ID of the control unit in the project run group that has verified the project data to be verified in the basic data file to the physical location ID of the control unit 113 in the other project run group. The basic data file is mapped to the other project run group according to the physical location ID of the control unit 113 in the other project run group, so that the other project run group can verify the project data to be verified. In this embodiment, the number of expansion units in the other project run group is the same as the number of expansion units in the project run group that has verified the project data to be verified, and the pin connections between the cascaded FPGAs in each expansion unit are the same.

[0053] For example, the main control module manages 8 expansion units (also called slots), and each slot contains multiple cascaded FPGAs. The pin connections between the FPGAs within each slot are identical. A backplane connects the 8 slots, and the pin connections between slots 1-4 are identical to those between slots 5-8, as are the pin connections between slots 1-2, 3-4, 5-6, and 7-8. Therefore, when the design verification project data occupies only one slot, any slot can be changed for the second design verification. When the design verification project data occupies 2 slots, slots 1 & 2 can be changed to slots 3 & 4, 5 & 6, or 7 & 8 for design verification. When the design verification project data occupies 3 slots, slots 1 & 2 & 3 can be changed to slots 5 & 6 & 7 for design verification.

[0054] It should be noted that the division of the various modules / units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules / units can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules / units can be implemented by processing element calls to software, while others are implemented in hardware. For example, module x can be a separate processing element, or it can be integrated into a chip in the above device. Alternatively, it can be stored as program code in the memory of the above device, and its function can be called and executed by a processing element of the device. The implementation of other modules / units is similar. Moreover, these modules / units can be fully or partially integrated together, or they can be implemented independently. The processing element mentioned here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules / units can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0055] For example, these modules / units can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). As another example, when a module / unit is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules / units can be integrated together to form a system-on-a-chip (SOC).

[0056] Example 2

[0057] This embodiment provides a data verification method based on a data verification platform, wherein the data verification platform includes at least two cascaded expansion modules and a main control module connected to the expansion modules; the data verification method includes:

[0058] When at least one set of extended modules receives the project data to be verified, the project data to be verified is verified, and the main control module compiles a basic data file related to the project data to be verified; the basic data file includes environment configuration variables used to characterize the data verification address;

[0059] When the main control module detects that the extended module that has verified the data to be verified is in an occupied state, and there is another set of extended modules in an idle state, the environment configuration variables in the basic data file are modified; the basic data file is mapped to the other set of extended modules according to the modified environment configuration variables, so that the other set of extended modules can verify the data to be verified.

[0060] The data verification method based on the data verification platform provided in this embodiment will be described in detail below with reference to the illustrations. The data verification platform includes at least two sets of expansion modules and a main control module connected to each expansion module. Each expansion module includes at least one FPGA; or each expansion module includes at least two cascaded expansion units and a control unit connected to each expansion unit; wherein each expansion unit includes several cascaded FPGAs, and each control unit has a physical location ID assigned to it by the main control module. The environmental configuration variables include the physical location ID of the FPGA and / or the physical location ID of the control unit.

[0061] Please see Figure 3 This is a flowchart illustrating a data verification method based on a data verification platform. For example... Figure 3 As shown, the data verification method based on the data verification platform specifically includes the following steps:

[0062] S31, when at least one set of extended modules receives the project data to be verified, the project data to be verified is verified, and the main control module compiles a basic data file related to the project data to be verified; the basic data file includes environment configuration variables used to characterize the data verification address.

[0063] In this embodiment, the main control module in S31 compiles the basic data files related to the project data to be verified, including compiling the code related to the project data to be verified, setting constraints, synthesizing RTL code, generating netlist files, and placement and routing.

[0064] S32, when the main control module detects that the extended module that has verified the data to be verified is in an occupied state, and there is another set of extended modules in an idle state, the environment configuration variables in the basic data file are modified; the basic data file is mapped to the other set of extended modules according to the modified environment configuration variables.

[0065] When each group of expansion modules includes at least one FPGA, the environment configuration variable includes the physical location ID of the FPGA.

[0066] When at least one FPGA forms a project run group, and the environment configuration variable includes the physical location ID of the FPGA, step S32 includes:

[0067] When the main control module detects that the project running group for which the project data to be verified has been used is in an occupied state, it checks whether there are any FPGAs in an idle state. If so, it combines the idle FPGAs into another project running group; it modifies the physical location ID of the FPGA in the project running group for which the project data to be verified has been used in the basic data file to the physical location ID of the FPGA in the other project running group; it maps the basic data file to the other project running group according to the physical location ID of the FPGA in the other project running group; wherein, the number of FPGAs in the other project running group is the same as the number of FPGAs in the project running group for which the project data to be verified has been used.

[0068] When each set of expansion modules includes at least two cascaded expansion units and a control unit connected to each expansion unit, and the expansion unit includes at least two cascaded FPGAs and a control unit connected to the FPGA, the environmental variable includes the physical location ID of the control unit.

[0069] When at least one extended unit constitutes a project run group, and the environment variable includes the physical location ID of the control unit, S32 includes:

[0070] When the main control module detects that the project run group for which the project data to be verified has been verified is in an occupied state, it checks whether there are any idle extension units. If so, it combines the idle extension units into another project run group. The main control module modifies the physical location ID of the control unit in the project run group for which the project data to be verified has been verified in the basic data file to the physical location ID of the control unit in the other project run group. The basic data file is then mapped to the other project run group based on the physical location ID of the control unit in the other project run group. The number of extension units in the other project run group is the same as the number of extension units in the project run group for which the project data to be verified has been verified.

[0071] S33, the other set of extended modules verifies the data of the project to be verified.

[0072] When at least one FPGA constitutes a project run group, the project run group including the FPGA verifies the project data to be verified.

[0073] When at least one extension unit constitutes a project run group, the project run group including the extension unit verifies the project data to be verified.

[0074] This embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the following... Figure 3 The data verification method.

[0075] At any possible level of technical detail, this application can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this application.

[0076] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0077] The computer-readable program described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer-readable program instructions from the network and forwards these instructions to a computer-readable storage medium in the respective computing / processing device. The computer program instructions used to perform the operations of this application may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and procedural programming languages ​​such as "C" or similar programming languages. Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions. This electronic circuitry can execute the computer-readable program instructions to implement various aspects of this application.

[0078] In summary, the data verification platform, data verification method, and computer-readable storage medium of this invention enable "designs" or "data" to be independent of specific hardware. Related designs and data can be mapped on demand to any available hardware resources for necessary IP core verification. Decoupling verification data from hardware allows multiple users to simultaneously verify multiple IP cores without waiting for specific hardware to be released. This provides users with the ability and flexibility to share the entire FPGA prototype / simulation system, enabling efficient use of FPGA resources. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A data verification platform, characterized in that, It includes at least two sets of expansion modules and a main control module connected to the expansion modules; The extended module is used to receive the data of the project to be verified and to verify the data of the project to be verified. The main control module is used to compile the basic data file related to the data to be verified and to detect the running status of the extended modules; and when it is detected that the extended module that has verified the data to be verified is in an occupied state, and there is another set of extended modules in an idle state, the environment configuration variables in the basic data file are modified; the basic data file is mapped to the other set of extended modules according to the modified environment configuration variables; the basic data file includes environment configuration variables used to represent the data verification address; The operating status of the expansion module includes occupied status and idle status; The main control module compiles basic data files related to the project data to be verified, including: code related to the project data to be verified, setting constraints, synthesizing RTL code, generating netlist files, and placement and routing; the environment configuration variables include the physical location ID of the FPGA and / or the physical location ID of the control unit.

2. The data verification platform according to claim 1, characterized in that, The expansion module includes at least one FPGA; or The expansion module includes at least two cascaded expansion units and a control unit connected to each expansion unit; wherein the expansion unit includes several cascaded FPGAs.

3. The data verification platform according to claim 2, characterized in that, The main control module is also used to assign a physical location ID to each of the control units.

4. A data verification method based on a data verification platform, characterized in that, The data verification platform includes at least two cascaded expansion modules and a main control module connected to the expansion modules; the data verification method includes: When at least one set of extended modules receives the project data to be verified, the project data to be verified is verified, and the main control module compiles the basic data file related to the project data to be verified; the basic data file includes environment configuration variables used to characterize the data verification address; When the main control module detects that the extended module that has verified the data to be verified is in an occupied state, and there is another set of extended modules in an idle state, the environment configuration variables in the basic data file are modified; the basic data file is mapped to the other set of extended modules according to the modified environment configuration variables, so that the other set of extended modules can verify the data to be verified. The compilation of basic data files related to the project data to be verified includes: code related to the project data to be verified, setting constraints, synthesizing RTL code, generating netlist files, and placement and routing; the environment configuration variables include the physical location ID of the FPGA and / or the physical location ID of the control unit.

5. The data verification method based on a data verification platform according to claim 4, characterized in that, When each group of expansion modules includes at least one FPGA, the environment configuration variable includes the physical location ID of the FPGA.

6. The data verification method based on a data verification platform according to claim 5, characterized in that, When at least one FPGA forms a project running group, and the environment configuration variable includes the FPGA's physical location ID, the data verification method includes: When the project operation group receives the project data to be verified, it verifies the project data to be verified, and the main control module compiles the basic data files related to the project data to be verified. When the main control module detects that the project running group that has verified the project data to be verified is in an occupied state, it checks whether there are any FPGAs in an idle state. If so, it combines the idle FPGAs into another project running group; it modifies the physical location ID of the FPGA in the project running group that has verified the project data to be verified in the basic data file to the physical location ID of the FPGA in the other project running group; it maps the basic data file to the other project running group according to the physical location ID of the FPGA in the other project running group, so that the other project running group can verify the project data to be verified; wherein, the number of FPGAs in the other project running group is the same as the number of FPGAs in the project running group that has verified the project data to be verified.

7. The data verification method based on a data verification platform according to claim 4, characterized in that, Each set of expansion modules includes at least two cascaded expansion units and a control unit connected to each expansion unit. The expansion unit includes at least two cascaded FPGAs. Each control unit is connected to the main control module. Each control unit has a physical location ID assigned to it by the main control module. The environmental configuration variable includes the physical location ID of the control unit.

8. The data verification method based on a data verification platform according to claim 7, characterized in that, When at least one extended unit constitutes a project run group, and the environment configuration variable includes the physical location ID of the control unit, the data verification method includes: When the project operation group receives the project data to be verified, it verifies the project data to be verified, and the main control module compiles the basic data files related to the project data to be verified. When the main control module detects that the project run group that has verified the project data to be verified is in an occupied state, it checks whether there are any idle extension units. If so, it combines the idle extension units into another project run group. The main control module modifies the physical location ID of the control unit in the project run group that has verified the project data to be verified in the basic data file to the physical location ID of the control unit in the other project run group. The basic data file is mapped to the other project run group according to the physical location ID of the control unit in the other project run group, so that the other project run group can verify the project data to be verified. The number of extension units in the other project run group is the same as the number of extension units in the project run group that has verified the project data to be verified.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the data verification method based on a data verification platform as described in any one of claims 4 to 8.

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