Arithmetic logic cache unit based on magnetic rotation logic tunnel junction and storage method thereof

Abstract

The present invention provides an arithmetic logic cache unit based on a magnetic spin logic tunnel junction and a storage method thereof, including MESO and MTJ; the horizontally bridged MESO includes a first interconnected electrode, a multiferroic layer is arranged on the first interconnected electrode, one end of the first ferromagnetic layer is located above the multiferroic layer, and below the other end are a spin injection layer and a spin charge conversion layer in sequence, and the side of the spin charge conversion layer is a second interconnected electrode; the vertically bridged MESO includes a first interconnected electrode, a multiferroic layer is arranged on the first interconnected electrode, and above the multiferroic layer are a first ferromagnetic layer, a spin injection layer, and a spin charge conversion layer in sequence, and the side of the spin charge conversion layer is a second interconnected electrode; the MTJ includes a core area and an electrode; the core area includes a first ferromagnetic layer, a tunneling barrier layer, and a second ferromagnetic layer, and the electrode includes: the third interconnected electrode is a top electrode, and the spin injection layer, the spin charge conversion layer, and the second interconnected electrode together constitute a bottom electrode. The present invention realizes the integration of ALU and Cache, that is, an arithmetic logic storage unit ALCU.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory, and in particular relates to an arithmetic logic cache unit based on a magnetic rotation logic tunnel junction and a storage method thereof. Background Art

[0002] In the past few decades, the ultra-large-scale integrated circuit chips based on complementary metal oxide semiconductor (CMOS) transistors have followed Moore's Law, with the integration density increasing and the chip performance increasing, laying the foundation for the information society. However, as the size of transistors continues to shrink, the quantum tunneling effect becomes increasingly obvious, and the leakage current caused by it becomes larger and larger, resulting in an increase in the standby power consumption (i.e., static power consumption) of the equipment. On the other hand, traditional computers are based on the von Neumann architecture, and their arithmetic logic units (ALUs) and caches are separate, and the two are connected through a bus. When the central processing unit (CPU) is operating, the ALU needs to read data from the cache through the bus first. After the data is processed in the ALU, the processing results are returned to the cache through the bus. The frequent transmission of data brings serious energy consumption (i.e., dynamic power consumption) and delay problems.

[0003] Magnetic random access memory (MRAM) with non-volatility is a reliable way to solve the static power consumption of CMOS. By using MRAM as a cache, the device can be hot-swapped, that is, the device data is not lost when the device is shut down or suddenly powered off, and the state after powering on is exactly the same as the state before powering off. The basic unit of MRAM is the magnetic tunnel junction (MTJ), and the core structure (excluding the electrode layer) can be equivalent to three layers, namely, ferromagnetic layer one, oxide isolation layer, and ferromagnetic layer two. The magnetization of one ferromagnetic layer is easier to be regulated by external magnetic field or current conditions than the other layer. The ferromagnetic layer that is easy to regulate is called the free layer, and the ferromagnetic layer that is difficult to regulate is called the reference layer or fixed layer. The magnetization directions of the two ferromagnetic layers can be both along the in-plane or both along the out-of-plane. When the magnetization direction of the free layer is the same as that of the reference layer, the MTJ resistance is small; when the magnetization direction of the free layer is opposite to that of the reference layer, the MTJ resistance is large. Different data bits ("1" and "0") are stored by using the difference in high and low state resistance. The resistance does not change after power failure, that is, the data is not lost. In traditional CMOS cache, the voltage difference is used to store data. When the power is off, the voltage difference disappears and the data is lost, so the device can only be in standby mode when not in use. MRAM formed by large-scale MTJ array can be used as computer cache, thus overcoming the static power consumption of CMOS.

[0004] First, the input signal (current or magnetic field) and output signal (resistance) of MTJ do not match, and the devices cannot be directly cascaded, making it difficult to be directly used in the arithmetic logic unit (ALU). MTJ is only used to store memory (including cache and flash memory), and dynamic power consumption will still exist.

[0005] Second, the current MRAM cache write speed does not match the ALU computing speed, resulting in a waste of ALU computing power.

[0006] The magneto-gyro logic device (MESO) has the characteristics of high speed, low power consumption, high integration density and cascadability, and is expected to replace CMOS as the basic unit of ALU. MESO mainly consists of two parts: an information writing unit based on magneto-electric coupling effect and an information reading unit based on spin-orbit coupling (SOC). The information writing unit of the magneto-gyro logic device is composed of multiferroic materials (for example, BiFeO3) and nanomagnets. When the input voltage acts on the multiferroic material and is greater than its flip threshold, the ferroelectric order and ferromagnetic order / antiferromagnetic order of the multiferroic material will flip, and the ferromagnetic order of the nanomagnet and the ferromagnetic order / antiferromagnetic order of the multiferroic material will be coupled together through exchange interaction, so the magnetization direction of the nanomagnet will also flip together to achieve information writing. The information reading unit of the magnetic spin logic device is composed of strong spin orbit coupling (SOC) material and nanomagnets. A working voltage is applied between the nanomagnet and the strong SOC material, and the spin current carrying the magnetization direction information of the nanomagnet is injected into the strong SOC material. The inverse spin Hall effect or the inverse Rashba effect converts the spin current into a charge flow, thereby realizing the conversion of the magnetization direction to the charge voltage and completing the information reading. There are two ways to connect the write and read parts of MESO, namely in-plane bridging and vertical bridging. Among them, vertical bridging is easier for micro-nano processing. The use of MESO in ALU does not solve the dynamic power consumption and delay problems of the CPU. Summary of the invention

[0007] The present invention provides an arithmetic logic cache unit based on magnetic rotation logic tunnel junction and a storage method thereof, aiming to solve the following problems: 1. The MTJ cannot be cascaded and is therefore difficult to be used in ALU; 2. The dynamic power consumption and delay problems when the MTJ is used in the cache architecture; 3. The dynamic power consumption and delay problems when the MESO is used in the ALU; 4. The static power consumption problem of the traditional CMOS integrated circuit.

[0008] An arithmetic logic cache unit based on a magnetic spin logic tunnel junction includes a MESO and an MTJ;

[0009] The horizontally bridged MESO comprises a first interconnecting electrode, a multiferroic layer is arranged on the first interconnecting electrode, one end of the first ferromagnetic layer is located above the multiferroic layer, and below the other end are a spin injection layer and a spin charge conversion layer in sequence, and a second interconnecting electrode is arranged on the side of the spin charge conversion layer;

[0010] The vertically bridged MESO comprises a first interconnecting electrode, a multiferroic layer is arranged on the first interconnecting electrode, a first ferromagnetic layer, a spin injection layer, and a spin charge conversion layer are arranged above the multiferroic layer in sequence, and a second interconnecting electrode is arranged on the side of the spin charge conversion layer;

[0011] The MTJ includes a core region and electrodes; the core region includes a first ferromagnetic layer, a tunneling barrier layer, and a second ferromagnetic layer; the electrodes include: a third interconnected electrode as a top electrode, a spin injection layer, a spin charge conversion layer, and a second interconnected electrode together forming a bottom electrode;

[0012] With the help of MESO, data operations are completed and the data is stored in situ in the MTJ, thus realizing the functions of ALU and Cache with a single device.

[0013] The multiferroic layer is a single-phase multiferroic material, or a hybrid multiferroic material composed of a piezoelectric material and an antiferromagnetic material;

[0014] The first ferromagnetic layer and the second ferromagnetic layer include one or more of the following materials: iron, cobalt, nickel, manganese, chromium, and ruthenium.

[0015] The spin-charge conversion layer includes various types of strong spin-orbit coupling materials, topological insulator materials, two-dimensional electron gas or Raschib surface materials, and Weyl semimetals.

[0016] Tunneling barrier layers include various semiconductors (such as germanium), topological insulators (such as bismuth telluride, bismuth selenide, bismuth antimonide) and oxide insulators (such as magnesium oxide, aluminum oxide, hafnium dioxide, tantalum oxide and silicon dioxide).

[0017] The storage method of the arithmetic logic cache unit based on the magnetic rotation logic tunnel junction is as follows:

[0018] The first interconnected electrode, the multiferroic layer, and the first ferromagnetic layer constitute the data writing part. By applying different potential levels on the first interconnected electrode, a positive or negative voltage is generated at both ends of the multiferroic layer, and the electric polarization of the multiferroic layer is reversed accordingly, driving the magnetization of the first ferromagnetic layer to reverse, thereby completing the information writing;

[0019] The first ferromagnetic layer, the spin injection layer, the spin charge conversion layer, and the second interconnected electrode constitute the data output part. By injecting a constant working current at the top or bottom of the first ferromagnetic layer, the current is polarized by the first ferromagnetic layer, filtered through the spin injection layer to form a spin current, injected into the spin charge conversion layer, converted into a charge current, and formed into a voltage output through the second interconnected electrode. When the magnetization of the first ferromagnetic layer changes, the output voltage of the second interconnected electrode will reverse. The output voltage of the second interconnected electrode is equivalent to the voltage at both ends of the multi-ferroic layer when the information is written in the previous step, so the output voltage can directly drive the next MESOTJ to write information.

[0020] The first ferromagnetic layer, the oxide isolation layer, and the second ferromagnetic layer constitute a data storage portion. The magnetization change of the first ferromagnetic layer is reflected as a change in the resistance of the MTJ formed by the first ferromagnetic layer, the oxide isolation layer, and the second ferromagnetic layer.

[0021] Beneficial effects brought by the technical solution of the present invention

[0022] MESOTJ can be directly cascaded and can be used in ALU;

[0023] MESO is used in MESOTJ to realize data calculation. The data is stored in the MTJ structure of MESOTJ. There is no transmission process, no dynamic power consumption and delay.

[0024] Data is stored in the form of MTJ resistance, there is no static power consumption, and hot swap is possible.

[0025] The present invention realizes the integration of ALU and Cache, which can be considered as an arithmetic logic storage unit (ALCU). The CPU can be constructed by using only the ALCU as a core device in combination with basic auxiliary switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the horizontal bridging structure of the present invention;

[0027] Figure 2 It is a schematic diagram of the vertical bridging structure of the present invention. DETAILED DESCRIPTION

[0028] The specific technical solution of the present invention is described in conjunction with the accompanying drawings.

[0029] The present invention proposes an arithmetic logic cache unit based on a magnetic spin logic tunnel junction, namely, MESOTJ, which is directly used in an arithmetic logic unit ALU and has a cache function, and is called an arithmetic logic cache unit ALCU.

[0030] like Figure 1As shown, the horizontally bridged MESO comprises a first interconnected electrode 1, on which a multiferroic layer 2 is disposed, one end of a first ferromagnetic layer 3 is located above the multiferroic layer 2, and below the other end are a spin injection layer 4 and a spin charge conversion layer 5, and a second interconnected electrode 6 is disposed on the side of the spin charge conversion layer 5;

[0031] like Figure 2 As shown, the vertically bridged MESO comprises a first interconnected electrode 1, on which a multiferroic layer 2 is disposed, above which are in turn a first ferromagnetic layer 3, a spin injection layer 4, and a spin charge conversion layer 5, and on the side of the spin charge conversion layer 5 is a second interconnected electrode 6;

[0032] like Figure 1 and Figure 2 As shown, the MTJ includes a core region and electrodes; the core region includes a first ferromagnetic layer 3, a tunneling barrier layer 7, and a second ferromagnetic layer 8, and the electrodes include: a third interconnected electrode 9 as a top electrode, and a spin injection layer 4, a spin charge conversion layer 5, and a second interconnected electrode 6 together constitute a bottom electrode.

[0033] In MESOTJ, data operations can be completed with the help of MESO, and the data is stored in situ in MTJ, thereby realizing the functions of ALU and Cache with a single device.

[0034] The first interconnection electrode 1, the second interconnection electrode 6, and the third interconnection electrode 9 can be any material suitable for ultra-large-scale integrated circuit interconnection technology, such as aluminum (Al), copper (Cu), gold (Au), titanium (Ti), molybdenum (Mo), etc., and can include one or more of them.

[0035] The multiferroic layer 2 can be a single-phase multiferroic material, including but not limited to bismuth ferrite (BiFeO3), bismuth ferrite (BiFeO3) doped with various elements (such as lanthanum), terbium manganate (TbMnO3), hexagonal ferrite, hafnium oxide (HfOx), chromium oxide (Cr2O3) and other materials; or a mixed multiferroic material composed of piezoelectric materials (such as lead magnesium niobate-titanate PMN-PT, lead zirconate titanate PZT, etc.) and antiferromagnetic materials (iridium manganese IrMn, platinum manganese PtMn, manganese gold Mn2Au, manganese tin Mn3Sn, manganese gallium Mn3Ga, etc.), such as PMN-PT / PtMn, PMN-PT / Mn2Au, etc.

[0036] The first ferromagnetic layer 3 and the second ferromagnetic layer 8 include one or more of the following materials: iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), chromium (Cr), and ruthenium (Ru).

[0037] The spin injection layer 4 may or may not be present. Its materials include metal materials such as copper Cu, aluminum Al, silver Ag; oxide materials such as magnesium oxide MgO, aluminum oxide Al2O3, hafnium dioxide HfO2, tantalum oxide TaOx, and silicon dioxide SiO2.

[0038] The spin charge conversion layer 5 includes various types of strong spin-orbit coupling materials, such as heavy metal materials such as platinum Pt, tantalum Ta, tungsten W, etc. and various tree material alloys; topological insulator materials such as bismuth telluride Bi2Te3 and antimony-doped bismuth telluride ((Bi, Sb)2Te3), bismuth selenide Bi2Se3, etc., α-phase tin (α-Sn); two-dimensional electron gas or Raschib surface materials such as rhenium aluminate (LaAlO3) / strontium titanate (SrTiO3), aluminum oxide (Al2O3) / potassium carbonate (KTaO3), bismuth (Bi) / silver (Ag), etc.; Weyl semimetals such as tungsten telluride (WTe2), etc.

[0039] The tunneling barrier layer 7 includes but is not limited to germanium (Ge), bismuth telluride (Bi2Te3), bismuth selenide (Bi2Se3), bismuth antimonide (BiSb), magnesium oxide (MgO), aluminum oxide (Al2O3), hafnium dioxide (HfO2), tantalum oxide (TaOx) and silicon dioxide (SiO2).

[0040] The first interconnected electrode 1, the multiferroic layer 2, and the first ferromagnetic layer 3 constitute the data writing part. By applying different potential levels on the first interconnected electrode 1, a positive or negative voltage is generated at both ends of the multiferroic layer 2, and the electric polarization of the multiferroic layer 2 is reversed accordingly, driving the magnetization of the first ferromagnetic layer 3 to reverse, thereby completing the information writing.

[0041] The first ferromagnetic layer 3, the spin injection layer 4, the spin charge conversion layer 5, and the second interconnected electrode 6 constitute the data output part. By injecting a constant working current at the top (or bottom) of the first ferromagnetic layer 3, the current is polarized by the first ferromagnetic layer 3, and is filtered through the spin injection layer to form a spin current, which is injected into the spin charge conversion layer 5, converted into a charge flow, and forms a voltage output through the second interconnected electrode 6. When the magnetization of the first ferromagnetic layer 3 changes, the output voltage of the second interconnected electrode 6 will be reversed. The output voltage of the second interconnected electrode 6 is equivalent to the voltage at both ends of the multiferroic layer 2 when the information is written in the previous step, so the output voltage can directly drive the next MESOTJ to write information.

[0042] The first ferromagnetic layer 3 , the oxide isolation layer 7 , and the second ferromagnetic layer 8 constitute a data storage part. The magnetization change of the first ferromagnetic layer 3 is reflected as a change in the MTJ resistance of the first ferromagnetic layer 3 , the oxide isolation layer 7 , and the second ferromagnetic layer 8 .

Claims

1. An arithmetic logic cache unit based on a magnetic rotation logic tunnel junction, characterized in that: It includes a magnetic rotation logic device MESO and a magnetic tunnel junction MTJ, and the MESO includes a horizontal bridge or a vertical bridge; The horizontally bridged MESO comprises a first interconnected electrode (1), a multiferroic layer (2) is provided on the first interconnected electrode (1), one end of the first ferromagnetic layer (3) is located above the multiferroic layer (2), and below the other end are a spin injection layer (4) and a spin charge conversion layer (5) in sequence, and a second interconnected electrode (6) is provided on the side of the spin charge conversion layer (5); The vertically bridged MESO comprises a first interconnected electrode (1), a multiferroic layer (2) is provided on the first interconnected electrode (1), a first ferromagnetic layer (3), a spin injection layer (4), and a spin charge conversion layer (5) are arranged above the multiferroic layer (2), and a second interconnected electrode (6) is arranged on the side of the spin charge conversion layer (5); The MTJ comprises a core region and electrodes; the core region comprises a first ferromagnetic layer (3), and the first ferromagnetic layer (3) is sequentially provided with a tunneling barrier layer (7) and a second ferromagnetic layer (8); the electrodes comprise a top electrode and a bottom electrode; the top electrode comprises a third interconnecting electrode (9) above the second ferromagnetic layer (8), and the bottom electrode comprises a spin injection layer (4) on one side of the first ferromagnetic layer (3), a spin charge conversion layer (5), and a second interconnecting electrode (6) adjacent to the spin charge conversion layer (5); in a horizontally bridged arithmetic logic cache unit, the bottom electrode is located below the first ferromagnetic layer (3), and in a vertically bridged arithmetic logic cache unit, the bottom electrode is located above the first ferromagnetic layer (3); With the help of MESO, data operations are completed and the data is stored in situ in the MTJ, thereby realizing the functions of the arithmetic logic unit ALU and the cache with a single device.

2. The arithmetic logic cache unit based on magnetic rotation logic tunnel junction according to claim 1, characterized in that: The multiferroic layer (2) is a single-phase multiferroic material, or a mixed multiferroic material composed of a piezoelectric material and an antiferromagnetic material.

3. The arithmetic logic cache unit based on magnetic rotation logic tunnel junction according to claim 1, characterized in that: The first ferromagnetic layer (3) and the second ferromagnetic layer (8) contain one or more of the following materials: iron, cobalt, nickel, manganese, chromium, and ruthenium.

4. The arithmetic logic cache unit based on magnetic rotation logic tunnel junction according to claim 1, characterized in that: The spin-charge conversion layer (5) comprises various types of strong spin-orbit coupling materials, topological insulator materials, two-dimensional electron gas, Raschib surface materials or Weyl semimetals.

5. The arithmetic logic cache unit based on magnetic rotation logic tunnel junction according to claim 1, characterized in that: The tunneling barrier layer (7) includes various types of semiconductors, topological insulators or oxide insulators.

6. A storage method of an arithmetic logic cache unit based on a magnetic rotation logic tunnel junction according to any one of claims 1 to 5, characterized in that: The following steps are involved: The first interconnected electrode (1), the multiferroic layer (2), and the first ferromagnetic layer (3) constitute a data writing part; by applying different potential levels on the first interconnected electrode (1), a positive or negative voltage is generated at both ends of the multiferroic layer (2), and the electric polarization of the multiferroic layer (2) is reversed accordingly, driving the magnetization of the first ferromagnetic layer (3) to be reversed, thereby completing the information writing; The first ferromagnetic layer (3), the spin injection layer (4), the spin charge conversion layer (5), and the second interconnected electrode (6) constitute a data output part. By injecting a constant working current at the top or bottom of the first ferromagnetic layer (3), the current is polarized by the first ferromagnetic layer (3), filtered by the spin injection layer (4) to form a spin current, which is injected into the spin charge conversion layer (5), converted into a charge current, and forms a voltage output through the second interconnected electrode (6); when the magnetization of the first ferromagnetic layer (3) changes, the output voltage of the second interconnected electrode (6) will reverse in sign; the output voltage of the second interconnected electrode (6) is equivalent to the voltage at both ends of the multi-ferroic layer (2) when information is written in the previous step, so the output voltage can directly drive the next magnetic spin logic tunnel junction to write information; The first ferromagnetic layer (3), the tunneling barrier layer (7) and the second ferromagnetic layer (8) constitute a data storage part, and the magnetization change of the first ferromagnetic layer (3) is reflected as a change in the resistance of the MTJ constituted by the first ferromagnetic layer (3), the tunneling barrier layer (7) and the second ferromagnetic layer (8).

Images