Storage device refresh method and system

Abstract

This application relates to a storage device refresh method and system. The storage device refresh method includes: obtaining a target refresh row address; determining whether the target refresh row address exists in the replaced row addresses in a reference module, wherein the replaced row address corresponds to a corrupted word line; if the target refresh row address exists in the replaced row addresses in the reference module, then skipping the refresh of the word line pointed to by the target refresh row address. This application can prevent data corruption during the refresh process.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a method and system for refreshing storage devices. Background Technology

[0002] To preserve the data stored in volatile memory, its word lines are typically refreshed periodically. The primary task of the refresh operation is to ensure that the data is not corrupted; therefore, the reliability of the refresh operation is a top priority.

[0003] However, in actual refresh processes, data corruption often occurs. Summary of the Invention

[0004] Therefore, it is necessary to provide a storage device refresh method and system that can prevent data corruption during the refresh process to address the aforementioned technical problems.

[0005] A method for refreshing a storage device, comprising:

[0006] Get the address of the target refresh row;

[0007] Determine whether the target refresh line address exists in the replaced line address in the reference module, wherein the replaced line address corresponds to the damaged word line;

[0008] If the target refresh line address exists in the replaced line address in the reference module, then the refresh of the word line pointed to by the target refresh line address is skipped.

[0009] In one embodiment, it further includes:

[0010] If the target refresh line address does not exist in the replaced line address in the reference module, then the word line pointed to by the target refresh line address is refreshed.

[0011] In one embodiment, the reference module includes k fuse units, each fuse unit storing a row address to be replaced, where k is an integer greater than 0.

[0012] In one embodiment,

[0013] The process of obtaining the target refresh row address includes:

[0014] Obtain n target refresh row addresses belonging to n different sectors, where n is an integer greater than 0. The target refresh row address and the replaced row address stored in the fuse unit both include a sector address bits and b coded address bits. The sector address bits are used to store sector address information, and the coded address bits are used to store row address information in each sector. The information stored in the b coded address bits of the n target refresh row addresses is the same, and the b coded addresses of the target refresh row addresses are used as target coded address bits, where a and b are both integers greater than 0.

[0015] The step of determining whether the target refresh line address exists in the replaced line address in the reference module includes:

[0016] For each fuse unit, based on the information stored in each sector address bit therein, the n sector address information signals of the fuse unit are decoded to obtain the signal.

[0017] For each fuse unit, the information stored in each of the encoded address bits is compared with the information stored in each of the target encoded address bits to obtain the matching information signal for each of the encoded address bits;

[0018] For each fuse unit, the full match information signal of the fuse unit is obtained based on the match information signal of each of the coded address bits therein;

[0019] For each fuse unit, based on its corresponding full match information signal and the n sector address information signals, the n sector fuse information signals of each fuse unit are obtained;

[0020] The sector fuse information signals belonging to the same sector of k fuse units are taken as a group of sector fuse information signals to form n groups of sector fuse information signals. Each group of sector fuse information signals includes k sector fuse information signals belonging to the same sector.

[0021] Based on k sector fuse information signals from the n groups of sector fuse information signals, obtain n sector existence information signals;

[0022] Based on the presence information signals of the n sectors, determine whether each target refresh row address exists in the replaced row address in the reference module.

[0023] In one embodiment, for each fuse unit, a full match information signal of the fuse unit is obtained based on the match information signal of each of the coded address bits therein, including:

[0024] For each fuse unit, perform a bitwise AND operation on the matching information signals of its various coded address bits to obtain the full matching information signal of each fuse unit.

[0025] In one embodiment, the step of performing a bitwise AND operation on the matching information signals of each coded address bit of each fuse unit to obtain the full matching information signal of each fuse unit includes:

[0026] For each fuse unit, the matching information signals of its various coded address bits are grouped and ANDed / NOT logically to obtain the group matching information signals;

[0027] Perform a OR-NOT operation on each set of matching information signals to obtain the full matching information signal for each fuse unit.

[0028] In one embodiment, for each fuse unit, obtaining the n sector fuse information signals for each fuse unit based on its corresponding full match information signal and the n sector address information signals includes:

[0029] For each fuse unit, perform an AND operation between its corresponding full match information signal and the n sector address information signals to obtain the n sector fuse information signals of the fuse unit.

[0030] In one embodiment, obtaining n sector presence information signals based on k sector fuse information signals from the n sets of sector fuse information signals includes:

[0031] Perform an OR operation on k sector fuse information signals from n groups of sector fuse information signals to obtain n sector presence information signals.

[0032] A storage device refresh system, comprising:

[0033] The acquisition module is used to obtain the address of the target refresh row;

[0034] A reference module is used to store the address of the line to be replaced, which corresponds to a damaged word line;

[0035] The judgment module, connected to the acquisition module and the reference module, is used to determine whether the target refresh row address exists in the replaced row address in the reference module;

[0036] The control module, connected to the judgment module, is used to control the skipping of the refresh of the word line pointed to by the target refresh line address when the target refresh line address exists in the replaced line address in the reference module.

[0037] In one embodiment, the reference module includes k fuse units, each fuse unit storing a row address to be replaced, where k is an integer greater than 0.

[0038] In one embodiment,

[0039] The target refresh row address includes n target refresh row addresses belonging to n different sectors. Both the target refresh row address and the replaced row address stored in the fuse unit include a sector address bits and b coded address bits. The sector address bits are used to store sector address information, and the coded address bits are used to store row address information in each sector. The information stored in the b coded address bits of the n target refresh row addresses is the same, and the b coded addresses of the target refresh row address are used as target coded address bits. a and b are both integers greater than 0.

[0040] The judgment module includes a judgment unit and k judgment units;

[0041] The judgment unit is connected to the fuse unit in a one-to-one correspondence, and each judgment unit includes:

[0042] The decoding circuit is connected to one of the fuse units, receives the information stored in each sector address bit of the fuse unit, and decodes and outputs n sector address information signals of the fuse unit according to the information stored in each sector address bit.

[0043] The comparison circuit is connected to one of the fuse units and includes b comparison sub-circuits. Each comparison sub-circuit simultaneously receives information stored in a pair of corresponding target encoding address bits and information stored in the encoding address bits of the fuse unit, and outputs a matching information signal for the corresponding encoding address bits based on the comparison between the information stored in a pair of corresponding target encoding address bits and information stored in the encoding address bits of the fuse unit.

[0044] A matching circuit is connected to each of the comparison sub-circuits of the comparison circuit, receives the matching information signals output by each of the comparison sub-circuits, and outputs the full matching information signal of the fuse unit according to each of the matching information signals.

[0045] The judgment circuit, connected to the matching circuit and the decoding circuit, includes n judgment sub-circuits. Each judgment sub-circuit receives the full match information signal output by the matching circuit and a corresponding sector address information signal, and obtains a sector fuse information signal of the fuse unit based on the full match information signal and the sector address information signal.

[0046] The determination unit is connected to k determination units, including n determination circuits. Each determination circuit receives k sector fuse information signals belonging to the same sector and obtains a sector existence information signal.

[0047] In one embodiment, the comparator circuitry includes an XNOR gate.

[0048] In one embodiment, the matching circuit includes a first matching circuit and at least two second matching circuits; each second matching circuit is connected to a set of comparator sub-circuits, receives matching information signals from the set of comparator sub-circuits, and outputs a group matching information signal based on the matching information signals output by the set of comparator sub-circuits; the first matching circuit is connected to each of the second matching circuits, receives the group matching information signals output by each of the second matching circuits, and outputs a full matching information signal for the fuse unit based on the group matching information signals.

[0049] In one embodiment, the second matching circuit includes a first NAND gate, and the first matching circuit includes a first NOR gate.

[0050] In one embodiment, the determination sub-circuit includes a second NAND gate and a first NOT gate. The input of the second NAND gate is connected to the matching circuit and the decoding circuit, the output of the second NAND gate is connected to the input of the first NOT gate, and the output of the first NOT gate is connected to the corresponding determination circuit.

[0051] In one embodiment, the determination circuit includes a second NOR gate and a second NOT gate. The input of the second NOR gate is connected to k determination units, and the output of the second NOR gate is connected to the input of the second NOT gate. The output of the second NOT gate is used to output the sector presence information signal.

[0052] The above-mentioned storage device refresh method and system determine whether the target refresh line address exists in the replaced line address in the reference module, and skip the refresh of the word line pointed to by the target refresh line address when the target refresh line address exists in the replaced line address in the reference module, thereby effectively reducing the risk of data corruption during the refresh process of the storage device. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a flowchart illustrating a storage device refresh method in one embodiment;

[0055] Figure 2 This is a flowchart illustrating the process of determining whether the target refresh row address exists in the replaced row address in the reference module in one embodiment.

[0056] Figure 3 A schematic diagram of the process for obtaining the full match information signal of a fuse unit in one embodiment;

[0057] Figure 4 This is a block diagram of a storage device refresh system in one embodiment;

[0058] Figure 5 This is a block diagram of a storage device refresh system in another embodiment;

[0059] Figure 6 This is a structural block diagram of the judgment unit in one embodiment;

[0060] Figure 7 This is a circuit diagram of the judgment unit in one embodiment;

[0061] Figure 8 This is a circuit diagram of the determination unit in one embodiment. Detailed Implementation

[0062] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0064] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0065] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0066] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0067] As described in the background section, in the prior art, data corruption may occur during the refresh process of storage devices. The inventors have discovered that the reason for this problem is:

[0068] Refreshing a damaged word line may corrupt data in adjacent word lines. This risk is particularly high as technology advances and line widths decrease, increasing the likelihood of data corruption in neighboring word lines during refresh. However, current technology does not avoid updating damaged word lines, thus posing a risk of data corruption.

[0069] For the reasons mentioned above, the present invention provides a method and system for refreshing storage devices.

[0070] In one embodiment, see Figure 1 A method for refreshing a storage device is provided, comprising:

[0071] Step S100: Obtain the target refresh row address;

[0072] Step S200: Determine whether the target refresh line address exists in the replaced line address in the reference module. The replaced line address corresponds to the damaged word line.

[0073] Step S300: If the target refresh line address exists in the replaced line address in the reference module, then skip refreshing the word line pointed to by the target refresh line address.

[0074] In step S100, the target refresh row address is the row address of the memory cell corresponding to the word line to be refreshed. The storage device has multiple word lines and multiple memory cells arranged in multiple rows and columns. Each row of memory cells corresponds to one word line. Each word line provides a gate voltage signal to the transistors of several memory cells in its corresponding row to control the switching of the transistors, thereby controlling the writing and reading of stored data. The row address of the memory cells corresponding to the same word line is the same.

[0075] In step S200, the row address to be replaced is the row address of the memory cell corresponding to the damaged word line. The row addresses of memory cells corresponding to the same word line are the same, and one replaced row address corresponds to one damaged word line.

[0076] The reference module is used to store the address of the line to be replaced.

[0077] In step S300, if the target refresh row address exists in the replaced row address in the reference module, it indicates that the word line pointed to by the target refresh row address is damaged. In this case, the refresh of the word line pointed to by the target refresh row address is skipped, thereby effectively avoiding the damaged word line and preventing the data in adjacent word lines from being corrupted due to refreshing the damaged word line.

[0078] In this embodiment, it is determined whether the target refresh line address exists in the replaced line address in the reference module. If the target refresh line address exists in the replaced line address in the reference module, the refresh of the word line pointed to by the target refresh line address is skipped, thereby effectively reducing the risk of data corruption in the storage device during the refresh process.

[0079] In one embodiment, the storage device refresh method further includes:

[0080] In step S400, if the target refresh line address does not exist in the replaced line address in the reference module, then refresh the word line pointed to by the target refresh line address.

[0081] At this point, the storage device can be refreshed promptly and effectively, thus preserving the data stored in the storage device.

[0082] In one embodiment, the reference module includes k fuse units, each fuse unit storing the address of a row to be replaced, where k is an integer greater than 0.

[0083] A fuse cell is a unit used to repair the row address of a memory cell that has suffered word line corruption. One fuse cell stores the row address of a memory cell with a corrupted word line. Each fuse cell also corresponds to a redundant word line.

[0084] When repairing the row address of a memory cell with a damaged word line, the row address A of the damaged cell is stored in a fuse cell. Then, a redundant word line is used to replace the corresponding word line of that memory cell. Subsequently, during read / write operations, if the row address being read or written is A, the redundant word line corresponding to the fuse cell storing row address A will be activated. Row address A is the replaced row address.

[0085] In this embodiment, the reference module is composed of fuse units, which can effectively utilize the fuse units and save storage space.

[0086] In one embodiment, step S100 includes: obtaining n target refresh row addresses belonging to n different sectors, where n is an integer greater than 0.

[0087] Both the target refresh row address and the replaced row address stored in the fuse unit include *a* sector address bits and *b* coded address bits. The sector address bits store sector address information. The coded address bits store the row address information within each sector; *a* and *b* are both integers greater than 0. The information stored in the *b* coded address bits of the *n* target refresh row addresses is identical, and the *b* coded addresses of the target refresh row addresses serve as the target coded address bits.

[0088] As an example, the first two bits (such as bits 15 and 14) of the target refresh row address and the replaced row address stored in the fuse unit can be used as sector address bits, while the following twelve bits (such as bits 13 to 2) can be used as encoding address bits. In this case, a = 2 and b = 12.

[0089] The information stored in the b encoded address bits of n target refresh line addresses is the same. That is, the information stored in the last twelve bits (such as bits 13 to 2) of the encoded address bits of the n target refresh line addresses is the same. In other words, the information stored in the i-th encoded address bit of each target refresh line address is the same (all are "1" or all are "0"), and the i-th bit is any one of the b encoded address bits.

[0090] In this embodiment, n target refresh line addresses belonging to n different sectors are obtained simultaneously, so that n word lines with the same information stored in b encoded address bits can be refreshed at the same time.

[0091] Please also see Figure 2 In this embodiment, step S200 includes:

[0092] Step S210: For each fuse unit, decode the n sector address information signals SecEn of the fuse unit according to the information stored in each sector address bit;

[0093] Step S220: For each fuse unit, compare the information stored in each coded address bit with the information stored in each target coded address bit to obtain the Match information signal for each coded address bit.

[0094] Step S230: For each fuse unit, obtain the full match information signal AllAddMatch of the fuse unit based on the Match information signal of each encoded address bit.

[0095] Step S240: For each fuse unit, obtain the n sector fuse information signals Sec based on its corresponding full match information signal AllAddMatch and n sector address information signals SecEn.

[0096] Step S250: The sector fuse information signals Sec belonging to the same sector of k fuse units are taken as a group of sector fuse information signals to form n groups of sector fuse information signals. Each group of sector fuse information signals includes k sector fuse information signals Sec belonging to the same sector.

[0097] Step S260: Based on k sector fuse information signals Sec from the n sets of sector fuse information signals, obtain n sector existence information signals SelSec;

[0098] Step S270: Based on the n sector existence information signals SelSec, determine whether each target refresh row address exists in the replaced row address in the reference module.

[0099] As an example, let k=3, n=4, a=2, b=12. In this case, the reference module includes three fuse units: Fuse0, Fuse1, and Fuse2. During refresh, the four word lines pointed to by the four target refresh line addresses of four different sectors are refreshed simultaneously. The first two bits (bits 15 and 14) of the target refresh line address and the replaced line address stored in the fuse unit are used as the sector address bits, while the last twelve bits (bits 13 to 2) are used as the encoding address bits.

[0100] Meanwhile, when a=2, both the target refresh row address and the replaced row address stored in the fuse unit include two sector address bits. The information stored in each sector address bit can be either "0" or "1", and after decoding, it can represent four sectors. Therefore, n is 4 in this case.

[0101] Steps S210 to S240 above process fuse units Fuse0, Fuse1, and Fuse2 simultaneously. Here, we will take fuse unit Fuse0 as an example for a detailed description.

[0102] For Fuse0:

[0103] In step S210, the two sector address bits (bit 15 and bit 14) of fuse unit Fuse0 are respectively Fuse0 <15> Fuse0 <14> .

[0104] Fuse0 <15> Fuse0 <14> The information stored in the circuit is input to the decoding circuit, which can then decode and obtain the four sector address information signals SecEn0 of the fuse unit Fuse0. <3> SecEn0 <2> SecEn0 <1> SecEn0 <0> The four sector address information signals SecEn0 <3> SecEn0 <2> SecEn0 <1> SecEn0 <0> Only one of the signals is high, indicating that the row address to be replaced stored in fuse unit Fuse0 belongs to the sector corresponding to that high signal. For example, the sector address information signal SecEn0. <3> SecEn0 <2> SecEn0 <1> The low-level signal is the sector address information signal SecEn0. <0> A high-level signal indicates that the replaced row address stored in the fuse unit Fuse0 belongs to sector zero.

[0105] In step S220, the twelve-bit encoded address bits (bits 13 to 2) of the fuse unit Fuse0 are respectively Fuse0 <13> To Fuse0 <2> The twelve-bit target encoding address of the target refresh row address is A. <13> To A <2> .

[0106] Compare Fuse0 <j>With A <j>The information stored in the middle is used to obtain the matching information signal Match0 for the j-th encoded address bit. <j>The j-th bit can be any bit from the 13th bit to the 2nd bit. Match information signal Match0 <j>When it is high, it represents Fuse0. <j>With A <j>The information stored in it is consistent. Match information signal Match0 <j>When it is low, it represents Fuse0. <j>With A <j>The information stored in the middle is inconsistent.

[0107] In step S230, the matching information signal Match0 of the twelve-bit coded address bits of the fuse unit Fuse0 is used. <13> To Match0 <2> The full match information signal AllAddMatch0 of fuse unit Fuse0 is obtained. When the full match information signal AllAddMatch0 is high, it represents the twelve-bit coded address bit Fuse0 of fuse unit Fuse0. <13> To Fuse0 <2> The information stored in the middle and the twelve-bit target encoding address A of the target refresh row address <13> To A <2> All the information stored in it is consistent.

[0108] In step S240, based on the full match information signal AllAddMatch0 of fuse unit Fuse0 and its four sector address information signals SecEn0... <3> SecEn0 <2> SecEn0 <2> SecEn0 <0> Obtain the four sector fuse information signals Sec0 of fuse unit Fuse0. <3> Sec0 <2> Sec0 <1> Sec0 <0> Four sector fuse information signals Sec0 <3> Sec0 <2> Sec0 <1> Sec0 <0> At most one signal in the four sector fuse information signals Sec0 is high. <3> Sec0 <2> Sec0 <1> Sec0 <0> When all four sector fuse information signals Sec0 are low, it indicates that the target refresh row address does not exist in the replaced row address stored in fuse cell Fuse0. <3> Sec0 <2> Sec0 <1> Sec0 <0> When one of the signals is high, it indicates that the target refresh row address exists in the replaced row address stored in fuse unit Fuse0. For example, Sec0 <0> When the level is high, it indicates that the target refresh row address exists in the replaced row address stored in the fuse unit Fuse0, and that the target refresh row address belongs to the zeroth sector.

[0109] For Fuse1 and Fuse2, the processing steps S210 to S240 are the same, and in step 240, the four sector fuse information signals Sec0 of fuse unit Fuse0 are obtained. <3> Sec0 <2> Sec0 <1> Sec0 <0> Simultaneously, it also acquires the four sector fuse information signals Sec1 of fuse unit Fuse1. <3> Sec1 <2> Sec1 <1> Sec1 <0> And the four sector fuse information signals Sec2 of fuse unit Fuse2 <3> Sec2 <2> Sec2 <1> Sec2 <0> .

[0110] In step S250, the Sec0 of the fuse unit Fuse0 is... <3> Fuse1's Sec1 <3> And Fuse2's Sec2 <3> This serves as a group of sector fuse information signals. The Sec0 of fuse unit Fuse0... <2> Fuse1's Sec1 <2> And Fuse2's Sec2 <2> This serves as a group of sector fuse information signals. The Sec0 of fuse unit Fuse0... <1> Fuse1's Sec1 <1> And Fuse2's Sec2 <1> This serves as a group of sector fuse information signals. The Sec0 of fuse unit Fuse0... <0> Fuse1's Sec1 <0> And Fuse2's Sec2 <0> As a set of sector fuse information signals, four sets of sector fuse information signals are thus formed.

[0111] In step S260, according to Fuse0's Sec0 <3> Fuse1's Sec1 <3> And Fuse2's Sec2 <3> Obtain a sector existence information signal SelSec <3> When Fuse0's Sec0 <3> Fuse1's Sec1 <3> And Fuse2's Sec2 <3> When any one of the signals is high, the sector has an information signal SelSec. <3> A high level indicates that the target refresh row address exists in the replaced row address stored in fuse units Fuse0, Fuse1, or Fuse2, and that the target refresh row address belongs to the third sector. This is based on the Sec0 parameter of fuse unit Fuse0. <2> Fuse1's Sec1 <2> And Fuse2's Sec2 <2> Obtain a sector existence information signal SelSec <2> When Fuse0's Sec0 <2> Fuse1's Sec1 <2> And Fuse2's Sec2 <2> When any one of the signals is high, the sector has an information signal SelSec. <2> A high level indicates that the target refresh row address exists in the replaced row address stored in fuse units Fuse0, Fuse1, or Fuse2, and that the target refresh row address belongs to the second sector. This is based on the Sec0 parameter of fuse unit Fuse0. <1> Fuse1's Sec1 <1> And Fuse2's Sec2 <1> Obtain a sector existence information signal SelSec <1> When Fuse0's Sec0 <1> Fuse1's Sec1 <1> And Fuse2's Sec2 <1> When any one of the signals is high, the sector has an information signal SelSec. <1> A high level indicates that the target refresh row address exists in the replaced row address stored in fuse units Fuse0, Fuse1, or Fuse2, and that the target refresh row address belongs to the first sector. This is based on the Sec0 parameter of fuse unit Fuse0. <0> Fuse1's Sec1 <0> And Fuse2's Sec2 <0> Obtain a sector existence information signal SelSec <0> When Fuse0's Sec0 <0> Fuse1's Sec1 <0> And Fuse2's Sec2 <0> When any one of the signals is high, the sector has an information signal SelSec. <0> A high level indicates that the target refresh row address exists in the replaced row address stored in fuse cells Fuse0, Fuse1, or Fuse2, and that the target refresh row address belongs to sector zero.

[0112] In step S270, based on the sector presence information signal SelSec <0> SelSec <1> SelSec <2> SelSec <3> Determine if the address of each target refresh line exists in the address of the replaced line in the reference module.

[0113] As an example, if SelSec <0> SelSec <1> SelSec <2> SelSec <3> If either of these signals is high, it indicates that the target refresh row address is stored in the fuse cell. In this case, the refresh of the word line pointed to by the target refresh row address is skipped.

[0114] If SelSec <0> SelSec <1> SelSec <2> SelSec <3> If multiple signals are high simultaneously, then the refresh of the word lines pointed to by multiple target refresh row addresses will be skipped at the same time. For example, SelSec <0> and SelSec <2> When both signals are high, the refresh of the word lines pointed to by the target refresh line address in both the zeroth and second sectors is skipped.

[0115] In one embodiment, step S230 includes: for each fuse unit, performing a bitwise AND operation on the Match information signal Match of each of its coded address bits to obtain the full match information signal AllAddMatch of each fuse unit.

[0116] As an example, for the aforementioned fuse unit Fuse0, the matching information signal Match0 for each of its encoded address bits can be used. <13> To Match0 <2> Perform an AND logic operation to obtain the full match information signal AllAddMatch0 from fuse unit Fuse0. When Match0... <13> To Match0 <2> When all signals are high, AllAddMatch0 will be a high-level signal.

[0117] In one embodiment, see Figure 3 Step S230 further includes:

[0118] Step S231: For each fuse unit, perform AND and NOT logic operations on the Match information signals of each encoded address bit to obtain the group matching information signals.

[0119] Step S232: Perform a OR-NOT operation on each group of matching information signals to obtain the full match information signal AllAddMatch for each fuse unit.

[0120] As an example, for the above fuse unit Fuse0:

[0121] In step S231, the matching information signal Match0 of each encoded address bit can be used. <13> To Match0 <2> Divide into four groups to perform AND and NOT logical operations.

[0122] Specifically, Match0 <13> Match0 <12> Match0 <11> Grouping the three together, perform a AND-NOT logical operation on them to obtain a group matching information signal. Match0 <10> Match0 <9> Match0 <8> Grouping the three together, perform a AND-NOT logical operation on them to obtain a group matching information signal. Match0 <7> Match0 <6> Match0 <5> Grouping the three together, perform a AND-NOT logical operation on them to obtain a group matching information signal. Match0 <4> Match0 <3> Match0 <2> Group them together, perform a AND-NOT logical operation on the three to obtain a group matching information signal.

[0123] When used as a pair of AND and NOT logical operators (such as Match0) <13> Match0 <12> Match0 <11> When all three signals are high, the group matching information signal output by the AND-NOT logic operation is low. Otherwise, it is high.

[0124] In step S232, a NOR operation is performed on the four group matching information signals obtained from the AND-NOT logic operation to obtain the full match information signal AllAddMatch for each fuse unit. When all four group matching information signals are low-level signals, the full match information signal AllAddMatch for the fuse unit is a high-level signal. Otherwise, it is a low-level signal.

[0125] In this embodiment, by performing AND-NOT operations on the Match information signals of each coded address bit, and then performing OR-NOT operations on each group of Match information signals, the AllAddMatch information signal of each fuse unit is obtained, thereby effectively reducing the number of devices and lowering production costs.

[0126] Of course, in other embodiments, the groups may not be used, and this application does not limit this.

[0127] In one embodiment, step S240 includes: for each fuse unit, performing an AND operation between its corresponding full match information signal AllAddMatch and n sector address information signals SecEn to obtain the n sector fuse information signals Sec of the fuse unit.

[0128] As an example, for the aforementioned fuse unit Fuse0, its full match information signal AllAddMatch0 and its four sector address information signals SecEn0 can be used. <3> SecEn0 <2> SecEn0 <2> SecEn0 <0> Perform AND logic operations on each sector to obtain the Sec0 sector fuse information signals of the fuse unit. <3> Sec0 <2> Sec0 <1> Sec0 <0> .

[0129] Four sector address information signals SecEn0 <3> SecEn0 <2> SecEn0 <1> SecEn0 <0> Only one of the four sector fuse information signals is high, indicating that the replaced row address stored in fuse unit Fuse0 belongs to the sector corresponding to that high-level signal. When AllAddMatch0 is high, the four sector fuse information signals Sec0 are acquired. <3> Sec0 <2> Sec0 <1> Sec0 <0> One of them is a high-level signal. This indicates that the address of the replaced row stored in Fuse0 is the same as the address of the target refresh row in one of the sectors.

[0130] Otherwise, when AllAddMatch0 is low, the four sector fuse information signals Sec0 are acquired. <3> Sec0 <2> Sec0 <1> Sec0 <0> All are low-level signals. This indicates that the address of the replaced row stored in Fuse0 is different from the target refresh row address in any sector.

[0131] In one embodiment, step S260 includes: performing an OR logic operation on k sector fuse information signals from n groups of sector fuse information signals to obtain n sector existence information signals SelSec.

[0132] As an example, for the above fuse units Fuse0, Fuse1, and Fuse2, the Sec0 of fuse unit Fuse0... <3> Fuse1's Sec1 <3> And Fuse2's Sec2 <3> Perform an OR logical operation to obtain the sector existence information signal SelSec <3> If Fuse0's Sec0 <3> Fuse1's Sec1 <3> And Fuse2's Sec2 <3> When any one of them is a high-level signal, the sector contains the information signal SelSec. <3> A high-level signal indicates that the target refresh row address located in the third sector is stored in fuse unit Fuse0, Fuse1, or Fuse2. Otherwise, if Fuse0's Sec0... <3> Fuse1's Sec1 <3> And Fuse2's Sec2 <3> When all signals are low, the sector contains the information signal SelSec. <3> If the signal is low, it means that the target refresh row address located in the third sector is not stored in any of the fuse units Fuse0, Fuse1, or Fuse2.

[0133] Similarly, Sec0 of fuse unit Fuse0... <2> Fuse1's Sec1 <2> And Fuse2's Sec2 <2> Perform an OR logical operation to obtain the sector existence information signal SelSec <2> This allows us to determine whether the target refresh line address located in the second sector is stored in fuse unit Fuse0, Fuse1, or Fuse2.

[0134] Sec0 of fuse unit Fuse0 <1> Fuse1's Sec1 <1> And Fuse2's Sec2 <1> Perform an OR logical operation to obtain the sector existence information signal SelSec <1> This allows us to determine whether the target refresh line address located in the first sector is stored in fuse unit Fuse0, Fuse1, or Fuse2.

[0135] Sec0 of fuse unit Fuse0 <0> Fuse1's Sec1 <0> And Fuse2's Sec2 <0> Perform an OR logical operation to obtain the sector existence information signal SelSec <0> This allows us to determine whether the target refresh line address located in sector zero is stored in fuse unit Fuse0, Fuse1, or Fuse2.

[0136] It should be understood that, although Figures 1-3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-3 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0137] In one embodiment, see Figure 4 A storage device refresh system is provided, comprising: an acquisition module 100, a reference module 200, a judgment module 300, and a control module 400.

[0138] The acquisition module 100 is used to acquire the target refresh line address. The reference module 200 is used to store the address of the replaced line, which corresponds to the damaged word line. The judgment module 300 is connected to the acquisition module 100 and the reference module 200, and is used to determine whether the target refresh line address exists in the replaced line address in the reference module 200. The control module 400 is connected to the judgment module, and is used to control the skipping of refreshing the word line pointed to by the target refresh line address when the target refresh line address exists in the replaced line address in the reference module 200.

[0139] In this embodiment, the judgment module 300 determines whether the target refresh line address exists in the replaced line address in the reference module 200. When the target refresh line address exists in the replaced line address in the reference module 200, the control module 400 skips the refresh of the word line pointed to by the target refresh line address. This can effectively avoid damaged word lines and prevent the data in adjacent word lines from being corrupted due to refreshing damaged word lines. This can effectively reduce the risk of data corruption in the storage device during the refresh process.

[0140] In one embodiment, see Figure 5 The reference module 200 includes k fuse units 210, each fuse unit storing the address of a row to be replaced, where k is an integer greater than 0.

[0141] In one embodiment, the target refresh row address includes n target refresh row addresses belonging to n different sectors. Both the target refresh row address and the replaced row address stored in the fuse unit include *a* sector address bits and *b* coded address bits. The sector address bits are used to store sector address information. The coded address bits are used to store row address information within each sector. The information stored in the *b* coded address bits of the n target refresh row addresses is identical, and the *b* coded addresses of the target refresh row addresses serve as the target coded address bits, where *a* and *b* are both integers greater than 0.

[0142] In this embodiment, please continue to refer to Figure 5 The judgment module 300 includes a judgment unit 320 and k judgment units 310. Each judgment unit 310 is connected to a fuse unit 210 in a one-to-one correspondence. Each judgment unit 310 processes the relevant data of a fuse unit 210.

[0143] Specifically, please refer to Figure 6 as well as Figure 7 Each judgment unit 310 includes a decoding circuit 311, a comparison circuit 312, a matching circuit 313, and a judgment circuit 314.

[0144] The decoding circuit 311 is connected to a fuse unit 210, receives the information stored in each sector address bit of the fuse unit 210, and decodes and outputs n sector address information signals SecEn of the fuse unit 210 according to the information stored in each sector address bit.

[0145] The comparator circuit 312 is connected to a fuse unit 210 and includes b comparator sub-circuits 3121. Each comparator sub-circuit 3121 simultaneously receives information stored in a pair of corresponding target encoded address bits and information stored in the encoded address bits of the fuse unit 210. Based on the comparison between the information stored in a pair of corresponding target encoded address bits and the information stored in the encoded address bits of the fuse unit 210, it outputs a matching information signal Match for the corresponding encoded address bits.

[0146] The matching circuit 313 is connected to each of the comparison sub-circuits 3121 of the comparison circuit 312, receives the matching information signal Match output by each comparison sub-circuit 3121, and outputs the full matching information signal AllAddMatch of the fuse unit 210 according to each matching information signal Match.

[0147] The judgment circuit 314 connects the matching circuit 313 and the decoding circuit 311, and includes n judgment sub-circuits 3141. Each judgment sub-circuit 3141 receives the full match information signal AllAddMatch output by the matching circuit 313 and a corresponding sector address information signal SecEn. Based on the full match information signal AllAddMatch and the sector address information signal SecEn, it obtains a sector fuse information signal Sec from the fuse unit 210.

[0148] Please see Figure 8 The determination unit 320 is connected to k determination units 310 and includes n determination circuits 321. Each determination circuit 321 receives k sector fuse information signals Sec belonging to the same sector and obtains a sector existence information signal SelSec.

[0149] In one embodiment, see Figure 7 The comparator circuit 3121 includes an XNOR gate. The number of comparator circuits 3121 can be the same as the number of encoding address bits. When the input levels are the same, the XNOR gate outputs a high level. Therefore, when the information stored in a pair of corresponding target encoding address bits received by a comparator circuit 3121 is the same as the information stored in the encoding address bits of the fuse unit 210 (both are "0" or both are "1"), the comparator circuit 3121 outputs a high level.

[0150] In one embodiment, see Figure 7 The matching circuit 313 includes a first matching circuit 3132 and at least two second matching circuits 3131. Each second matching circuit 3132 is connected to a set of comparison sub-circuits 3121, receives the matching information signal Match from the set of comparison sub-circuits, and outputs a set of matching information signals according to the Match signals Match output by the set of comparison sub-circuits.

[0151] The first matching circuit 3132 is connected to each of the second matching circuits 3131, receives the group matching information signals output by each of the second matching circuits 3131, and outputs the full matching information signal AllAddMatch of the fuse unit 210 according to each group matching information signal.

[0152] In this embodiment, a matching circuit 313 is formed by the first matching circuit 3132 and at least two second matching circuits 3131, and then the matching information signal Match output by each comparator sub-circuit 3121 is grouped for processing, thereby effectively reducing the number of devices and reducing production costs.

[0153] Of course, in other embodiments, the Match information signals output by each comparator circuit 3121 may not be grouped, and this application does not limit this.

[0154] In one embodiment, see Figure 7 The second matching circuit 3131 includes a first NAND gate, and the first matching circuit 3132 includes a first NOR gate.

[0155] In this embodiment, the first NAND gate and the first NOR gate can effectively perform AND logic operations on the Match information signal output by each comparator sub-circuit 3121.

[0156] In one embodiment, see Figure 7 The decision sub-circuit 3141 includes a second NAND gate and a first NOT gate. The input of the second NAND gate is connected to the matching circuit 3132 and the decoding circuit 311. The output of the second NAND gate is connected to the input of the first NOT gate, and the output of the first NOT gate is connected to the corresponding decision circuit 321.

[0157] In this embodiment, the second NAND gate and the first NOT gate can effectively perform an AND logic operation on the full match information signal AllAddMatch output by the matching circuit 3132 and the sector address information signal SecEn output by the decoding circuit 311.

[0158] In one embodiment, see Figure 8 The determination circuit 321 includes a second NOR gate and a second NOT gate. The input of the second NOR gate is connected to k determination units 310. The output of the second NOR gate is connected to the input of the second NOT gate, and the output of the second NOT gate is used to output the sector presence information signal SelSec.

[0159] In this embodiment, the OR logic operation is effectively implemented on the fuse information signals Sec of the k sectors belonging to the same sector of the k judgment units 310 through the second NOR gate and the second NOT gate.

[0160] Understandable, Figure 7 , Figure 8 The circuit diagram shown is a specific embodiment, which is consistent with the implementation of the memory device refresh system in the previous embodiments and can implement the memory device refresh method in the previous embodiments. However, this application is not limited to... Figure 7 , Figure 8 The specific embodiment shown is an example of a method that can implement the storage device refresh function of this application. All implementation methods that can achieve the storage device refresh function of this application are within the protection scope of this application.

[0161] Specific limitations regarding the storage device refresh system can be found in the limitations of the storage device refresh method described above, and will not be repeated here. Each module in the aforementioned storage device refresh system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module. It should be noted that the module division in this embodiment is illustrative and only represents a logical functional division; other division methods may be used in actual implementation.

[0162] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0163] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0164] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0165] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.< / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A method for refreshing a storage device, characterized in that, include: Get the address of the target refresh row; Determine whether the target refresh line address exists in the replaced line address in the reference module, wherein the replaced line address corresponds to the damaged word line; If the target refresh line address exists in the replaced line address in the reference module, then skip refreshing the word line pointed to by the target refresh line address; If the target refresh line address does not exist in the replaced line address in the reference module, then the word line pointed to by the target refresh line address is refreshed; The reference module includes k fuse units, each fuse unit storing the address of a row to be replaced, where k is an integer greater than 0; The process of obtaining the target refresh row address includes: Obtain n target refresh row addresses belonging to n different sectors, where n is an integer greater than 0. The target refresh row address and the replaced row address stored in the fuse unit both include a sector address bits and b coded address bits. The sector address bits are used to store sector address information, and the coded address bits are used to store row address information in each sector. The information stored in the b coded address bits of the n target refresh row addresses is the same, and the b coded addresses of the target refresh row addresses are used as target coded address bits, where a and b are both integers greater than 0. The step of determining whether the target refresh line address exists in the replaced line address in the reference module includes: For each fuse unit, based on the information stored in each sector address bit therein, the n sector address information signals of the fuse unit are decoded to obtain the signal. For each fuse unit, the information stored in each of the encoded address bits is compared with the information stored in each of the target encoded address bits to obtain the matching information signal for each of the encoded address bits; For each fuse unit, the full match information signal of the fuse unit is obtained based on the match information signal of each of the coded address bits therein; For each fuse unit, based on its corresponding full match information signal and the n sector address information signals, the n sector fuse information signals of each fuse unit are obtained; The sector fuse information signals belonging to the same sector of k fuse units are taken as a group of sector fuse information signals to form n groups of sector fuse information signals. Each group of sector fuse information signals includes k sector fuse information signals belonging to the same sector. Based on k sector fuse information signals from the n groups of sector fuse information signals, obtain n sector existence information signals; Based on the presence information signals of the n sectors, determine whether each target refresh row address exists in the replaced row address in the reference module.

2. The storage device refresh method according to claim 1, characterized in that, For each fuse unit, based on the matching information signal of each of the encoded address bits therein, the full match information signal of the fuse unit is obtained, including: For each fuse unit, perform a bitwise AND operation on the matching information signals of its various coded address bits to obtain the full matching information signal of each fuse unit.

3. The storage device refresh method according to claim 2, characterized in that, For each fuse unit, the matching information signals of its various coded address bits are subjected to a bitwise AND operation to obtain the full matching information signal of each fuse unit, including: For each fuse unit, the matching information signals of its various coded address bits are grouped and ANDed / NOT logically to obtain the group matching information signals; Perform a OR-NOT operation on each set of matching information signals to obtain the full matching information signal for each fuse unit.

4. The storage device refresh method according to claim 1, characterized in that, For each fuse unit, the process of obtaining n sector fuse information signals for each fuse unit based on its corresponding full match information signal and the n sector address information signals includes: For each fuse unit, perform an AND operation between its corresponding full match information signal and the n sector address information signals to obtain the n sector fuse information signals of the fuse unit.

5. The storage device refresh method according to claim 1, characterized in that, The step of obtaining n sector presence information signals based on k sector fuse information signals from the n sets of sector fuse information signals includes: Perform an OR operation on k sector fuse information signals from n groups of sector fuse information signals to obtain n sector presence information signals.

6. A storage device refresh system, characterized in that, include: The acquisition module is used to obtain the address of the target refresh row; A reference module is used to store the address of the line to be replaced, which corresponds to a damaged word line; The judgment module, connected to the acquisition module and the reference module, is used to determine whether the target refresh row address exists in the replaced row address in the reference module; The control module, connected to the judgment module, is used to control the skipping of the word line pointed to by the target refresh line address when the target refresh line address exists in the replaced line address in the reference module. The reference module includes k fuse units, each fuse unit storing the address of a row to be replaced, where k is an integer greater than 0; The target refresh row address includes n target refresh row addresses belonging to n different sectors. Both the target refresh row address and the replaced row address stored in the fuse unit include a sector address bits and b coded address bits. The sector address bits are used to store sector address information, and the coded address bits are used to store row address information in each sector. The information stored in the b coded address bits of the n target refresh row addresses is the same, and the b coded addresses of the target refresh row address are used as target coded address bits. a and b are both integers greater than 0. The judgment module includes a judgment unit and k judgment units; The judgment unit is connected to the fuse unit in a one-to-one correspondence, and each judgment unit includes: The decoding circuit is connected to one of the fuse units, receives the information stored in each sector address bit of the fuse unit, and decodes and outputs n sector address information signals of the fuse unit according to the information stored in each sector address bit. The comparison circuit is connected to one of the fuse units and includes b comparison sub-circuits. Each comparison sub-circuit simultaneously receives information stored in a pair of corresponding target encoding address bits and information stored in the encoding address bits of the fuse unit, and outputs a matching information signal for the corresponding encoding address bits based on the comparison between the information stored in a pair of corresponding target encoding address bits and information stored in the encoding address bits of the fuse unit. A matching circuit is connected to each of the comparison sub-circuits of the comparison circuit, receives the matching information signals output by each of the comparison sub-circuits, and outputs the full matching information signal of the fuse unit according to each of the matching information signals. The judgment circuit, connected to the matching circuit and the decoding circuit, includes n judgment sub-circuits. Each judgment sub-circuit receives the full match information signal output by the matching circuit and a corresponding sector address information signal, and obtains a sector fuse information signal of the fuse unit based on the full match information signal and the sector address information signal. The determination unit is connected to k determination units, including n determination circuits. Each determination circuit receives k sector fuse information signals belonging to the same sector and obtains a sector existence information signal.

7. The storage device refresh system according to claim 6, characterized in that, The comparator circuit includes an XNOR gate.

8. The storage device refresh system according to claim 6, characterized in that, The matching circuit includes a first matching circuit and at least two second matching circuits; each second matching circuit is connected to a set of comparator sub-circuits, receives matching information signals from the set of comparator sub-circuits, and outputs a set matching information signal based on the matching information signals output by the set of comparator sub-circuits; the first matching circuit is connected to each of the second matching circuits, receives the set matching information signals output by each of the second matching circuits, and outputs the full matching information signal of the fuse unit based on the set matching information signals.

9. The storage device refresh system according to claim 8, characterized in that, The second matching circuit includes a first NAND gate, and the first matching circuit includes a first NOR gate.

10. The storage device refresh system according to claim 6, characterized in that, The judgment sub-circuit includes a second NAND gate and a first NOT gate. The input of the second NAND gate is connected to the matching circuit and the decoding circuit. The output of the second NAND gate is connected to the input of the first NOT gate. The output of the first NOT gate is connected to the corresponding judgment circuit.

11. The storage device refresh system according to claim 6, characterized in that, The determination circuit includes a second NOR gate and a second NOT gate. The input of the second NOR gate is connected to k determination units, and the output of the second NOR gate is connected to the input of the second NOT gate. The output of the second NOT gate is used to output the sector presence information signal.

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