Method for improving chip warpage

Abstract

A method for improving warpage of a chip is disclosed. The method includes providing a substrate having a plurality of metal interconnects formed thereon, forming a dielectric layer on the substrate and the plurality of metal interconnects using a high density plasma chemical vapor deposition process, wherein a surface of the dielectric layer is higher than a top surface of the plurality of metal interconnects, planarizing the dielectric layer using a chemical mechanical planarization process, wherein a surface of the planarized dielectric layer is higher than the top surface of the plurality of metal interconnects, and forming a first high stress tetraethoxysilane layer on the dielectric layer.

Description

Technical Field

[0001] This invention relates to a method for improving chip warpage, and more specifically, to a method for improving chip warpage through a high-stress tetraethyl orthosilicate (TEOS) layer structure. Background Technology

[0002] 3D ICs are a technology that vertically integrates multiple chips or wafers in three-dimensional space to address the limitations of current electronic and materials physics in semiconductor manufacturing processes. In wafer-on-wafer (WoW) technology, electronic components are built on two or more semiconductor chips, which are then aligned, bonded, and diced to form a 3D integrated circuit. Signal transmission between components is achieved through vertical interconnect structures using through-silicon vias (TSVs). The advantages of 3D ICs include: integrating more functionality into a smaller layout space, extending Moore's Law and enabling smaller yet more powerful next-generation devices; reduced circuit design and manufacturing costs; the ability to build circuit layers on different types of manufacturing processes and chips for component optimization; shorter internal interconnects; and significantly reduced chip power consumption.

[0003] However, chip stacking technology has very strict requirements regarding the warpage of the constituent chips. Generally, the layered structures formed on a chip exert stress on it, whether tensile or compressive, causing the chip to warp upwards or downwards. Severe warpage can affect chip bonding and the electrical connections after stacking. Therefore, improving chip warpage is one of the important issues in 3D chip technology. Summary of the Invention

[0004] In view of the aforementioned problems with chip warpage, this invention proposes a method to improve chip warpage, characterized by offsetting the inherent stress of the chip by additionally forming a high-stress tetraethylorthosilicate (TEOS) layer in the inter-metal dielectric layer. Simultaneously, this method also avoids the formation of vias between metal interconnects.

[0005] The present invention aims to provide a method for improving chip warpage, the steps of which include providing a substrate on which a plurality of metal interconnects are formed; forming a dielectric layer on the substrate and the metal interconnects using a high-density plasma chemical vapor deposition process, wherein the surface of the dielectric layer is higher than the top surface of the metal interconnects; performing a chemical mechanical planarization process to planarize the dielectric layer, wherein the surface of the planarized dielectric layer is higher than the top surface of the metal interconnects; and forming a first high-stress tetraethoxysilane layer on the dielectric layer.

[0006] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0007] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of the embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0008] Figures 1 to 3 This is a cross-sectional schematic diagram of the method flow for improving chip warpage in a preferred embodiment of the present invention;

[0009] Figure 4 This is a line graph showing the relationship between the thickness ratio of the first high-stress TEOS layer and the normalized value of chip warpage in a preferred embodiment of the present invention.

[0010] Figures 5 to 7 This is a cross-sectional schematic diagram of a method flow for improving chip warpage in another embodiment of the present invention;

[0011] Figure 8 This is a line graph showing the thickness ratio of the second high-stress TEOS layer versus the normalized chip warpage value in another embodiment of the present invention; and

[0012] Figure 9 This is a flowchart of a method for improving chip warpage in another embodiment of the present invention.

[0013] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0014] Symbol Explanation

[0015] 100 base

[0016] 102 Metal interconnect

[0017] 104 dielectric layer

[0018] 106 High-stress tetraethoxysilane (TEOS) layer

[0019] 108 High-stress tetraethoxysilane (TEOS) layer

[0020] 110 holes

[0021] Steps S1 to S8 Detailed Implementation

[0022] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various features in the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0023] Readers should easily understand that the meanings of "on," "above," and "above" in this case should be interpreted broadly, so that "on" not only means "directly on" something but also includes the meaning of being "on" something with an intermediary feature or layer, and "above" or "above" not only means "above" or "above" something but can also include the meaning of being "above" or "above" something without an intermediary feature or layer (i.e., directly on something).

[0024] In addition, spatial terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein for convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0025] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in multiple senses. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0026] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0027] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0028] The following embodiments will now be implemented in sequence according to... Figures 1 to 3 The cross-sectional structure is used to illustrate the method flow for improving chip warpage according to the present invention. It should be noted that the method for improving chip warpage according to the present invention is preferably implemented in the inter-metal dielectric (IMD) layer in the back-end semiconductor fabrication process (BEOL), particularly in chips that will subsequently undergo chip stacking and bonding, to ensure the formation of good electrical connections after chip stacking and bonding, as claimed by the invention. As for the structures and components generally present in the front-end semiconductor fabrication process (FEOL), such as active regions and transistors, since they are not the focus of this invention and are not related to the features of this invention, these components will be omitted in the figures for the sake of brevity in the illustration and description.

[0029] First, please refer to... Figure 1A substrate 100 is provided, such as a substrate made of a semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium compounds, silicon carbide, and gallium arsenide. The substrate 100 preferably includes active regions, transistors, inter-layer dielectric (ILD) and / or inter-metal dielectric (IMD), metal interconnect structures, etc. (not shown). Metal interconnects 102 are formed on the substrate 100, which are spaced apart and have top surfaces of equal height. In embodiments of the invention, the metal interconnects 102 may be metal interconnect layers in general back-end fabrication processes, such as M1, M2, M3, etc., and their material may be an aluminum-copper alloy. They may be formed by physical vapor deposition (PVD) or various chemical vapor deposition (CVD) processes to form metal layers, followed by patterning by photolithography. Different metal interconnect layers may be electrically interconnected by vias (not shown).

[0030] Please refer to Figure 2 After forming the metal interconnect 102, a dielectric layer 104 is then formed on the substrate 100 and the metal interconnect 102. In this embodiment of the invention, the dielectric layer 104 can be an inter-metal dielectric layer, and its material can be silicon oxide or a low-k material, such as porous silicon oxide, fluorinated silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), amorphous carbon (aC and aC:H), fluorinated amorphous carbon (aC:F), etc. It can be formed by a high-density plasma chemical vapor deposition (HDP-CVD) process with high hole-filling capability to avoid the generation of voids between the metal interconnects 102. After the dielectric layer 104 is formed, a chemical mechanical planarization (CMP) process can be performed to planarize its surface. The planarized dielectric layer 104 surface is higher than the top surface of the metal interconnect 102.

[0031] In existing technologies, high-density plasma chemical vapor deposition (HDPD) processes exhibit good cavity-filling properties, but the low-stress characteristics of the resulting layer structure cannot alleviate chip warpage issues. Therefore, this invention aims to create an additional layer to address this problem. Please refer to... Figure 3 After forming the dielectric layer 104, a first high-stress tetraethyl orthosilicate (TEOS) layer 106 is then formed on the surface of the dielectric layer 104, which can be formed by plasma-assisted chemical vapor deposition (PECVD). After the first high-stress tetraethyl orthosilicate layer 106 is formed, its surface can be planarized and its thickness controlled by a chemical mechanical planarization process.

[0032] In this embodiment of the invention, the stress of the first high-stress TEOS layer 106 changes with its deposition thickness. For example... Figure 4 As shown, this is a line graph of the thickness ratio of the first high-stress TEOS layer 106 versus the normalized chip warpage. The x-axis represents the thickness ratio of the first high-stress TEOS layer 106, where POR represents the standard fabrication process without any TEOS layer (thickness 0), 100% represents the case where the TEOS layer thickness is maximized, and so on. The y-axis represents the normalized warpage of the chip with the first high-stress TEOS layer 106 formed, where positive values ​​represent the degree of downward warpage and negative values ​​represent the degree of upward warpage. As can be seen from the graph, in the embodiment of the present invention, in the standard fabrication process (POR) without any TEOS layer, the chip will warp downward due to the stress generated by the various layer structures formed on it (normalized value 1). In the example where a TEOS layer of maximum thickness is formed, the stress causing the chip to warp downward is offset by the stress generated by the first high-stress TEOS layer 106, and the resulting stress is even too large, causing the chip to warp upward (normalized value -1.37). In the example where a first high-stress TEOS layer 106 with a thickness of approximately 52.4% is formed, the stress causing the chip to warp downwards is precisely offset by the stress generated by depositing this first high-stress TEOS layer 106, resulting in the chip hardly warping in any direction (normalized value -0.49), achieving optimal performance. Therefore, it can be seen that in this embodiment of the invention, forming a first high-stress TEOS layer 106 of a specific thickness on the gap-filling dielectric layer 104 can effectively improve the chip warping problem.

[0033] The following text will proceed in sequence according to... Figures 5 to 7 The cross-sectional structure is used to illustrate the method flow for improving chip warpage according to another embodiment of the present invention. In this embodiment, in addition to the first high-stress TEOS layer 106 mentioned in the foregoing embodiments, an additional high-stress TEOS layer can be formed on the substrate before forming the dielectric layer 104. Please refer to... Figure 5 After the metal interconnects 102 are formed, a second high-stress TEOS layer 108 is first formed on the substrate 100. This second high-stress TEOS layer 108 can be formed using a plasma-assisted chemical vapor deposition (PECVD) process, and its thickness can be controlled by subsequent planarization and / or etch-back processes. In this embodiment of the invention, the surface of the second high-stress TEOS layer 108 is lower than the top surface of the metal interconnects 102 and is located between the metal interconnects 102.

[0034] Please refer to Figure 6After forming the second high-stress TEOS layer 108, a dielectric layer 104 is then formed on the second high-stress TEOS layer 108 and the metal interconnect 102. The dielectric layer 104 can be an intermetallic dielectric layer, and its material can be silicon oxide or a low-k material, such as porous silicon oxide, fluorinated silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), amorphous carbon (aC and aC:H), fluorinated amorphous carbon (aC:F), etc., which can be formed by a high-density plasma chemical vapor deposition (HDP-CVD) process. In this embodiment of the invention, since the second high-stress TEOS layer 108 does not have good hole-filling ability, after the dielectric layer 104 is formed, a hole 110 will be formed between the dielectric layer 104 and the second high-stress TEOS layer 108. However, since the dielectric layer 104 is formed by high-density plasma chemical vapor deposition (HDP-CVD) with good hole-filling ability, the formed holes 110 will be confined to the area near the second high-stress TEOS layer 108, and their tops will not exceed the top surface of the metal interconnect 102, thus avoiding these holes from affecting subsequent manufacturing processes.

[0035] Please refer to Figure 7 After the dielectric layer 104 is formed, a chemical mechanical planarization (CMP) process is performed to planarize the surface of the dielectric layer 104. The planarized surface of the dielectric layer 104 is higher than the top surface of the metal interconnect 102. Then, similar to the previous embodiment, a first high-stress TEOS layer 106 is formed on the surface of the dielectric layer 104, which can be formed using a plasma-assisted chemical vapor deposition (PECVD) process. After the first high-stress TEOS layer 106 is formed, a chemical mechanical planarization process can be performed to planarize its surface and control its thickness.

[0036] In this embodiment of the invention, the stress of the second high-stress TEOS layer 108 formed on the substrate 100 changes with its deposition thickness, and it also has the effect of improving chip warpage. Figure 8As shown, POR represents the standard fabrication process without any TEOS layer (thickness 0), the percentage represents the thickness ratio of the formed TEOS layer, and so on. The y-axis represents the normalized warpage of the chip with the second high-stress TEOS layer 108 formed, where positive values ​​represent the degree of downward warping of the chip, and negative values ​​represent the degree of upward warping of the chip. As can be seen from the figure, in the embodiment of the present invention, in the standard fabrication process (POR) without any TEOS layer, the chip will warp downward due to the stress generated by the various layer structures formed on it (normalized value 1). In the example where the substrate 100 has a second high-stress TEOS layer 108 formed, the stress portion that causes the chip to warp downward is offset by the stress generated by the deposition of the second high-stress TEOS layer 108 (normalized value decreases to 0.64), improving the chip warpage problem.

[0037] Please refer to now. Figure 9 This is a flowchart of a method according to the above embodiment of the present invention. First, in step S1, a second high-stress TEOS layer 108 (e.g., ...) is deposited on the substrate 100. Figure 5 (As shown). Next, in step S2, a dielectric layer 104 (as shown) is deposited on the second high-stress TEOS layer 108 using a high-density plasma chemical vapor deposition (HDP-CVD) process. Figure 6 (As shown). Next, in step S3, CMP fabrication is performed to planarize the dielectric layer 104 (as shown). Figure 7 (As shown). Next, in step S4, a first high-stress TEOS layer 106 is deposited on the dielectric layer 104 (as shown). Figure 7 (As shown). Next, in step S5, CMP fabrication is performed to planarize the first high-stress TEOS layer 106 (as shown). Figure 7 (As shown). After the above manufacturing process is completed, the next step S6 can measure the chip warpage, for example, using a specialized optical measuring machine or pressure measuring machine, which can determine whether the chip warpage is within the allowable range. After the chip warpage measurement, in step S7, the chip can be sliced ​​to check whether the holes formed between the metal interconnects extend beyond their top surface. If they do, the entire process will return to step S1, reset the thickness of the first high-stress TEOS layer 106 and the second high-stress TEOS layer 108 to be deposited, and repeat steps S1-S7 until the chip warpage measurement and hole slicing inspection are both passed. This ensures that the thickness of the two high-stress TEOS layers is set to the optimal value, ensuring the quality of the final product after actual production. If the warpage does not exceed the allowable range, the process ends in S8.

[0038] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for improving chip warpage, comprising: A substrate is provided on which multiple metal interconnects are formed; A dielectric layer is formed on the substrate and the metal interconnects using a high-density plasma chemical vapor deposition process, wherein the surface of the dielectric layer is higher than the top surface of the metal interconnects; The dielectric layer is planarized using a chemical mechanical planarization process, and the surface of the planarized dielectric layer is higher than the top surface of the metal interconnects. as well as A first high-stress tetraethoxysilane layer is formed on the surface of the planarized dielectric layer, wherein the first high-stress tetraethoxysilane layer is a single layer and the stress of the first high-stress tetraethoxysilane layer varies with its thickness. By adjusting the thickness of the first high-stress tetraethoxysilane layer, the stress of the first high-stress tetraethoxysilane layer is set to counteract the inherent stress of the substrate.

2. The method for improving chip warpage as claimed in claim 1 further comprises forming a second high-stress tetraethoxysilane layer on the substrate before forming the dielectric layer, wherein the surface of the second high-stress tetraethoxysilane layer is lower than the top surface of the metal interconnects and located between the metal interconnects, and the dielectric layer is formed on the second high-stress tetraethoxysilane layer.

3. The method for improving chip warpage as claimed in claim 2, wherein a hole is formed between the dielectric layer and the second high-stress tetraethoxysilane layer, the top of the hole being lower than the top surface of the metal interconnects.

4. The method for improving chip warpage as described in claim 2, wherein the second high-stress tetraethoxysilane layer is formed using a plasma-assisted chemical vapor deposition process.

5. The method for improving chip warpage as claimed in claim 2, wherein the stress of the second high-stress tetraethoxysilane layer varies with its thickness, and the stress of the second high-stress tetraethoxysilane layer is set to counteract the inherent stress of the substrate.

6. The method for improving chip warpage as claimed in claim 1, wherein the first high-stress tetraethoxysilane layer is formed using a plasma-assisted chemical vapor deposition process.

7. The method for improving chip warpage as described in claim 1 further comprises performing another chemical mechanical planarization process to planarize the first high-stress tetraethoxysilane layer after its formation.

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