Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The semiconductor device manufacturing method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a redundant area and an array area; sequentially forming a dielectric layer, a conductive layer and a mask structure layer in the redundant area and the array area respectively; patterning the mask structure layer to form a positioning hole; depositing a photoresist layer; removing the photoresist layer in the array area; in the array area, patterning the conductive layer, the dielectric layer and part of the semiconductor substrate along the positioning hole, and removing the mask structure layer with the positioning hole; and in the array area, removing the conductive layer on the dielectric layer to form a bit line contact hole. The semiconductor device manufacturing method can effectively remove the part of the conductive layer corresponding to the formation of the peripheral gate in the bit line structure in the array area, reduce the parasitic capacitance, and the process is simple.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0002] In the fabrication process of semiconductor devices, a conductive layer needs to be deposited to form the gate structure when making the peripheral gate. When forming the bit line structure, this conductive layer is also formed in the bit line contact plugs in the bit line structure. Parasitic capacitance can easily be generated between this conductive layer in the bit line contact plugs and the conductive layer in the storage contact plugs, which affects the performance of the semiconductor device.

[0003] The information disclosed in the background section is only for enhancing the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] A primary objective of this invention is to provide a method for manufacturing a semiconductor device that can remove the conductive layer deposited during the fabrication of the peripheral gate, reduce parasitic capacitance, and is simple and low-cost.

[0005] Another object of the present invention is to provide a semiconductor device that has a simple fabrication process and can reduce parasitic capacitance.

[0006] To achieve the above objectives, according to one aspect of the present invention, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the semiconductor substrate including a redundant region and an array region; sequentially forming a dielectric layer, a conductive layer, and a mask structure layer in the redundant region and the array region, respectively; patterning the mask structure layer to form positioning holes; depositing a photoresist layer; removing the photoresist layer in the array region; patterning the conductive layer, the dielectric layer, and a portion of the semiconductor substrate along the positioning holes in the array region, and removing the mask structure layer having the positioning holes; and removing the conductive layer on the dielectric layer in the array region to form bit line contact holes.

[0007] According to an exemplary embodiment of the present invention, the mask structure layer includes a first mask layer, a second mask layer, a first etch stop layer, a third mask layer, a second etch stop layer and a fourth mask layer formed sequentially on the conductive layer.

[0008] According to an exemplary embodiment of the present invention, the step of patterning the mask structure layer to form a positioning hole includes: patterning the second etch stop layer and the third mask layer to form a first mask opening; forming a fifth mask layer in the first mask opening; and using the fifth mask layer as a mask, patterning the first etch stop layer, the second mask layer, and the first mask layer to form the positioning hole.

[0009] According to an exemplary embodiment of the present invention, the step of patterning the second etch stop layer and the third mask layer to form a first mask opening includes: patterning the fourth mask layer; using the patterned fourth mask layer as a mask, patterning the second etch stop layer and the third mask layer, and removing the fourth mask layer to form the first mask opening.

[0010] According to an exemplary embodiment of the present invention, the patterning of the fourth mask layer includes: forming a first photoresist layer on the fourth mask layer, patterning the first photoresist layer, and using the patterned first photoresist layer as a mask to pattern the fourth mask layer.

[0011] According to an exemplary embodiment of the present invention, forming a fifth mask layer in the first mask opening includes: filling the first mask opening with the fifth mask layer, wherein the fifth mask layer covers the upper surface of the second etch stop layer; removing the fifth mask layer covering the upper surface of the second etch stop layer, such that the upper surface of the fifth mask layer filling the first mask opening is flush with the upper surface of the second etch stop layer.

[0012] According to an exemplary embodiment of the present invention, before patterning the first etch stop layer, the second mask layer and the first mask layer using the fifth mask layer as a mask to form the positioning hole, the method further includes: removing the second etch stop layer; and removing the third mask layer.

[0013] According to an exemplary embodiment of the present invention, using the fifth mask layer as a mask, patterning the first etch stop layer, the second mask layer, and the first mask layer to form the positioning hole includes: using the fifth mask layer as a mask to remove portions of the first etch stop layer, the second mask layer, and the first mask layer not covered by the fifth mask layer, retaining the portions covered by the fifth mask layer to form a second mask opening; removing the fifth mask layer and the first etch stop layer; and removing the second mask layer to form the positioning hole.

[0014] According to an exemplary embodiment of the present invention, the mask structure layer having the positioning hole is the first mask layer having the positioning hole.

[0015] According to an exemplary embodiment of the present invention, after removing the conductive layer on the dielectric layer in the array region to form a bit line contact hole, the method further includes: removing the photoresist layer in the redundant region; and removing the first mask layer in the redundant region.

[0016] According to an exemplary embodiment of the present invention, the dielectric layer is made of silicon nitride, silicon oxide, silicon carbonitride, or silicon oxynitride, and the conductive layer is made of polycrystalline silicon, doped polycrystalline silicon, titanium nitride, tungsten nitride, or tungsten.

[0017] According to an exemplary embodiment of the present invention, the first mask layer, the fourth mask layer, and the fifth mask layer are made of the same material, including silicon oxide or silicon nitride; the second mask layer and the third mask layer are made of the same material, including spin-coated hard masks; the first etch stop layer and the second etch stop layer are made of the same material, including silicon oxynitride, silicon nitride, or silicon carbonitride.

[0018] According to an exemplary embodiment of the present invention, the process for forming the dielectric layer, the conductive layer and the mask structure layer includes atomic layer deposition, chemical vapor deposition, physical vapor deposition or spin coating.

[0019] According to an exemplary embodiment of the present invention, the removal process includes dry etching or wet etching.

[0020] According to an exemplary embodiment of the present invention, a bit line contact plug is formed in the bit line contact hole, the bit line contact plug being flush with the top surface of the dielectric layer.

[0021] According to an exemplary embodiment of the present invention, a conductive structure layer, a protective layer and an isolation structure are sequentially formed on the bit line contact plug to form a bit line structure.

[0022] According to an exemplary embodiment of the present invention, a storage node contact hole is formed between the bit line structures, and a storage node contact plug is formed in the storage node contact hole.

[0023] According to another aspect of the present invention, an embodiment of the present invention provides a semiconductor device, which is prepared by the manufacturing method described in any of the above embodiments.

[0024] As can be seen from the above technical solution, the present invention possesses at least one of the following advantages and positive effects:

[0025] The semiconductor device manufacturing method of the present invention can effectively remove the conductive layer portion in the bit line structure of the array region corresponding to the formation of the peripheral gate, reduce parasitic capacitance, and has a simple process. Attached Figure Description

[0026] The above and other features and advantages of the present invention will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0027] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device in the prior art;

[0028] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention;

[0029] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device in an exemplary embodiment of the present invention, showing the formation of a first photoresist layer on a fourth mask layer.

[0030] Figure 4 This is a cross-sectional schematic diagram of the removal of the patterned fourth mask layer in a semiconductor device according to an exemplary embodiment of the present invention;

[0031] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device forming a first mask opening in an exemplary embodiment of the present invention;

[0032] Figure 6 This is a cross-sectional schematic diagram of the formation of a fifth mask layer in a semiconductor device according to an exemplary embodiment of the present invention;

[0033] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device removing the second etch stop layer in an exemplary embodiment of the present invention;

[0034] Figure 8 This is a cross-sectional schematic diagram of a semiconductor device removing the third mask layer in an exemplary embodiment of the present invention;

[0035] Figure 9 This is a cross-sectional schematic diagram of a semiconductor device forming a second mask opening in an exemplary embodiment of the present invention;

[0036] Figure 10 This is a cross-sectional schematic diagram of the removal of the fifth mask layer and the first etch stop layer in a semiconductor device according to an exemplary embodiment of the present invention;

[0037] Figure 11 This is a cross-sectional schematic diagram of a semiconductor device in an exemplary embodiment of the present invention, showing the removal of a second mask layer to form a positioning hole.

[0038] Figure 12 This is a cross-sectional schematic diagram of a semiconductor device in an exemplary embodiment of the present invention, showing the formation of photoresist in a positioning hole;

[0039] Figure 13 This is a cross-sectional schematic diagram of the removal of photoresist in the array region of a semiconductor device according to an exemplary embodiment of the present invention;

[0040] Figure 14 This is a cross-sectional schematic diagram of the conductive layer, dielectric layer and part of the semiconductor substrate of the semiconductor device in an exemplary embodiment of the present invention, with the first mask layer etched along the positioning hole and removed.

[0041] Figure 15 This is a cross-sectional schematic diagram of a semiconductor device with the conductive layer removed from the array region in an exemplary embodiment of the present invention;

[0042] Figure 16 This is a schematic diagram of the slope surface of a semiconductor device in an exemplary embodiment of the present invention, showing the removal of the photoresist layer and the first mask layer in the redundant region.

[0043] Figure 17 This is a top view of a semiconductor device according to an exemplary embodiment of the present invention;

[0044] Figure 18 for Figure 17 A schematic diagram of the cross section along AA.

[0045] Explanation of reference numerals in the attached figures:

[0046] Related technologies:

[0047] BL', bit line structure; 3', conductive layer; 10', memory node contact plug.

[0048] This invention:

[0049] 1. Semiconductor substrate; 11. Active region; WL, word line; BL, bit line structure; 2. Dielectric layer; 3. Conductive layer; 4. Mask structure layer; 41. First mask layer; 42. Second mask layer; 43. First etch stop layer; 44. Third mask layer; 45. Second etch stop layer; 46. Fourth mask layer; 47. Fifth mask layer; 48. First photoresist layer; 5. Photoresist layer; 6. Bit line contact plug; 7. Conductive structure layer; 8. Protective layer; 9. Isolation structure; 10. Memory node contact plug;

[0050] S1, Redundancy area; S2, Array area; H1, Positioning hole; H2, Bit line contact hole; O1, First mask opening; O2, Second mask opening; STI, Shallow trench isolation. Detailed Implementation

[0051] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0052] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0053] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0054] Furthermore, in the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Above" and "below" are technical terms indicating orientation. In the embodiments of this invention, "above" refers to the direction in which other functional layers are sequentially formed on the semiconductor substrate. For example, the dielectric layer is located above the semiconductor substrate. This technical term is only for clearer description and has no limiting effect.

[0055] In related technologies, when fabricating a peripheral gate on a semiconductor device, a conductive layer 3' needs to be deposited to form the gate structure, such as... Figure 1 As shown, when forming the bit line structure BL', this conductive layer 3' is also formed in the bit line contact plug in the bit line structure BL'. Parasitic capacitance is easily generated between the conductive layer 3' of the bit line structure BL' and the conductive layer in the storage contact plug 10', which affects the performance of the semiconductor device.

[0056] According to one aspect of the present invention, an embodiment of the present invention provides a method for manufacturing a semiconductor device, please refer to... Figures 2 to 18 ,in, Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Figures 3 to 18 The diagram illustrates semiconductor devices at different manufacturing stages according to embodiments of the present invention. Figures 2 to 18 As shown, the method for manufacturing the semiconductor device of the present invention includes:

[0057] Step S10: Provide a semiconductor substrate 1, which includes a redundant region S1 and an array region S2.

[0058] Step S30: Dielectric layer 2, conductive layer 3 and mask structure layer 4 are formed sequentially in redundant region S1 and array region S2, respectively.

[0059] Step S50: Pattern the mask structure layer 4 to form positioning holes H1.

[0060] Step S70: Deposit photoresist layer 5.

[0061] Step S90: Remove the photoresist layer 5 in the array region S2.

[0062] Step S110: In the array region S2, the conductive layer 3, dielectric layer 2 and part of the semiconductor substrate 1 are patterned along the positioning hole H1, and the mask structure layer 4 with the positioning hole H1 is removed.

[0063] Step S130: In array region S2, remove the conductive layer 3 on dielectric layer 2 to form bit line contact hole H2.

[0064] The semiconductor device manufacturing method provided by the present invention can effectively remove the conductive layer 3 portion corresponding to the formation of the peripheral gate in the bit line structure BL in the array region S2, reduce parasitic capacitance, and the process is simple.

[0065] The manufacturing method of the semiconductor device of the present invention will be described in detail below.

[0066] Step S10: Provide a semiconductor substrate 1, which includes a redundant region S1 and an array region S2.

[0067] A shallow trench isolation (STI) is formed in a semiconductor substrate 1, defining multiple active regions 11. Array cells are formed on the semiconductor substrate 1, including word lines (WL), bit lines, and the aforementioned active regions 11. The array cells are located in array region S2, while redundant region S1 is the edge portion of array region S2, which includes incomplete array cells (such as...). Figure 17 (As shown).

[0068] The substrate material of the semiconductor device in this embodiment of the invention can be silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, or germanium-on-insulator, etc.

[0069] Step S30: Dielectric layer 2, conductive layer 3 and mask structure layer 4 are formed sequentially in redundant region S1 and array region S2, respectively.

[0070] Specifically, dielectric layer 2 is an insulating layer, and the material of dielectric layer 2 may include silicon nitride, silicon oxide, silicon carbonitride, or silicon oxynitride. The material of conductive layer 3 includes polycrystalline silicon, doped polycrystalline silicon, titanium nitride, tungsten nitride, or tungsten. Specifically, shallow trench isolation (STI) in semiconductor substrate 1 is also formed on the upper surface of semiconductor substrate 1, that is, there is a thin shallow trench isolation layer between semiconductor substrate 1 and dielectric layer 2, which is not shown here for simplified schematic diagram.

[0071] The above-mentioned sequential formation refers to the formation in sequence upwards, that is, forming a dielectric layer 2 on the semiconductor substrate 1, forming a conductive layer 3 on the dielectric layer 2, and forming a mask structure layer 4 on the conductive layer 3.

[0072] like Figure 3 As shown, the mask structure layer 4 includes multiple different layers. Specifically, these multiple different layers are a first mask layer 41, a second mask layer 42, a first etch stop layer 43, a third mask layer 44, a second etch stop layer 45, and a fourth mask layer 46, which are formed sequentially from the self-conductive layer 3.

[0073] The mask structure layer 4 can be patterned to form a desired pattern. In some embodiments, the first mask layer 41 and the fourth mask layer 46 may be made of the same material, including silicon oxide or silicon nitride. The second mask layer 42 and the third mask layer 44 may be made of the same material, including a spin-coated hard mask. The first etch stop layer 43 and the second etch stop layer 45 may be made of the same material, including silicon oxynitride, silicon nitride, or silicon carbonitride.

[0074] The processes for forming the dielectric layer 2, conductive layer 3, and mask structure layer 4 described above may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, or spin coating. Those skilled in the art can select specific processes according to actual conditions, and no special limitations are made here.

[0075] Step S50: Pattern the mask structure layer 4 to form the positioning hole H1, which includes the following sub-steps.

[0076] Step S501: Pattern the second etch stop layer 45 and the third mask layer 44 to form the first mask opening O1.

[0077] like Figure 3 and Figure 4 As shown, a first photoresist layer 48 is formed on the fourth mask layer 46, and the first photoresist layer 48 is patterned. Using the patterned first photoresist layer 48 as a mask, the fourth mask layer 46 is patterned. That is, the patterned first photoresist layer 48 forms a first photoresist pattern, and this first photoresist pattern is used to pattern the fourth mask layer 46, such as... Figure 4 As shown, the portion of the fourth mask layer 46 that is not covered by the first photoresist pattern is removed.

[0078] like Figure 5 As shown, a patterned fourth mask layer 46 is used as a mask, and a second etch stop layer 45 and a third mask layer 44 are patterned sequentially. The fourth mask layer 46 is then removed to form a first mask opening O1.

[0079] Step S502: Form a fifth mask layer 47 in the first mask opening O1.

[0080] A fifth mask layer 47 is filled into the first mask opening O1, and the fifth mask layer 47 covers the upper surface of the second etch stop layer 45. That is, the fifth mask layer 47 fills the first mask opening O1 and extends above the upper surface of the second etch stop layer 45.

[0081] The material of the fifth mask layer 47 can be the same as that of the first mask layer 41 and the fourth mask layer 46, including silicon oxide or silicon nitride, and the fifth mask layer 47 can be filled into the first mask opening O1 by atomic layer deposition, chemical vapor deposition or physical vapor deposition process.

[0082] like Figure 6 The fifth mask layer 47 covering the upper surface of the second etch stop layer 45 is removed, so that the upper surface of the fifth mask layer 47 filling the first mask opening O1 is flush with the upper surface of the second etch stop layer 45.

[0083] The above process is to make the upper surface of the mask structure layer 4 planar. The process of removing the fifth mask layer 47 can be a wet etching process or a dry etching process.

[0084] Step S503: Using the fifth mask layer 47 as a mask, pattern the first etch stop layer 43, the second mask layer 42 and the first mask layer 41 to form the positioning hole H1.

[0085] like Figure 7 and Figure 8 As shown, before patterning the first etch stop layer 43, the second etch stop layer 42, and the first etch stop layer 41 using the fifth etch stop layer 47 as a mask, the second etch stop layer 45 and the third etch stop layer 44 can be removed sequentially using a wet etching process or a dry etching process.

[0086] First, the second etch stop layer 45 is removed to form a blind hole. Then, the third mask layer 44 is removed by etching along the blind hole to increase the depth of the blind hole and make the outline of the fifth mask layer 47 clearer.

[0087] like Figure 9 As shown, the portions of the first etch stop layer 43, the second mask layer 42, and the first mask layer 41 that are not covered by the fifth mask layer 47 are removed using the fifth mask layer 47 as a mask, while the portions covered by the fifth mask layer 47 are retained, forming the second mask opening O2.

[0088] The second mask opening O2 is actually an opening formed by the aforementioned blind hole extending downwards to the upper surface of the conductive layer 3. Therefore, as Figure 9 As shown, the second mask opening O2 penetrates the fifth mask layer 47, the first etch stop layer 43, the second mask layer 42, and the first mask layer 41.

[0089] The process used to remove the first etch stop layer 43, the second mask layer 42 and the first mask layer 41 can be a wet etching process or a dry etching process.

[0090] like Figure 10 and Figure 11 As shown, after removing the fifth mask layer 47 and the first etch stop layer 43, the second mask layer 42 is then removed to form the positioning hole H1.

[0091] The removal of the fifth mask layer 47, the first etch stop layer 43, and the second mask layer 42 can be performed using either a wet etching process or a dry etching process.

[0092] like Figure 11 As shown, the final positioning hole H1 is formed in the first mask layer 41. Therefore, the mask structure layer 4 in step S50 is the first mask layer 41.

[0093] Step S70: Deposit photoresist layer 5.

[0094] like Figure 12 As shown, after forming the positioning hole H1, a photoresist layer 5 is deposited in the positioning hole H1 and on the first mask layer 41, so that the photoresist layer 5 fills the positioning hole H1 and is higher than the upper surface of the first mask layer 41. The photoresist layer 5 and the first photoresist layer 48 can be made of the same material.

[0095] Step S90: Remove the photoresist layer 5 in the array region S2.

[0096] like Figure 13 As shown, in this step, the photoresist layer 5 in the array region S2 is removed using a mask and photolithography process, exposing the positioning hole H1 and the first mask layer 41 in the array region S2, while the positioning hole H1 and the first mask layer 41 in the redundant region S1 are still covered by the photoresist layer 5.

[0097] Step S110: In the array region S2, the conductive layer 3, dielectric layer 2 and part of the semiconductor substrate 1 are patterned along the positioning hole H1, and then the mask structure layer 4 with the positioning hole H1 is removed.

[0098] like Figure 14As shown, in the array region S2, a dry etching or wet etching process is used to sequentially etch away the conductive layer 3, the dielectric layer 2, and a portion of the semiconductor substrate 1 along the positioning hole H1, extending the positioning hole H1 into the semiconductor substrate 1. By adjusting the etching process parameters, the first mask layer 41 can be removed during the etching of the conductive layer 3, the dielectric layer 2, and a portion of the semiconductor substrate 1, or it can be removed after etching the conductive layer 3, the dielectric layer 2, and a portion of the semiconductor substrate 1. At this point, the exposed conductive layer 3 exists in the array region S2; this conductive layer 3 is the same conductive layer 3 formed during the formation of the peripheral gate.

[0099] Step S130: In array region S2, remove the conductive layer 3 on dielectric layer 2 to form bit line contact hole H2.

[0100] like Figure 14 and Figure 15 As shown, since the conductive layer 3 in the array region S2 is exposed, it can be directly removed using an etching process. However, in the redundant region S1, because the conductive layer 3 is covered by the photoresist layer 5 and the first mask layer 41, the conductive layer 3 in the redundant region S1 will not be removed simultaneously with the conductive layer 3 in the array region S2. After removing the conductive layer 3 in the array region S2, the positioning hole H1 extending from the dielectric layer 2 to the semiconductor substrate 1 forms the final bit line contact hole H2.

[0101] After that, as Figure 16 As shown, dry etching or wet etching processes can be used to remove the photoresist layer 5 and the first mask layer 41 in the redundant area S1, respectively, to expose the conductive layer 3.

[0102] In this embodiment of the invention, by designing a new semiconductor device manufacturing method, only one mask and photolithography process is required. In the subsequent etching process, only the conductive layer 3 in the array region S2 is removed, while the conductive layer 3 in the redundant region S1 is retained. Therefore, the manufacturing method of the present invention removes the conductive layer 3 located in the array region S2 when forming the peripheral gate, reducing the generation of parasitic capacitance, and at the same time does not damage the structure of the conductive layer 3 in the redundant region S1. That is, it minimizes the impact on the peripheral gate to the greatest extent, ensuring the stability and yield of the semiconductor device. At the same time, the manufacturing method of the present invention can reduce the size of the bit line structure, which is beneficial to improving the semiconductor integration.

[0103] It should be noted that the dry etching or wet etching process used in the embodiments of the present invention can be adjusted by adjusting the process parameters. For example, dry etching can be plasma etching, and the etching gas used in plasma process can be chlorine. By controlling the amount of etching gas, the degree of etching can be controlled. Wet etching can use concentrated sulfuric acid and hydrogen peroxide as etchants. By adjusting the concentration of the etchant, the degree of etching can also be controlled to etch different layers in the mask structure layer 4. Those skilled in the art can continue to adjust according to actual needs, and no special limitation is made here.

[0104] like Figure 17 and Figure 18 As shown, where Figure 18 for Figure 17 The schematic cross-sectional view along AA shows that after forming the bit line contact hole H2, the manufacturing method of the semiconductor device of the present invention may further include: forming a bit line contact plug 6 in the bit line contact hole H2, wherein the bit line contact plug 6 is flush with the top surface of the dielectric layer 2.

[0105] The bit line contact plug 6 can be deposited using atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The bit line contact plug 6 can be a metal silicide, polysilicon, metal nitride, or metal, without any special limitation.

[0106] In this step, it is necessary to ensure that the bit line contact plug 6 is flush with or slightly lower than the top surface of the dielectric layer 2, so as to reduce the generation of parasitic capacitance.

[0107] Continue to refer to Figure 18 A conductive structure layer 7, a protective layer 8, and an isolation structure 9 are sequentially formed on the bit line contact plug 6 to form the bit line structure BL. The conductive structure layer 7 may include two layers, one of which is TiN and the other can be W, or it may be a single layer, which is not specifically limited here.

[0108] A protective layer 8 is formed on the conductive structure layer 7. This protective layer 8 is made of an insulating material, such as silicon nitride or silicon oxynitride, without special limitation. The protective layer 8 insulates the top of the conductive structure, preventing it from being affected by other components.

[0109] An isolation structure 9 is formed on the sidewalls of the bit line contact plug 6, the conductive structure layer 7, and the protective layer 8, as well as on the top of the protective layer 8. The isolation structure 9 is made of an insulating material, such as silicon oxide or silicon nitride. By setting the isolation structure 9, the bit line contact plug 6 and the conductive structure layer 7 of the bit line structure BL can be protected, parasitic capacitance can be reduced, and leakage can be prevented.

[0110] Continue to refer to Figure 18After forming the bit line structure BL, memory node contact holes are formed between the bit line structures BL, and memory node contact plugs 10 are formed in the memory node contact holes. The memory node contact plugs 10 can be metal silicides, polysilicon, metal nitrides, or metals, and no special limitation is made here.

[0111] In summary, the semiconductor device manufacturing method of the present invention can effectively remove the conductive layer portion in the bit line structure BL in the array region S2 corresponding to the formation of the peripheral gate, reduce parasitic capacitance, simplify the process, and does not affect the peripheral gate, thereby improving the stability and yield of the semiconductor device. At the same time, the manufacturing method of the present invention can reduce the size of the bit line structure, which is beneficial to improving the semiconductor integration density.

[0112] According to another aspect of the invention, such as Figures 3 to 18 As shown, this embodiment of the invention provides a semiconductor device, which is prepared by the manufacturing method described in any of the above embodiments. The structure of this semiconductor device has been specifically described in the manufacturing methods of the above embodiments and will not be repeated here.

[0113] It should be understood that the application of this invention is not limited to the detailed structure and arrangement of the components presented in this specification. The invention can have other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this invention. It should be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of the invention. The embodiments described in this specification illustrate the best known mode for carrying out the invention and will enable those skilled in the art to utilize the invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a redundant region and an array region; A dielectric layer, a conductive layer, and a mask structure layer are sequentially formed in the redundant region and the array region, respectively. The mask structure layer is graphically represented to form positioning holes; Deposit photoresist layer; Remove the photoresist layer from the array region; In the array region, the conductive layer, the dielectric layer, and a portion of the semiconductor substrate are patterned along the positioning holes, and the mask structure layer having the positioning holes is removed; In the array region, the conductive layer on the dielectric layer is removed to form bit line contact holes.

2. The method according to claim 1, characterized in that, The mask structure layer includes a first mask layer, a second mask layer, a first etch stop layer, a third mask layer, a second etch stop layer, and a fourth mask layer formed sequentially on the conductive layer.

3. The method according to claim 2, characterized in that, The patterning of the mask structure layer to form positioning holes includes: The second etch stop layer and the third mask layer are patterned to form a first mask opening; A fifth mask layer is formed in the first mask opening; Using the fifth mask layer as a mask, the first etch stop layer, the second mask layer, and the first mask layer are patterned to form the positioning hole.

4. The method according to claim 3, characterized in that, The patterning of the second etch stop layer and the third mask layer to form a first mask opening includes: Graphicalize the fourth mask layer; Using the patterned fourth mask layer as a mask, the second etch stop layer and the third mask layer are patterned, and the fourth mask layer is removed to form the first mask opening.

5. The method according to claim 4, characterized in that, The graphical representation of the fourth mask layer includes: A first photoresist layer is formed on the fourth mask layer, the first photoresist layer is patterned, and the patterned first photoresist layer is used as a mask to pattern the fourth mask layer.

6. The method according to claim 3, characterized in that, The formation of a fifth mask layer in the first mask opening includes: The fifth mask layer is filled into the first mask opening, and the fifth mask layer covers the upper surface of the second etch stop layer; Remove the fifth mask layer covering the upper surface of the second etch stop layer, so that the upper surface of the fifth mask layer filling the opening of the first mask is flush with the upper surface of the second etch stop layer.

7. The method according to claim 3, characterized in that, Before patterning the first etch stop layer, the second mask layer, and the first mask layer using the fifth mask layer as a mask to form the positioning hole, the method further includes: Remove the second etch stop layer; Remove the third mask layer.

8. The method according to claim 7, characterized in that, Using the fifth mask layer as a mask, the first etch stop layer, the second mask layer, and the first mask layer are patterned to form the positioning hole, including: Using the fifth mask layer as a mask, the first etch stop layer, the second mask layer, and the portion of the first mask layer not covered by the fifth mask layer are removed, while the portion covered by the fifth mask layer is retained, forming a second mask opening; Remove the fifth mask layer and the first etch stop layer; Remove the second mask layer to form the positioning hole.

9. The method according to claim 8, characterized in that, The mask structure layer having the positioning hole is the first mask layer having the positioning hole.

10. The method according to claim 8, characterized in that, After removing the conductive layer on the dielectric layer in the array region to form bit line contact holes, the method further includes: Remove the photoresist layer from the redundant region; Remove the first mask layer from the redundant region.

11. The method according to claim 1, characterized in that, The dielectric layer is made of silicon nitride, silicon oxide, silicon carbonitride, or silicon oxynitride, and the conductive layer is made of polycrystalline silicon, doped polycrystalline silicon, titanium nitride, tungsten nitride, or tungsten.

12. The method according to claim 3, characterized in that, The first mask layer, the fourth mask layer, and the fifth mask layer are made of the same material, including silicon oxide or silicon nitride; The second and third mask layers are made of the same material, including spin-coated hard masks; The first etch stop layer and the second etch stop layer are made of the same material, including silicon oxynitride, silicon nitride, or silicon carbonitride.

13. The method according to claim 1, characterized in that, The process for forming the dielectric layer, the conductive layer, and the mask structure layer includes atomic layer deposition, chemical vapor deposition, physical vapor deposition, or spin coating.

14. The method according to any one of claims 1 to 10, characterized in that, The removal process includes dry etching or wet etching.

15. The method according to claim 14, characterized in that, A bit line contact plug is formed in the bit line contact hole, and the bit line contact plug is flush with the top surface of the dielectric layer.

16. The method according to claim 15, characterized in that, A conductive structure layer, a protective layer, and an isolation structure are sequentially formed on the bit line contact plug to form a bit line structure.

17. The method according to claim 16, characterized in that, Storage node contact holes are formed between the bit line structures, and storage node contact plugs are formed in the storage node contact holes.

18. A semiconductor device, characterized in that, The semiconductor device is prepared by the manufacturing method according to any one of claims 1-17.

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