Semiconductor structure, method of fabricating the same, and memory system
By first forming material pillars with a small aspect ratio in the dynamic random access memory, and then performing etching and electrode formation, the problem of high aspect ratio capacitor etching difficulty is solved, and the stability and area utilization of the capacitor are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2022-07-22
- Publication Date
- 2026-05-22
AI Technical Summary
As the size of dynamic random access memory shrinks, the size of capacitors also shrinks. How to ensure the performance of capacitors has become an urgent problem to be solved, especially since erosion is difficult and collapse is easy when forming capacitors with high aspect ratios.
By first forming a first material pillar with a small depth-to-width ratio in the first insulating layer, and then etching its sidewalls to form a second material pillar with a large depth-to-width ratio, and using atomic layer etching to reduce the etching difficulty, the dielectric layer and electrodes are then formed to ensure the stability of the capacitor.
It improves the etching difficulty of high aspect ratio capacitors, increases area utilization, avoids capacitor collapse, and ensures capacitor performance and stability.
Smart Images
Figure CN115223952B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory system. Background Technology
[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the size of capacitors also shrinks. Ensuring the performance of capacitors in DRAM has become a pressing issue.
[0004] Public content
[0005] In view of this, the present disclosure provides a semiconductor structure and a method for fabricating the same.
[0006] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:
[0007] A first insulating layer is provided, wherein at least one first material pillar is formed in the first insulating layer;
[0008] Remove the first insulating layer to expose the sidewalls of the first material column;
[0009] The sidewall of the first material column is etched to form a second material column; the width of the second material column in the first direction is smaller than the width of the first material column in the first direction; the first direction is perpendicular to the extension direction of the first material column;
[0010] A dielectric layer and a first electrode are formed; the dielectric layer covers the sidewall of the second material pillar, and the first electrode covers the sidewall of the dielectric layer;
[0011] The second electrode is formed using the second material column.
[0012] In the above scheme, the material of the first material column includes a conductive material;
[0013] The method of forming the second electrode using the second material pillar includes:
[0014] The second material column directly constitutes the second electrode.
[0015] In the above scheme, the material of the first material column includes sacrificial material;
[0016] The method of forming the second electrode using the second material pillar includes:
[0017] After forming the dielectric layer and the first electrode, the second material pillar is removed to form the first groove;
[0018] The first groove is filled with conductive material to form a second electrode.
[0019] In the above scheme, the aspect ratio of the second material column is greater than the first preset value, and the aspect ratio of the first material column is less than the second preset value.
[0020] In the above scheme, both the first preset value and the second preset value are 50:1.
[0021] In the above scheme, the first preset value is 50:1, and the second preset value is 40:1.
[0022] In the above scheme, the etching process on the sidewall of the first material column includes:
[0023] The sidewalls of the first material pillar are etched using atomic layer etching (ALE).
[0024] The method in the above scheme further includes:
[0025] After the first electrode is formed, a second insulating layer is formed to cover the first electrode.
[0026] In the above scheme, the number of the first material pillars includes multiple components, and the number of the formed second electrodes includes multiple components; the method further includes:
[0027] Multiple transistor units are formed; the transistor units are coupled to the second electrode.
[0028] In the above scheme, the transistor forming unit includes:
[0029] A semiconductor layer is provided, wherein the semiconductor layer is stacked with the first insulating layer;
[0030] A first transistor and a second transistor are formed in the semiconductor layer in a symmetrical arrangement along a second direction; each of the first transistor and the second transistor includes a source, a drain, a channel region, a gate, and a gate oxide layer; the extension direction of the channel region of the first transistor and the second transistor is perpendicular to the second direction, and the first transistor and the second transistor share a source or a drain; the second direction is parallel to the extension direction of the first material pillar; the second electrode is coupled to one of the source and drain of the transistor unit.
[0031] The method in the above scheme further includes:
[0032] Multiple bit lines are formed; each bit line is coupled to another of the source and drain of the transistor cell.
[0033] In the above scheme, the semiconductor structure includes a dynamic random access memory.
[0034] According to another aspect of this disclosure, a semiconductor structure is provided, formed using the method described in any of the above embodiments.
[0035] According to another aspect of this disclosure, a memory system is provided, comprising:
[0036] One or more semiconductor structures as described in the above scheme; and
[0037] A memory controller that is coupled to and controls the semiconductor structure.
[0038] This disclosure provides a semiconductor structure and a method for fabricating the same. The method includes: providing a first insulating layer in which at least one first material pillar is formed; removing the first insulating layer to expose the sidewalls of the first material pillar; etching the sidewalls of the first material pillar to form a second material pillar; the width of the second material pillar in a first direction is smaller than the width of the first material pillar in the first direction; the first direction is perpendicular to the extension direction of the first material pillar; forming a dielectric layer and a first electrode; the dielectric layer covering the sidewalls of the second material pillar, and the first electrode covering the sidewalls of the dielectric layer; and forming a second electrode using the second material pillar. In this disclosure, a first material pillar with a wider width in the first direction is first formed in the first insulating layer. After removing the first insulating layer, the sidewalls of the first material pillar are etched to form a second material pillar with a narrower width in the first direction. The second electrode is then formed using the second material pillar. This improves the difficulty of etching when directly forming a second material pillar with a narrower width in the first direction in the first insulating layer. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;
[0040] Figures 2-5 A cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this disclosure;
[0041] Figures 6-7 A cross-sectional schematic diagram of the manufacturing process of another semiconductor structure provided in this disclosure embodiment;
[0042] Figure 8A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;
[0043] Figures 9-16 This is a cross-sectional schematic diagram of the manufacturing process of another semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation
[0044] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.
[0045] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0046] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0047] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.
[0048] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0049] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.
[0050] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0051] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.
[0052] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.
[0053] In some embodiments of this disclosure, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.
[0054] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.
[0055] As memory technology advances, the size of dynamic random access memory (DRAM) continues to shrink, while the storage capacity of memory continues to increase, making the process of forming capacitors increasingly difficult.
[0056] This disclosure provides a method for fabricating a semiconductor structure, the method comprising: firstly, as... Figure 2 As shown, a third groove 101 is formed in the first insulating layer 102, wherein the aspect ratio of the third groove 101 is approximately 50:1; as Figure 3 As shown, conductive material is filled into the third groove 101 to form a second electrode 103, which is the lower electrode of the capacitor; as Figure 4 As shown, the first insulating layer 102 surrounding the second electrode 103 is removed using a wet etching process; next, as... Figure 5 As shown, a dielectric layer 104 is formed around the second electrode 103, and a first electrode 105 is formed around the dielectric layer 104. The dielectric layer 104 serves as the dielectric of the capacitor, and the first electrode 105 serves as the upper electrode of the capacitor. The dielectric layer 104, the first electrode 105, and the second electrode 103 together constitute the capacitor.
[0057] Research has found that in the semiconductor structure fabrication method provided in the above embodiments, it is difficult to directly form a third groove 101 with a large depth-to-width ratio in the first insulating layer 102 through etching. Furthermore, during the process of removing the first insulating layer 102 surrounding the second electrode 103 to form the second electrode 103 using a wet etching process, the wet etching solution is adsorbed on the surface of the second electrode 103. Due to the surface tension of the wet etching solution, adjacent second electrodes 103 tend to tilt towards each other or even connect together. In addition, due to the large depth-to-width ratio of the second electrode 103, there is a risk that the second electrode 103 may collapse.
[0058] Based on this, the present disclosure provides another method for fabricating a semiconductor structure, the method comprising: firstly as follows Figure 6 As shown, a fourth groove 106 is formed in the first insulating layer 102, wherein the aspect ratio of the fourth groove is approximately 40:1; next, as Figure 7 As shown, a first electrode 105, a dielectric layer 104, and a second electrode 103 are sequentially formed in the fourth groove 106.
[0059] It is understood that the above embodiments form a capacitor by first forming a fourth groove 106 with a small aspect ratio in the first insulating layer 102, and then forming a first electrode 105, a dielectric layer 104, and a second electrode 103 in the fourth groove 106. The method provided by the above embodiments can improve the problem of high etching difficulty in forming a second electrode with a high aspect ratio, but the area utilization rate is not high.
[0060] Based on this, in order to solve one or more of the above problems, this disclosure provides another method for fabricating a semiconductor structure, which can improve the problem of high etching difficulty in forming a second electrode with a high aspect ratio, while ensuring a high area utilization rate. Figure 8 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 8 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:
[0061] S100: Provide a first insulating layer, wherein at least one first material pillar is formed in the first insulating layer;
[0062] S200: Remove the first insulating layer to expose the sidewall of the first material column;
[0063] S300: The sidewall of the first material pillar is etched to form a second material pillar; the width of the second material pillar in the first direction is smaller than the width of the first material pillar in the first direction; the first direction is perpendicular to the extension direction of the first material pillar;
[0064] S400: Forming a dielectric layer and a first electrode; the dielectric layer covers the sidewall of the second material pillar, and the first electrode covers the sidewall of the dielectric layer;
[0065] S500: The second electrode is formed using the second material column.
[0066] It should be understood that Figure 8 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 8 The steps shown can be adjusted in order according to actual needs. Figures 9 to 16 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 9 to 16 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 8 , Figures 9 to 16 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.
[0067] In step S100, as Figures 9 to 10 As shown, the main feature is to provide a first insulating layer 102 and form at least one first material pillar 114 in the first insulating layer 102.
[0068] In some specific examples, the material of the first insulating layer 102 includes, but is not limited to, silicon nitride and silicon oxide.
[0069] In some specific examples, the methods for forming the first insulating layer 102 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.
[0070] In some specific examples, such as Figures 9 to 10 As shown, the process of forming the first material pillar 114 includes: forming a second groove 107 in the first insulating layer 102; filling the second groove 107 with the first material to form the first material pillar 114.
[0071] In some specific examples, when the first material is filled in the second groove 107, the top surface of the first insulating layer 102 is also filled with the first material. After the first material is filled, the first material is also planarized to expose the top surface of the first insulating layer 102.
[0072] In some specific examples, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP) processes.
[0073] In some specific examples, the method for forming the second groove 107 includes, but is not limited to, dry etching process, specifically dry plasma etching process.
[0074] In some specific examples, the methods for filling the first material include, but are not limited to, PVD, CVD, and ALD.
[0075] In some embodiments, the number of the first material pillars 114 includes a plurality of the first material pillars 114 arranged in an array along a first direction and a third direction, wherein the first direction and the third direction are both perpendicular to the extension direction of the first material pillars, and the first direction and the third direction intersect each other.
[0076] The first direction here is Figure 9 The Y-axis direction is shown in the figure, and the second direction is... Figure 9 The Z-axis direction shown in the figure, the third direction is Figure 9 The X-axis direction is shown in the figure.
[0077] Here, the intersection of the first direction and the third direction can be understood as the angle between the first direction and the third direction being 0-90 degrees.
[0078] In some embodiments, the number of the first material pillars 114 may be multiple, and the number of the second electrodes formed may be multiple;
[0079] The method further includes:
[0080] like Figure 9 As shown, a plurality of transistor units 10 are formed; the transistor units 10 are coupled to the second electrode (in Figure 9 The second electrode 103 has not yet been formed, and the transistor unit 10 is coupled to the second electrode 103. Figure 16 (as shown in the image).
[0081] The second electrode 103 here is the lower electrode of a storage structure such as a capacitor.
[0082] It should be noted that the order in which the transistor unit 10 and the memory structure are formed is not limited. The transistor unit 10 can be formed after the memory structure is formed or before the memory structure is formed. In this embodiment, the transistor unit 10 is formed first and then the memory structure is formed as an example for illustrative explanation.
[0083] In some embodiments, the transistor forming unit 10 includes:
[0084] A semiconductor layer 112 is provided, which is stacked with the first insulating layer 102;
[0085] A first transistor 1001 and a second transistor 1002 are formed in the semiconductor layer 112 in a symmetrical arrangement along a second direction. Each of the first transistor 1001 and the second transistor 1002 includes a source 108, a drain 109, a channel region, a gate 110, and a gate oxide layer 111. The extension direction of the channel region of the first transistor 1001 and the second transistor 1002 is perpendicular to the second direction, and the first transistor 1001 and the second transistor 1002 share a source 108 or a drain 109. The second direction is parallel to the extension direction of the first material pillar 114. The second electrode 103 is coupled to one of the source 108 and the drain 109 of the transistor unit 10.
[0086] It should be noted that, Figure 9 The diagram only shows the case where the first transistor 1001 and the second transistor 1002 share the drain 109. Figure 9 The above is merely an exemplary demonstration and is not intended to limit the embodiments disclosed herein. The first transistor 1001 and the second transistor 1002 may also share the source 108.
[0087] It should be noted that the structural limitations of the transistors in the above embodiments are merely illustrative examples and are not intended to limit the structure of the transistors in this disclosure. In practical applications, the structure of the transistors coupled to the storage structure is not limited to these.
[0088] In some specific examples, the semiconductor layer 112 may include a substrate, which may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.
[0089] Here, the gate oxide layer 111 is located between the gate 110 and the channel region, and is used to electrically isolate the channel region and the gate 110 to reduce the hot carrier effect of the transistor.
[0090] In some specific examples, the material of gate 110 includes, but is not limited to, polysilicon, conductive metal, or conductive alloy. Conductive metal may include tungsten or copper, etc.
[0091] In some specific examples, the methods for forming the gate oxide layer 111 include, but are not limited to, PCD, CVD, and ALD.
[0092] In some specific examples, the gate oxide layer 111 includes, but is not limited to, silicon oxide.
[0093] In some specific examples, the methods for forming the source 108 and drain 109 include, but are not limited to, doping and diffusion processes. In some specific examples, the first transistor 1001 and the second transistor 1002 can be N-type transistors or P-type transistors.
[0094] In an N-type transistor, both the source 108 and the drain 109 are N-type doped; in a P-type transistor, both the source 108 and the drain 109 are P-type doped. For example, when the doping type is P-type, the P-type impurity source can be boron (B), aluminum (Al), etc., and is not limited to these; when the doping type is N-type, the N-type impurity source can be phosphorus (P), arsenic (As), etc., and is not limited to these.
[0095] Here, the first transistor 1001 and the second transistor 1002 are symmetrically distributed along the second direction, which can be referred to as... Figure 9 To understand: Both the first transistor 1001 and the second transistor 1002 include a source 108, a drain 109, a channel region, a gate 110, and a gate oxide layer 111. The gate 110 of both transistors 1001 and 1002 is located on the gate oxide layer 111. The source 108 and drain 109 of the transistors are formed in the semiconductor layer 112. In a transistor unit 10, the first transistor 1001 and the second transistor 1002 can share either the source 108 or the drain 109. The choice can be made based on actual needs.
[0096] In some specific examples, such as Figure 9 As shown, a third insulating layer 113 is also formed on the semiconductor layer 112, and the gate oxide layer 111, the gate 110, the lead of the source 108, and the lead of the drain 109 of the transistor unit 10 are formed in the third insulating layer 113.
[0097] In some specific examples, the material of the third insulating layer 113 includes, but is not limited to, silicon oxide and silicon nitride.
[0098] In some specific examples, the methods for forming the third insulating layer 113 include, but are not limited to, PVD, CVD, and ALD.
[0099] In step S200, as Figure 11 As shown, the main process involves removing the first insulating layer 102 to expose the sidewalls of the first material pillar 114.
[0100] In some specific examples, the methods for removing the first insulating layer 102 include, but are not limited to, wet etching.
[0101] In some embodiments, the aspect ratio of the first material column 114 is less than a second preset value.
[0102] It is understood that in the embodiments of this disclosure, a first material pillar 114 with a small depth-to-width ratio is formed first, and then the first insulating layer 102 surrounding the first material pillar 114 is removed. This makes it possible that during the removal of the first insulating layer 102, since the first material pillar 114 has a small depth-to-width ratio, the force required to make the first material pillar 114 with a small depth-to-width ratio collapse is greater than that required for a columnar material with a large depth-to-width ratio. Therefore, even if the etching solution of wet etching is applied to the surface of the first material pillar 114, the first material pillar 114 is not easy to collapse under the action of the surface tension of the wet etching solution.
[0103] In step S300, as Figure 12 As shown, the main process involves etching the sidewall of the first material pillar 114 to form a second material pillar 115; the width of the second material pillar 115 in the first direction is smaller than the width of the first material pillar 114 in the first direction.
[0104] Here, the first direction is perpendicular to the extension direction of the first material column, and the extension direction of the first material column can be understood as follows: Figure 12 The Z-axis direction is shown in the figure.
[0105] It is understood that in this embodiment of the present disclosure, a first material pillar 114 with a relatively large width in the first direction is first formed, and then the sidewall of the first material pillar 114 is etched to form a second material pillar 115 with a smaller width in the first direction. This eliminates the need to first form a groove with a smaller width, thereby reducing the difficulty of etching.
[0106] In some embodiments, the aspect ratio of the second material column 115 is greater than a first preset value.
[0107] Understandably, if a first material pillar 114 with a smaller depth-to-width ratio is not formed first, and a second material pillar 115 with a larger depth-to-width ratio is formed directly, the larger depth-to-width ratio of the second material pillar 115 would require etching a groove with a larger depth-to-width ratio in the first insulating layer 102, which would be more difficult. Furthermore, during the direct formation of the second material pillar 115, due to its larger depth-to-width ratio, the second material pillar 115 would lose its support and be prone to collapse after the first insulating layer 102 is removed.
[0108] In this embodiment, a first material pillar 114 with a small depth-to-width ratio is first formed, and the sidewalls of the first material pillar 114 are etched to form a second material pillar 115 with a large depth-to-width ratio, thus reducing the difficulty of etching. Furthermore, when removing the first insulating layer 102, the small depth-to-width ratio of the first material pillar 114 makes it less prone to collapse. Then, the sidewalls of the first material pillar 114 are etched. Since atomic layer etching is used in subsequent processes, the formed second material pillar 115 will not collapse due to the surface tension of the wet etching solution, thus ensuring that a second material pillar 115 with a large depth-to-width ratio is formed and that it is not prone to collapse.
[0109] It is understandable that the depth-to-width ratio of the first material column 114 is small, and the depth-to-width ratio of the first material column 114 is less than the second preset value; the depth-to-width ratio of the second material column 115 is large, and the depth-to-width ratio of the second material column 115 is greater than the first preset value; the depth-to-width ratio of the first material column 114 is less than the depth-to-width ratio of the second material column 115, therefore the first preset value can be greater than or equal to the second preset value.
[0110] In some specific embodiments, both the first preset value and the second preset value are 50:1. It can be understood that when the aspect ratio of the first material pillar 114 is less than that of the second material pillar 115, it indicates that the aspect ratio has been reduced, and the problem of high etching difficulty has been alleviated to some extent.
[0111] In some other specific embodiments, the first preset value is 50:1, and the second preset value is 40:1. It is understood that when the aspect ratio of the first material pillar 114 is smaller, the etching difficulty in forming the first material pillar 114 is lower.
[0112] In some other specific embodiments, the first preset value and the second preset value are both 45:1, or the first preset value and the second preset value are both 47:1, or the first preset value and the second preset value are both 43:1.
[0113] It should be noted that the first and second preset values given in the above embodiments are merely exemplary demonstrations and are not intended to limit the first and second preset values in this disclosure. In practical applications, the first and second preset values can be easily set according to the specific actual process conditions.
[0114] In some embodiments, the etching process on the sidewall of the first material pillar 114 includes:
[0115] The sidewalls of the first material pillar 114 are etched using atomic layer etching (ALT) technology.
[0116] It is understood that in this embodiment of the present disclosure, the first material pillar 114 is etched using an atomic layer etching process, which reduces the width of the first material pillar 114 in the first direction to form a second material pillar 115. Since the first material pillar 114 and the formed second material pillar 115 are in a gas atmosphere when the sidewall of the first material pillar 114 is etched using an atomic layer etching process, the surface of the first material pillar 114 will not generate a large surface tension, thereby making the formed second material pillar 115 with a large depth-to-width ratio less prone to collapse.
[0117] In step S400, as Figure 13 As shown, the main components are a dielectric layer 104 and a first electrode 105; the dielectric layer 104 covers the sidewall of the second material pillar 115, and the first electrode 105 covers the sidewall of the dielectric layer 104.
[0118] In some specific examples, the dielectric layer 104 is composed of a high-dielectric-constant (High-K) material, which generally refers to a material with a dielectric constant higher than 3.9, and is usually significantly higher than that value. In some specific examples, the material of the dielectric layer 104 may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc.
[0119] In some specific examples, the material of the first electrode 105 may include, but is not limited to, conductive materials, specifically including titanium nitride (TiN).
[0120] Here, the methods for forming the dielectric layer 104 and the first electrode 105 include, but are not limited to, PVD, CVD, ALD, and other processes. In some specific examples, the methods for forming the dielectric layer 104 and the first electrode 105 include, but are not limited to, PVD, CVD, and ALD.
[0121] In some embodiments, such as Figure 14 As shown, the method further includes:
[0122] After the first electrode 105 is formed, a second insulating layer 116 is formed to cover the first electrode 105.
[0123] In some specific examples, the material of the second insulating layer 116 includes, but is not limited to, silicon nitride and silicon oxide.
[0124] In some specific examples, the methods for forming the second insulating layer 116 include, but are not limited to, PVD, CVD, and ALD.
[0125] Here, the second insulating layer 116 can be used to isolate multiple capacitors and improve mutual interference between them.
[0126] In step S500, the second electrode 103 is mainly formed using the second material pillar 115.
[0127] Here, the first electrode 105, the dielectric layer 104, and the second electrode 103 together constitute a storage structure. The second electrode 103 is used as the lower electrode of the capacitor; the dielectric layer 104 is used as the dielectric of the capacitor; and the first electrode 105 is used as the upper electrode of the capacitor.
[0128] In some specific examples, the material of the second electrode 103 may include, but is not limited to, conductive materials, specifically including titanium nitride.
[0129] In some specific examples, the methods for forming the second electrode 103 include, but are not limited to, PVD, CVD, and ALD.
[0130] The specific method of using the second material column 115 to form the second electrode 103 is related to the material of the first material column 114. The following is a detailed explanation of how to use the second material column 115 to form the second electrode 103.
[0131] In some embodiments, the material of the first material column 114 includes a conductive material;
[0132] The process of forming the second electrode 103 using the second material pillar 115 includes:
[0133] The second material column 115 directly constitutes the second electrode 103.
[0134] It is understood that in the above embodiments, conductive material is directly used as the first material pillar 114. After etching the sidewall of the first material pillar 114 with a small depth-to-width ratio, the second material pillar 115 with a large depth-to-width ratio formed directly constitutes the second electrode 103. This can save process steps and process time.
[0135] In some embodiments, the material of the first material column 114 includes a sacrificial material;
[0136] The process of forming the second electrode 103 using the second material pillar 115 includes:
[0137] After forming the dielectric layer 104 and the first electrode 105, the second material pillar 115 is removed to form the first groove;
[0138] The first groove is filled with conductive material to form the second electrode 103.
[0139] like Figure 15 As shown, the second material column 115 is removed to form the first groove 117.
[0140] In some specific examples, the methods for removing the second material pillar 115 include, but are not limited to, dry etching processes and wet etching processes.
[0141] Next, as Figure 16 As shown, conductive material is filled in the first groove 117 to form the second electrode 103.
[0142] In some specific examples, the methods for filling conductive materials include, but are not limited to, PVD, CVD, and ALD.
[0143] Regarding the selection of the sacrificial material, firstly, it is necessary to consider that the sacrificial material has a certain etching selectivity relative to the first insulating layer 102, so as to reduce the impact on the sacrificial material when removing the first insulating layer 102; secondly, the sacrificial material needs to be easy to remove in subsequent processes; thirdly, it is necessary to consider that the sacrificial material pillar has a certain etching selectivity relative to the material of the dielectric layer 104, so as to reduce the impact on the dielectric layer 104 when removing the sacrificial material to form the first groove 117; fourthly, a material with low surface tension can be selected as the sacrificial material, so that the first material pillar 114 is not easy to collapse when removing the first insulating layer 102.
[0144] In some specific examples, the material of the sacrificial material includes, but is not limited to, carbon.
[0145] It is understood that in the above embodiments, when the material of the first material pillar 114 is a sacrificial material, after the second material pillar 115 with a large depth-to-width ratio is formed, and the first electrode 105 and the dielectric layer 104 are formed, the second material pillar 115 is removed to form the first groove 117, and the first groove 117 is filled with conductive material to form the second electrode 103 with a large depth-to-width ratio. This can save the amount of material used to form the second electrode 103, thereby saving costs.
[0146] In some embodiments, the method further includes:
[0147] Multiple bit lines are formed; the bit lines are coupled to another of the source 108 and drain 109 of the transistor unit 10.
[0148] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.
[0149] In some specific examples, bit lines are formed by forming metal lines at predetermined bit line locations. These metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof.
[0150] In some embodiments, the semiconductor structure includes dynamic random access memory.
[0151] The embodiments disclosed herein merely exemplify some common memories, and the scope of protection of this disclosure is not limited thereto. Any memory containing the semiconductor structure provided in the embodiments of this disclosure falls within the scope of protection of this invention.
[0152] It is understood that the embodiments disclosed herein... Figures 6-7 The corresponding solution is to first form a fourth groove with a small depth-to-width ratio, and then directly deposit conductive material and dielectric material in the fourth groove to form the two electrodes of the capacitor and the dielectric layer. Because the fourth groove has a small depth-to-width ratio, the resulting capacitor also has a small depth-to-width ratio, meaning it is a short and thick columnar structure. However, the embodiments disclosed herein... Figures 9-16 In the corresponding scheme, because a second material column with a large depth-to-width ratio is used to form the second electrode, and a dielectric layer surrounding the second electrode and a first electrode surrounding the dielectric layer are formed on the sidewall of the second electrode, the resulting capacitor has a large depth-to-width ratio. In other words, the resulting capacitor is a tall and thin columnar structure, relative to... Figures 6-7 Regarding the proposed solution, Figures 9-16 When forming capacitors with the same storage capacity, the area occupied is smaller, thereby improving the area utilization rate.
[0153] This disclosure provides a semiconductor structure and a method for fabricating the same. The method includes: providing a first insulating layer 102, wherein at least one first material pillar 114 is formed in the first insulating layer 102; removing the first insulating layer 102 to expose the sidewalls of the first material pillar 114; etching the sidewalls of the first material pillar 114 to form a second material pillar 115; wherein the width of the second material pillar 115 in a first direction is smaller than the width of the first material pillar 114 in the first direction; the first direction is perpendicular to the extension direction of the first material pillar 114; forming a dielectric layer 104 and a first electrode 105; wherein the dielectric layer 104 covers the sidewalls of the second material pillar 115, and the first electrode 105 covers the sidewalls of the dielectric layer 104; and forming a second electrode 103 using the second material pillar 115. In this embodiment, a first material pillar 114 with a wider width in the first direction is first formed in the first insulating layer 102. After removing the first insulating layer 102, the sidewalls of the first material pillar 114 are etched to form a second material pillar 115 with a narrower width in the first direction than the first material pillar 114. The second electrode 103 is then formed using the second material pillar 115. This improves the problem of high etching difficulty when directly forming the second material pillar 115 with a narrower width in the first direction in the first insulating layer 102.
[0154] According to another aspect of this disclosure, embodiments of this disclosure also provide a semiconductor structure formed using a semiconductor structure fabrication method as described in any of the above embodiments.
[0155] The semiconductor structure provided in the above embodiments has been described in detail in the method section and will not be repeated here.
[0156] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory system, including:
[0157] One or more semiconductor structures as described in the above embodiments; and
[0158] A memory controller that is coupled to and controls the semiconductor structure.
[0159] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form a final device structure. Here, the final device may include a memory.
[0160] In some specific examples, the memory system includes a memory card or a solid-state drive.
[0161] In some specific examples, the memory controller is coupled to the memory and the host and is configured to control the memory. The memory controller can manage the data stored in the memory and communicate with the host. In some implementations, the memory controller is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some implementations, the memory controller is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which serve as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.
[0162] A memory controller and one or more memories can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system can be implemented and packaged into different types of end electronic products. For example, a memory controller and a single memory can be integrated into a memory card. Memory cards can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host. For example, a memory controller and multiple memories can be integrated into an SSD. The SSD may also include an SSD connector that couples the SSD to the host.
[0163] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.
[0164] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.
[0165] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A first insulating layer is provided, wherein at least one first material pillar is formed in the first insulating layer; Remove the first insulating layer to expose the sidewalls of the first material column; The sidewall of the first material column is etched to form a second material column; the width of the second material column in the first direction is smaller than the width of the first material column in the first direction; the first direction is perpendicular to the extension direction of the first material column; A dielectric layer and a first electrode are formed; the dielectric layer covers the sidewall of the second material pillar, and the first electrode covers the sidewall of the dielectric layer; The second electrode is formed using the second material column.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The material of the first material column includes conductive materials; The method of forming the second electrode using the second material pillar includes: The second material column directly constitutes the second electrode.
3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The material of the first material column includes sacrificial material; The method of forming the second electrode using the second material pillar includes: After forming the dielectric layer and the first electrode, the second material pillar is removed to form the first groove; The first groove is filled with conductive material to form the second electrode.
4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The aspect ratio of the second material column is greater than the first preset value, and the aspect ratio of the first material column is less than the second preset value.
5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, Both the first preset value and the second preset value are 50:
1.
6. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The first preset value is 50:1, and the second preset value is 40:
1.
7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The etching process on the sidewall of the first material column includes: The sidewalls of the first material pillar are etched using atomic layer etching (ALT) technology.
8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method further includes: After the first electrode is formed, a second insulating layer is formed to cover the first electrode.
9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The number of the first material pillars may be multiple, and the number of the second electrodes formed may be multiple; the method further includes: Multiple transistor units are formed; the transistor units are coupled to the second electrode.
10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The transistor unit includes: A semiconductor layer is provided, wherein the semiconductor layer is stacked with the first insulating layer; A first transistor and a second transistor are formed in the semiconductor layer in a symmetrical arrangement along a second direction; each of the first transistor and the second transistor includes a source, a drain, a channel region, a gate, and a gate oxide layer; the extension direction of the channel region of the first transistor and the second transistor is perpendicular to the second direction, and the first transistor and the second transistor share a source or a drain; the second direction is parallel to the extension direction of the first material pillar; the second electrode is coupled to one of the source and drain of the transistor unit.
11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The method further includes: Multiple bit lines are formed; each bit line is coupled to another of the source and drain of the transistor cell.
12. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes dynamic random access memory.
13. A semiconductor structure, characterized in that, Formed using the method described in any one of claims 1-12.
14. A memory system, characterized in that, include: One or more semiconductor structures as described in claim 13; as well as A memory controller that is coupled to and controls the semiconductor structure.