Semiconductor interconnect structures having conductive elements, and associated systems and methods

Abstract

The present disclosure relates to semiconductor interconnect structures having conductive elements and associated systems and methods. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure may include a plurality of conductive elements made of a first conductive material having a first modulus of elasticity. The pillar structure may further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material may have a second modulus of elasticity that is less than the first modulus of elasticity.

Description

Technical Field

[0001] The present technology relates generally to semiconductor devices, and more particularly to semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stress. Background Art

[0002] Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a protective covering. The semiconductor die may include functional features, such as memory cells, processor circuitry, and imager devices, as well as bonding pads electrically connected to the functional features. The bonding pads may be electrically connected to terminals external to the protective covering to allow the semiconductor die to be connected to higher-level circuitry.

[0003] In some semiconductor packages, the bonding pads of a semiconductor die can be electrically coupled to an organic substrate or another semiconductor die via various bonding methods, such as thermal compression bonding (TCB), reflow bonding, or diffusion bonding. During the bonding operation, conductive posts are formed on the bonding pads and coupled to the substrate via a bonding material disposed between the conductive posts and the substrate. To attach the bonding material to the substrate, the semiconductor package is heated to heat and reflow the bonding material. However, heating the semiconductor package and / or subsequently cooling the semiconductor package can induce significant mechanical stress between the semiconductor die and the substrate due to the mismatch in the thermal expansion coefficients of these components. The stress can often cause cracking of one or more nearby semiconductor dies in the bonding pads, which can render the semiconductor package inoperable. Summary of the Invention

[0004] Aspects of the present application are directed to a semiconductor device comprising: a semiconductor die; and a pillar structure coupled to the semiconductor die, wherein the pillar structure comprises: a plurality of conductive elements electrically coupled to the semiconductor die, wherein each conductive element comprises a first conductive material having a first elastic modulus; and a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements, the second conductive material having a second elastic modulus less than the first elastic modulus.

[0005] Another aspect of the present application is directed to a semiconductor device comprising: a semiconductor die, and a pillar structure comprising a first end portion coupled to the semiconductor die and a second end portion remote from the semiconductor die, wherein the pillar structure comprises: a plurality of conductive elements electrically coupled to the semiconductor die; and a first solder material at least partially surrounding the plurality of conductive elements; and a second solder material coupled to the second end portion of the pillar structure, wherein the second solder material is different from the first solder material.

[0006] Another aspect of the present application is directed to a method of manufacturing a semiconductor device, the method comprising: forming a plurality of conductive elements on a semiconductor die, wherein each conductive element is formed of a first conductive material having a first modulus of elasticity; and forming a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements, wherein the second conductive material has a second modulus of elasticity less than the first modulus of elasticity. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Many aspects of the present inventive technique can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. In fact, the emphasis is on clearly illustrating the principles of the present inventive technique.

[0008] Figure 1A Is a side cross-sectional view of a semiconductor package.

[0009] Figure 1B Is of the semiconductor package after a TCB / reflow operation Figure 1A Is a side cross-sectional view of a semiconductor package.

[0010] Figure 2A Is a side cross-sectional view of a semiconductor package configured according to an embodiment of the present inventive technique.

[0011] Figure 2B Is of Figure 2A Is a close-up side cross-sectional view of an interconnect structure.

[0012] Figure 2C Is of Figure 2B Is an axial cross-sectional view of an interconnect structure.

[0013] Figures 3A to 3F Is an axial cross-sectional view of a pillar structure configured according to an additional embodiment of the present inventive technique.

[0014] Figures 4A to 4K Is a side cross-sectional view of a semiconductor package at various stages of a manufacturing process according to an embodiment of the present inventive technique.

[0015] Figure 5 Is a schematic diagram of a system including a semiconductor device or package configured according to an embodiment of the present inventive technique.

[0016] Figure 6A Is a block diagram illustrating a method of manufacturing a semiconductor package according to an embodiment of the present inventive technique.

[0017] Figure 6B Is for illustrating a method of manufacturing Figure 6A Is a block diagram of a method of elements of a method.

[0018] Figure 6C Is for illustrating a method of manufacturing Figure 6ABlock diagram of a method of another element of the method. Detailed Description

[0019] Details of several embodiments of semiconductor devices and associated systems and methods are described below. In several embodiments described below, a semiconductor package configured according to the techniques of the present invention may include a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure may include one or more conductive elements (e.g., a set of copper or nickel pillars) electrically coupled to the semiconductor die. The conductive elements may be at least partially surrounded by a conductive material (e.g., a solder material). The conductive material may have a modulus of elasticity lower than that of the conductive elements, such that the pillar structure is less rigid and / or more flexible compared to conventional semiconductor pillars (e.g., pillars made entirely of a single metallic material). Thus, when the package is subjected to stress (e.g., thermomechanical stress), the pillar structure may bend and / or deform to dissipate at least some of the stress, thereby reducing the amount of stress applied to the interface having the semiconductor die, which may be mechanically weaker than the pillar structure. The pillar structures of the techniques of the present invention are expected to reduce yield losses during the manufacture of semiconductor packages (e.g., after the TCB bonding step and / or the reflow step, due to thermal cycling and / or thermal shock during package reliability testing), and increase the reliability of the semiconductor package during operation (e.g., during power cycling during end-customer use).

[0020] Those skilled in the art will recognize that suitable stages of the methods described herein may be performed at the package, wafer, and / or die level. Thus, depending on its usage context, the term "substrate" may refer to a package-level substrate, a wafer-level substrate, or a singulated die-level substrate. Additionally, unless the context indicates otherwise, the structures disclosed herein may be formed using semiconductor manufacturing techniques well known to those skilled in the art in their details. For example, materials may be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, for example, materials may be removed using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0021] Many specific details are disclosed herein to provide a thorough and useful description of embodiments of the techniques of the present invention. However, those skilled in the art will understand that the techniques may have additional embodiments, and that the techniques may be practiced without some of the details of the embodiments described below with reference to Figures 1A to 6C Some details of semiconductor devices and / or packages well known in the art have been omitted so as not to obscure the techniques of the present invention. In general, it should be understood that various other devices and systems in addition to those specific embodiments disclosed herein may be within the scope of the techniques of the present invention.

[0022] As used herein, the terms "vertical," "lateral," "upper," "lower," "above," and "below" may refer to the relative directions or positions of features in a semiconductor device in view of the orientation shown in the figures. For example, "upper" or "uppermost" may refer to a feature positioned closer to the top of the page than another feature. However, these terms should be broadly understood to encompass semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, above / below, over / under, up / down, and left / right may be interchanged depending on the orientation.

[0023] Figure 1A FIG. 4 is a side cross-sectional view of a semiconductor package 100 ("package 100"). Package 100 includes a semiconductor die 102 carried by a package substrate 104. In the illustrated embodiment, semiconductor die 102 includes a semiconductor substrate 106 having a first side or surface 108a and a second side or surface 108b opposite the first side 108a. The first side 108a of semiconductor substrate 106 is the active side or region that includes one or more circuit elements formed in and / or on the first side 108a. In the illustrated embodiment, semiconductor die 102 further includes an insulating material 112 formed over at least a portion of the first side 108a of semiconductor substrate 106. Package substrate 104 further includes electrical connectors 114 that are electrically coupled to package substrate 104 and configured to electrically couple package 100 to an external device or circuitry (not shown). Semiconductor die 102 is electrically coupled to package substrate 104 via a plurality of interconnect structures 120. In the illustrated embodiment, each of interconnect structures 120 includes a pillar structure 122 and a bonding material 124. Pillar structure 122 is coupled to semiconductor die 102, and bonding material 124 is coupled to package substrate 104.

[0024] In some embodiments, package 100 is subjected to thermo-mechanical stresses (e.g., wafer package interaction (CPI) stresses) during manufacturing and / or use. Thermo-mechanical stresses may be induced, for example, by an assembly process (e.g., a DCA method, such as TCB / mass reflow), by thermal cycling and / or thermal shock during component / board-level reliability testing, and / or by power cycling during end-customer use.

[0025] For example, with reference to Figure 1A and 1B , package 100 is illustrated at the beginning and end of a TCB / reflow operation, respectively. In Figure 1AIn [description], heating of the package 100 has caused the bonding material 124 in the interconnect structure 120 to reflow and has electrically connected the pillar structure 122 to the package substrate 104. In some embodiments, the package 100 can be heated to 200° C. or greater (e.g., to 217° C. or greater) to reflow the bonding material 124. During the TCB operation, a compressive force can be applied to fasten the interconnect structure 120 to the package substrate 104. In Figure 1B [description], upon completion of the TCB operation, after the compressive force has been applied and after cooling the package 100 (e.g., to about 25° C.), the package 100 is illustrated. By cooling the package 100 at this time, the bonding material 124 can solidify, thereby fastening the semiconductor die 102 to the package substrate 104.

[0026] In some embodiments, the semiconductor die 102 has a coefficient of thermal expansion (CTE) that is different from that of the package substrate 104, and the CTE mismatch between these components can cause them to deform (e.g., twist, bend) relative to each other during cooling and / or heating of the package 100. For example, the CTE of the semiconductor die 102 (e.g., about 3 ppm / ° C.) can be lower than the CTE of the package substrate 104 (e.g., about 14 ppm / ° C.). Thus, as Figure 1B shown [description], the package substrate 104 can have a twisted non-planar shape after cooling. In other embodiments, the semiconductor die 102 or both the semiconductor die 102 and the package substrate 104 can have a non-planar twisted shape after cooling. The relative deformation of the semiconductor die 102 and the package substrate 104 can introduce lateral stress and mechanical (e.g., thermo-mechanical) stress that bends the interconnect structure 120 into the package 100 (e.g., CPI stress). This can cause cracking to form and propagate at the interface between the interconnect structure 120 and the semiconductor die 102 (e.g., at or within the insulating material 112), which can create mechanical and / or electrical failures within the package 100.

[0027] Figure 2A FIG. [description] is a side cross-sectional view of a semiconductor package 200 (“package 200”) configured in accordance with an embodiment of the technology of the present invention. The package 200 can include a semiconductor die 202 carried by a package substrate 204. In the illustrated embodiment, the semiconductor die 202 includes a semiconductor substrate 206 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.), the semiconductor substrate 206 having a first side or surface 208a and a second side or surface 208b opposite the first side 208a.

[0028] The first side 208a of the semiconductor substrate 206 can be an active side or region that includes one or more circuit elements 210 (e.g., wires, traces, interconnects, transistors, etc.) (shown schematically), and the one or more circuit elements are formed in and / or on the first side 208a. The circuit elements 210 can include, for example, memory circuits (e.g., dynamic random access memory (DRAM) or other types of memory circuits), controller circuits (e.g., DRAM controller circuits), logic circuits, and / or other circuits. In other embodiments, the semiconductor substrate 206 can be a “blank” substrate that does not include integrated circuit components and is formed of, for example, crystalline, semi-crystalline, and / or ceramic substrate materials such as silicon, polysilicon, aluminum oxide (Al2O3), sapphire, and / or other suitable materials.

[0029] In the illustrated embodiment, the semiconductor die 202 further includes an insulating material 212 formed over at least a portion of the first side 208a of the semiconductor substrate 206. The insulating material 212 can include one or more layers of a suitable dielectric material (e.g., a passivation material, a polyimide material, and / or other materials for covering the surface of a semiconductor device). For example, the insulating material 212 can include silicon oxide, silicon nitride, polysilicon nitride, polysilicon oxide, tetraethyl orthosilicate (TEOS), etc. In some embodiments, the insulating material 212 can at least partially include a dielectric material having a lower dielectric constant relative to silicon oxide (“low-κ dielectric material”). Such low-κ dielectric materials can include fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, organic polymer dielectrics, silicon-based polymer dielectrics, etc. Notably, low-κ dielectric materials can increase the performance of the package 200 but can be mechanically fragile, for example, compared to conventional (e.g., high-κ) dielectric materials. Thus, compared to other parts / components of the package 200, the insulating material 212 can be relatively prone to mechanical failures (e.g., cracking, delamination, etc. due to thermo-mechanical stress).

[0030] The package substrate 204 can be or include a redistribution layer, an interposer, a printed circuit board, a dielectric spacer, another semiconductor die (e.g., a logic die), or another suitable substrate. The package substrate 204 can further include electrical connectors 214 (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxies, and / or other suitable conductive elements) that are electrically coupled to the package substrate 204 (e.g., through pads, traces, vias, and / or other conductive structures in or on the package substrate 204) and are configured to electrically couple the package 200 to an external device or circuit system (not shown).

[0031] In the illustrated embodiment, a first side 208a of the semiconductor substrate 206 faces the package substrate 204 (e.g., in a direct chip attach (DCA) configuration). In other embodiments, the semiconductor die 202 may be arranged in a different manner. For example, a second side 208b of the semiconductor substrate 206 may face the package substrate 204, and the semiconductor die 202 may include one or more through-silicon vias (TSVs) that extend through the semiconductor substrate 206 to electrically couple the circuit elements 210 to the interconnect structure 220. Additionally, although Figure 2A only a single semiconductor die 202 is shown, in other embodiments, the package 200 may include multiple semiconductor dies, such as one or more additional semiconductor dies stacked on and / or above the semiconductor die 202.

[0032] The semiconductor die 202 may be electrically coupled to the package substrate 204 via a plurality of interconnect structures 220 (e.g., bumps, micro-bumps, pillars, posts, studs, etc.). For example, in some embodiments, the semiconductor die 202 includes a plurality of bond pads (not shown) that are electrically coupled to the circuit elements 210 of the semiconductor die 202. The bond pads may be at least partially exposed through openings in the insulating material 212 such that at least some of the interconnect structures 220 (e.g., directly or indirectly via an under-bump metallization (UBM) structure) are electrically coupled to the corresponding bond pads. The interconnect structures 220 may also be electrically coupled to bond pads (not shown) formed on the package substrate 204, thereby electrically coupling the circuit elements 210 on the semiconductor die 202 to the package substrate 204. Optionally, at least some of the interconnect structures 220 may be “dummy” structures that are not electrically coupled to electrically active bond pads on the semiconductor die 202 and / or the package substrate 204. Although Figure 2A six interconnect structures 220 are illustrated, the package 200 may include fewer or more interconnect structures 220. For example, the package 200 may include dozens, hundreds, thousands, or more interconnect structures 220 arranged between the semiconductor die 202 and the package substrate 204. The interconnect structures 220 may be configured to mitigate thermo-mechanical stress (e.g., due to CTE mismatch between the semiconductor die 202 and the package substrate 204), as described in detail below with reference to Figure 2B and 2C .

[0033] The package 200 may include other components commonly found in semiconductor devices and well known to those skilled in the art. For example, the package 200 may further include an underfill or molding material (not shown) formed over the package substrate 204 and / or at least partially surrounding the semiconductor die 202. In some embodiments, the package 200 includes other components such as an external heat sink, a sleeve (e.g., a conductive sleeve), an electromagnetic interference (EMI) shielding component, etc.

[0034] Figure 2B and 2C are respectively Figure 2A a side cross-sectional view and an axial cross-sectional view of one of the interconnect structures 220. First, referring to Figure 2B , the interconnect structure 220 includes a pillar structure 222 coupled to the semiconductor die 202 (e.g., for clarity only, to the insulating material and / or bonding pad at the surface of the semiconductor die 202 Figure 2B omitted). The pillar structure 222 may have an elongated shape having a first end portion 224 and a second end portion 226. The first end portion 224 may be electrically coupled to the semiconductor die 202 (e.g., to the insulating material and / or bonding pad at the surface of the semiconductor die 202). The second end portion 226 may be opposite to and located away from the first end portion 224 and the semiconductor die 202.

[0035] Next, referring together to Figure 2B and 2C , the pillar structure 222 may include a plurality of conductive elements 228 mechanically and electrically coupled to the semiconductor die 202. For example, the pillar structure 222 may include at least two, three, four, five, six, seven, eight, nine, ten, fifteen, twenty, fifty or more conductive elements 228. Each conductive element 228 may have an elongated shape extending from the first end portion 224 of the pillar structure 222 to the second end portion 226 of the pillar structure 222. For example, the conductive element 228 may be configured as a pillar, rod, column, fiber, filament, etc. Although Figure 2B each conductive element 228 is illustrated as having a straight linear shape, in other embodiments, some or all of the conductive elements 228 may have a curved, serpentine, Z-shaped, serpentine or any other suitable shape. Each conductive element 228 may have any suitable width and / or diameter, such as a width and / or diameter less than or equal to 10 μm, 5 μm, 2 μm, 1 μm, 500 nm, 200 nm or 100 nm. The conductive element 228 may be made of a first conductive material 229, such as copper, nickel, gold, silicon, tungsten, conductive epoxy, combinations thereof, etc.

[0036] Referring again together to Figure 2B and 2C , the conductive elements 228 may be partially or completely surrounded by a continuous region of a second conductive material 230. For example, as in Figure 2CBest seen in, the second conductive material 230 may fill the lateral spaces between the conductive elements 228 such that the column structure 222 has a solid cross-section having few or no internal voids or gaps. The second conductive material 230 may be electrically coupled to the semiconductor die 202 and may extend from the first end portion 224 of the column structure 222 to the second end portion 226 of the column structure 222. The second conductive material 230 may be or include any suitable conductive material, such as a solder material (e.g., SnAg-based solder).

[0037] As best seen in Figure 2C Best seen in, the column structure 222 and the conductive elements 228 may have a circular cross-sectional shape. However, in other embodiments, the column structure 222 and / or the conductive elements 228 may have different cross-sectional shapes (e.g., square, rectangular, triangular, etc.). Additional examples of suitable geometries for the conductive elements 228 are further provided below with reference to Figures 3A to 3F The conductive elements 228 may be spaced apart from each other and spatially distributed within the column structure 222 in various ways. For example, although the illustrated embodiment shows the conductive elements 228 as being evenly distributed throughout the column structure 222, in other embodiments, the conductive elements 228 may be clustered near the inner portion of the column structure 222, clustered near the outer peripheral portion of the column structure 222, arranged to form a pattern (e.g., linear, circular, triangular, square, etc.) within the column structure 222, arranged to form a shape having linear and / or radial symmetry relative to the column structure 222, or any other suitable distribution within the column structure.

[0038] In some embodiments, the first conductive material 229 and the second conductive material 230 are different materials having different physical properties. For example, the first conductive material 229 may have a relatively high modulus of elasticity (e.g., Young's modulus), such as a Young's modulus of at least 50 MPa, 75 MPa, 100 MPa, 150 MPa, 200 MPa, 500 MPa, 1 GPa, 10 GPa, 25 GPa, 50 GPa, 100 GPa, 200 GPa, 500 GPa, or 1000 GPa. The second conductive material 230 may have a lower modulus of elasticity than the first conductive material, such as a Young's modulus of less than or equal to 500 GPa, 200 GPa, 100 GPa, 10 GPa, 1 GPa, 100 MPa, 50 MPa, 25 MPa, or 10 MPa. The modulus of elasticity of the first conductive material 229 may be at least 2 times, 5 times, 10 times, 20 times, 50 times, or 100 times greater than the modulus of elasticity of the second conductive material 230. In such embodiments, the conductive element 228 may provide mechanical strength and / or structural integrity to the column structure 222, while the second conductive material 230 may dissipate stresses (e.g., thermomechanical stresses) applied to the column structure 222 through deformation (e.g., bending, pressing, etc.). This configuration may advantageously reduce the overall hardness and / or effective modulus of elasticity of the column structure 222, e.g., compared to a column structure made entirely of the first conductive material 229 (e.g., a solid copper column). For example, the effective Young's modulus of the column structure 222 may be reduced by at least 1%, 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% compared to the Young's modulus of the first conductive material 229. In some embodiments, the reduced hardness of the column structure 222 reduces the likelihood of electrical and / or mechanical failures due to applied stresses (e.g., thermomechanical stresses resulting from CTE mismatch). For example, when a stress is applied to the column structure 222, the column structure 222 may dissipate at least a portion of the stress through deformation (e.g., elastically and / or plastically). The deformation may reduce the amount of stress transmitted to Figure 2A the insulating material 212 and / or other portions of the package 200, thus reducing the likelihood of fracture, cracking, and / or other failures.

[0039] The relative amounts of the first conductive material 229 and the second conductive material 230 can be varied as needed to adjust the overall hardness of the pillar structure 222. For example, the volume of the first conductive material 229 and / or the conductive element 228 can be no greater than 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% of the total volume of the pillar structure 222. Alternatively or in combination, the volume of the first conductive material 229 and / or the conductive element 228 can be greater than or equal to 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% of the total volume of the pillar structure 222. The volume of the second conductive material 230 can be equal to or substantially equal to the remaining volume of the pillar structure 222. In some embodiments, the ratio of the volume of the first conductive material 229 to the volume of the second conductive material 230 can be at least 100:1, 50:1, 20:1, 10:1, 2:1, 1:1, 1:2, 1:5, 1:10, 1:20, 1:50, or 1:100.

[0040] The interconnect structure 220 can optionally include a barrier material 232 formed at least in part between the conductive element 228 and the second conductive material 230. For example, the barrier material 232 can coat the surface of the conductive element 228 that would otherwise be in direct contact with the second conductive material 230. In some embodiments, the barrier material 232 can have a thickness in the range from 1 μm to 5 μm. The barrier material 232 can facilitate bonding between the conductive element 228 and the second conductive material 230, and / or prevent or reduce electromigration of the first conductive material 229 of the conductive element 228. The barrier material 232 can be made of any suitable material, such as nickel, nickel-based intermetallic compounds, gold, tungsten, tantalum, titanium, or alloys or combinations thereof. However, in other embodiments, the barrier material 232 can be omitted (e.g., in cases where the first conductive material 229 exhibits little or no tendency for electromigration).

[0041] Referring again to Figure 2B , the interconnect structure 220 can further include a third conductive material 234 that is mechanically and electrically coupled to the pillar structure 222. In the illustrated embodiment, the third conductive material 234 has a first end portion 236 coupled to the second end portion 226 of the pillar structure 222, and a second end portion 238 that can be optionally coupled to another component, such as Figure 2A the package substrate 204, a second semiconductor die, and / or a second semiconductor device (not shown). In embodiments where the pillar structure 222 includes the barrier material 232, the barrier material 232 can be located between the conductive element 228 and the third conductive material 234, for example to facilitate bonding and / or reduce electromigration.

[0042] The third conductive material 234 can be any suitable conductive material, such as a solder material (e.g., SnAg-based solder). In some embodiments, for example, the second conductive material 230 is made of a first solder material, and the third conductive material 234 is made of a second solder material. The first and second solder materials can be the same solder material or can be different solder materials. Optionally, the first and second solder materials can have different physical properties. For example, the first solder material (corresponding to the second conductive material 230) can have a first melting temperature, and the second solder material (corresponding to the third conductive material 234) can have a second melting temperature lower than the first melting temperature. This can be advantageous in embodiments where the interconnect structure 220 is attached to the package substrate or other components via a TCB / reflow operation, because the first solder material can remain substantially or completely solid to maintain structural integrity and / or avoid voiding or wicking, while the second solder material melts to form a binder. As another example, the first solder material (corresponding to the second conductive material 230) can have a first modulus of elasticity, and the second solder material (corresponding to the third conductive material 234) can have a second modulus of elasticity lower than the first modulus of elasticity. In such embodiments, the first solder material can be more compliant to dissipate stress at the column structure 222, while the second solder material can be harder to resist fracture, cracking, etc.

[0043] Figures 3A to 3F Axial cross-sectional views of column structures 322a to 322f configured according to the techniques of the present invention. Figures 3A to 3F The components of the column structures 322a to 322f in can be generally similar to Figures 2A to 2C the components of the column structure 222 of. Thus, like numerals (e.g., conductive elements 328a to 328f relative to conductive element 228) are used to identify similar or identical components, and Figures 3A to 3F the discussion of the column structures 322a to 322f of will be limited to those features that are different from Figures 2A to 2C the column structure 222 of. Additionally, Figures 3A to 3F any one feature of the column structures 322a to 322f of can be combined with each other and / or with Figures 2A to 2C the column structure 222 of.

[0044] Figure 3A Illustrates a column structure 322a having a plurality of conductive elements 328a with a square cross-sectional shape. In the illustrated embodiment, the conductive elements 328a have rounded corners, which can be beneficial for reducing stress concentration. However, in other embodiments, the conductive elements 328a can have sharp corners.

[0045] Figure 3BDescribe a column structure 322b having a plurality of conductive elements 328b, the plurality of conductive elements 328b having a rectangular cross-sectional shape. The conductive elements 328b may optionally have rounded corners (e.g., to reduce stress concentration) or sharp corners. In yet another embodiment, the conductive elements 328b may have an elliptical, triangular, rhombic, trapezoidal, pentagonal, or hexagonal cross-sectional shape or any other suitable cross-sectional shape.

[0046] Figure 3C Describe a column structure 322c having a conductive element 328c configured to have a circular cross-sectional shape. Although the illustrated embodiment shows the conductive element 328c concentrated in the column structure 322c, in other embodiments, the conductive element 328c may be offset from the center of the column structure 322c. Additionally, in other embodiments, the conductive element 328c may have a cross-sectional shape of an elliptical, square, rectangular, triangular, rhombic, trapezoidal, pentagonal, or hexagonal shape or any other suitable cross-sectional shape.

[0047] Figure 3D Describe a column structure 322d having a set of conductive elements 328d configured as a plurality of nested structures. For example, in the illustrated embodiment, the conductive elements 328d are configured as a plurality of nested circular rings. The rings may be arranged in a concentric configuration or may be offset from each other. Although Figure 3D each conductive element 328d is described as a continuous closed circle, in other embodiments, some or all of the conductive elements 328d may be semi-circles, arcs, circular segments, etc. The column structure 322d may optionally include a barrier material 332d between the conductive elements 328d and a second conductive material 330d such that the barrier material 332d extends along the inner and / or outer surfaces of the conductive elements 328d.

[0048] Figure 3E Describe a column structure 322e having a set of conductive elements 328e configured as a plurality of nested square rings. In the illustrated embodiment, the conductive elements 328e have rounded corners, which may be beneficial for reducing stress concentration. However, in other embodiments, the conductive elements 328e may have sharp corners. The conductive elements 328d may be arranged concentrically, offset from each other, or in any other suitable configuration. The column structure 322e may optionally include a barrier material 332e that extends along the inner and / or outer surfaces of each conductive element 328e.

[0049] Figure 3FDescribe a column structure 322f having a set of conductive elements 328f configured as multiple nested diamond rings. The conductive elements 328f may have rounded or sharp corners and may be concentric, offset from each other, or any other suitable configuration. In yet another embodiment, the column structure 322f may include nested rings that are triangular, trapezoidal, pentagonal, hexagonal, octagonal, or any other suitable shape. In some embodiments, the conductive elements 328f may be positioned relative to each other (e.g., concentrically). The column structure 322f may optionally include a barrier material 332f extending along the inner and / or outer surfaces of each conductive element 328f.

[0050] Figures 4A to 4K Is a side cross-sectional view of a semiconductor package at various stages of a manufacturing process or method according to an embodiment of the technology of the present invention. The method can be used to manufacture any embodiment of the semiconductor package described herein and / or one or more of its components (e.g., Figures 2A to 2C the column structure 222, Figures 3A to 3F the column structures 322a to 322f).

[0051] First refer to Figure 4A , the method includes providing a semiconductor die 402 including one or more bonding pads 410. The method may optionally include applying a first seed layer 404 (e.g., a titanium layer) to the semiconductor die 402 and / or applying a second seed layer 406 (e.g., a copper layer) on top of the first seed layer 404. According to techniques well known to those skilled in the art, the method further includes applying a photoresist material 408 on the semiconductor die 402 and on the first seed layer 404 and / or the second seed layer 406 (if present). The method may further include patterning regions of the photoresist material 408 above the bonding pads 410 to form a set of grooves 412 in the photoresist material 408. The position and / or geometry of the grooves 412 may correspond to the desired position and / or geometry of the conductive elements.

[0052] Next refer to Figure , the method further includes depositing a first conductive material 429 (e.g., copper, nickel, etc.) into the grooves 412 of the patterned photoresist material 408 ( ​ ). Any suitable technique well known to those skilled in the art can be used to deposit the first conductive material 429, such as plating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroless plating, spin coating, and / or other suitable techniques.

[0053] Next refer to ​ , the method further includes removing the photoresist material 408 after the first conductive material 429 has been deposited in the grooves 412. The first conductive material 429 may form a set of conductive elements 428 that are electrically coupled to the semiconductor die 402. Although ​The conductive element 428 described in [reference] includes a plurality of pillars (e.g., similar to the conductive element 228 of [reference ​ ]), but in other embodiments, the conductive element 428 can be configured according to any one of the embodiments discussed with respect to [reference ​ ] or according to any other suitable embodiment of the technology of the present invention. ​ However, in other embodiments, the conductive element 428 can be configured according to any one of the embodiments discussed with respect to [reference ​ ] or according to any other suitable embodiment of the technology of the present invention. ​ Referring now to [reference ], the method further includes depositing another photoresist material 416 to at least partially cover the semiconductor die 402 and the conductive element 428 according to techniques well known to those skilled in the art. The thickness of the photoresist material 416 can be greater than the height of the conductive element 428.

[0054] Referring now to [reference ​ ], the method further includes removing portions of the photoresist material 416 above and / or around the conductive element 428 to form a recess 418. The geometry of the recess 418 can correspond to the desired geometry of the pillar structure to be formed. For example, the cross-sectional shape of each recess 418 can correspond to the cross-sectional shape of the pillar structure to be formed (e.g., a circular cross-sectional shape). ​ Referring now to [reference ], the method further includes removing portions of the photoresist material 416 above and / or around the conductive element 428 to form a recess 418. The geometry of the recess 418 can correspond to the desired geometry of the pillar structure to be formed. For example, the cross-sectional shape of each recess 418 can correspond to the cross-sectional shape of the pillar structure to be formed (e.g., a circular cross-sectional shape).

[0055] Referring now to [reference ​ ], the method optionally includes depositing a barrier material 432 (e.g., nickel) in the recess 418 to at least partially cover the exposed surface of the conductive element 428. The barrier material 432 can be deposited using plating and / or other suitable techniques well known to those skilled in the art. ​ Referring now to [reference ], the method optionally includes depositing a barrier material 432 (e.g., nickel) in the recess 418 to at least partially cover the exposed surface of the conductive element 428. The barrier material 432 can be deposited using plating and / or other suitable techniques well known to those skilled in the art. <00,00185>

[0056] Referring now to [reference ​ ], the method further includes depositing a second conductive material 430 (e.g., a first solder material) in the recess 418 to at least partially cover the conductive element 428 and (if present) the barrier material 432. As previously described, the second conductive material 430 can partially or completely surround the conductive element 428, thus forming a solid pillar structure 422. The second conductive material 430 can be deposited using plating and / or other suitable processes well known to those skilled in the art. The volume of the second conductive material 430 added to the recess 418 can be such that the second conductive material 430 covers and / or seals the conductive element 428 but only partially fills the recess 418. For example, in the illustrated embodiment, the second conductive material 430 covers the conductive element 428 and the barrier material 432 but does not completely fill the recess 418, such that the height of the pillar structure 422 is less than the total thickness of the photoresist material 416. ​ Referring now to [reference ], the method optionally includes depositing a barrier material 432 (e.g., nickel) in the recess 418 to at least partially cover the exposed surface of the conductive element 428. The barrier material 432 can be deposited using plating and / or other suitable techniques well known to those skilled in the art.

[0057] Referring now to [reference ​ ], the method further includes depositing a second conductive material 430 (e.g., a first solder material) in the recess 418 to at least partially cover the conductive element 428 and (if present) the barrier material 432. As previously described, the second conductive material 430 can partially or completely surround the conductive element 428, thus forming a solid pillar structure 422. The second conductive material 430 can be deposited using plating and / or other suitable processes well known to those skilled in the art. The volume of the second conductive material 430 added to the recess 418 can be such that the second conductive material 430 covers and / or seals the conductive element 428 but only partially fills the recess 418. For example, in the illustrated embodiment, the second conductive material 430 covers the conductive element 428 and the barrier material 432 but does not completely fill the recess 418, such that the height of the pillar structure 422 is less than the total thickness of the photoresist material 416. ​ Referring now to [reference ], the method further includes depositing a second conductive material 430 (e.g., a first solder material) in the recess 418 to at least partially cover the conductive element 428 and (if present) the barrier material 432. As previously described, the second conductive material 430 can partially or completely surround the conductive element 428, thus forming a solid pillar structure 4,. The second conductive material 430 can be deposited using plating and / or other suitable processes well known to those skilled in the art. The volume of the second conductive material 430 added to the recess 418 can be such that the second conductive material 430 covers and / or seals the conductive element 428 but only partially fills the recess 418. For example, in the illustrated embodiment, the second conductive material 430 covers the conductive element 428 and the barrier material 432 but does not completely fill the recess 418, such that the height of the pillar structure 422 is less than the total thickness of the photoresist material 416.

[0058] Referring now to [reference ​ ], the method further includes depositing a second conductive material 430 (e.g., a first solder material) in the recess 418 to at least partially cover the conductive element 428 and (if present) the barrier material 432. As previously described, the second conductive material 430 can partially or completely surround the conductive element 428, thus forming a solid pillar structure 422, The second conductive material 430 can be deposited using plating and / or other suitable processes well known to those skilled in the art. The volume of the second conductive material 430 added to the recess 418 can be such that the second conductive material 430 covers and / or seals the conductive element 428 but only partially fills the recess 418. For example, in the illustrated embodiment, the second conductive material 430 covers the conductive element 428 and the barrier material 432 but does not completely fill the recess 418, such that the height of the pillar structure 422 is less than the total thickness of the photoresist material 416. ​, the method optionally includes depositing a third conductive material 434 (e.g., a second solder material) in the recess 418 onto the end portion 426 of the pillar structure 422, thereby forming an interconnect structure 420. The third conductive material 434 can be the same as or different from the second conductive material 430, as previously discussed. The third conductive material 434 can be deposited using plating and / or any other suitable technique.

[0059] Next, referring to ​ , the method includes removing the photoresist material 416 using a photoresist stripping technique well known to those skilled in the art to expose the interconnect structure 420.

[0060] Next, referring to ​ , the method optionally includes removing portions of the first seed layer 404 and the second seed layer 406 surrounding the interconnect structure 420 from the semiconductor die 402, for example, by etching (e.g., anisotropic etching using the third conductive material 434 as a mask) and / or other suitable processes.

[0061] Next, referring to ​ , the method optionally includes using a TCB / reflow process to electrically and mechanically couple the semiconductor die 402 and the interconnect structure 420 to another component 440, such as a package substrate or a semiconductor die. The component 440 can include one or more bonding pads 442, and the bonding pads 442 can each be electrically and mechanically coupled to the third conductive material 434 of the corresponding interconnect structure 420 during the TCB / reflow process. As described above, the second conductive material 430 can have a higher melting temperature than the third conductive material 434, such that the heat in the TCB / reflow process melts the third conductive material 434 while the second conductive material 430 remains substantially or completely solid.

[0062] Any of the semiconductor devices and / or packages having the features described above with reference to ​ can be incorporated into any of numerous larger and / or more complex systems, representative examples of which are ​ the system 500 schematically shown in. The system 500 can include a processor 502, a memory 504 (e.g., SRAM, DRAM, flash, and / or other memory devices), an input / output device 506, and / or other subsystems or components 508. The semiconductor die, package, and / or interconnects described above with reference to ​ can be included in ​in any of the components shown. The resulting system 500 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Thus, representative examples of system 500 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, network appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics devices, network computers, and minicomputers. Additional representative examples of system 500 include lights, cameras, vehicles, etc. With respect to these and other examples, system 500 can be housed in a single unit or distributed, for example, over multiple interconnected units via a communication network. Thus, the components of system 500 can include local and / or remote memory storage devices and any of a wide variety of suitable computer-readable media.

[0063] ​ FIG. is a block diagram illustrating a method 600 of manufacturing a semiconductor package in accordance with an embodiment of the technology of the present invention. Method 600 can be used to manufacture any embodiment of the semiconductor packages described herein and / or one or more of its components (e.g., ​ the pillar structure 222 of ​ the pillar structures 322a to 322f of ​ FIG. is a block diagram of a method of block 610 of manufacturing method 600. ​ FIG. is a block diagram of a method of block 620 of manufacturing method 600. Method 600, block 610, and / or block 620 can be accomplished using techniques that are well known to those skilled in the art and that include the techniques previously discussed with respect to FIG. 4.

[0064] Referring to ​ , method 600 includes forming a plurality of conductive elements on a semiconductor die, wherein each conductive element is formed of a first conductive material having a first modulus of elasticity (block 610). Method 600 further includes forming a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements, wherein the second conductive material has a second modulus of elasticity that is less than the first modulus of elasticity (block 620).

[0065] Referring to ​ , forming a plurality of conductive elements (block 610 of method 600) can include forming a patterned photoresist material on the semiconductor die, wherein the patterned photoresist material includes a plurality of grooves corresponding to the locations of the plurality of conductive elements (block 612). Forming a plurality of conductive elements (block 610) can further include depositing the first conductive material in the plurality of grooves of the patterned photoresist material (block 614).

[0066] Referring to ​, forming a continuous region of the second conductive material (block 620 of method 600) may include forming a patterned photoresist material on the semiconductor die, wherein the patterned photoresist material includes grooves surrounding a plurality of conductive elements (block 622). Block 620 of method 600 may further include depositing the second conductive material in the grooves of the patterned photoresist material to at least partially surround the plurality of conductive elements (block 624). Method 600 may optionally include depositing a barrier material on the plurality of conductive elements before depositing the second conductive material (block 630). Method 600 may also optionally include depositing a third conductive material in the grooves of the patterned photoresist material and on top of the second conductive material (block 640).

[0067] It should be understood from the foregoing that, for purposes of illustration, specific embodiments of the technology have been described herein, but various modifications may be made without departing from the disclosure. Accordingly, the invention is not limited except as by the appended claims. Additionally, certain aspects of the technology described in the context of a particular embodiment may be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology may cover other embodiments not expressly shown or described herein.

Claims

1. A semiconductor device, comprising: A semiconductor die; And A column structure coupled to the semiconductor die, wherein the column structure comprises - A plurality of conductive elements, each electrically coupled to the semiconductor die and linearly extending away from the semiconductor die, wherein each conductive element comprises a first conductive material having a first modulus of elasticity, and A continuous region of a second conductive material that at least partially surrounds the plurality of conductive elements, the second conductive material having a second modulus of elasticity less than the first modulus of elasticity.

2. The semiconductor device according to claim 1, wherein the plurality of conductive elements comprise a plurality of posts extending from the semiconductor die.

3. The semiconductor device according to claim 2, wherein each of the plurality of posts has a circular cross-sectional shape or a square cross-sectional shape.

4. The semiconductor device according to claim 1, wherein the plurality of conductive elements comprise a plurality of nested structures.

5. The semiconductor device according to claim 1, wherein the volume of the first conductive material is in the range of 1% to 30% of the total volume of the column structure.

6. The semiconductor device according to claim 1, wherein the first conductive material comprises copper or nickel, and the second conductive material comprises a solder material.

7. The semiconductor device according to claim 1, wherein the column structure comprises a first end portion coupled to the semiconductor die and a second end portion away from the semiconductor die, and wherein the semiconductor device further comprises a third conductive material coupled to the second end portion of the column structure.

8. The semiconductor device according to claim 7, wherein the second conductive material comprises a first solder material, and the third conductive material comprises a second solder material.

9. The semiconductor device according to claim 8, wherein the first solder material has a melting temperature different from that of the second solder material.

10. The semiconductor device according to claim 9, wherein the first solder material has a higher melting temperature than the second solder material.

11. The semiconductor device according to claim 8, further comprising a barrier material between the first conductive material and the second conductive material.

12. The semiconductor device according to claim 7, wherein the second conductive material and the third conductive material are the same solder material.

13. The semiconductor device according to claim 7, wherein the third conductive material is electrically coupled to a second semiconductor device.

14. A semiconductor device, comprising: A semiconductor die; And A column structure comprising a first end portion coupled to the semiconductor die and a second end portion away from the semiconductor die, wherein the column structure comprises - A plurality of conductive elements, each electrically coupled to the semiconductor die and linearly extending away from the semiconductor die, and A first solder material that at least partially surrounds the plurality of conductive elements; And A second solder material coupled to the second end portion of the column structure, wherein the second solder material is different from the first solder material.

15. The semiconductor device according to claim 14, wherein the first solder material has a higher melting temperature than the second solder material.

16. The semiconductor device according to claim 14, wherein the first solder material and the second solder material have different Young's moduli.

17. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of conductive elements on a semiconductor die, wherein each conductive element is formed of a first conductive material having a first modulus of elasticity; and forming a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements, wherein the second conductive material has a second modulus of elasticity less than the first modulus of elasticity.

18. The method according to claim 17, wherein forming the plurality of conductive elements comprises: forming a patterned photoresist material on the semiconductor die, wherein the patterned photoresist material includes a plurality of grooves corresponding to the positions of the plurality of conductive elements; and depositing the first conductive material in the plurality of grooves of the patterned photoresist material.

19. The method according to claim 17, wherein forming the continuous region of the second conductive material comprises: forming a patterned photoresist material on the semiconductor die, wherein the patterned photoresist material includes a groove surrounding the plurality of conductive elements; and depositing the second conductive material in the groove of the patterned photoresist material to at least partially surround the plurality of conductive elements.

20. The method according to claim 19, further comprising: depositing a barrier material on the plurality of conductive elements before depositing the second conductive material.

21. The method according to claim 19, further comprising: depositing a third conductive material in the groove of the patterned photoresist material and above the second conductive material.

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