Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same include: after forming a dielectric wall, forming a first protective layer in a second device region covering the top and sidewalls of a channel stack, the first protective layer exposing the channel stack in the first device region; using the first protective layer as a mask, removing the first channel layer exposed by a gate opening in the first device region to form a first through-groove connected to the gate opening; after forming the first through-groove, forming a second protective layer in the first device region covering the gate opening and the second channel layer exposed by the first through-groove; using the second protective layer as a mask, removing the first protective layer and the second channel layer exposed by the gate opening in the second device region to form a second through-groove connected to the gate opening. The first channel layer and the second channel layer can meet the carrier mobility requirements of the second-type transistor and the first-type transistor, respectively, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are moving towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor transistors, are currently widely used. Therefore, as the component density and integration of semiconductor transistors increase, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.

[0003] To better adapt to the requirement of scaling down transistor size, semiconductor processes have gradually begun to transition from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. Among them, GAA transistors include vertical GAA transistors and horizontal GAA transistors. In GAA transistors, the gate surrounds the channel area on all sides. Compared with planar transistors, the gate of GAA transistors has stronger control over the channel and can better suppress short channel effects.

[0004] As device sizes continue to shrink, improving the carrier mobility of the conductive channels of both NMOS devices with a fully encircling gate structure and PMOS devices with a fully encircling gate structure becomes increasingly difficult and challenging. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is conducive to further improving the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, the first device region and the second device region being adjacent to each other in a first direction; a first channel structure layer extending along a second direction, located on the substrate in the second device region, the first channel structure layer including one or more first channel layers spaced apart in a longitudinal direction, and the bottommost first channel layer is in contact with the substrate, and the second direction is perpendicular to the first direction; a second channel structure layer extending along the second direction, located on the substrate in the first device region and spaced apart from the substrate, the second channel structure layer including one or more second channel layers spaced apart in a longitudinal direction, and the second channel layer is in contact with the first channel layer. A channel layer is staggered in the longitudinal direction; a dielectric wall extending along the second direction is located on the substrate at the junction of the first device region and the second device region, and covers the sidewalls of the first channel structure layer and the second channel structure layer; a first gate dielectric layer is located in the first device region, and the first gate dielectric layer covers part of the top, part of the sidewall and part of the bottom of the second channel layer; a second gate dielectric layer is located in the second device region, and the second gate dielectric layer covers part of the top, part of the sidewall and part of the bottom of the first channel layer; a gate structure is located on the top of the substrate and spans the first channel structure layer, the second channel structure layer and the dielectric wall, and the gate structure covers part of the top of the first channel structure layer, the dielectric wall and the second channel structure layer, and surrounds the first gate dielectric layer and the second gate dielectric layer.

[0007] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, the first device region and the second device region being adjacent in a first direction, one or more longitudinally stacked channel stacks being formed on the substrate, each channel stack comprising a first channel layer and a second channel layer located on the first channel layer, the second channel layer being used to provide a channel of the first-type transistor, the first channel layer being used to provide a channel of the second-type transistor, and the channel materials of the first-type transistor and the second-type transistor being different; forming a dielectric wall penetrating the channel stack and extending along a second direction at a junction of the first device region and the second device region in the channel stack, the dielectric wall separating the channel stacks in the first device region and the second device region in the first direction, and the first direction being perpendicular to the second direction; forming a dummy gate spanning the channel stack and the dielectric wall, the dummy gate covering the channel stack Part of the top and part of the sidewall; removing the dummy gate to form a gate opening; after forming the dielectric wall, forming a first protective layer covering the top and sidewalls of the channel stack in the second device area, the first protective layer exposing the channel stack in the first device area; using the first protective layer as a mask, removing the first channel layer exposed by the gate opening in the first device area to form a first through-groove connected to the gate opening; after forming the first through-groove, forming a second protective layer covering the gate opening and the second channel layer exposed by the first through-groove in the first device area; using the second protective layer as a mask, removing the first protective layer and the second channel layer exposed by the gate opening in the second device area to form a second through-groove connected to the gate opening; forming a gate structure in the gate opening, the first through-groove and the second through-groove, the gate structure surrounding the first channel layer in the first device area exposed by the dielectric wall and the second channel layer in the second device area exposed by the dielectric wall.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a semiconductor structure, wherein a first channel structure layer is located on a substrate of the second device region, the first channel structure layer includes one or more first channel layers spaced apart in a vertical direction, and the bottommost first channel layer is in contact with the substrate; a second channel structure layer is located on a substrate of the first device region and spaced apart from the substrate, the second channel structure layer includes one or more second channel layers spaced apart in a vertical direction, and the second channel layer and the first channel layer are staggered in the vertical direction. Compared with the existing solution in which the first channel structure layer and the second channel structure layer are symmetrical with each other in the horizontal direction, in the embodiment of the present invention, the second channel layer and the first channel layer are staggered in the vertical direction, and the first channel layer and the second channel layer can respectively meet the requirements of the second-type transistor and the first-type transistor for carrier mobility, so as to respectively meet the respective performance requirements of the second-type transistor and the first-type transistor, thereby improving the performance of the semiconductor structure; at the same time, the second channel layer and the first channel layer are staggered in the vertical direction, so that during the formation of the semiconductor structure, the same channel stack can be formed on the substrate of the first device area and the second device area, and each channel stack includes a first channel layer and a second channel layer located on the first channel layer. It is only necessary to remove the first channel layer in the first device area and the second channel layer in the second device area respectively, which reduces the process difficulty of forming the first channel layer and the second channel layer and improves the process manufacturing efficiency.

[0010] Accordingly, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein after forming a dielectric wall, a first protective layer covering the top and sidewalls of the channel stack is formed in the second device area, and the first protective layer exposes the channel stack in the first device area; using the first protective layer as a mask, the first channel layer exposed by the gate opening is removed in the first device area to form a first through groove connected to the gate opening; after forming the first through groove, a second protective layer covering the gate opening and the second channel layer exposed by the first through groove is formed in the first device area; using the second protective layer as a mask, the first protective layer exposed by the gate opening and the second channel layer are removed in the second device area to form a second through groove connected to the gate opening. Compared with the current solution of simultaneously removing the first channel layer of the first device area and the second device area after forming the gate opening, the embodiment of the present invention forms a first protective layer in the second device area to cover the top and sidewalls of the channel stack, that is, in the step of removing the first channel layer of the first device area, the first protective layer can play a protective isolation role for the channel stack of the second device area, and then forms a second protective layer conformally covering the second channel layer in the first device area, that is, in the step of removing the second channel layer of the second device area, the second protective layer can play a role of etching mask, and accordingly, the first channel layer in the first device area and the second channel layer in the second device area can be removed respectively, so that the first channel layer and the second channel layer can respectively meet the carrier mobility requirements of the second-type transistor and the first-type transistor, so as to respectively meet the performance requirements of the second-type transistor and the first-type transistor, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figure 6 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 7 to 23 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure.

[0015] Figures 1 to 5 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1, providing a substrate, the substrate including a first device region 10a for forming a first type transistor and a second device region 10b for forming a second type transistor, the first device region 10a and the second device region 10b in a first direction (such as Figure 1 The substrate is adjacent to the first device region 10a and the second device region 10b, and one or more longitudinally stacked channel stacks 13 are formed on the substrate. Each channel stack 13 includes a sacrificial layer 11 and a channel layer 12 located on the sacrificial layer 11. An isolation layer 18 is formed on the substrate exposed by the channel stack 13. At the junction of the first device region 10a and the second device region 10b, a channel stack 13 is formed in the channel stack 13 and extends along the second direction (as shown in FIG. Figure 1 The dielectric wall 17 extends in the Y direction, and the dielectric wall 17 separates the channel stack 13 in the first device region 10a and the second device region 10b in the first direction, and the first direction is perpendicular to the second direction.

[0017] It should be noted that the second direction refers to a direction parallel to the horizontal direction and perpendicular to the first direction.

[0018] refer to Figure 2 , forming a dummy gate 16 spanning the channel stack 13 and the dielectric wall 17, the dummy gate 16 covering part of the top and part of the sidewall of the channel stack 13, the sidewall of the dummy gate 16 is formed with a sidewall 15, and an interlayer dielectric layer 14 is formed on the isolation layer exposed by the dummy gate 16 and the sidewall 15, and the interlayer dielectric layer covers the sidewall of the sidewall 15.

[0019] refer to Figure 3 , the dummy gate 16 is removed to form a gate opening 18 .

[0020] refer to Figure 4 The sacrificial layer 11 is removed along the gate opening 18 , and the remaining channel layers 12 in the first device region 10 a and the second device region 10 b are arranged symmetrically with each other in the horizontal direction.

[0021] refer to Figure 5 A gate structure 19 is formed in the gate opening 18 , and the gate structure 19 surrounds the channel layer 12 in the first device region 10 a exposed by the dielectric wall 17 , and the channel layer 12 in the second device region 10 b exposed by the dielectric wall 17 .

[0022] The first device region 10a is used to form an NMOS transistor, and the second device region 10b is used to form a PMOS transistor.

[0023] like Figure 4As shown, the gate opening 18 exposes the sacrificial layer 11 in the first device region 10a and the second device region 10b at the same time. Therefore, the first device region 10a and the second device region 10b can only retain the same channel layer 12. That is, in the formation method, the first-type transistor and the second-type transistor can only use the same channel layer material. When the first-type transistor and the second-type transistor need to use different channel layers (for example, channel layers of different materials are required to meet the requirements for carrier mobility), the formation method cannot meet the requirements of retaining the required channel layers in the first device region 10a and the second device region 10b, making it difficult to meet the performance requirements of the second-type transistor and the first-type transistor respectively.

[0024] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, the first device region and the second device region being adjacent in a first direction, one or more longitudinally stacked channel stacks being formed on the substrate, each channel stack comprising a first channel layer and a second channel layer located on the first channel layer, the second channel layer being used to provide a channel for the first-type transistor, the first channel layer being used to provide a channel for the second-type transistor, and the channel materials of the first-type transistor and the second-type transistor being different; forming a dielectric wall in the channel stack at a junction of the first device region and the second device region, the dielectric wall penetrating the channel stack and extending along a second direction, the dielectric wall separating the channel stacks in the first device region and the second device region in the first direction, and the first direction being perpendicular to the second direction; forming a dummy gate spanning the channel stack and the dielectric wall, the dummy gate covering the channel. The invention relates to a method for manufacturing a semiconductor device of the present invention and a semiconductor device comprising: forming a semiconductor device comprising: ...

[0025] In an embodiment of the present invention, a first protective layer is formed in the second device region to cover the top and sidewalls of the channel stack, that is, in the step of removing the first channel layer in the first device region, the first protective layer can play a protective and isolating role for the channel stack in the second device region. Then, a second protective layer is formed in the first device region to conformally cover the second channel layer, that is, in the step of removing the second channel layer in the second device region, the second protective layer can play a role of an etching mask. Accordingly, the first channel layer and the second channel layer can respectively meet the carrier mobility requirements of the second-type transistor and the first-type transistor, so as to respectively meet the performance requirements of the second-type transistor and the first-type transistor, thereby improving the performance of the semiconductor structure.

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figure 6 FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0028] The semiconductor structure includes a substrate, wherein the substrate includes a first device region 200a for forming a first-type transistor and a second device region 200b for forming a second-type transistor, wherein the first device region 200a and the second device region 200b are arranged in a first direction (eg Figure 6 along the second direction (as shown in the X direction); Figure 6 The first channel structure layer 260 extending along the second direction (shown in the Y direction) is located on the substrate of the second device area 200b, and the first channel structure layer 260 includes one or more first channel layers 201 spaced apart in the longitudinal direction, and the bottom first channel layer 201 is in contact with the substrate, and the second direction is perpendicular to the first direction; the second channel structure layer 270 extending along the second direction is located on the substrate of the first device area 200a and spaced apart from the substrate, and the second channel structure layer 270 includes one or more second channel layers 202 spaced apart in the longitudinal direction, and the second channel layer 202 is in contact with the first channel layer 202. A channel layer 201 is staggered in the longitudinal direction; a dielectric wall 207 extending along the second direction is located on the substrate at the junction of the first device area 200a and the second device area 200b, and covers the side walls of the first channel structure layer 260 and the second channel structure layer 270; a gate structure 225 is located on the top of the substrate and spans the first channel structure layer 260, the second channel structure layer 270 and the dielectric wall 207, and the gate structure 225 covers part of the top of the first channel structure layer 260, the dielectric wall 207 and the second channel structure layer 270, and surrounds the first channel layer 201 and the second channel layer 202.

[0029] In this embodiment, the second channel layer 202 and the first channel layer 201 are staggered in the vertical direction. The first channel layer 201 and the second channel layer 202 can respectively meet the carrier mobility requirements of the second-type transistor and the first-type transistor, so as to respectively meet the performance requirements of the second-type transistor and the first-type transistor, thereby improving the performance of the semiconductor structure. At the same time, the second channel layer 202 and the first channel layer 201 are staggered in the vertical direction. Therefore, during the formation of the semiconductor structure, the same channel stack can be formed on the substrate of the first device area 200a and the second device area 200b. Each channel stack includes a first channel layer 201 and a second channel layer 202 located on the first channel layer 201. It is sufficient to remove the first channel layer 201 in the first device area 200a and the second channel layer 202 in the second device area 200b respectively. This reduces the process difficulty of forming the first channel layer 201 and the second channel layer 202 and improves the process manufacturing efficiency.

[0030] In this embodiment, the substrate includes a first device region 200 a for forming a first-type transistor and a second device region 200 b for forming a second-type transistor. The first device region 200 a and the second device region 200 b are adjacent to each other in a first direction.

[0031] The first-type transistor and the second-type transistor have different channel conductivity types. Specifically, the first-type is N-type and the second-type is P-type.

[0032] In this embodiment, the first-type transistor is used to form an NMOS transistor, and the second-type transistor is used to form a PMOS transistor; the material of the first channel layer 201 includes silicon germanium; and the material of the second channel layer 202 includes silicon.

[0033] It should be noted that the material of the second channel layer 202 of the first device area 200a is silicon, and the Si channel technology is used for the NMOS transistor, which is beneficial to improving the performance of the NMOS transistor, that is, improving the carrier mobility of the NMOS transistor; the material of the first channel layer 201 of the second device area 200b is silicon germanium, and the SiGe channel technology is used for the PMOS transistor, which is beneficial to improving the performance of the PMOS transistor, that is, improving the carrier mobility of the PMOS transistor.

[0034] In other embodiments, the first-type transistor is used to form a PMOS transistor, and the second-type transistor is used to form an NMOS transistor; the material of the first channel layer includes silicon; and the material of the second channel layer includes silicon germanium.

[0035] In this embodiment, the substrate is a three-dimensional structure, comprising a substrate 200 and fins 280 disposed on the substrate 200 in separate first and second device regions 200a and 200b. In other embodiments, the substrate may also be a planar substrate. In this embodiment, the substrate 200 is a silicon substrate, and the fins 280 are made of the same material as the substrate 200, namely silicon.

[0036] In this embodiment, the semiconductor structure further includes an isolation layer 208 located on the substrate 200 where the fins 280 are exposed. The isolation layer 208 exposes the first channel structure layer 260 and the second channel structure layer 270. The isolation layer is used to isolate adjacent fins 280. The isolation layer 208 is also used to isolate the gate structure 225 from the substrate 200.

[0037] In this embodiment, the isolation layer 208 is made of silicon nitride.

[0038] In this embodiment, the semiconductor structure further includes a sidewall spacer 213 . The sidewall spacer 213 is located on the top of the substrate and covers the side of the gate structure 225 .

[0039] The sidewall spacer 213 may be a single-layer structure or a stacked-layer structure, and the material of the sidewall spacer 213 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacer 213 is a single-layer structure, and the material of the sidewall spacer 213 is silicon nitride.

[0040] In this embodiment, the first channel structure layer 260 extending along the second direction is located on the substrate of the second device area 200b. The first channel structure layer 260 includes one or more first channel layers 201 spaced apart in the longitudinal direction, and the bottommost first channel layer 201 is in contact with the substrate. The second direction is perpendicular to the first direction.

[0041] The first channel layer 201 is used to provide a conductive channel of the first-type transistor.

[0042] In this embodiment, the number of the first channel layers 201 is four. In other embodiments, the number of the first channel layers may be other numbers.

[0043] In this embodiment, the second channel structure layer 270 extending along the second direction is located on the substrate of the first device area 200a and is spaced apart from the substrate. The second channel structure layer 270 includes one or more spaced apart second channel layers 202 in the longitudinal direction, and the second channel layer 202 and the first channel layer 201 are staggered in the longitudinal direction.

[0044] The second channel layer 202 is used to provide a conductive channel of the second-type transistor.

[0045] In this embodiment, the number of the second channel layers 202 is four. In other embodiments, the number of the second channel layers may be other numbers.

[0046] In this embodiment, the second channel layer 202 and the first channel layer 201 are staggered in the longitudinal direction, which means that along the first direction, the second channel layer 202 corresponds to the gap between the adjacent first channel layer 201, or the first channel layer 201 corresponds to the gap between the adjacent second channel layer 202, or the first channel layer 201 corresponds to the gap between the second channel layer 202 and the fin 280.

[0047] The second channel layer 202 and the first channel layer 201 are staggered in the vertical direction. Therefore, during the formation of the semiconductor structure, the same channel stack can be formed on the substrate of the first device area 200a and the second device area 200b. Each channel stack includes a first channel layer 201 and a second channel layer 202 located on the first channel layer 201. It is only necessary to remove the first channel layer 201 in the first device area 200a and the second channel layer 202 in the second device area 200b respectively. This reduces the process difficulty of forming the first channel layer 201 and the second channel layer 202 and improves the process efficiency.

[0048] In this embodiment, the first channel structure layer 260 and the second channel structure layer 270 are both located on the fin 280 .

[0049] In this embodiment, the dielectric wall 207 extending along the second direction is located on the substrate at the junction of the first device region 200 a and the second device region 200 b and covers the sidewalls of the first channel structure layer 260 and the second channel structure layer 270 .

[0050] Along the first direction, the dielectric wall 207 serves to isolate the first channel structure layer 260 and the second channel structure layer 270, as well as the gate structure 225. The dielectric wall 207 is used to isolate the first-type transistor and the second-type transistor, which is conducive to achieving a smaller spacing between the first-type transistor and the second-type transistor.

[0051] In this embodiment, the dielectric wall 207 is also located between the fins 280 of the first device region 200 a and the second device region 200 b , so as to isolate the fins 280 of the first device region 200 a and the second device region 200 b .

[0052] To this end, the dielectric wall 207 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boronitride and carbonitride, to ensure that the dielectric wall 207 can perform an isolation function. In this embodiment, the dielectric wall 207 is made of silicon nitride.

[0053] As an example, a top surface of the dielectric wall 207 is higher than a top surface of the second channel structure layer 270 .

[0054] In this embodiment, the first gate dielectric layer 290 is located in the first device region 200 a , and the first gate dielectric layer 290 covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the second channel layer 202 .

[0055] The first gate dielectric layer 290 is mainly used to electrically isolate the second channel structure layer 270 from the gate structure 225 .

[0056] In this embodiment, the first gate dielectric layer 290 includes a first gate oxide layer 218 and a high-k gate dielectric layer 222 conformally covering the first gate oxide layer 218 .

[0057] The material of the high-k gate dielectric layer 222 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 222 can be selected from one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and Al2O3.

[0058] In this embodiment, the first gate dielectric layer 290 also covers the top of the isolation layer 208 of the first device region 200 a and the sidewalls of the spacer 213 .

[0059] In this embodiment, the first gate dielectric layer 290 includes a first gate oxide layer 218. As an example, the material of the first gate oxide layer 218 is silicon oxide.

[0060] In this embodiment, the thickness of the first gate oxide layer 218 is 5 angstroms to 15 angstroms.

[0061] It should be noted that the thickness of the first gate oxide layer 218 should not be too large or too small. If the thickness of the first gate oxide layer 218 is too large, it will occupy too much space between the adjacent second channel layers 202. In the process of forming the gate structure 225, it is easy to cause the aspect ratio of the gap between the adjacent second channel layers 202 to be too large, thereby increasing the difficulty of filling the various film layers of the gate structure 225; if the thickness of the first gate oxide layer 218 is too small, the electrical isolation effect between the second channel structure layer 270 and the gate structure is reduced. For this reason, in this embodiment, the thickness of the first gate oxide layer 218 is 5 angstroms to 15 angstroms. For example, the thickness of the first gate oxide layer 218 is 7 angstroms, 10 angstroms or 12 angstroms.

[0062] In this embodiment, the second gate dielectric layer 291 is located in the second device region 200 b , and the second gate dielectric layer 291 covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the first channel layer 201 .

[0063] The second gate dielectric layer 291 is mainly used to electrically isolate the first channel structure layer 260 from the gate structure 225 .

[0064] In this embodiment, the second gate dielectric layer 291 includes a second gate oxide layer 250 and a high-k gate dielectric layer 222 conformally covering the second gate oxide layer 250 .

[0065] The material of the high-k gate dielectric layer 222 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 222 can be selected from one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and Al2O3.

[0066] In this embodiment, the second gate dielectric layer 291 includes a second gate oxide layer 250. As an example, the material of the second gate oxide layer 250 is silicon oxide.

[0067] In this embodiment, the second gate dielectric layer 291 also covers the top of the isolation layer 208 of the second device region 200 b and the sidewalls of the spacer 213 .

[0068] It should be noted that, in other embodiments, the semiconductor structure further includes: a channel transition layer located in the second device region and between the second gate oxide layer and the first channel layer. In the process of forming the second gate oxide layer, the second gate oxide layer is formed by performing a second oxidation treatment on the channel transition layer. Therefore, when a portion of the channel transition layer is oxidized to form the second gate oxide layer, the remaining thickness of the channel transition layer will remain.

[0069] In this embodiment, the channel transition layer has been completely consumed in the process of forming the second gate oxide layer 250 . Therefore, the semiconductor structure does not contain the channel transition layer.

[0070] The channel transition layer can improve the interface state between the surface of the first channel structure layer and the second gate oxide layer, and can improve the reliability of the semiconductor structure.

[0071] The material of the channel transition layer includes Si, Si (1-X) Ge x and one or more of SiC.

[0072] The material of the channel transition layer and the material of the first channel structure layer have a certain etching selectivity ratio. Wherein, X represents the atomic percentage content of Ge, and the Ge concentration is in the range of 0.3 to 0.7.

[0073] In this embodiment, the gate structure 225 is located on the top of the substrate and spans the first channel structure layer 260, the second channel structure layer 270 and the dielectric wall 207. The gate structure 225 covers part of the top of the first channel structure layer 260, the dielectric wall 207 and the second channel structure layer 270, and surrounds the first gate dielectric layer 290 and the second gate dielectric layer 291.

[0074] When the device is in operation, the gate structure 225 is used to control the opening or closing of the conductive channels of the first-type transistor and the second-type transistor.

[0075] In this embodiment, the gate structure 225 is a metal gate structure.

[0076] In this embodiment, the gate structure includes a work function layer 223 .

[0077] The work function layer 223 is used to adjust the threshold voltage of the first type transistor or the second type transistor. In this embodiment, the material of the work function layer 223 includes one or more of TiAl, Mo, MoN, AlN, TiN, TaN, TaSiN, TaAlN, TiAlN and TiAlC. The specific material and film structure of the work function layer 223 are determined according to the performance of the first type transistor or the second type transistor.

[0078] Specifically, the first-type transistor is an NMOS transistor, the work function layer 223 of the first device region 200a is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. The second-type transistor is a PMOS transistor, the work function layer 223 of the second device region 200b is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN.

[0079] In this embodiment, the metal gate structure includes a gate electrode layer 224 .

[0080] The gate electrode layer 224 is used for subsequent electrical connection to external structures. The material of the gate electrode layer 224 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0081] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 212 , and the interlayer dielectric layer 212 covers the sidewalls of the spacer 213 .

[0082] The interlayer dielectric layer 212 is used to isolate adjacent devices. The material of the interlayer dielectric layer 212 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 212 is silicon oxide.

[0083] Figures 7 to 23 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0084] refer to Figure 7 , providing a substrate, the substrate including a first device region 100a for forming a first type transistor and a second device region 100b for forming a second type transistor, the first device region 100a and the second device region 100b being arranged in a first direction (such as Figure 7 One or more longitudinally stacked channel stacks 103 are formed on the substrate, and each channel stack 103 includes a first channel layer 101 and a second channel layer 102 located on the first channel layer 101. The second channel layer 102 is used to provide a channel for the first-type transistor, and the first channel layer 101 is used to provide a channel for the second-type transistor, and the channel materials of the first-type transistor and the second-type transistor are different.

[0085] The substrate is used to provide a process platform for the manufacturing process.

[0086] In the step of providing a substrate, the first-type transistor and the second-type transistor have different channel conductivity types. Specifically, the first-type transistor is N-type and the second-type transistor is P-type.

[0087] In this embodiment, the first-type transistor is used to form an NMOS transistor, and the second-type transistor is used to form a PMOS transistor; the material of the first channel layer 101 includes silicon germanium; and the material of the second channel layer 102 includes silicon.

[0088] It should be noted that the material of the second channel layer 102 of the first device area 100a is silicon, and the Si channel technology is used for the NMOS transistor, which is beneficial to improving the performance of the NMOS transistor, that is, improving the carrier mobility of the NMOS transistor; the material of the first channel layer 101 of the second device area 100b is silicon germanium, and the SiGe channel technology is used for the PMOS transistor, which is beneficial to improving the performance of the PMOS transistor, that is, improving the carrier mobility of the PMOS transistor.

[0089] In some other embodiments, the first-type transistor is used to form a PMOS transistor, and the second-type transistor is used to form an NMOS transistor; the material of the first channel layer includes silicon; and the material of the second channel layer includes silicon germanium.

[0090] It should be noted that in other embodiments, the first channel layer may also be made of other materials that can meet the performance requirements of the second-type transistor. Similarly, the second channel layer may also be made of other materials that can meet the performance requirements of the first-type transistor, and there is an etching selectivity ratio between the materials of the first channel layer and the second channel layer.

[0091] In this embodiment, the substrate is a three-dimensional structure, comprising a substrate 100 and fins 180 disposed on the substrate 100 in separate first and second device regions 100a and 100b. In other embodiments, the substrate may also be a planar substrate. In this embodiment, the substrate 100 is a silicon substrate, and the fins 180 are made of the same material as the substrate 100, namely silicon.

[0092] Accordingly, in this embodiment, the channel stacks 103 are formed on the fins 180 , and the channel stacks 103 extend in the same direction as the fins 180 . The stacking direction of the plurality of channel stacks 103 is perpendicular to the surface of the substrate 100 .

[0093] In this embodiment, the channel stack 103 is arranged along the second direction (eg Figure 7 It should be noted that the second direction refers to a direction parallel to the horizontal direction and perpendicular to the first direction.

[0094] The channel stack 103 provides a process basis for subsequently forming a channel layer with suspended spacing.

[0095] As an example, the number of the channel stacks 103 is four. In other embodiments, the number of the channel stacks can be other numbers.

[0096] In this embodiment, the second channel layer 102 of the first device area 100a is used to provide a conductive channel for the first type transistor. Therefore, for the first device area 100a, the first channel layer 101 is used as a first sacrificial layer, that is, the first channel layer 101 is used to support the second channel layer 102. After the first channel layer 101 of the first device area 100a is subsequently removed, the second channel layer 102 can be suspended at intervals. The first channel layer 101 of the first device area 100a also occupies space for the subsequent formation of a gate structure.

[0097] In this embodiment, the first channel layer 101 of the second device region 100b is used to provide a conductive channel for the second-type transistor. Therefore, for the second device region 100b, the second channel layer 102 is used as a second sacrificial layer, that is, the second channel layer 102 is used to support the first channel layer 101. After the second channel layer 102 of the second device region 100b is subsequently removed, the first channel layer 101 can be suspended in an interval. The second channel layer 102 of the second device region 100b also occupies space for the subsequent formation of a gate structure.

[0098] In this embodiment, in the step of providing the substrate, the number of the first channel layers 101 and the number of the second channel layers 102 are the same.

[0099] In this embodiment, during the step of providing the substrate, a hard mask layer 105 is further formed on top of the channel stack 103. The hard mask layer 105 is used as a patterning mask when forming the channel stack 103 and the fin 180. In this embodiment, the material of the hard mask layer 105 is silicon nitride.

[0100] In this embodiment, the formation method further includes forming a filling layer 104 on top of the substrate where the trench stack 103 is exposed, wherein the filling layer 104 covers the sidewalls of the trench stack 103 and the hard mask layer 105. The filling layer 104 protects the top of the substrate during the subsequent formation of the dielectric wall.

[0101] In this embodiment, the filling layer 104 is made of a dielectric material so that the filling layer 104 can be used to form an isolation layer later, thereby simplifying the process steps.

[0102] In this embodiment, the material of the filling layer 104 is silicon oxide.

[0103] refer to Figures 8 and 9 At the junction of the first device region 100a and the second device region 100b, a channel is formed in the channel stack 103 that penetrates the channel stack 103 and extends along the second direction (eg Figure 9 The dielectric wall 107 extends in the first direction (as shown in the Y direction). Figure 9 The channel stacks 103 in the first device region 100a and the second device region 100b are separated in the X direction, and the first direction is perpendicular to the second direction.

[0104] Along the first direction, the dielectric wall 107 can isolate the channel stack 103 between the first device region 100a and the second device region 100b. The dielectric wall 107 is used to isolate the first-type transistor and the second-type transistor, which is conducive to achieving a smaller spacing between the first-type transistor and the second-type transistor.

[0105] In this embodiment, the dielectric wall 107 is also located between the fins 180 of the first device region 100a and the second device region 100b, and is also used to isolate the fins 180 of the first device region 100a and the second device region 100b, and can ensure that the channel stacks 103 of the first device region 100a and the second device region 100b can be completely isolated, thereby improving the isolation effect of the dielectric wall 107 on the adjacent channel stacks 103 of the first device region 100a and the second device region 100b.

[0106] To this end, the dielectric wall 107 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbon boron nitride, thereby ensuring that the dielectric wall 107 can function as an isolation device. In this embodiment, the dielectric wall 107 is made of silicon carbon boron nitride.

[0107] As an example, the top surface of the dielectric wall 107 is higher than the top surface of the channel stack 103, which is beneficial to improving the isolation effect of the dielectric wall 107 on the adjacent channel stack 103 and also beneficial to improving the isolation effect of the dielectric wall 107 on the subsequent source and drain doping layers.

[0108] In this embodiment, the steps of forming the dielectric wall 107 include: Figure 8 As shown, the channel stack 103 at the junction of the first device region 100a and the second device region 100b is removed to form a groove 106 penetrating the channel stack 103; Figure 9As shown, a dielectric material layer (not shown) is formed in the groove 106, and the dielectric material layer also covers the top of the filling layer 104. The dielectric material layer above the top of the filling layer 104 is removed, and the remaining dielectric material layer located in the groove 106 serves as the dielectric wall 107.

[0109] Specifically, the top of the hard mask layer 105 is used as the stop position of the planarization process to remove the dielectric material layer above the top of the filling layer 104 .

[0110] refer to Figure 10 After forming the dielectric wall 107 , the method further includes: etching back a portion of the thickness of the filling layer 104 to form an isolation layer 108 covering the sidewalls of the fin 180 , wherein the isolation layer 108 exposes the channel stack 103 .

[0111] The isolation layer 108 is used to isolate adjacent fins 180 and is also used to isolate the substrate 100 from a subsequently formed gate structure. As an example, the isolation layer 108 is made of silicon oxide.

[0112] It should also be noted that after forming the isolation layer 108 , the process further includes: removing the hard mask layer 105 .

[0113] The hard mask layer 105 is removed to expose the top surface of the channel stack 103 , facilitating the subsequent formation of a dummy gate spanning the channel stack 105 and the dielectric wall 107 .

[0114] This embodiment uses the formation of the isolation layer 108 after forming the dielectric wall 107 as an example. In other embodiments, the isolation layer can also be formed after forming the channel stack and before forming the dielectric wall. Accordingly, during the step of forming the dielectric wall, the dielectric wall is also formed on the isolation structure between the fins of the first device region and the second device region.

[0115] refer to Figures 11 to 12 After forming the dielectric wall 107, a first protective layer 110 is formed in the second device region 100b to cover the top and sidewalls of the channel stack 103, and the first protective layer 110 exposes the channel stack 103 of the first device region 100a.

[0116] In this embodiment, a first protective layer 110 is formed in the second device area 100b to cover the top and sidewalls of the channel stack 103. That is, in the subsequent step of removing the first channel layer 101 of the first device area 100a, the first protective layer 110 can play a protective and isolating role for the channel stack 103 of the second device area 100b, so that the second channel layer 102 of the second device area 100b can be selectively removed subsequently.

[0117] In this embodiment, after forming the dielectric wall 107 and before subsequently forming the dummy gate, the first protection layer 110 is formed on the top and sidewalls of the channel stack 103 and the top of the substrate in the second device region 100 b .

[0118] It should be noted that forming the first protection layer 110 before subsequently forming the dummy gate can protect the top and sidewalls of the channel stack 103 during the subsequent process of removing the dummy gate to form a gate opening.

[0119] In other embodiments, the first protection layer may also be formed after forming the gate opening.

[0120] In this embodiment, the steps of forming the first protective layer 110 include: Figure 11 As shown, in the first device region 100a and the second device region 100b, a protective material layer 109 is formed to cover the top and sidewalls of the channel stack 103 and the top of the substrate; Figure 12 As shown, the protective material layer 109 in the first device region 100 a is removed, and the remaining protective material layer 109 in the second device region 100 b serves as the first protective layer 110 .

[0121] Specifically, a mask is used to selectively remove the protective material layer 109 in the first device region 100 a .

[0122] During the subsequent step of removing the first channel layer 101 of the first device region 100a, the first protective layer 110 can provide protection and isolation for the channel stack 103 of the second device region 100b. Specifically, the material of the first protective layer 110 has properties such as etching resistance and high hardness. To this end, the material of the first protective layer 110 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon oxycarbide. In this embodiment, the material of the first protective layer 110 is silicon nitride.

[0123] In this embodiment, the thickness of the first protective layer 110 is 10 angstroms to 30 angstroms.

[0124] It should be noted that the thickness of the first protective layer 110 should not be too large or too small. If the thickness of the first protective layer 110 is too large, it will easily occupy too much space for the dummy gate formed subsequently; if the thickness of the first protective layer 110 is too small, during the subsequent step of removing the first channel layer 101 of the first device region 100a, the protective effect of the first protective layer 110 on the channel stack of the second device region 100b will be reduced, thereby affecting the electrical performance of the second-type transistor formed subsequently. To this end, in this embodiment, the thickness of the first protective layer 110 is 10 angstroms to 30 angstroms. For example, the thickness of the first protective layer 110 is 15 angstroms, 20 angstroms, or 25 angstroms.

[0125] In this embodiment, the process of forming the protective material layer 109 includes an atomic layer deposition process.

[0126] The atomic layer deposition process includes multiple atomic layer deposition cycles, which is beneficial for improving the thickness uniformity of the first protective layer 110 and enabling the first protective layer 110 to cover the top and sidewalls of the channel stack 103. In other embodiments, the first protective layer can also be formed using a chemical vapor deposition (CVD) process.

[0127] In this embodiment, the process of removing the protective material layer 109 in the first device region 100 a includes a dry etching process.

[0128] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has anisotropic etching characteristics, so its longitudinal etching rate is much greater than its lateral etching rate. While achieving fairly accurate pattern transfer, it is also beneficial for ensuring the sidewall morphology quality of the channel stack 103 in the first device region 100a and for ensuring that the first protective layer 110 can completely cover the channel stack 103 in the first device region 100a.

[0129] refer to Figure 13 After forming the first protection layer 110 and before subsequently forming the dummy gate, the method further includes: forming a dummy gate oxide layer 111 covering the top and sidewalls of the channel stack 103 in the first device region 100a.

[0130] The dummy gate oxide layer 111 protects the top and sidewalls of the channel stack 103 in the first device region 100 a during the subsequent process of removing the dummy gate and forming a gate opening, thereby reducing the probability of damage to the channel stack 103 .

[0131] The material of the dummy gate oxide layer 111 includes one or more of silicon oxide, silicon oxynitride, and silicon oxycarbon nitride. In this embodiment, the material of the dummy gate oxide layer 111 is silicon oxide.

[0132] In order for the dummy gate oxide layer 111 to better protect the top and sidewalls of the channel stack 103 of the first device region 100 a , in this embodiment, the thickness of the dummy gate oxide layer 111 is 10 angstroms to 30 angstroms.

[0133] In this embodiment, an oxidation process is used to form the dummy gate oxide layer 111. The dummy gate oxide layer 111 is formed after the first protective layer 110 is formed. The first protective layer 110 covers the channel stack 103 of the second device region 100b, so that the dummy gate oxide layer 111 is formed only in the first device region 100a. This eliminates the need for patterning the dummy gate oxide layer 111, thereby simplifying the process steps.

[0134] refer to Figure 14 A dummy gate 115 is formed across the channel stack 103 and the dielectric wall 107 , and the dummy gate 115 covers a portion of the top and a portion of the sidewall of the channel stack 103 .

[0135] The dummy gate 115 occupies a space for forming a gate structure subsequently.

[0136] In this embodiment, the dummy gate 115 spans the channel stack 103 and the dielectric wall 107, that is, the dummy gate 115 covers part of the top of the channel stack 103 and the dielectric wall 107, part of the sidewall of the dielectric wall 107, and part of the sidewall of the channel stack 103 opposite to the dielectric wall 107.

[0137] In this embodiment, the dummy gate 115 includes a dummy gate layer. The material of the dummy gate layer includes polysilicon.

[0138] In this embodiment, the dummy gate 115 is a strip-shaped structure. The dummy gate 115 is arranged along a first direction (eg, Figure 14 The X direction is shown in FIG.

[0139] In this embodiment, after forming the dummy gate 115 , the forming method further includes: forming a spacer 113 on a sidewall of the dummy gate 115 .

[0140] The sidewall spacers 113 are used to protect the sidewalls of the subsequently formed gate structure. The sidewall spacers 113 may be a single-layer structure or a stacked-layer structure, and the material of the sidewall spacers 113 may include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacers 113 are a single-layer structure, and the material of the sidewall spacers 113 is silicon nitride.

[0141] In this embodiment, after forming the sidewall spacer 113, the formation method further includes forming source and drain doping layers (not shown) in the channel stack 103 on both sides of the dummy gate 115. The conductivity type of the doped ions in the source and drain doping layers is the same as the conductivity type of the channel of the transistor in the region in which they are located. The detailed description of the source and drain doping layers is omitted here.

[0142] In this embodiment, the forming method further includes: forming an interlayer dielectric layer 112 on top of the isolation layer 108 where the dummy deletion 115 and the sidewall spacer 113 are exposed, and the interlayer dielectric layer 112 covers the sidewalls of the sidewall spacer 113 .

[0143] The interlayer dielectric layer 112 is used to isolate adjacent devices. The material of the interlayer dielectric layer 112 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 112 is silicon oxide.

[0144] Continue to refer Figure 14 As an example, a gate mask layer 114 is further formed on the top of the dummy gate 115 .

[0145] The gate mask layer 114 serves as an etching mask when forming the dummy gate 115. It also protects the top of the dummy gate 115 during the formation of the spacers 113 and the interlayer dielectric layer 112, thereby reducing the probability of damage to the top of the dummy gate 115. Accordingly, the spacers 113 also cover the sidewalls of the gate mask layer 114.

[0146] refer to Figure 15 , the dummy gate 115 is removed to form a gate opening 116 .

[0147] The gate opening 116 is used to provide a space for the subsequent formation of a gate structure.

[0148] Moreover, after the dummy gate 115 is removed, the gate opening 116 exposes the dummy gate oxide layer 111 and the first protection layer 110 , which facilitates the subsequent removal of the dummy gate oxide layer 111 and the first protection layer 110 through the gate opening 116 .

[0149] Specifically, the process of removing the dummy gate 115 includes one or both of a dry etching process and a wet etching process.

[0150] refer to Figures 16 and 17 Using the first protection layer 110 as a mask, in the first device region 100 a , the first channel layer 101 exposed by the gate opening 116 is removed to form a first through groove 117 communicating with the gate opening 116 .

[0151] The first through groove 117 and the gate opening 116 of the first device region 100 a provide space for the subsequent formation of a gate structure.

[0152] In the first device region 100 a , the first channel layer 101 exposed by the gate opening 116 is removed, and the remaining second channel layer 102 is used to provide a conductive channel when the first-type transistor is in operation.

[0153] The first through groove 117 is surrounded by the adjacent second channel layer 102 , or by the second channel layer 102 and the substrate.

[0154] In this embodiment, after the first through groove 117 is formed, the Figure 17 The second channel layer 102 is suspended in the gate opening 116, providing a process basis for the subsequently formed gate structure to surround the second channel layer 102 of the first device region 100a.

[0155] In this embodiment, the process of removing the first channel layer 101 of the first device region 100 a to form the first through groove 117 includes a wet etching process.

[0156] It should be noted that a wet etching process is used to remove the first channel layer 101. The wet etching process is an isotropic process that has a high etching rate, is simple to operate, and has low process costs. The material of the first channel layer 101 is SiGe, and the etching solution used in the corresponding wet etching process is a hydrogen chloride solution.

[0157] refer to Figure 16 In the step of forming the first through groove 117 , before removing the first channel layer 101 in the channel stack 103 exposed in the first device region 100 a , the method further includes: removing the dummy gate oxide layer 111 .

[0158] The dummy gate oxide layer 111 is removed to expose the top and sidewalls of the channel stack 103 of the first device region 100 a , so as to facilitate the removal of the exposed first channel layer 101 during the process of forming the first through-grooves 117 .

[0159] refer to Figure 18 After forming the first through-groove 117 , a second protection layer 118 is formed in the first device region 100 a to cover the gate opening 116 and the second channel layer 102 exposed by the first through-groove 117 .

[0160] The second protective layer 118 is used to protect the surface of the second channel layer 102 exposed in the first device area 100a during the subsequent removal of the second channel layer 102 in the second device area 100b, thereby reducing the probability of damage to the surface of the second channel layer 102 exposed in the first device area 100a.

[0161] Therefore, in this embodiment, a first protective layer 110 is formed in the second device region 100b to cover the top and sidewalls of the channel stack 103, that is, in the step of removing the first channel layer 101 of the first device region 100a, the first protective layer 110 can play a protective and isolating role for the channel stack 103 of the second device region 100b, and then a second protective layer 118 is formed in the first device region 100a to conformally cover the second channel layer 102, that is, in the step of removing the second channel layer 102 of the second device region 100b, the second protective layer 102 can play a role of an etching mask, and accordingly, the first channel layer 101 in the first device region 100a and the second channel layer 102 in the second device region 100b can be removed respectively, so that the first channel layer 101 and the second channel layer 102 can respectively meet the carrier mobility requirements of the second-type transistor and the first-type transistor, so as to respectively meet the performance requirements of the second-type transistor and the first-type transistor, thereby improving the performance of the semiconductor structure.

[0162] In this embodiment, the step of forming the second protective layer 118 includes: in the first device area 100a, performing a first oxidation treatment on the second channel layer 102 exposed by the gate opening 116 and the first through groove 117 to form a first gate oxide layer covering each surface of the second channel layer 102, and the first gate oxide layer is used as the second protective layer 118.

[0163] The first gate oxide layer is used as a part of the gate dielectric layer of the subsequent first device region 100a. By using the first gate oxide layer as the second protective layer 118, the step of forming an additional second protective layer is omitted, and the process steps are correspondingly simplified.

[0164] Moreover, a first protective layer 110 is formed in the second device area 100b. Therefore, during the first oxidation treatment, the second protective layer 118 can be selectively formed on the exposed surface of the second channel layer 102, that is, selectively formed on the surface of the second channel layer 102 exposed by the gate opening 116 and the first through groove 117, which correspondingly reduces the process complexity of forming the second protective layer 118.

[0165] In this embodiment, the thickness of the second protection layer 118 is 10 angstroms to 50 angstroms.

[0166] It should be noted that the thickness of the second protective layer 118 should not be too large or too small. If the second protective layer 118 is too thick, it will occupy too much space in the first through-slot 117. This will easily lead to an excessively large aspect ratio of the remaining space in the first through-slot 117 during the subsequent formation of the gate structure, thereby increasing the difficulty of filling the various film layers of the gate structure. Furthermore, when the second protective layer 118 is formed by performing a first oxidation treatment on the second channel layer 102, an excessively large thickness of the second protective layer 118 can also lead to excessive consumption of the second channel layer 102, thereby affecting the size of the second channel layer 102 and, in turn, the performance of the first transistor. If the second protective layer 118 is too thin, the protective effect of the second channel layer 102 in the first device region 100a will be reduced during the subsequent removal of the second channel layer 102 in the second device region 100b, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the second protective layer 118 is 10 angstroms to 50 angstroms. For example, the thickness of the second protection layer 118 is 20 angstroms, 30 angstroms, or 40 angstroms.

[0167] The material of the second protective layer 118 includes one or more of silicon oxide, silicon oxynitride, and silicon oxycarbon nitride. In this embodiment, the material of the second protective layer 118 is silicon oxide.

[0168] It should be noted that, in other embodiments, the process for forming the second protective layer may also be an atomic layer deposition process.

[0169] refer to Figures 19 to 20 Using the second protection layer 118 as a mask, in the second device region 100 b , the first protection layer 110 and the second channel layer 102 exposed by the gate opening 116 are removed to form a second through groove 119 communicating with the gate opening 116 .

[0170] The second through groove 119 and the gate opening 116 of the second device region 100 b provide space for the subsequent formation of a gate structure.

[0171] In the second device region 100 b , the second channel layer 102 exposed by the gate opening 116 is removed, and the remaining first channel layer 101 is used to provide a conductive channel when the second-type transistor is in operation.

[0172] The second through groove 119 is surrounded by the adjacent first channel layer 101 and the dielectric wall 107 .

[0173] In this embodiment, after the second through groove 119 is formed, Figure 20The second channel layer 119 is suspended in the gate opening 116, providing a process basis for the subsequently formed gate structure to surround the first channel layer 101 of the second device region 100b.

[0174] In this embodiment, the process of removing the first protective layer 110 includes a dry etching process.

[0175] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has anisotropic etching characteristics, so its longitudinal etching rate is much greater than its lateral etching rate. While achieving fairly accurate pattern transfer, it is also beneficial to ensure the sidewall morphology quality of the channel stack 103 in the second device region 100b.

[0176] In this embodiment, the process of removing the second channel layer 102 of the second device region 100 b to form the second through groove includes a wet etching process.

[0177] It should be noted that a wet etching process is used to remove the second channel layer 102 of the second device region 100b. The wet etching process is an isotropic process, which has a high etching rate, simple operation, and low process cost. The material of the second channel layer 102 is Si, and the etching solution used in the corresponding wet etching process is a tetramethylammonium hydroxide (TMAH) solution.

[0178] refer to Figure 21 After forming the second through groove 119 and before subsequently forming the second gate oxide layer, the method further includes: forming a channel transition layer 120 in the second device region 100 b to conformally cover each surface of the first channel layer 101 .

[0179] The channel transition layer 120 can improve the interface state between the surface of the first channel layer 101 and the second gate oxide layer formed subsequently, and can also improve the reliability of the semiconductor structure.

[0180] In this embodiment, the process of forming the channel transition layer 120 includes an atomic layer deposition process.

[0181] The atomic layer deposition process includes multiple atomic layer deposition cycles, which has good step filling capability, is conducive to improving the thickness uniformity of the channel transition layer 120, and enables the channel transition layer 120 to cover the top and sidewalls of the first channel layer 101. In other embodiments, the channel transition layer can also be formed using a chemical vapor deposition (CVD) process.

[0182] In this embodiment, in the step of forming the channel transition layer 120, the material of the channel transition layer 120 includes Si, Si (1-X) Ge x and one or more of SiC, wherein X represents the Ge atomic percentage content, and the Ge concentration is in the range of 0.3 to 0.7.

[0183] The material of the channel transition layer 120 is conducive to forming a second gate oxide layer covering various surfaces of the first channel layer 101 during the subsequent second oxidation process.

[0184] In this embodiment, in the step of forming the channel transition layer 120 , the thickness of the channel transition layer 120 is 20 angstroms to 200 angstroms.

[0185] It should be noted that the thickness of the channel transition layer 120 should not be too large or too small. If the thickness of the channel transition layer 120 is too large, it will occupy too much of the space of the second through-groove 119. In the subsequent process of forming the gate structure, it is easy to cause the aspect ratio of the remaining space of the second through-groove 119 to be too large, thereby increasing the difficulty of filling the various film layers of the gate structure. If the thickness of the channel transition layer 120 is too small, the thickness of the second gate oxide layer formed to cover the various surfaces of the first channel layer 101 during the second oxidation process will also be too small, thereby affecting the electrical isolation effect between the first channel layer 101 and the subsequently formed gate structure. To this end, in this embodiment, the thickness of the channel transition layer 120 is 20 angstroms to 200 angstroms. For example, the thickness of the channel transition layer 120 is 60 angstroms, 100 angstroms, or 150 angstroms.

[0186] It should be noted that, in other embodiments, the channel transition layer may not be formed according to process requirements.

[0187] refer to Figure 22 After forming the second through-groove 119 and before subsequently forming the gate structure, the method further includes: performing a second oxidation treatment on the first channel layer 101 exposed by the gate opening 116 and the second through-groove 119 to form a second gate oxide layer 150 covering each surface of the first channel layer 101.

[0188] The second gate oxide layer 150 serves as a part of the gate dielectric layer of the second device region 100 b . The second gate oxide layer 150 is mainly used to electrically isolate the first channel layer 101 from a subsequently formed gate structure.

[0189] In this embodiment, a channel transition layer 120 is formed on the surface of the first channel layer 101 . Therefore, in the step of performing the second oxidation treatment, the channel transition layer 120 is subjected to the second oxidation treatment to transform the channel transition layer 120 into the second gate oxide layer 150 .

[0190] In other embodiments, during the second oxidation step, a portion of the channel transition layer may be oxidized to form the second gate oxide layer. Accordingly, oxygen in the portion of the channel transition layer may be retained between the second gate oxide layer and the first channel layer.

[0191] refer to Figure 23 After forming the second gate oxide layer 150 , the forming method further includes: forming a high-k gate dielectric layer 122 in the gate opening 116 to conformally cover the first channel layer 101 and the second channel layer 102 .

[0192] Specifically, the high-k gate dielectric layer 122 conformally covers the first gate oxide layer and the second gate oxide layer 150 .

[0193] The first gate oxide layer and the high-k gate dielectric layer 122 constitute a first gate dielectric layer (not labeled) of the first device region 100a, and the second gate oxide layer 150 and the high-k gate dielectric layer 122 constitute a second gate dielectric layer (not labeled) of the second device region 100b.

[0194] The material of the high-k gate dielectric layer 122 is a high-k dielectric material, wherein a high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 122 can be selected from one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and Al2O3.

[0195] Continue to refer Figure 23 After forming the high-k gate dielectric layer 122, a gate structure 125 is formed in the gate opening 116, the first through-groove 117, and the second through-groove 119. The gate structure 125 surrounds the first channel layer 101 in the first device area 100a exposed by the dielectric wall 107, and the second channel layer 102 in the second device area 100b exposed by the dielectric wall 107.

[0196] Specifically, the gate structure 125 surrounds the first gate dielectric layer and the second gate dielectric layer.

[0197] When the device is in operation, the gate structure 125 is used to control the opening or closing of the conductive channels of the first-type transistor and the second-type transistor.

[0198] In this embodiment, the gate structure 125 is a metal gate structure.

[0199] As an example, the steps of forming the gate structure 125 include: forming a work function layer 123 in the gate opening 116 that conformally covers the high-k gate dielectric layer 122; forming a gate electrode layer 124 in the remaining space of the gate opening 116 that conformally covers the work function layer 123, and the gate electrode layer 124 spans the first channel layer 101 and the second channel layer 102.

[0200] It should be noted that the work function layer 123 in the first device region 100 a and the second device region 100 b can be formed in different steps.

[0201] The work function layer 123 is used to adjust the threshold voltage of the first-type transistor or the second-type transistor. In this embodiment, the material of the work function layer 123 includes one or more of TiAl, Mo, MoN, AlN, TiN, TaN, TaSiN, TaAlN, TiAlN, and TiAlC. The specific material and film structure of the work function layer 123 are determined according to the performance of the first-type transistor or the second-type transistor.

[0202] Specifically, the first-type transistor is an NMOS transistor, the work function layer 123 of the first device region 100a is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. The second-type transistor is a PMOS transistor, the work function layer 123 of the second device region 100b is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN.

[0203] The gate electrode layer 124 is used for subsequent electrical connection to external structures. The material of the gate electrode layer 124 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. In this embodiment, the material of the gate electrode layer 124 includes W.

[0204] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, wherein the first device region and the second device region are adjacent to each other in a first direction; a first channel structure layer extending along a second direction, located on the substrate of the second device region, the first channel structure layer including one or more first channel layers spaced apart in the longitudinal direction, with the bottommost first channel layer in contact with the substrate, and the second direction being perpendicular to the first direction; a second channel structure layer extending along the second direction, located on the substrate of the first device region and spaced apart from the substrate, the second channel structure layer including one or more spaced apart second channel layers in the longitudinal direction, and the second channel layers and the first channel layers being staggered in the longitudinal direction; a dielectric wall extending along the second direction, located on the substrate at the junction of the first device region and the second device region, and covering the sidewalls of the first channel structure layer and the second channel structure layer; a first gate dielectric layer, located in the first device region, the first gate dielectric layer covering a portion of the top, a portion of the sidewall, and a portion of the bottom of the second channel layer; a second gate dielectric layer, located in the second device region, the second gate dielectric layer covering a portion of the top, a portion of the sidewall, and a portion of the bottom of the first channel layer; A gate structure is located on the top of the substrate and spans the first channel structure layer, the second channel structure layer and the dielectric wall. The gate structure covers part of the top of the first channel structure layer, the dielectric wall and the second channel structure layer, and surrounds the first gate dielectric layer and the second gate dielectric layer.

2. The semiconductor structure according to claim 1, wherein The first gate dielectric layer includes a first gate oxide layer and a high-k gate dielectric layer conformally covering the first gate oxide layer; The second gate dielectric layer includes a second gate oxide layer and a high-k gate dielectric layer conformally covering the second gate oxide layer.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes a channel transition layer located in the second device region and between the second gate oxide layer and the first channel layer.

4. The semiconductor structure according to claim 3, wherein: The material of the channel transition layer includes Si, Si (1-X) Ge x and SiC; Wherein, X represents the Ge atomic percentage content, and the Ge concentration is in the range of 0.3 to 0.

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5. The semiconductor structure according to claim 1, wherein The first-type transistor and the second-type transistor have different channel conductivity types.

6. The semiconductor structure according to claim 1, wherein The first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor; the material of the first channel layer includes silicon germanium; the material of the second channel layer includes silicon; Alternatively, the first device region is used to form a PMOS transistor, and the second device region is used to form an NMOS transistor; The material of the first channel layer includes silicon; the material of the second channel layer includes silicon germanium.

7. The semiconductor structure according to claim 2, wherein: The material of the high-k gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the first gate oxide layer includes SiO2; The material of the second gate oxide layer includes SiO2.

8. The semiconductor structure according to claim 2, wherein: The thickness of the first gate oxide layer is 5 angstroms to 15 angstroms.

9. The semiconductor structure according to claim 1, wherein: The gate structure includes a metal gate structure; The metal gate structure includes a gate electrode layer, and a material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

10. The semiconductor structure according to claim 1, wherein: The base comprises: a substrate, a fin portion located on the substrate, and an isolation layer located on the substrate where the fin portion is exposed, wherein the isolation layer covers the sidewall of the fin portion; The first channel structure layer and the second channel structure layer are both located on the fin.

11. The semiconductor structure according to claim 10, wherein: The semiconductor structure further includes: a sidewall spacer, the sidewall spacer being located on the top of the substrate and covering the side of the gate structure; The first gate dielectric layer also covers the top of the isolation layer of the first device region and the sidewalls of the spacer; The second gate dielectric layer also covers the top of the isolation layer of the second device region and the sidewalls of the spacer.

12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate including a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, the first device region and the second device region being adjacent in a first direction, one or more longitudinally stacked channel stacks being formed on the substrate, each channel stack including a first channel layer and a second channel layer located on the first channel layer, the second channel layer being used to provide a channel for the first-type transistor, the first channel layer being used to provide a channel for the second-type transistor, and the channel materials of the first-type transistor and the second-type transistor being different; At the junction of the first device region and the second device region, a dielectric wall is formed in the channel stack, which penetrates the channel stack and extends along a second direction, wherein the dielectric wall separates the channel stack in the first device region and the second device region in the first direction, and the first direction is perpendicular to the second direction; forming a dummy gate across the trench stack and the dielectric wall, wherein the dummy gate covers a portion of the top and a portion of the sidewall of the trench stack; removing the dummy gate to form a gate opening; After forming the dielectric wall, forming a first protection layer covering the top and sidewalls of the trench stack in the second device region, wherein the first protection layer exposes the trench stack in the first device region; Using the first protection layer as a mask, in the first device region, removing the first channel layer exposed by the gate opening to form a first through-groove communicating with the gate opening; After forming the first through-groove, forming a second protection layer in the first device region to cover the gate opening and the second channel layer exposed by the first through-groove; Using the second protection layer as a mask, in the second device region, removing the first protection layer and the second channel layer exposed by the gate opening to form a second through-groove communicating with the gate opening; A gate structure is formed in the gate opening, the first through-groove and the second through-groove, and the gate structure surrounds the first channel layer in the first device region exposed by the dielectric wall and the second channel layer in the second device region exposed by the dielectric wall.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing a substrate, the first-type transistor and the second-type transistor have different channel conductivity types.

14. The method for forming a semiconductor structure according to claim 12, wherein: After forming the dielectric wall and before forming the dummy gate, in the second device region, the first protection layer is formed on the top and sidewalls of the channel stack and the top of the substrate.

15. The method for forming a semiconductor structure according to claim 12 or 14, wherein: In the second device region, the step of forming the first protective layer on the top and sidewalls of the channel stack and the top of the substrate includes: In the first device region and the second device region, forming a protective material layer covering the top and sidewalls of the channel stack and the top of the substrate; The protective material layer in the first device region is removed, and the remaining protective material layer in the second device region serves as the protective layer.

16. The method for forming a semiconductor structure according to claim 14, wherein: After forming the first protection layer and before forming the dummy gate, the method further includes: forming a dummy gate oxide layer covering the top and sidewalls of the channel stack in the first device region; In the step of forming the first through-grooves, before removing the first channel layer in the channel stack exposed in the first device region, the method further includes: removing the dummy gate oxide layer.

17. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the first protective layer, a material of the first protective layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide and silicon oxycarbide.

18. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming the second protective layer includes: in the first device area, performing a first oxidation treatment on the second channel layer exposed by the gate opening and the first through groove to form a first gate oxide layer covering each surface of the second channel layer, and the gate oxide layer is used as the second protective layer.

19. The method for forming a semiconductor structure according to claim 12, wherein: After forming the second through-grooves and before forming the gate structure, the method further includes: performing a second oxidation treatment on the gate opening and the first channel layer exposed by the second through-grooves to form a second gate oxide layer covering all surfaces of the first channel layer.

20. The method for forming a semiconductor structure according to claim 19, wherein: After forming the second through groove and before forming the second gate oxide layer, the method further includes: forming a channel transition layer in the second device region to conformally cover each surface of the first channel layer; In the step of performing the second oxidation treatment, the channel transition layer is subjected to the second oxidation treatment to oxidize the channel transition layer or a portion of the channel transition layer into the second gate oxide layer.

21. The method for forming a semiconductor structure according to claim 20, wherein: The process of forming the channel transition layer includes an atomic layer deposition process.

22. The method for forming a semiconductor structure according to claim 20, wherein: In the step of forming the channel transition layer, the material of the channel transition layer includes Si, Si (1-X) Ge x and one or more of SiC; wherein X represents the Ge atomic percentage content, and the Ge concentration is in the range of 0.3 to 0.

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23. The method for forming a semiconductor structure according to claim 20, wherein: In the step of forming the channel transition layer, the thickness of the channel transition layer is 20 angstroms to 200 angstroms.

24. The method for forming a semiconductor structure according to claim 12, wherein: The first-type transistor is used to form an NMOS transistor, and the second-type transistor is used to form a PMOS transistor; The material of the first channel layer includes silicon germanium; the material of the second channel layer includes silicon; Alternatively, the first-type transistor is used to form a PMOS transistor, and the second-type transistor is used to form an NMOS transistor; the material of the first channel layer includes silicon; and the material of the second channel layer includes silicon germanium.

25. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the first protective layer, the thickness of the first protective layer is 10 angstroms to 30 angstroms; In the step of forming the second protective layer, the thickness of the second protective layer is 10 angstroms to 50 angstroms.

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