Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a first dielectric layer on the sidewall of a word line at the junction of a storage cell region and an isolation region, on the top of a protective layer, and on the top of a gate insulating layer in the isolation region, the first dielectric layer also filling an opening in the isolation region; after forming the first dielectric layer, removing the first dielectric layer in the storage cell region and the first dielectric layer located on the top of the gate insulating layer in the isolation region, the remaining first dielectric layer being located in the opening in the isolation region; after removing the first dielectric layer in the storage cell region and the first dielectric layer located on the top of the gate insulating layer in the isolation region, removing the protective layer; after removing the protective layer, forming a barrier layer conformally covering the word line on the top of the substrate, the barrier layer also covering the top of the remaining first dielectric layer in the isolation region. The probability of dislocation of the bit line due to stress changes in a subsequent annealing process is reduced, thereby improving the performance of the semiconductor.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] At present, Flash memory, also known as flash memory, has become the mainstream of non-volatile memory (NVM). According to different structures, flash memory can be divided into two types: Nor Flash and NAND Flash. The main feature of flash memory is that it can keep the stored information for a long time without power supply, and it has the advantages of high integration, fast access speed, easy erasure and rewriting, so it has been widely used in many fields such as microcomputers and automation control.

[0003] Due to the advantages of NAND flash memory devices such as higher cell density, higher storage density, faster writing and erasing speeds, it has gradually become a more commonly used structure in flash memory and is currently mainly used in flash memory cards and MP3 players in digital cameras.

[0004] However, the performance of current NAND flash memory devices still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a substrate and a bit line protruding from the substrate, the substrate comprising a storage cell area and an isolation area located between adjacent storage cell areas; a gate insulating layer, located on the top of the bit line; an isolation layer, located on the top of the substrate where the bit line is exposed, and the isolation layer covers part of the side wall of the bit line; a word line, located on the top of the gate insulating layer and the isolation layer in the storage cell area, and the extension direction of the word line is perpendicular to the extension direction of the bit line, and the side wall of the word line and the top of the gate insulating layer and the top of the substrate form a groove; a first dielectric layer, located on the top of the isolation layer in the isolation area and filled between adjacent bit lines; a barrier layer, located in the isolation area and covering the side wall of the first dielectric layer; a side wall, covering the side wall of the word line at the junction of the storage cell area and the isolation area; a top dielectric layer, covering the metal silicide layer and the side wall, the top dielectric layer is also located in the groove, and the top dielectric layer seals the groove at the groove opening position and forms an air gap in the groove.

[0007] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a substrate and a bit line protruding from the substrate, a gate insulating layer being formed on the top of the bit line, an isolation layer being formed on the top of the substrate where the bit line is exposed, the isolation layer covering part of the side wall of the bit line, the adjacent gate insulating layers, the bit line and the isolation layer forming an opening, along the extension direction of the bit line, the substrate comprising a storage cell area and an isolation area located between the adjacent storage cell areas, a word line being formed on the top of the gate insulating layer and the isolation layer in the storage cell area, the extension direction of the word line being perpendicular to the extension direction of the bit line; in the storage cell area, a protective layer is formed on the top of the gate insulating layer and the isolation layer, the protective layer covering the top and side wall of the word line ; forming a first dielectric layer on the side walls of the word line at the junction of the storage cell area and the isolation area, the top of the protective layer, and the top of the gate insulating layer in the isolation area, and the first dielectric layer also fills the opening in the isolation area; after forming the first dielectric layer, removing the first dielectric layer in the storage cell area and the first dielectric layer in the isolation area that is higher than the gate insulating layer, and the remaining first dielectric layer is located in the opening in the isolation area; after removing the first dielectric layer in the storage cell area and the first dielectric layer in the isolation area that is higher than the gate insulating layer, removing the protective layer; after removing the protective layer, forming a barrier layer on the top of the substrate that conformally covers the word line, and the barrier layer also covers the top of the remaining first dielectric layer in the isolation area.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a protective layer is formed on the top of a gate insulating layer in a storage cell region, the protective layer covers the top and side walls of the word line; a first dielectric layer is formed on the side walls of the word line at the junction of the storage cell region and the isolation region, on the top of the protective layer, and on the top of the gate insulating layer in the isolation region, and the first dielectric layer also fills the opening in the isolation region; after forming the first dielectric layer, the first dielectric layer in the storage cell region and the first dielectric layer in the isolation region that is higher than the gate insulating layer are removed, and the remaining first dielectric layer is located in the opening in the isolation region; after removing the first dielectric layer in the storage cell region and the first dielectric layer in the isolation region that is higher than the gate insulating layer, the protective layer is removed, and after removing the protective layer, a barrier layer conformally covering the word line is formed on the top of the substrate, and the barrier layer also covers the top of the remaining first dielectric layer in the isolation region. The embodiment of the present invention fills the remaining space of the opening with a first dielectric layer before forming the barrier layer to occupy the space of the opening, so as to prevent the barrier layer from being formed in the opening. This helps to completely remove the barrier layer located in the isolation region in the subsequent process of removing the barrier layer at the top of the bit line. Accordingly, the probability of dislocation of the bit line due to stress changes in the subsequent annealing process is reduced, so that the quality of the bit line is guaranteed. Moreover, it helps to reduce the probability of morphological bending of the bit line due to stress changes in the subsequent annealing process. Accordingly, in the subsequent process of forming a plug at the top of the bit line, the probability of mutual alignment between the plug and the bit line is increased, and the probability of punch-through of the plug is reduced, thereby improving the performance of the semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figure 4 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0012] Figures 5 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed. Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 , Figure 1 (b) Yes Figure 1(a) A cross-sectional view along the AB direction, providing a substrate, the substrate comprising a substrate 10 and a bit line 13 protruding from the substrate 10, a gate insulating layer 11 being formed on the top of the bit line 13, an isolation layer 14 being formed on the top of the substrate 10 where the bit line 13 is exposed, the isolation layer 14 covering a portion of the side wall of the bit line 13, the adjacent gate insulating layer 11, the bit line 13 and the isolation layer 14 forming an opening 80, along the extension direction of the bit line 13, the substrate comprising a storage cell area 10a and an isolation area 10b located between the adjacent storage cell areas 10a, a word line 12 being formed on the top of the gate insulating layer 11 and the isolation layer 14 in the storage cell area 10a, the extension direction of the word line 12 being perpendicular to the extension direction of the bit line 13.

[0015] refer to Figure 2 , Figure 2 (b) Yes Figure 2 (a) A cross-sectional view along the AB direction, wherein a barrier layer 15 is formed on the top of the substrate to conformally cover the side walls and the top of the word line 12, and the barrier layer 15 also covers the bottom and the side walls of the opening 80 in the isolation region 10b, and the top of the gate insulating layer 11. After the barrier layer 15 is formed, a sidewall 16 is formed to conformally cover the top and the sidewall of the barrier layer 15, and the sidewall 16 also fills the remaining space in the opening 80 of the isolation region 10b.

[0016] refer to Figure 3 , Figure 3 (b) Yes Figure 3 (a) A cross-sectional view along the AB direction, in which the spacer layer 16 and the barrier layer 15 located on the top of the word line 12 are removed.

[0017] It is found that since the sidewall 16 is also filled in the remaining space of the opening 80 of the isolation region 10b, after removing the sidewall layer 16 and the barrier layer 15 located on the top of the word line 12, part of the sidewall layer 16 and the barrier layer 15 (such as Figure 3 In the subsequent annealing process, the barrier layer 15 is prone to generate stress, which in turn easily causes dislocation of the bit lines 13 on both sides of the barrier layer 15, thereby increasing the probability that the bit lines 13 will bend in shape due to stress changes in the subsequent annealing process. Correspondingly, in the subsequent process of forming a plug on the top of the bit line 13, the probability of the plug and the bit line 13 being aligned with each other is reduced, and the probability of the plug being punched through is increased, thereby affecting the performance of the semiconductor.

[0018] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a substrate and a bit line protruding from the substrate, a gate insulating layer formed on the top of the bit line, an isolation layer formed on the top of the substrate where the bit line is exposed, the isolation layer covering part of the side wall of the bit line, adjacent gate insulating layers, bit lines and isolation layers forming an opening, along the extension direction of the bit line, the substrate comprising a storage cell area and an isolation area located between adjacent storage cell areas, a word line formed on the top of the gate insulating layer and the isolation layer in the storage cell area, the extension direction of the word line being perpendicular to the extension direction of the bit line; in the storage cell area, a protective layer is formed on the top of the gate insulating layer and the isolation layer, the protective layer covering the top of the word line The invention relates to a method for forming a first dielectric layer on the side wall of the word line at the junction of the storage cell area and the isolation area, the top of the protective layer, and the top of the gate insulating layer of the isolation area, and the first dielectric layer is also filled in the opening of the isolation area; after forming the first dielectric layer, the first dielectric layer of the storage cell area and the first dielectric layer in the isolation area that is higher than the gate insulating layer are removed, and the remaining first dielectric layer is located in the opening of the isolation area; after removing the first dielectric layer of the storage cell area and the first dielectric layer in the isolation area that is higher than the gate insulating layer, the protective layer is removed; after removing the protective layer, a barrier layer is formed on the top of the substrate that conformally covers the word line, and the barrier layer also covers the top of the remaining first dielectric layer in the isolation area.

[0019] In the scheme disclosed in the embodiment of the present invention, before the step of forming the barrier layer, the first dielectric layer is first filled in the remaining space of the opening to occupy the space of the opening to prevent the barrier layer from being formed in the opening, so that in the subsequent process of removing the barrier layer on the top of the bit line, it is beneficial to completely remove the barrier layer located in the isolation area, and accordingly, the probability of dislocation of the bit line due to stress changes in the subsequent annealing process is reduced, so that the quality of the bit line is guaranteed, and it is also beneficial to reduce the probability of morphological bending of the bit line due to stress changes in the subsequent annealing process. Accordingly, in the subsequent process of forming a plug on the top of the bit line, the probability of mutual alignment between the plug and the bit line is increased, and the probability of punch-through of the plug is reduced, thereby improving the performance of the semiconductor.

[0020] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] Figure 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, wherein: Figure 4 (b) Yes Figure 4(a) Cross-sectional view along direction EF.

[0022] The semiconductor structure includes: a substrate, the substrate includes a substrate 200 and a bit line 206 protruding from the substrate 200, the substrate includes a storage cell area 200a and an isolation area 200b located between adjacent storage cell areas 200a; a gate insulating layer 201, located on the top of the bit line 206; an isolation layer 207, located on the top of the substrate 200 where the bit line 206 is exposed, and the isolation layer 207 covers a portion of the side wall of the bit line 206; a word line (not shown), located on the top of the gate insulating layer 201 and the isolation layer 207 in the storage cell area 200a, and the extension direction of the word line is perpendicular to the extension direction of the bit line 206; a metal silicide layer 290, located on the top of the word line, The side walls of the metal silicide layer 290, the side walls of the word lines and the top of the gate insulation layer 201 form a groove; the first dielectric layer 211 is located on the top of the isolation layer 207 in the isolation area 200b and fills between the adjacent bit lines 206; the barrier layer 214 is located in the isolation area 200b and covers the side walls of the first dielectric layer 211; the side walls 296 cover the side walls of the word lines at the junction of the storage cell area 200a and the isolation area 200b; the top dielectric layer 291 covers the metal silicide layer 290 and the side walls 296, the top dielectric layer 291 is also located in the groove, and the top dielectric layer 291 seals the groove at the groove opening position, and forms an air gap 292 in the groove.

[0023] In this embodiment, the first dielectric layer is located on the top of the isolation layer in the isolation region and fills between the adjacent bit lines to occupy the open space surrounded by the adjacent bit lines and the top of the isolation layer, so that in the subsequent process of removing the barrier layer 214 on the top of the bit line 206, it is beneficial to completely remove the barrier layer 214 located in the isolation region 200b. Accordingly, the probability of dislocation of the bit line 206 due to stress changes in the subsequent annealing process is reduced, so that the quality of the bit line is guaranteed, and it is also beneficial to reduce the probability of morphological bending of the bit line 206 due to stress changes in the subsequent annealing process. Accordingly, in the subsequent process of forming a plug on the top of the bit line 206, the probability of mutual alignment between the plug and the bit line 206 is improved, and the probability of plug punch-through is reduced, thereby improving the performance of the semiconductor.

[0024] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0025] The bit line 206 and the substrate 200 are an integrated structure, and the material of the bit line 206 is the same as that of the substrate. As an example, the material of the bit line 206 is silicon.

[0026] The isolation layer 207 is used to isolate the adjacent bit lines 206. To this end, the isolation layer 207 is a dielectric material. In this embodiment, the material of the isolation layer 207 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the isolation layer 207 is silicon oxide.

[0027] The gate insulating layer 201 is a tunnel oxide layer of the NAND flash memory device, and is used as an isolation layer between the floating gate layer 202 and the substrate 200, so as to prevent the electrons stored in the floating gate layer 202 from entering the substrate 200 during the data storage process, thereby reducing the loss of electrons, that is, the gate insulating layer 201 is suitable for preventing the data stored in the flash memory from being lost. The material of the gate insulating layer 201 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. In this embodiment, the material of the gate insulating layer 201 is silicon oxide.

[0028] In this embodiment, the word line of the storage cell area 200a includes a first gate stack structure 205, which includes a floating gate (FG) layer 202 located on the gate insulation layer 201, a gate dielectric layer 203 located on the floating gate layer 202, and a control gate (CG) layer 204 located on the gate dielectric layer 203.

[0029] The floating gate layer 202 is used to store electrons in the formed NAND flash memory device, so that the NAND flash memory device can store data. In this embodiment, the material of the floating gate layer 202 is polysilicon.

[0030] The gate dielectric layer 203 is used as a first gate dielectric layer. The gate dielectric layer 203 is used as an insulating layer between the floating gate layer 202 and the control gate layer 204. The material of the gate dielectric layer 203 includes one or both of silicon oxide and silicon nitride. In this embodiment, the gate dielectric layer 203 is an ONO (Oxide-Nitride-Oxide) structure, that is, the gate dielectric layer 203 includes a first silicon oxide layer, a first silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the first silicon nitride layer.

[0031] The control gate layer 204 is used as a part of a word line of a NAND flash memory device. In this embodiment, the material of the control gate layer 204 is polysilicon.

[0032] The word line at the junction of the storage cell region 200 a and the isolation region 200 b includes a second gate stack structure 263 . The second gate stack structure 263 includes a select gate (SG) located on the gate insulating layer 201 .

[0033] Specifically, the second gate stack structure 263 also includes a floating gate layer 202 located on the gate insulation layer 201, a gate dielectric layer 203 located on the floating gate layer 202, and a control gate layer 204 located on the gate dielectric layer 203, wherein the control gate layer 204 in the second gate stack structure 263 penetrates a partial area of ​​the gate dielectric layer 203 and contacts the top of the floating gate layer 202, and the floating gate layer 202 and the control gate layer 204 constitute a selection gate.

[0034] Through the selection gate, during the operation of the NAND flash memory device, the write and erase bits required for the operation can be selected. In this embodiment, the material of the selection gate includes polysilicon.

[0035] In this embodiment, the first dielectric layer 212 is located on the top of the isolation layer 207 in the isolation region 200 b and covers the sidewalls of the bit line 206 .

[0036] The material of the first dielectric layer 212 includes one or more of silicon oxide, silicon oxynitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0037] Silicon oxide, silicon oxynitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide have smaller thermal expansion coefficients and can generate smaller stress during the relevant annealing process, thereby reducing damage to the substrate 200 and the bit line 206 .

[0038] In this embodiment, the semiconductor structure also includes: a second dielectric layer 211, located in the isolation region 200b, the second dielectric layer 211 is located between the side wall of the first dielectric layer 212 and the side wall of the bit line 206 and the side wall of the gate insulation layer 201, and is also located between the bottom of the first dielectric layer 212 and the top of the isolation layer 207.

[0039] The second dielectric layer 211 also extends to cover the top of the gate insulating layer 201 in the isolation region 200 b.

[0040] In this embodiment, the top of the second dielectric layer 211 is flush with the top of the first dielectric layer 212 .

[0041] Specifically, the top of the second dielectric layer 211 is flush with the top of the first dielectric layer 212 , which is beneficial to provide a good flat surface.

[0042] In this embodiment, the material of the second dielectric layer 211 includes one or more of silicon oxide, silicon oxynitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0043] Silicon oxide, silicon oxynitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide have smaller thermal expansion coefficients and can generate smaller stresses in related annealing processes, thereby reducing damage to the substrate 200, the bit lines 206, and the word lines.

[0044] In this embodiment, the metal silicide layer 290 is located on the top of the word line, and the sidewalls of the metal silicide layer 290, the sidewalls of the word line and the top of the gate insulating layer 201 form a trench.

[0045] Among them, the metal silicide layer 290 is used to reduce the gate resistance of the NAND flash memory device, thereby improving the programming operation capability and efficiency of the NAND flash memory device, improving the repeated read and write capability of the NAND flash memory device, and improving the RC (Resistance Capacitance) delay, thereby improving the performance of the NAND flash memory device.

[0046] In this embodiment, the material of the metal silicide layer 290 is nickel silicon compound. In another embodiment, the material of the metal silicide layer can also be titanium silicon compound or cobalt silicon compound.

[0047] In this embodiment, the oxide layer 213 is located on the top of the substrate and covers the sidewalls of the word lines in the storage cell region 200 a and the sidewalls of the first dielectric layer 212 in the isolation region 200 b .

[0048] The oxide layer 213 protects the top and sidewalls of the word line, and reduces the probability of the related etching process causing damage to the word line during the formation process of removing the barrier layer 214 .

[0049] In this embodiment, the blocking layer 214 is located in the memory cell region 200 a and covers the sidewalls of the word lines.

[0050] The barrier layer 214 is used to enclose an air gap 292 with the top dielectric layer 291 .

[0051] Specifically, in order to avoid adverse effects on the performance of the NAND flash memory device, a dielectric material with high process compatibility is selected as the material of the barrier layer 214. To this end, the material of the barrier layer 214 can be one or more of silicon oxide, silicon nitride and silicon oxynitride. As an embodiment, the material of the barrier layer 214 is silicon nitride.

[0052] In this embodiment, the spacer 296 covers the sidewall of the word line at the junction of the memory cell region 200a and the isolation region 200b.

[0053] The spacer 296 is used to protect the sidewalls of the first gate stack structure and the second gate stack structure.

[0054] The sidewall spacer 296 may be a single-layer structure or a stacked structure, and the material of the sidewall spacer 296 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacer 296 is a single-layer structure, and the material of the sidewall spacer 240 is silicon oxide.

[0055] In this embodiment, the top dielectric layer 291 covers the metal silicide layer 290 and the oxide layer 213. The top dielectric layer 291 is also located in the groove, and the top dielectric layer 291 seals the groove at the groove opening position and forms an air gap 292 in the groove.

[0056] The top dielectric layer 291 is used to seal the top of the trench, thereby forming a sealed air gap 292 .

[0057] In this embodiment, the material of the top dielectric layer 291 is one or both of plasma enhanced tetraethoxysilane (PETEOS) and plasma enhanced silicon oxide (PEOX).

[0058] The air gap 292 is used as an air sidewall. Compared with the sidewall material, the dielectric constant of air is smaller, so the setting of the air sidewall can reduce the capacitance between adjacent word lines in the NAND flash memory device, thereby improving the crosstalk problem of the NAND flash memory device during the programming process and the repeated reading and writing capability of the NAND flash memory device.

[0059] Accordingly, the present invention also provides a method for forming a semiconductor structure, referring to Figures 5 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0060] refer to Figure 5 , Figure 5 (b) Yes Figure 5(a) A cross-sectional view along the CD direction, providing a substrate, the substrate comprising a substrate 100 and a bit line 106 protruding from the substrate 100, a gate insulating layer 101 being formed on the top of the bit line 106, an isolation layer 107 being formed on the top of the substrate 100 where the bit line 106 is exposed, the isolation layer 107 covering a portion of the side wall of the bit line 106, the adjacent gate insulating layer 101, the bit line 106 and the isolation layer 107 forming an opening 109, along the extension direction of the bit line 106, the substrate comprising a storage cell area 100a and an isolation area 100b located between the adjacent storage cell areas 100a, a word line (not shown) being formed on the top of the gate insulating layer 101 and the isolation layer 107 in the storage cell area 100a, the extension direction of the word line being perpendicular to the extension direction of the bit line 106.

[0061] The substrate 100 provides a process platform for the subsequent formation of a memory. Specifically, the formation method is used to form a flash memory. In this embodiment, the flash memory is a NAND Flash memory.

[0062] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0063] The bit line 106 and the substrate 100 are an integrated structure, and the material of the bit line 106 is the same as that of the substrate. As an example, the material of the bit line 106 is silicon.

[0064] In this embodiment, an isolation layer 107 is formed on the top of the substrate 100 where the bit line 106 is exposed, and the isolation layer 107 covers a portion of the sidewall of the bit line 106 .

[0065] The isolation layer 107 is used to isolate the adjacent bit lines 106. To this end, the isolation layer 107 is a dielectric material. In this embodiment, the material of the isolation layer 107 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the isolation layer 107 is silicon oxide.

[0066] The gate insulating layer 101 is a tunnel oxide layer of the NAND flash memory device, and is used as an isolation layer between the floating gate layer 102 and the substrate 100, so that when the memory is working, the tunneling effect is used to allow electrons to enter the floating gate 102 through the gate insulating layer 101, and in the data storage process, the electrons stored in the floating gate layer 102 are prevented from entering the substrate 100, thereby reducing the loss of electrons, that is, the gate insulating layer 101 is suitable for preventing the data stored in the flash memory from being lost. In this embodiment, the material of the gate insulating layer 101 is silicon oxide.

[0067] In this embodiment, the word line of the storage cell area 100a includes a first gate stack structure 105, which includes a floating gate (FG) layer 102 located on the gate insulation layer 101, a gate dielectric layer 103 located on the floating gate layer 102, and a control gate (CG) layer 104 located on the gate dielectric layer 103.

[0068] The floating gate layer 102 is used to store electrons in the formed NAND flash memory device, so that the NAND flash memory device can store data. In this embodiment, the material of the floating gate layer 102 is polysilicon.

[0069] The gate dielectric layer 103 is used as a first gate dielectric layer. The gate dielectric layer 103 is used as an insulating layer between the floating gate layer 102 and the control gate layer 104. The material of the gate dielectric layer 103 includes one or more of silicon oxide and silicon nitride. In this embodiment, the gate dielectric layer 103 is an ONO (Oxide-Nitride-Oxide) structure, that is, the gate dielectric layer 103 includes a first silicon oxide layer, a first silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the first silicon nitride layer.

[0070] The control gate layer 104 is used as a part of a word line of a NAND flash memory device. In this embodiment, the material of the control gate layer 104 is polysilicon.

[0071] In this embodiment, the word line at the junction of the storage cell region 100 a and the isolation region 100 b includes a second gate stack structure 163 , and the second gate stack structure 163 includes a select gate (SelectGate, SG) located on the gate insulation layer 101 .

[0072] Through the selection gate, the write and erase bits required for the operation can be selected during the operation of the NAND flash memory device. In this embodiment, the material of the selection gate is polysilicon.

[0073] It should be noted that, in order to reduce process steps, shorten manufacturing time, and save costs, the first gate stack structure 105 and the second gate stack structure 163 are formed in the same process step.

[0074] To this end, in this embodiment, the second gate stack structure 163 also includes a floating gate layer 102 located on the gate insulation layer 101, a gate dielectric layer 103 located on the floating gate layer 102, and a control gate layer 104 located on the gate dielectric layer 103; wherein, in the second gate stack structure 160, the gate dielectric layer 103 has an opening (not shown) exposing a portion of the floating gate layer 102, the control gate layer 104 is also located in the opening, the control gate layer 104 is in contact with the floating gate layer 102 through the opening, and the control gate layer 104 and the floating gate layer 102 are used to constitute the selection gate.

[0075] Specifically, the steps of forming the first gate stack structure 105 and the second gate stack structure 163 include: forming a first gate film on the gate insulating layer 101, and forming a gate dielectric film on the first gate film; etching the gate dielectric film corresponding to the selection gate position, and forming an opening in the gate dielectric film to expose a portion of the first gate film; after forming the opening, forming a second gate film on the gate dielectric film, and the second gate film is also formed in the opening; forming a hard mask layer 108 on the second gate film, and the hard mask layer 108 covers the first gate The second gate film corresponding to the position of the stacked structure 105 and the second gate stacked structure 163; using the hard mask layer 108 as an etching mask, the second gate film, the gate dielectric film, and the first gate film are etched in sequence to form a first gate stacked structure 105 composed of the floating gate layer 102, the gate dielectric layer 103 and the control gate layer 104 on the substrate 100 of the storage cell area 100a, and a second gate stacked structure 163 composed of the floating gate layer 102, the gate dielectric layer 103 and the control gate layer 104 on the substrate 100 of the isolation area 100b.

[0076] The first gate film is used to form a floating gate layer 102 , the gate dielectric film is used to form a gate dielectric layer 103 , and the second gate film is used to form a control gate layer 104 .

[0077] The hard mask layer 108 is used as an etching mask for forming the first gate stack structure 105 and the second gate stack structure 163. The hard mask layer 108 is also used to protect the top of the first gate stack structure 105 and the second gate stack structure 163 in subsequent processes. In this embodiment, the material of the hard mask layer 108 is silicon oxide.

[0078] In this embodiment, the opening 109 has a preset depth H1.

[0079] The preset depth H1 is the distance from the top surface of the isolation layer 107 to the top surface of the gate insulation layer 101 .

[0080] refer to Figure 6 , Figure 6 (b) Yes Figure 6 (a) A cross-sectional view along the CD direction. In the storage cell region 100a, a protection layer 110 is formed on the top of the gate insulating layer 101 and the isolation layer 107. The protection layer 110 covers the top and sidewall of the word line.

[0081] Specifically, after the first dielectric layer and the second dielectric layer are subsequently formed, a process of removing the first dielectric layer and the second dielectric layer will be performed. During the process of removing the first dielectric layer and the second dielectric layer, the protective layer 110 can reduce the probability of the related etching process causing damage to the word line.

[0082] Moreover, under the effect of the protection layer 110 , the subsequent first dielectric layer and the second dielectric layer will not be formed between adjacent word lines of the storage cell region 100 a , thereby further reducing the impact on the word lines.

[0083] To facilitate the subsequent removal of the protective layer 110, in this embodiment, in the step of forming the protective layer 110, the material of the protective layer 110 is an organic material. Specifically, the material of the protective layer 110 includes one or more of a photoresist, a spin-on carbon (SOC), an ODL (organic dielectric layer) material, and an APF (Advanced Patterning Film) material.

[0084] As an example, the material of the protection layer 110 is photoresist.

[0085] In this embodiment, the process of forming the protection layer 110 includes a spin coating process.

[0086] The spin coating process has the characteristics of good filling and covering properties, which is conducive to the protection layer 110 covering the top and side walls of the word line.

[0087] refer to Figure 7 , Figure 7 (b) Yes Figure 7(a) A cross-sectional view along the CD direction, after forming the protection layer 110 and before subsequently forming the first dielectric layer, further comprising: forming a second dielectric layer 111 on the side walls of the word lines at the junction of the storage cell area 100a and the isolation area 100b, the top of the protection layer 100, and the top of the gate insulation layer 101 of the isolation area 100b, and the second dielectric layer 111 also covers the bottom and side walls of the opening 109 of the isolation area 100b.

[0088] Since the material of the protective layer 110 is an organic material, in the subsequent process of forming the first dielectric layer, the organic material is likely to contaminate the first dielectric layer. Therefore, the second dielectric layer 111 reduces the probability of the first dielectric layer being contaminated by the protective layer 110, thereby improving the performance of the semiconductor structure.

[0089] In this embodiment, in the step of forming the second dielectric layer 111 , the material of the second dielectric layer 111 includes one or more of silicon oxide, silicon oxynitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0090] Silicon oxide, silicon oxynitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide have smaller thermal expansion coefficients and can generate smaller stress in subsequent related annealing processes, thereby reducing damage to the substrate 100 and the bit line 106 .

[0091] In this embodiment, the process of forming the second dielectric layer 111 includes a low-pressure furnace tube process.

[0092] In the process of forming the second dielectric layer 111 using the low-pressure furnace tube process, the process temperature and pressure are relatively low, which is beneficial to reducing the thermal budget. In addition, the low-pressure furnace tube process has excellent step performance, thereby forming silicon oxide with higher quality, better uniformity and better flatness.

[0093] refer to Figure 8 , Figure 8 (b) Yes Figure 8 (a) A cross-sectional view along the CD direction, in which a first dielectric layer 112 is formed on the sidewalls of the word line at the junction of the storage cell area 100a and the isolation area 100b, the top of the protection layer 110, and the top of the gate insulation layer 101 of the isolation area 100b, and the first dielectric layer 112 is also filled in the opening 109 of the isolation area 100b.

[0094] In this embodiment, before the subsequent step of forming a barrier layer, the first dielectric layer 112 is first filled in the remaining space of the opening 109 to occupy the space of the opening 109, so as to prevent the barrier layer from being formed in the opening 109. Therefore, in the subsequent process of removing the barrier layer on the top of the bit line 106, it is beneficial to completely remove the barrier layer located in the isolation region 100b. Accordingly, the probability of dislocation of the bit line 106 due to stress change in the subsequent annealing process is reduced, so that the quality of the bit line is guaranteed. Moreover, it is also beneficial to reduce the probability of morphological bending of the bit line 106 due to stress change in the subsequent annealing process. Accordingly, in the subsequent process of forming a plug on the top of the bit line 106, the probability of mutual alignment between the plug and the bit line is increased, and the probability of punch-through of the plug is reduced, thereby improving the performance of the semiconductor.

[0095] In this embodiment, in the step of forming the first dielectric layer 112 , the first dielectric layer 112 conformally covers the second dielectric layer 111 .

[0096] Specifically, after the second dielectric layer 111 is formed, there is still remaining space in the opening 109 of the isolation region 100b. In order to reduce the probability that the subsequently formed barrier layer is located in the opening 109 , the first dielectric layer 112 conformally covers the second dielectric layer 111 and fills the remaining space in the opening 109 .

[0097] Accordingly, the thickness of the first dielectric layer 112 is affected by the preset depth H1 of the opening 109 .

[0098] In this embodiment, in the step of forming the first dielectric layer 112 , the thickness H2 of the first dielectric layer 112 is greater than 1 times the preset depth H1 .

[0099] In order to fill the remaining space of the opening 109 and reduce the probability of a barrier layer being formed in the opening 109 , the first dielectric layer 112 needs to fill the remaining space of the opening 109 , that is, the thickness H2 of the first dielectric layer 112 is greater than 1 times the preset depth H1 .

[0100] Specifically, according to the preset depth H1 of the opening 109 and the thickness of the second dielectric layer 111 , the thickness H2 of the first dielectric layer 112 is reasonably set so that the second dielectric layer 111 can fill the remaining space of the opening 109 .

[0101] In this embodiment, the process of forming the first dielectric layer 112 includes a low-pressure furnace tube process.

[0102] In the process of forming the first dielectric layer 112 using the low-pressure furnace tube process, the process temperature and pressure are relatively low, which is beneficial to reducing the thermal budget. In addition, the low-pressure furnace tube process has excellent step performance, thereby forming silicon oxide with higher quality, better uniformity and better flatness.

[0103] In this embodiment, in the step of forming the first dielectric layer 112 , the material of the first dielectric layer 112 includes one or more of silicon oxide, silicon oxynitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0104] Silicon oxide, silicon oxynitride, boron-doped silicon oxide and phosphorus-doped silicon oxide have smaller thermal expansion coefficients and can generate smaller stress in subsequent related annealing processes, thereby reducing damage to the substrate 100, the bit line 106 and the word line.

[0105] As an example, the material of the first dielectric layer 112 is boron-doped silicon oxide.

[0106] refer to Fig. 9 , Fig. 9 (b) Yes Fig. 9 (a) A cross-sectional view along the CD direction. After the first dielectric layer 112 is formed, the first dielectric layer 112 in the storage cell area 100a and the first dielectric layer 112 located on the top of the gate insulation layer 101 in the isolation area 100b are removed, and the remaining first dielectric layer 112 is located in the opening 109 of the isolation area 100b.

[0107] The first dielectric layer 112 in the storage cell region 100 a and the first dielectric layer 112 in the isolation region 100 b that is higher than the gate insulating layer 101 are removed, thereby providing a space for the subsequent formation of a blocking layer.

[0108] Among them, the remaining first dielectric layer 112 is located in the opening 109 of the isolation area 100b to prevent a subsequent barrier layer from being formed in the opening, thereby facilitating the complete removal of the barrier layer located in the isolation area in the subsequent process of removing the barrier layer on the top of the bit line.

[0109] Furthermore, the first dielectric layer 112 of the storage unit area 100a is removed to prevent the first dielectric layer 112 from affecting the storage unit area 100a, so that subsequent processes can proceed normally, that is, reducing the impact on the traditional process.

[0110] In this embodiment, the process of removing the first dielectric layer 112 in the storage cell region 100 a and the first dielectric layer 112 located on the top of the gate insulating layer 101 in the isolation region 100 b includes a dry etching process.

[0111] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is greater than the lateral etching rate, and the process controllability is high. Under the condition of meeting the process requirements for removing the first dielectric layer 112, it is easy to ensure that the remaining first dielectric layer 112 is filled in the opening 109 of the isolation region 100b, and it is beneficial to improve the top surface flatness of the first dielectric layer 112 in the opening 109.

[0112] Continue to refer Fig. 9 In this embodiment, the step of removing the first dielectric layer 112 of the storage cell area 100a and the first dielectric layer 112 located on the top of the gate insulating layer 101 in the isolation area 100b also includes: removing the second dielectric layer 111 of the storage cell area 100a, and the remaining second dielectric layer 111 is located at the bottom and side walls of the opening 109 of the isolation area 100b, and the top of the gate insulating layer 101.

[0113] Since the etching rates of the first dielectric layer 112 and the second dielectric layer 111 are similar, in order to simplify the process steps and save process costs, in the step of removing the first dielectric layer 112 of the storage cell area 100a and the first dielectric layer 112 in the isolation area 100b that is higher than the gate insulation layer 101, the second dielectric layer 111 of the storage cell area 100a is removed.

[0114] In the process of removing the second dielectric layer 111 of the storage cell region 100 a , the top of the protection layer 110 of the storage cell region 100 a is used as an etching stop position.

[0115] It should be noted that, in the process of removing the second dielectric layer 111 in the storage cell area 100a, the removal rate of the second dielectric layer 111 on the top of the protective layer 110 is greater than the removal rate of the second dielectric layer 111 in the isolation area 100b, and thus after the second dielectric layer 111 in the storage cell area 100a is completely removed, the second dielectric layer 111 located on the top of the gate insulation layer 101 in the isolation area 100b can be retained.

[0116] refer to Fig.10 , Fig.10 (b) Yes Fig.10 (a) A cross-sectional view along the CD direction, after removing the first dielectric layer 112 of the storage cell region 100a and the first dielectric layer 112 in the isolation region 100b that is higher than the gate insulating layer 101, the protection layer 110 is removed.

[0117] Removing the protection layer 110 provides space for the subsequent formation of a barrier layer and a spacer layer.

[0118] In this embodiment, the process of removing the protective layer 110 includes an ashing process or a wet etching process.

[0119] refer to Fig.11 , Fig.11 (b) Yes Fig.11 (a) A cross-sectional view along the CD direction. After removing the protection layer 110, a barrier layer 114 is formed on the top of the substrate to conformally cover the word line. The barrier layer 114 also covers the top of the remaining first dielectric layer 112 in the isolation region 100b.

[0120] Subsequently, the barrier layer 114 at a partial height on the side wall of the first gate stack structure 105 is removed to expose a portion of the side wall of the control gate layer 104, thereby defining the thickness of the formed metal silicide layer in the subsequent metal silicide process, that is, only the control gate layer 104 exposed by the remaining barrier layer 114 is subsequently converted into a metal silicide layer.

[0121] It should be noted that, in order to avoid adverse effects on the performance of the NAND flash memory device, a dielectric material with high process compatibility is selected as the material of the barrier layer 114. To this end, the material of the barrier layer 114 may include one or more of silicon oxide, silicon nitride and silicon oxynitride. As an embodiment, the material of the barrier layer 114 is silicon nitride.

[0122] Specifically, the process of forming the barrier layer 114 includes an atomic layer deposition process.

[0123] In this embodiment, in order to enable the barrier layer 114 to protect the substrate 100 and the second gate stack structure 163 in the subsequent process and reduce the process difficulty of forming the barrier layer 114, the barrier layer 114 conformally covers the substrate 100, the first gate stack structure 105 and the second gate stack structure 163. Since the hard mask layer 108 is formed on the top of the first gate stack structure 105 and the second gate stack structure 163, the barrier layer 114 also covers the top and sidewalls of the hard mask layer 108.

[0124] In this embodiment, the formation method further includes: before forming the blocking layer 114, it also includes: forming an oxide layer 113 conformally covering the word line on the top of the substrate, and the oxide layer 113 also covers the top of the remaining first dielectric layer 112 in the isolation region 100b.

[0125] Accordingly, when the barrier layer 114 is formed, the barrier layer 114 conformally covers the oxide layer 113 .

[0126] The oxide layer 113 protects the top and sidewalls of the word line, and reduces the probability of the related etching process causing damage to the word line during the subsequent removal of the barrier layer 114 .

[0127] Continue to refer Fig.11 The formation method further includes: after forming the barrier layer 114 , forming a spacer material layer 115 on the top of the substrate, wherein the spacer material layer 115 covers the top and sidewalls of the barrier layer 114 .

[0128] The spacer material layer 115 provides a process basis for the subsequent formation of a spacer layer.

[0129] The process for forming the spacer material layer 115 has good conformal coverage, and in order to avoid adverse effects on the barrier layer 114, a process with a lower process temperature is selected to form the spacer material layer 115. To this end, in this embodiment, the process for forming the spacer material layer 115 is an atomic layer deposition process.

[0130] The material of the spacer material layer 115 may include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the spacer material layer 115 is silicon oxide.

[0131] refer to Fig.12 , Fig.12 (b) Yes Fig.12 (a) A cross-sectional view along the CD direction. In the memory cell area 100a, the spacer material layer 115 and the barrier layer 114 located on the top of the word line are removed, and the barrier layer 114 and the spacer material layer 115 in the isolation area 100b are removed, and the spacer material layer 115 on the side wall of the word line in the memory cell area 100b is retained as the spacer layer 196.

[0132] The spacer layer 196 between adjacent word lines occupies space for the air gap formed subsequently.

[0133] In this embodiment, the process of removing the spacer material layer 115 and the barrier layer 114 located on the top of the word line and removing the barrier layer 114 and the spacer material layer 115 in the isolation region 100b includes a dry etching process (eg, an anisotropic dry etching process).

[0134] It should be noted that the process of removing the spacer material layer 115 and the barrier layer 114 also includes: removing the oxide layer 113 located on the top of the word line and the oxide layer 113 in the isolation region 100 b.

[0135] refer to Fig.13 , Fig.13 (b) Yes Fig.13 (a) A cross-sectional view along the CD direction, after forming the spacer layer 196, the forming method further comprises: etching back a portion of the thickness of the spacer layer 196, the barrier layer 114 and the oxide layer 113 to expose the top and a portion of the sidewalls of the first gate stack structure 105 and the second gate stack structure 163, and converting the exposed first gate stack structure 105 and the second gate stack structure 163 into a metal silicide layer 190; after forming the metal silicide layer 190, removing the spacer layer 196 in the memory cell area 100a. 96 and the barrier layer 114, forming a groove (not shown) surrounded by the side walls of the metal silicide layer 190, the side walls of the word lines, the top of the gate insulation layer 101 and the top of the substrate; forming a top dielectric layer 191 covering the metal silicide layer 190, the remaining oxide layer 113, the remaining sidewalls 196 and the barrier layer 114, the top dielectric layer 191 is also formed in the groove (not shown), and the top dielectric layer 191 seals the groove at the groove opening position, and surrounds an air gap 192 in the groove.

[0136] Specifically, after etching back a portion of the thickness of the spacer layer 196 , the barrier layer 114 , and the oxide layer 113 , a portion of the sidewalls of the control gate layer 104 and the top gate layer 160 are exposed.

[0137] The air gap 192 is used as an air sidewall. Compared with the sidewall material, the dielectric constant of air is smaller, so the setting of the air sidewall can reduce the capacitance between adjacent word lines in the NAND flash memory device, thereby improving the crosstalk problem of the NAND flash memory device during the programming process and the repeated reading and writing capability of the NAND flash memory device.

[0138] In this embodiment, the top dielectric layer 191 is formed by a plasma enhanced chemical vapor deposition process. The hole filling performance of the plasma enhanced chemical vapor deposition process is poor, especially when the spacing between adjacent first gate stack structures 105 is small, the top dielectric layer 191 is more likely to seal the groove at the groove opening position first, thereby forming the air gap 192. Accordingly, in this embodiment, the material of the top dielectric layer 191 is one or both of plasma enhanced tetraethoxysilane (PETEOS) and plasma enhanced silicon oxide (PEOX).

[0139] In this embodiment, the exposed first gate stack structure 105 and the exposed second gate stack structure 163 are converted into a metal silicide layer 190 through the metal silicide process.

[0140] After the metal silicide process, the remaining selection gate and the metal silicide layer 190 are used as the drain selection line (DSL) or source selection line (SSL) of the formed NAND flash memory device. The metal silicide layer 190 is used to reduce the gate resistance of the NAND flash memory device, thereby improving the programming operation capability and efficiency of the NAND flash memory device, improving the repeated read and write capability of the NAND flash memory device, and improving the RC (Resistance Capacitance) delay, thereby improving the performance of the NAND flash memory device.

[0141] In this embodiment, the material of the metal silicide layer 190 is nickel silicon compound. In another embodiment, the material of the metal silicide layer can also be titanium silicon compound or cobalt silicon compound.

[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a substrate and a bit line protruding from the substrate, the substrate comprising a storage cell region and an isolation region located between adjacent storage cell regions; a gate insulating layer, located on top of the bit line; An isolation layer, located on the top of the substrate where the bit line is exposed, and the isolation layer covers a portion of the side wall of the bit line; A word line is located on top of the gate insulating layer and the isolation layer in the storage cell area, and an extension direction of the word line is perpendicular to an extension direction of the bit line; A first dielectric layer, located on the top of the isolation layer in the isolation region and filled between adjacent bit lines; A barrier layer, located in the storage cell region and covering the sidewalls of the word line; A sidewall covering a sidewall of a word line at a junction of the storage cell region and the isolation region; A metal silicide layer is located on the top of the word line, and the sidewall of the metal silicide layer, the sidewall of the word line, the top of the gate insulating layer and the top of the substrate form a groove; A top dielectric layer covers the metal silicide layer and the sidewalls. The top dielectric layer is also located in the trench. The top dielectric layer seals the trench at the trench opening and forms an air gap in the trench.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a second dielectric layer located in the isolation region, the second dielectric layer located between the sidewall of the first dielectric layer and the sidewall of the bit line and the sidewall of the gate insulation layer, and also located between the bottom of the first dielectric layer and the top of the isolation layer.

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: an oxide layer located on the top of the substrate and covering the sidewalls of the word lines in the storage cell area and the sidewalls of the first dielectric layer in the isolation area; The barrier layer covers a sidewall of the oxide layer.

4. The semiconductor structure according to claim 2, wherein: The second dielectric layer also extends to cover the top of the gate insulating layer in the isolation region; The top of the second dielectric layer is flush with the top of the first dielectric layer.

5. The semiconductor structure according to claim 2, wherein: The material of the second dielectric layer includes one or more of silicon oxide, silicon oxynitride, boron-doped silicon oxide and phosphorus-doped silicon oxide.

6. The semiconductor structure according to claim 1, wherein: The material of the first dielectric layer includes one or more of silicon oxide, silicon oxynitride, boron-doped silicon oxide and phosphorus-doped silicon oxide.

7. The semiconductor structure according to claim 1, wherein: The material of the gate insulating layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride; The material of the isolation layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride; The material of the barrier layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

8. The semiconductor structure according to claim 1, wherein: The word line of the storage cell area includes a first gate stack structure, wherein the first gate stack structure includes a floating gate layer located on the gate insulating layer, a gate dielectric layer located on the floating gate layer, and a control gate layer located on the gate dielectric layer; The word line at the junction of the storage cell area and the isolation area includes a second gate stack structure, and the second gate stack structure includes a selection gate located on the gate insulation layer.

9. The semiconductor structure according to claim 8, characterized in that The material of the floating gate layer includes polysilicon, the material of the gate dielectric layer includes one or both of silicon oxide and silicon nitride, the material of the control gate layer includes polysilicon; and the material of the select gate includes polysilicon.

10. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, the substrate comprising a substrate and a bit line protruding from the substrate, a gate insulating layer is formed on the top of the bit line, an isolation layer is formed on the top of the substrate where the bit line is exposed, the isolation layer covers part of the side wall of the bit line, the adjacent gate insulating layers, the bit line and the isolation layer form an opening, along the extension direction of the bit line, the substrate comprises a storage cell area and an isolation area located between the adjacent storage cell areas, a word line is formed on the top of the gate insulating layer and the isolation layer in the storage cell area, and the extension direction of the word line is perpendicular to the extension direction of the bit line; In the storage cell region, a protection layer is formed on top of the gate insulating layer and the isolation layer, wherein the protection layer covers the top and sidewalls of the word line; Forming a first dielectric layer on the sidewalls of the word line at the junction of the storage cell area and the isolation area, the top of the protection layer, and the top of the gate insulation layer of the isolation area, wherein the first dielectric layer is also filled in the opening of the isolation area; After forming the first dielectric layer, removing the first dielectric layer in the storage unit area and the first dielectric layer located on the top of the gate insulating layer in the isolation area, and the remaining first dielectric layer is located in the opening of the isolation area; After removing the first dielectric layer in the storage cell area and the first dielectric layer located on the top of the gate insulating layer in the isolation area, removing the protective layer; After removing the protection layer, a barrier layer is formed on the top of the substrate to conformally cover the word line, and the barrier layer also covers the top of the remaining first dielectric layer in the isolation region.

11. The method for forming a semiconductor structure according to claim 10, wherein: The forming method further comprises: after forming the barrier layer, forming a spacer material layer on the top of the substrate, wherein the spacer material layer covers the top and sidewalls of the barrier layer; In the storage cell area, the sidewall material layer and the barrier layer at the top of the word line are removed, and the barrier layer and the sidewall material layer in the isolation area are removed, and the sidewall material layer on the side wall of the word line in the storage cell area is retained as a sidewall layer.

12. The method for forming a semiconductor structure according to claim 10, wherein: After forming the protection layer and before forming the first dielectric layer, the method further includes: forming a second dielectric layer on the sidewalls of the word line at the junction of the storage cell area and the isolation area, the top of the protection layer, and the top of the gate insulation layer of the isolation area, wherein the second dielectric layer also covers the bottom and sidewalls of the opening of the isolation area; In the step of forming the first dielectric layer, the first dielectric layer conformally covers the second dielectric layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process of removing the first dielectric layer in the storage cell area and the first dielectric layer located on the top of the gate insulating layer in the isolation area also includes: removing the second dielectric layer in the storage cell area, and the remaining second dielectric layer is located at the bottom and sidewalls of the opening in the isolation area and the top of the gate insulating layer; In the isolation region, the top of the first dielectric layer remaining in the opening is flush with the top of the second dielectric layer.

14. The method for forming a semiconductor structure according to claim 10, wherein: The process of removing the first dielectric layer in the storage cell area and the first dielectric layer located on the top of the gate insulating layer in the isolation area includes a dry etching process.

15. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming the second dielectric layer includes a low-pressure furnace tube process.

16. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming the opening, the opening has a preset depth; In the step of forming the first dielectric layer, the thickness of the first dielectric layer is greater than 1 times the preset depth.

17. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the first dielectric layer includes a chemical vapor deposition process.

18. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the protection layer includes a spin coating process or a chemical vapor deposition process.

19. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming the protective layer, the material of the protective layer includes one or more of photoresist, SOC, ODL and APF.

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