Semiconductor device and manufacturing method

Abstract

Semiconductor devices and methods of manufacture are disclosed. A ferroelectric random access memory array is formed with bit line drivers and source line drivers formed below the ferroelectric random access memory array. A via is formed using the same process used to form individual memory cells within the ferroelectric random access memory array.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and manufacturing methods. Background Technology

[0002] Semiconductor memories are used in integrated circuits for electronic applications, including devices such as radios, televisions, mobile phones, and personal computing devices. Semiconductor memories fall into two main categories: volatile memories and non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose the information they store when power is off.

[0003] On the other hand, non-volatile memory can store stored data. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include its fast read / write speed and small size. Summary of the Invention

[0004] According to a first aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a source line driver on a semiconductor substrate; forming a first metallization layer on the source line driver; directly depositing a multilayer stack on the first metallization layer; forming a ferroelectric random access memory cell within the multilayer stack; and simultaneously forming a via leading to the first metallization layer with the ferroelectric random access memory cell.

[0005] According to a second aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a multilayer stack on a semiconductor substrate, wherein an active device array is formed directly beneath the multilayer stack; patterning the multilayer stack to form a first opening and a second opening, the first opening exposing a dielectric material and the second opening exposing a conductive portion of a metallization layer connected to the active device array; replacing some layers of the multilayer stack to form word lines; depositing a ferroelectric layer along the sidewalls of the first and second openings; depositing a semiconductor layer in the first and second openings adjacent to the ferroelectric layer; depositing a second dielectric material to fill the remaining portions of the first and second openings; planarizing the second dielectric material down to the multilayer stack; and forming a conductive material extending through the second dielectric material, the conductive material being in physical contact with a conductive portion of the metallization layer.

[0006] According to a third aspect of this disclosure, a semiconductor device is provided, comprising: a bit line driver located on a semiconductor substrate; a first metallization layer on the bit line driver, the first metallization layer comprising a dielectric material; a ferroelectric random access memory array on the first metallization layer, wherein each memory cell in the ferroelectric random access memory array comprises a ferroelectric material, a semiconductor material, and a conductive material; and a via electrically connected to the first metallization layer, the via being adjacent to the ferroelectric material and the semiconductor material. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily enlarged or reduced for clarity of discussion.

[0008] Figure 1A-Figure 1B Some embodiments illustrate the formation of active devices and metallization layers on a substrate.

[0009] Figure 2 The formation of material stacks is illustrated in some embodiments.

[0010] Figure 3 The placement of the photoresist is illustrated in some embodiments.

[0011] Figure 4 Patterning of material stacks is shown according to some embodiments.

[0012] Figure 5 The formation of a stepped pattern is illustrated in some embodiments.

[0013] Figure 6 The deposition of intermetallic dielectrics is illustrated in some embodiments.

[0014] Figures 7A-7B Planarization of intermetallic dielectrics is illustrated in some embodiments.

[0015] Figures 8A-8B The deposition of a hard mask is illustrated in some embodiments.

[0016] Figures 9A-9B The formation of a first trench and the filling of the first trench with conductive and dielectric materials are shown in some embodiments.

[0017] Figures 10A-10B The formation of the second trench and the filling of the second trench with conductive and dielectric materials are shown in some embodiments.

[0018] Figures 11A-11B The removal of dielectric material is illustrated in some embodiments.

[0019] Figures 12A-12B Patterning of conductive materials is shown according to some embodiments.

[0020] Figures 13A-13B The deposition of ferroelectric bands, semiconductor bands, and dielectric layers is illustrated in some embodiments.

[0021] Figures 14A-14B The deposition of dielectric plugs, bit lines, and source lines is illustrated in some embodiments.

[0022] Figures 15A-15G The formation of the interconnect structure is illustrated according to some embodiments.

[0023] Figure 16 Some embodiments are shown where the via is located within the center of the memory array. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., are used herein to describe the relationship of an element or feature to other elements(s) or features(s) shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0026] Embodiments will now be described with respect to specific examples in which a CMOS under-area (CuA) design is used to connect drivers to 3DFeRAM memory cells. However, the embodiments described herein are not intended to be limited to the precise descriptions included, as the ideas can be implemented in a wide variety of embodiments. All such embodiments are intended to be included entirely within the scope of the present description.

[0027] Turn now Figure 1A-Figure 1B The diagram illustrates a semiconductor device 100 comprising the following components: a semiconductor substrate 101, an active device 103, an interlayer dielectric (ILD) 105, and a metallization layer 110, the metallization layer comprising at least a first dielectric layer 107 and a first metal layer 109 (M1) within the first dielectric layer 107. The semiconductor substrate 101 may comprise an active layer of doped or undoped bulk silicon or a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate comprises a layer of semiconductor material, such as silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0028] Semiconductor substrate 101 may include active device 103. Those skilled in the art will recognize that a wide variety of active and passive devices (e.g., transistors, capacitors, resistors, combinations thereof, etc.) can be used to meet the desired structural and functional requirements of the design for semiconductor device 100. Active device 103 may be a planar transistor, a fin field-effect transistor, a nanostructure field-effect transistor, a combination thereof, etc., and any suitable method may be used.

[0029] In one particular embodiment, the source / drain regions are formed in the semiconductor substrate 101 on the opposite side of the gate dielectric, and a gate electrode is formed on top of the gate dielectric. In embodiments where the semiconductor substrate 101 is an n-type substrate, the source / drain regions are formed by implanting suitable p-type dopants such as boron, gallium, or indium. Alternatively, in embodiments where the semiconductor substrate is a p-type substrate, the source / drain regions can be formed by implanting suitable n-type dopants such as phosphorus or arsenic. These source / drain regions are implanted using the gate dielectric and the gate electrode as masks.

[0030] Furthermore, active devices 103 can be grouped and / or connected together to form functional circuitry. In one particular embodiment, active devices 103 in bit line driver region 127 can be fabricated to form bit line drivers, while active devices 103 in source line driver region 129 can be fabricated to form word line drivers. However, any suitable combination of connections can be used to form any suitable functional circuitry.

[0031] An ILD layer 105 is formed over the active device 103 to protect and isolate the active device 103. In one embodiment, the ILD layer 105 may comprise a material such as borosilicate glass (BPSG), although any suitable dielectric may be used for either layer. The ILD layer 105 may be formed using a process such as PECVD, but alternatively, other processes such as LPCVD may be used. The ILD layer 105 may be formed as approximately Peace Treaty The thickness between.

[0032] Once the ILD layer 105 is formed, a contact plug 104 can be formed through the ILD layer 105 to electrically connect the active device 103. In one embodiment, the formation of the contact plug 104 can be initiated by first forming a contact plug opening through the ILD layer 105 to expose the source / drain region or, in other cases, the gate electrode of the active device 103, filling the opening with a conductive material, and then planarizing the conductive material using a process such as chemical mechanical polishing. However, any suitable method for forming the contact plug 104 can be used.

[0033] A first dielectric layer 107 can be formed on top of the ILD layer 105. The first dielectric layer 107 can be made of one or more suitable dielectric materials, such as low-k dielectrics (e.g., carbon-doped oxides), very low-k dielectrics (e.g., porous carbon-doped silicon dioxide, silicon oxide, silicon nitride, polymers such as polyimide, combinations thereof, etc.). The first dielectric layer 107 can be formed by processes such as spin coating or chemical vapor deposition (CVD), but any suitable process can be used, and it can have a dielectric layer thickness of approximately [missing information]. Peace Treaty The first thickness T1 between, for example, approximately

[0034] Figure 1A Additionally, a first metal layer 109 is shown formed within the first dielectric layer 107. In one embodiment, the first metal layer 109 can be formed using, for example, a dual damascene process, thereby first forming openings for trenches and vias within the first dielectric layer 107. In one embodiment, one or more photolithographic masks and etching processes can be used to form the openings. Once formed, the openings can be filled and / or overfilled with a conductive material, followed by planarization. However, any suitable method can be used.

[0035] A second dielectric layer 111 may be formed over the first dielectric layer 107. In one embodiment, the second dielectric layer 111 may be formed using a method and process similar to that used for the first dielectric layer 107. However, any suitable method may be used to form the second dielectric layer 111.

[0036] A second metal layer 113 may be formed in the second dielectric layer 111. In one embodiment, the second metal layer 113 may be formed using a similar material and a similar process (e.g., damascene or dual damascene) as described above with the first metal layer 109. However, any suitable method may be used to form the second metal layer 113.

[0037] A third dielectric layer 115 may be formed on top of the second dielectric layer 111. In one embodiment, the third dielectric layer 115 may be formed using a method and process similar to that used for the first dielectric layer 107 described above. However, any suitable method may be used to form the third dielectric layer 115.

[0038] A third metal layer 117 may be formed in the third dielectric layer 115. In one embodiment, the third metal layer 117 may be formed using a similar material and a similar process (e.g., damascene or dual damascene) as described above with the first metal layer 109. However, any suitable method may be used to form the third metal layer 117.

[0039] A fourth dielectric layer 119 may be formed over the third dielectric layer 115. In one embodiment, the fourth dielectric layer 119 may be formed using a method and process similar to that used for the first dielectric layer 107 as described above. However, any suitable method may be used to form the fourth dielectric layer 119.

[0040] A fourth metal layer 121 may be formed in the fourth dielectric layer 119. In one embodiment, the fourth metal layer 121 may be formed using a similar material and a similar process (e.g., damascene or dual damascene) as described above with the first metal layer 109. However, any suitable method may be used to form the fourth metal layer 121.

[0041] A fifth dielectric layer 123 may be formed over the fourth dielectric layer 119. In one embodiment, the fifth dielectric layer 123 may be formed using a method and process similar to that used for the first dielectric layer 107 as described above. However, any suitable method may be used to form the fifth dielectric layer 123.

[0042] A fifth metal layer 125 may be formed within the fifth dielectric layer 123. In one embodiment, the fifth metal layer 125 may be a material such as aluminum, titanium, titanium nitride, tantalum nitride, cobalt, silver, gold, copper, nickel, chromium, hafnium, ruthenium, tungsten, platinum, tungsten nitride, or combinations thereof. The fifth metal layer 125 may be formed using a process similar to that used for the first metal layer 109 as described above (e.g., damascene or dual damascene). However, any suitable materials and manufacturing methods may be used to form the fifth metal layer 125.

[0043] Figure 1B It shows Figure 1A A three-dimensional diagram of the structure formed in the middle, in which Figure 1A yes Figure 1B A cross-sectional view along line A-A'. Furthermore, to facilitate viewing of the various structures, the dielectric portion of the structure, along with most of the semiconductor substrate 101, has been removed to show the conductive connections.

[0044] This view provides a better view of the active device 103 on the semiconductor substrate 101, which is connected to the overlying metal lines. Furthermore, the fifth metal layer 125 will act as a gateway via to access the overlying memory cell region 503 (hereinafter referred to as...). Figure 5 (To be further described).

[0045] Figure 2 A multilayer stack 201 is shown formed on top of a fifth dielectric layer 123. To separate the multilayer stack 201 from the fifth dielectric layer 123, a first hard mask layer 202 is first deposited. In one embodiment, the first hard mask layer 202 may be a material such as silicon oxynitride, silicon carbide, silicon carbide, or a combination thereof, deposited using processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or combinations thereof. However, any suitable material and fabrication method may be used.

[0046] The multilayer stack 201 includes alternating first dielectric layers 201A and second dielectric layers 201B. The first dielectric layer 201A is formed of a first dielectric material, while the second dielectric layer 201B is formed of a second dielectric material. In the illustrated embodiment, the multilayer stack 201 includes five first dielectric layers 201A and four second dielectric layers 201B. It should be understood that the multilayer stack 201 may include any number of first dielectric layers 201A and second dielectric layers 201B.

[0047] The multilayer stack 201 will be patterned in subsequent processing. The patterned first dielectric layer 201A will be used to isolate the subsequently formed thin-film transistor (TFT). The patterned second dielectric layer 201B is a sacrificial layer (or dummy layer), which will be removed in subsequent processing and used for the word line 1013 of the TFT. Figure 2 (Not shown in the figure, but further shown and described below with reference to Figure 10) is substituted. Therefore, the second dielectric material of the second dielectric layer 201B has high etch selectivity compared to the etching of the first dielectric material of the first dielectric layer 201A. In an embodiment, the first dielectric layer 201A may be formed of an oxide such as silicon oxide, while the second dielectric layer 201B may be formed of a nitride such as silicon nitride. Other combinations of dielectric materials having acceptable etch selectivity different from each other may also be used.

[0048] Each layer in the multilayer stack 201 can be formed by an acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The thickness of each layer can be in the range of about 15 nm to about 90 nm. In some embodiments, the first dielectric layer 201A is formed to have a different thickness from the second dielectric layer 201B. For example, the first dielectric layer 201A can be formed to have a first thickness T1 and the second dielectric layer 201B can be formed to have a second thickness T2, the second thickness T2 being approximately 0% to about 100% of the first thickness T1 [large / small]. The multilayer stack 201 can have a total height H1 in the range of about 1000 nm to about 10000 nm (e.g., about 2000 nm). However, any suitable thickness can be used.

[0049] exist Figure 3 In this process, photoresist 301 is formed on top of the multilayer stack 201. For ease of discussion, Figure 3 The structure beneath the first hard mask layer 202 is not shown. The photoresist 301 can be formed using spin coating and patterning with acceptable photolithography techniques. Patterning the photoresist 301 can expose the multilayer stack 201 in region 303 while masking the remainder of the multilayer stack 201. For example, the topmost layer of the multilayer stack 201 can be exposed in region 303.

[0050] exist Figure 4 In this process, photoresist 301 is used as a mask to etch exposed portions of the multilayer stack 201 in region 303. Etching can be any acceptable etching process, such as wet or dry etching, RIE, NBE, or a combination thereof. Etching can be anisotropic. Etching can remove portions of the first dielectric layer 201A and the second dielectric layer 201B in region 303. Since the first dielectric layer 201A and the second dielectric layer 201B have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, when etching the first dielectric layer 201A, the second dielectric layer 201B serves as an etch stop layer, and when etching the second dielectric layer 201B, the underlying first dielectric layer 201A serves as an etch stop layer. As a result, portions of the first dielectric layer 201A and the second dielectric layer 201B can be selectively removed without removing the remaining layers of the multilayer stack 201, and the opening can extend to a desired depth. In another embodiment, a timed etching process can be used to stop etching the opening after it reaches a desired depth.

[0051] Once the opening is formed, the photoresist 301 needs to be trimmed to expose additional portions of the multilayer stack 201. An acceptable photolithography technique can be used to trim the photoresist 301. As a result of trimming, the width of the photoresist 301 is reduced, and portions of the additional area of ​​the multilayer stack 201 are exposed. These newly exposed portions of the multilayer stack 201 (along with the underlying portions previously exposed by the etching process) can then be etched using the newly trimmed photoresist 301 as a mask. The etching can be any suitable etching process, such as wet or dry etching, RIE, NBE, etc., or combinations thereof. The etching process can be anisotropic. Etching can further extend the opening into the multilayer stack 201.

[0052] Figure 5 This demonstrates that a stepped pattern can be formed by repeatedly trimming and etching the photoresist 301. Specifically, a stepped pattern is formed in which the edges of the upper overlay in the first dielectric layer 201A and the lower overlay in the second dielectric layer 201B are staggered.

[0053] Figure 5 Additionally, it is shown that the photoresist 301 can be removed during the formation of the stepped pattern. In one embodiment, an ashing process can be used to remove the photoresist 301, thereby increasing the temperature of the photoresist 301 until the photoresist 301 undergoes decomposition and can be easily removed. However, any suitable process for removing the photoresist 301 can be used.

[0054] By forming a stepped pattern and then removing the photoresist 301, the original multilayer stack 201 is divided into stepped regions 501 and memory cell regions 503. In the stepped regions 501, the number of first dielectric layers 201A and second dielectric layers 201B varies; some regions have a single group of first dielectric layers 201A and second dielectric layers 201B, while other regions contain more groups, such as four groups of first dielectric layers 201A and second dielectric layers 201B. Furthermore, the memory cell regions 503 have each layer initially deposited within the multilayer stack 201.

[0055] Figure 6 The deposition of an intermetallic dielectric (IMD) 601 is illustrated. In one embodiment, IMD 601 may be a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, other low-k dielectric materials, or combinations thereof. IMD 601 can be deposited using chemical vapor deposition, atomic layer deposition, physical vapor deposition, spin coating processes, or combinations thereof. However, any suitable material and any suitable method can be used.

[0056] Figures 7A-7BThis shows that after IMD 601 has been deposited, it is planarized to be coplanar with the top layer of the multilayer stack 201. For ease of observation and discussion, Figure 6 The structure shown is divided into two diagrams, in which Figure 7A The memory cell region 503 is shown, while Figure 7B A stepped region 501 is shown. In one embodiment, the IMD 601 can be planarized using a polishing process such as chemical mechanical polishing, grinding, or even one or more etching processes. However, any suitable process can be used to planarize the IMD 601.

[0057] Figures 8A-8B (in Figure 8A The memory cell region 503 is shown and Figure 8B The stepped region 501 illustrates the start of a patterning process for forming trenches through the memory cell region 503. In one embodiment, the process is initiated by depositing a first hard mask layer 801, which can be a material such as silicon oxynitride, silicon carbide, silicon carbide, or a combination thereof, and can be deposited using methods such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. However, any suitable material and deposition method can be used.

[0058] Figures 9A-9B ( Figure 9A Memory cell region 503 is shown. Figure 9B A stepped region 501 is shown, illustrating the formation of a first trench 901 within a multilayer stack 201. In the illustrated embodiment, the first trench 901 extends through the multilayer stack 201. The first trench 901 can be formed using acceptable photolithography and etching techniques, such as an etching process selectively applied to the multilayer stack 201 (e.g., etching the dielectric material of the first dielectric layer 201A and the second dielectric layer 201B faster than the underlying material). The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. In a particular embodiment, the first trench 901 can be formed by dry etching using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2). However, any suitable process can be used.

[0059] A portion of the multilayer stack 201 is disposed between each pair of first trenches 901. The width Wl of each portion of the multilayer stack 201 can be in the range of about 50 nm to about 500 nm (e.g., about 240 nm), and has about Figure 2The height H1 is discussed. The aspect ratio (AR) of each portion of the multilayer stack 201 is the ratio of the height H1 of that portion of the multilayer stack 201 to the width of the narrowest feature (width W1 in this processing step). According to some embodiments, the aspect ratio of each portion of the multilayer stack 201 is in the range of about 5 to about 15 when the first trench 901 is formed. Forming each portion of the multilayer stack 201 with an aspect ratio less than about 5 may not allow the memory array 52 to have sufficient memory cell density. Forming each portion of the multilayer stack 201 with an aspect ratio greater than about 15 may cause the multilayer stack 201 to be distorted or collapsed in subsequent processing.

[0060] Once the first trench 901 is formed, it is expanded to form a first sidewall recess 903. Specifically, the sidewall portion of the second dielectric layer 201B exposed by the first trench 901 is recessed from the first sidewall recess 903. Although the sidewalls of the second dielectric layer 201B are illustrated as straight, they can be concave or convex. The first sidewall recess 903 can be formed by an acceptable etching process, such as an etching process selective for the material of the second dielectric layer 201B. The etching can be isotropic. In an embodiment, the first trench 901 can be expanded by wet etching using phosphoric acid (H3PO4). However, any suitable etching process can also be used, such as selective dry etching.

[0061] Once recessed, a first conductive feature 909 is formed in the first sidewall recess 903 to fill and / or overfill the first trench 901. The first conductive feature 909 may comprise one or more layers, such as a seed layer, adhesive layer, barrier layer, and diffusion layer. In some embodiments, the first conductive feature 909 includes a seed layer 905 (or adhesive layer) and a main layer 907, but in other embodiments, the seed layer 905 may be omitted. Each seed layer 905 extends along three sides (e.g., top, sidewall, and bottom) of the material corresponding to the main layer 907 within the first sidewall recess 903. The seed layer 905 is formed of a first conductive material that can be used to aid in the growth or adhesion of subsequently deposited materials, such as titanium nitride, tantalum nitride, titanium, tantalum, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides thereof, etc. The main layer 907 may be formed of a second conductive material, such as metals like tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum nitride, titanium, titanium nitride, tantalum nitride, chromium, hafnium, platinum, tungsten nitride, and alloys thereof. In a particular embodiment where the first dielectric layer 201A is formed of an oxide such as silicon oxide, the seed layer 905 may be formed of titanium nitride and the main layer may be formed of tungsten. Both the seed layer 905 and the main layer 907 may be formed by acceptable deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0062] Once the first conductive feature 909 has been formed, the remaining portion of the first trench 901 can be filled with a first dielectric material 911 to provide additional structural support. In one embodiment, the first dielectric material 911 may be a material such as silicon oxide, formed using deposition processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or combinations thereof. However, any suitable material and method may be used.

[0063] Once the first conductive feature 909 and the first dielectric material 911 have been deposited to fill and / or overfill the first trench 901, the first conductive feature 909 and the first dielectric material 911 can be planarized to remove excess material outside the first trench 901, such that after planarization, the first conductive feature 909 and the first dielectric material 911 completely extend across the top of the first trench 901. The first conductive feature 909 and the first dielectric material 911 can be planarized using, for example, a chemical mechanical planarization (CMP) process. However, any suitable planarization process, such as a polishing process, can also be used.

[0064] Figure 9B The first conductive feature 909 is shown to be formed not only within the memory cell region 503 but also within the stepped region 501. However, in the stepped region 501, the first conductive feature 909 may be formed with a single first sidewall recess 903 only at the point shown (although additional first sidewall recesses 903 may be formed in an additional layer not shown). Therefore, the length of the first conductive feature 909 along the straight sidewall is much longer than within the memory cell region 503.

[0065] Figures 10A-10B (in Figure 10A The memory cell region 503 is shown, and Figure 10B A stepped region 501 is shown, illustrating the formation of a second trench 1001 within the multilayer stack 201. In the illustrated embodiment, the second trench 1001 extends through the multilayer stack 201. The second trench 1001 can be formed using acceptable photolithography and etching techniques, such as an etching process selectively applied to the multilayer stack 201 (e.g., etching the dielectric material of the first dielectric layer 201A and the second dielectric layer 201B at a faster rate than the material of the substrate 102). The etching can be any acceptable etching process, and in some embodiments, it can be similar to the process described above. Figure 9A and Figure 9B The etching discussed is used to form the first trench 901.

[0066] A portion of the multilayer stack 201 is disposed between each second trench 1001 and the first trench 901. The width W2 of each portion of the multilayer stack 201 can be in the range of approximately 50 nm to approximately 500 nm, and has approximately... Figure 2 The height H1 is discussed. The aspect ratio (AR) of each portion of the multilayer stack 201 is the ratio of the height H1 of that portion of the multilayer stack 201 to the width of the narrowest feature (width W2 in this processing step). According to some embodiments, the aspect ratio of each portion of the multilayer stack 201 is in the range of about 5 to about 15 when the second trench 1001 is formed. Forming each portion of the multilayer stack 201 with an aspect ratio less than about 5 may not allow the memory array 52 to have sufficient memory cell density. Forming each portion of the multilayer stack 201 with an aspect ratio greater than about 15 may cause the multilayer stack 201 to distort or collapse in subsequent processing.

[0067] Once the second trench is formed, the second trench 1001 is expanded to form the second sidewall recess 1003. Specifically, the remaining portion of the second dielectric layer 201B is removed to form the second sidewall recess 1003. The second sidewall recess 1003 thus exposes a portion of the first conductive feature 909. The second sidewall recess 1003 can be formed by an acceptable etching process, such as an etching process selectively etching the material of the second dielectric layer 201B (e.g., selectively etching the material of the second dielectric layer 201B at a faster rate than for the material of the first dielectric layer 201A). The etching can be any acceptable etching process, and in some embodiments, it can be similar to the process described above. Figure 9A and Figure 9B The etching discussed is for forming the first sidewall recess 903.

[0068] Once the second sidewall recess 1003 is formed, a second conductive feature 1009 and a second dielectric material 1011 are formed in the second sidewall recess 1003 to fill and / or overfill the second trench 1001. The second conductive feature 1009 may be formed of a material selected from the same group of candidate materials selected from the first conductive feature 909, and may be formed using a method selected from the same group of candidate methods selected for forming the material of the first conductive feature 909. The first conductive feature 909 and the second conductive feature 1009 may be formed of the same material, or may include different materials. In some embodiments, each second conductive feature 1009 includes a seed layer 1005 and a main layer 1007, but in other embodiments the seed layer 1005 may be omitted. The seed layer 1005 and the main layer 1007 of the second conductive feature 1009 may each have a similar thickness to the seed layer 905 and the main layer 907 of the first conductive feature 909. In some embodiments, seed layer 905 and seed layer 1005 are formed of similar materials. In this case, seed layer 905 and seed layer 1005 may merge during formation, such that there is no distinguishable interface between them. In other embodiments, seed layer 905 and seed layer 1005 are formed of different materials. In this case, seed layer 905 and seed layer 1005 may not merge during formation, such that there is a distinguishable interface between them.

[0069] Once the second conductive feature 1009 has been formed, the remaining portion of the second trench 1001 can be filled with the second dielectric material 1011 to provide additional structural support. In one embodiment, the second dielectric material 1011 can be a material such as silicon oxide, formed using deposition processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or combinations thereof. However, any suitable material and method can be used.

[0070] Once the second conductive feature 1009 and the second dielectric material 1011 have been deposited to fill and / or overfill the second trench 1001, the second conductive feature 1009 and the second dielectric material 1011 can be planarized to remove excess material outside the second trench 1001, such that after planarization, the second conductive feature 1009 and the second dielectric material 1011 completely extend across the top of the second trench 1001. A chemical mechanical planarization (CMP) process can be used, for example, to planarize the second conductive feature 1009 and the second dielectric material 1011. However, any suitable planarization process, such as a polishing process, can also be used.

[0071] The first conductive feature 909 and the second conductive feature 1009 are collectively referred to as word lines 1013 of the memory cell region 503. Adjacent pairs of first conductive features 909 and second conductive features 1009 are physically in contact with each other and electrically coupled to each other. Therefore, each pair of first conductive features 909 and second conductive features 1009 serves as a single word line 1013.

[0072] Figure 10B The second conductive feature 1009 is shown to be formed not only within the memory cell region 503 but also within the stepped region 501. However, in the stepped region 501, the second conductive feature 1009 may be formed with a single second sidewall recess 1003 only at the point shown (although additional sidewall recesses may be formed in an additional layer not clearly shown). Therefore, the length of the second conductive feature 1009 along the straight sidewall is much longer than that within the memory cell region 503.

[0073] Figures 11A-11B (in Figure 11A The memory cell region 503 is shown and Figure 11B The stepped region 501 illustrates an etch-back process to remove the first dielectric material 911 and the second dielectric material 1011. The etch-back process can be performed using, for example, a wet etching process or anisotropic etching process. However, any suitable etching process can be utilized.

[0074] Figures 12A-12B (in Figure 12A The memory cell region 503 is shown and Figure 12B The stepped region 501 illustrates an etch-back process to remove excess portions of the first conductive feature 909 and the second conductive feature 1009. In one embodiment, an anisotropic etching process can be used to perform the etch-back process. However, any suitable etching process can be utilized. Furthermore, for convenience, portions of the first conductive feature 909 (e.g., seed layer 905 and main layer 907) and the second conductive feature 1009 (e.g., seed layer 1005 and main layer 1007) have been merged into a single structure, labeled as the first conductive feature 909 and the second conductive feature 1009.

[0075] In one embodiment, an etch-back process is performed until the material of the first conductive feature 909 and the second conductive feature 1009 not covered by the first dielectric layer 201A is removed. Therefore, the width of the remaining material of the first conductive feature 909 and the second conductive feature 1009 is similar to the width of the remaining portion of the first dielectric layer 201A. However, any suitable size can be used.

[0076] Figure 12BThe diagram illustrates the execution of an etch-back process to pattern the first conductive feature 909 and the second conductive feature 1009, which are formed not only within the memory cell region 503 but also within the step region 501. However, since the first dielectric material 911 and the second dielectric material 1011 are removed and the first conductive feature 909 and the second conductive feature 1009 are patterned, an additional word line 1013 exists.

[0077] Figures 13A-13B (in Figure 13A The memory cell region 503 is shown, and Figure 13B The stepped region 501 illustrates the formation of a TFT thin film stack in the first trench 901 and the second trench 1001. Specifically, two ferroelectric strips 1301, a semiconductor strip 1303, and a dielectric layer 1305 are formed in each of the first trench 901 and the second trench 1001. In this embodiment, no other layers are formed in the first trench 901 and the second trench 1001. In another embodiment, additional layers may be formed in the first trench 901 and the second trench 1001.

[0078] Ferroelectric band 1301 is a data storage band formed from acceptable ferroelectric materials for storing digital values, such as hafnium zirconium oxide (HfZrO); hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO); hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), gadolinium (Gd), aluminum (Al), etc.; undoped hafnium oxide (HfO); lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), etc. The material for ferroelectric band 1301 can be formed using acceptable deposition processes, such as ALD, CVD, physical vapor deposition (PVD), etc.

[0079] Semiconductor strip 1303 is formed of an acceptable semiconductor material for providing the channel region of the TFT, such as indium tin oxide (ITO), zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), polycrystalline silicon, amorphous silicon, etc. The material of semiconductor strip 1303 can be formed by an acceptable deposition process, such as ALD, CVD, PVD, etc.

[0080] The dielectric layer 1305 is formed of a dielectric material. Acceptable dielectric materials include oxides such as silicon oxide and aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc. The material of the dielectric layer 1305 can be formed by an acceptable deposition process, such as ALD, CVD, flowable CVD (FCVD), etc.

[0081] The ferroelectric strip 1301, semiconductor strip 1303, and dielectric layer 1305 can be formed by a combination of deposition, etching, and planarization. For example, the ferroelectric layer can be conformally deposited on the multilayer stack 201 and in the first trench 901 (e.g., on the sidewalls of the first conductive feature 909 and the sidewalls of the first dielectric layer 201A). A semiconductor layer can then be conformally deposited on the ferroelectric layer. The semiconductor layer can then be anisotropically etched to remove the horizontal portions of the semiconductor layer, thereby exposing the ferroelectric layer. A dielectric layer can then be conformally deposited on the remaining vertical portions of the semiconductor layer and the exposed portions of the ferroelectric layer. A planarization process is then applied to each layer to remove excess material on the multilayer stack 201. The planarization process can be chemical mechanical polishing (CMP), etch-back, a combination thereof, etc. The remaining portions of the ferroelectric layer, semiconductor layer, and dielectric layer in the first trench 901 form the ferroelectric strip 1301, semiconductor strip 1303, and dielectric layer 1305, respectively. The planarization process exposes the multilayer stack 201, so that the top surfaces of the multilayer stack 201, ferroelectric strip 1301, semiconductor strip 1303 and dielectric layer 1305 are coplanar after the planarization process (within the range of process differences).

[0082] Figure 13B The deposition of the ferroelectric strip 1301, semiconductor strip 1303, and dielectric layer 1305 is shown to occur not only within the memory cell region 503 but also within the stepped region 501. Therefore, the ferroelectric strip 1301, semiconductor strip 1303, and dielectric layer 1305 extend into the stepped region 501 adjacent to the word line 1013.

[0083] Figures 14A-14B (in Figure 14A The memory cell region 503 is shown and Figure 14B The stepped region 501 is shown, illustrating a dielectric plug 1401 formed through the dielectric layer 1305 and semiconductor strip 1303, with the underlying bit line driver region 127 and source line driver region 129 added back to the figure. The dielectric plug 1401 is an isolation pillar to be arranged between adjacent TFTs and to physically and electrically isolate adjacent TFTs. In the illustrated embodiment, the dielectric plug 1401 does not extend through the ferroelectric strip 1301. Different regions of the ferroelectric strip 1301 can be independently polarized, so the ferroelectric strip 1301 can function as a storage value even when adjacent regions are not physically and electrically isolated. In another embodiment, the dielectric plug 1401 is also formed through the ferroelectric strip 1301. The dielectric plug 1401 further extends through the first dielectric layer 201A.

[0084] As an example of forming the dielectric plug 1401, an opening for the dielectric plug 1401 can be formed through the dielectric layer 1305 and the semiconductor strip 1303. The opening can be formed using acceptable photolithography and etching techniques. One or more dielectric materials are then formed in the opening. Acceptable dielectric materials include oxides such as silicon oxide; nitrides such as silicon nitride; carbides such as silicon carbide; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc. The dielectric material(s) can be formed by acceptable deposition processes, such as ALD, CVD, etc. In some embodiments, silicon oxide or silicon nitride is deposited in the opening. A planarization process is then applied to each layer to remove excess dielectric material(s) above the topmost first dielectric layer 201A. The planarization process can be chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc. The remaining dielectric material(s) forms the dielectric plug 1401 in the opening.

[0085] Once formed, bit lines 1403 and source lines 1405 are formed through the dielectric layer 1305. Bit lines 1403 and source lines 1405 further extend through the first dielectric layer 201A. Bit lines 1403 and source lines 1405 serve as the source / drain regions of the TFT. Bit lines 1403 and source lines 1405 are paired conductive pillars, with each semiconductor strip 1303 contacting the corresponding bit line 1403 and the corresponding source line 1405. Each TFT includes bit lines 1403, source lines 1405, word lines 1013, and regions of semiconductor strips 1303 and ferroelectric bands 1301 intersecting with the word lines 1013. Each dielectric plug 1401 is disposed between the bit line 1403 of one TFT and the source line 1405 of another TFT. In other words, bit lines 1403 and source lines 1405 are disposed on opposite sides of each dielectric plug 1401. Therefore, each dielectric plug 1401 physically and electrically isolates adjacent TFTs.

[0086] As an example of forming bit line 1403 and source line 1405, openings for bit line 1403 and source line 1405 can be formed through dielectric layer 1305 and first hard mask layer 202. Acceptable photolithography and etching techniques can be used to form the openings. Specifically, openings are formed on opposite sides of dielectric plug 1401. One or more conductive materials, such as adhesive layers and bulk conductive materials, are then formed in the openings. Acceptable conductive materials include metals such as aluminum, titanium, titanium nitride, tantalum nitride, cobalt, silver, gold, copper, nickel, chromium, hafnium, ruthenium, tungsten, platinum, tungsten nitride, combinations thereof, etc. The conductive material(s) can be formed by acceptable deposition processes (e.g., ALD or CVD), acceptable plating processes (e.g., electroplating or electroless plating, etc.). In some embodiments, tungsten is deposited in the openings. A planarization process is then applied to each layer to remove excess conductive material(s) above the topmost first dielectric layer 201A. The planarization process can be chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc. The remaining conductive material (one or more) forms bit lines 1403 and source lines 1405 in the opening.

[0087] Figure 14B As shown, although the dielectric plug 1401, bit line 1403, and source line 1405 are formed within the memory cell region 503, no similar structure is formed within the step region 501. Therefore, the structure within the step region 501 is not modified.

[0088] Figures 15A-15B (in Figure 15A The memory cell region 503 is shown, and Figure 15B The stepped region 501 shows an interconnect structure 1501 formed over the topmost first dielectric layer 201A. The interconnect structure 1501 may include, for example, a metallization pattern in the dielectric, wherein, for clarity, Figure 15A Only the conductive characteristics of interconnect structure 1501 are shown. The dielectric material may include one or more dielectric layers, such as one or more low-k (LK) or ultra-low-k (ELK) dielectric materials. The metallization pattern may be a metal interconnect comprising metal lines formed in one or more dielectric layers (see below for details). Figure 15C (Further discussion) and conductive via 1517. The interconnect structure 1501 can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

[0089] Figure 15B As shown, although the interconnect structure 1501 is formed within the memory cell region 503, no similar structure is formed within the stepped region 501. Therefore, the structure within the stepped region 501 is not modified.

[0090] Figure 15C A top-down view of the interconnect structure 1501 over the memory cell region 503 is shown (where bit lines and source lines are partially transparent for clarity). In some embodiments, and as shown, the interconnect structure 1501 and the underlying structure include a memory array region 1503 and a connection region 1505 positioned along the outer edge of the memory array region 1503. In one embodiment, the memory array region 1503 includes a TFT array, where each TFT is a ferroelectric random access memory (FeRAM) cell for storing data, and the memory array region 1503 additionally includes portions of the interconnect structure 1501 for providing electrical connections to the bit lines 1403 and the source lines 1405 for reading and / or writing to the individual memory cells.

[0091] In one particular embodiment, interconnect structure 1501 includes a series of bit lines (e.g., first bit line 1506, second bit line 1507, third bit line 1509, fourth bit line 1511, fifth bit line 1513, and sixth bit line 1515) formed as conductive lines within interconnect structure 1501, and also includes conductive vias 1517 for connecting individual memory cells to the bit line series. Furthermore, interconnect structure 1501 includes a series of source lines (e.g., first source line 1519, second source line 1521, third source line 1523, fourth source line 1525, fifth source line 1527, and sixth source line 1529), also formed as conductive lines within interconnect structure 1501, and also includes conductive vias 1517 for connecting individual memory cells to the source line series.

[0092] However, while the connection region 1505 includes the same structure as the memory cell region 503, it is used to provide electrical connections between the memory cells within the memory cell region 503 and the underlying bit line drivers (e.g., within the bit line driver region 127) and the source line drivers located below the memory cell region 503 and the connection region 1505 (e.g., within the source line driver region 129). Specifically, the connection region 1505 (using the same structure as the TFTs formed within the memory array region 1503) uses power line 1405 and bit line 1403 to connect the memory cells within the memory cell region 503 to the CMOS devices located below the memory region design (e.g., in a CuA configuration).

[0093] To provide this connection, bit line 1403 and source line 1405 located within connection region 1505 are connected to the fifth dielectric layer 123 (see...). Figure 1A-Figure 1BThe fifth metal layer 125 (e.g., vias) within the memory array region 1505 is physically contacted with each metal layer therein. Specifically, since the vias within the fifth metal layer 125 are already located in the connection region 1505, when openings for bit lines 1403 and source lines 1405 are formed, the vias within the fifth metal layer 125 in the connection region 1505 will also be exposed (although the openings for bit lines 1403 and source lines 1405 formed in the memory array region 1503 will expose the fifth dielectric layer 123), and the material of the bit lines 1403 and source lines 1405 will be deposited to physically contact the vias within the fifth metal layer 125. Therefore, the bit lines 1403 and source lines 1405 located in the connection region 1505 are used as conductive vias, even though the structure of the bit lines 1403 and source lines 1405 is the same as the structure of the bit lines 1403 and source lines 1405 in the memory cell region 503.

[0094] By using bit lines 1403 and source lines 1405 to provide connections, the same structure (except for the presence of a fifth metal layer 125) can be used to store data (e.g., where the TFT is located within the memory array region 1503) and also to provide electrical connections through the memory array (e.g., where the same structure is located within the connection region 1505). This identical structure allows the structure to be formed simultaneously using the same process, and eliminates the need for separate processes to form the required connections, such as through-holes.

[0095] Figure 15D It shows along Figure 15C A cross-sectional view of the memory array region 1503 and the connection region 1505 of line D-D' in the diagram. It can be seen that the memory cells are connected to the active device 103 in the source line driver region 129 (e.g., connected to the source line driver) through the first of the conductive vias 1517, the first source line 1519, the second of the conductive vias 1517, the source line 1405 adjacent to the semiconductor strip 1303 in the connection region 1505, the fifth metal layer 125, and the remaining metallization layers 110.

[0096] Figure 15E It shows along Figure 15C A cross-sectional view of the memory array region 1503 and the connection region 1505 of the E-E' line. It can be seen that the memory cell is connected to the active device 103 in the source line driver region 129 (e.g., connected to the source line driver) through the first and second source lines 1521 in the conductive via 1517, the second source line 1405 adjacent to the semiconductor strip 1303 in the connection region 1505, the fifth metal layer 125, and the remaining metallization layer 110.

[0097] Figure 15F It shows along Figure 15CA cross-sectional view of the memory array region 1503 and the connection region 1505 along line F-F'. It can be seen that the memory cells are connected to the active device 103 within the bit line driver region 127 (e.g., connected to a bit line driver) via the first of the conductive vias 1517, the first bit line 1506, the second of the conductive vias 1517, the bit line 1403 adjacent to the semiconductor strip 1303 in the connection region 1505, the fifth metal layer 125, and the remaining metallization layers 110.

[0098] Figure 15G A cross-sectional view of the memory array region 1503 and the connection region 1505 along line G-G' adjacent to semiconductor strip 1303 is shown. It can be seen that the memory cells are connected to the active device 103 within the bit line driver region 127 (e.g., connected to a bit line driver) via the first and second bit lines 1507 in the conductive vias 1517, the second bit line 1403 in the connection region 1505 adjacent to semiconductor strip 1303, the fifth metal layer 125, and the remaining metallization layers 110.

[0099] Once the interconnect structure 1501 has been formed to interconnect the memory cells with the driver, additional processing can be performed. For example, in one embodiment, it can be fabricated to the stepped region (see example) by forming openings through the IMD 601 and filling these openings with one or more conductive materials. Figure 15B The conductive contacts of each word line 1013 in the (not shown separately). However, any suitable additional treatment may be used.

[0100] Figure 16 Another embodiment is shown, wherein the connection region 1505 is not located at the edge of the memory array region 1503 (e.g., Figures 15A-15G (As shown), instead of being located in the center region of the memory array region 1503, it is located in the central region of the memory array region 1503. Thus, the discrete portions of the memory array region 1503 are located on multiple sides of the connection region 1505. However, any suitable arrangement of the connection region 1505 can be utilized simply by moving the position of the fifth metal layer 125.

[0101] By using the same structure to form the TFTs for the memory cells and the vias for connecting the TFTs to the underlying devices located below the memory array, a synchronous process can be used to form both the TFTs and the electrical connections. By employing a synchronous process, the formation of the memory cells and vias shares the same photolithographic mask, and the use of additional masks and processes to form the vias can be avoided, thus simplifying and reducing the overall cost of the process. Furthermore, by placing the drivers below the memory array instead of placing them at the outer edge of the memory array, the overall device footprint can be reduced, resulting in a smaller device.

[0102] According to one embodiment, a method of manufacturing a semiconductor device includes: forming a source line driver on a semiconductor substrate; forming a first metallization layer over the source line driver; directly depositing a multilayer stack on the first metallization layer; forming a ferroelectric random access memory (RAM) cell within the multilayer stack; and simultaneously forming a via leading to the first metallization layer along with the ferroelectric RAM cell. In one embodiment, the method further includes: forming a second metallization layer over the ferroelectric RAM cell, the second metallization layer electrically connecting the source line driver to the ferroelectric RAM cell through the via. In one embodiment, the method further includes: forming a bit line driver on the semiconductor substrate prior to forming the first metallization layer. In one embodiment, the method further includes: forming a second via leading to the first metallization layer, the second via being formed simultaneously with the ferroelectric RAM cell. In one embodiment, after forming the via, the via is adjacent to the semiconductor layer. In one embodiment, after forming the via, the semiconductor layer is adjacent to the ferroelectric layer. In one embodiment, the method further includes: forming a dielectric layer over a first metallization layer; forming a via through the dielectric layer, wherein the dielectric layer isolates the ferroelectric random access memory cell from the first metallization layer, and the via is electrically connected to the first metallization layer through the via.

[0103] According to another embodiment, a method of manufacturing a semiconductor device includes: depositing a multilayer stack on a semiconductor substrate, wherein an active device array is formed directly beneath the multilayer stack; patterning the multilayer stack to form a first opening and a second opening, the first opening exposing a dielectric material and the second opening exposing a conductive portion of a metallization layer connected to the active device array; replacing some layers of the multilayer stack to form word lines; depositing a ferroelectric layer along the sidewalls of the first and second openings; depositing a semiconductor layer in the first and second openings adjacent to the ferroelectric layer; depositing a second dielectric material to fill the remaining portions of the first and second openings; planarizing the second dielectric material down to the multilayer stack; and forming a conductive material extending through the second dielectric material, the conductive material being in physical contact with a conductive portion of the metallization layer. In one embodiment, the method further includes: forming a second metallization layer on the conductive material to electrically connect a first portion of the conductive material within one of the first openings to a second portion of the conductive material within one of the second openings. In one embodiment, a first plurality of active device arrays is part of a bit line driver. In one embodiment, a second plurality of active device arrays is part of a source line driver. In one embodiment, the second opening is positioned along an edge of a memory array. In one embodiment, the second opening is located within the memory array. In another embodiment, the ferroelectric layer is part of a ferroelectric random access memory cell.

[0104] In yet another embodiment, a semiconductor device includes: a bit line driver located on a semiconductor substrate; a first metallization layer on the bit line driver, the first metallization layer comprising a dielectric material; a ferroelectric random access memory (RAM) array on the first metallization layer, wherein each memory cell within the RAM array comprises a ferroelectric material, a semiconductor material, and a conductive material; and a via electrically connected to the first metallization layer, the via being adjacent to the ferroelectric material and the semiconductor material. In one embodiment, the semiconductor device further includes a second metallization layer on the memory cells. In one embodiment, the second metallization layer electrically connects the via to the memory cells of the RAM array. In one embodiment, the via is positioned along the edge of the RAM array. In one embodiment, the via is located at the center of the RAM array. In one embodiment, the bit line driver is located directly below the via.

[0105] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention.

[0106] Example

[0107] Example 1. A method for manufacturing a semiconductor device, the method comprising: forming a source line driver on a semiconductor substrate; forming a first metallization layer on the source line driver; directly depositing a multilayer stack on the first metallization layer; forming a ferroelectric random access memory cell within the multilayer stack; and simultaneously forming a via leading to the first metallization layer with the ferroelectric random access memory cell.

[0108] Example 2. The method according to Example 1 further includes: forming a second metallization layer on the ferroelectric random access memory cell, the second metallization layer electrically connecting the source line driver to the ferroelectric random access memory cell through the via.

[0109] Example 3. The method according to Example 1 further includes: forming a bit line driver on the semiconductor substrate prior to forming the first metallization layer.

[0110] Example 4. The method according to Example 1 further includes: forming a second via leading to the first metallization layer, the second via being formed simultaneously with the ferroelectric random access memory cell.

[0111] Example 5. The method according to Example 1, wherein after the via is formed, the via is adjacent to the semiconductor layer.

[0112] Example 6. The method according to Example 5, wherein, after the via is formed, the semiconductor layer is adjacent to the ferroelectric layer.

[0113] Example 7. The method according to Example 1 further includes: forming a dielectric layer on the first metallization layer; and forming a via through the dielectric layer, wherein the dielectric layer isolates the ferroelectric random access memory cell from the first metallization layer, and the via is electrically connected to the first metallization layer through the via.

[0114] Example 8. A method of manufacturing a semiconductor device, the method comprising: depositing a multilayer stack on a semiconductor substrate, wherein an array of active devices is formed directly beneath the multilayer stack; patterning the multilayer stack to form a first opening and a second opening, the first opening exposing a dielectric material and the second opening exposing a conductive portion of a metallization layer connected to the array of active devices; replacing some layers of the multilayer stack to form word lines; depositing a ferroelectric layer along the sidewalls of the first and second openings; depositing a semiconductor layer in the first and second openings adjacent to the ferroelectric layer; depositing a second dielectric material to fill the remaining portions of the first and second openings; planarizing the second dielectric material down to the multilayer stack; and forming a conductive material extending through the second dielectric material, the conductive material being in physical contact with a conductive portion of the metallization layer.

[0115] Example 9. The method according to Example 8 further includes: forming a second metallization layer on the conductive material to electrically connect a first portion of the conductive material within one of the first openings to a second portion of the conductive material within one of the second openings.

[0116] Example 10. The method according to Example 8, wherein the first plurality of active device arrays in the active device array is part of a bit line driver.

[0117] Example 11. The method according to Example 10, wherein the second plurality of active device arrays in the active device array is part of a source line driver.

[0118] Example 12. The method according to Example 8, wherein the second opening is positioned along the edge of the memory array.

[0119] Example 13. The method according to Example 8, wherein the second opening is located within the memory array.

[0120] Example 14. The method according to Example 8, wherein the ferroelectric layer is part of a ferroelectric random access memory cell.

[0121] Example 15. A semiconductor device comprising: a bit line driver located on a semiconductor substrate; a first metallization layer on the bit line driver, the first metallization layer comprising a dielectric material; a ferroelectric random access memory array on the first metallization layer, wherein each memory cell in the ferroelectric random access memory array comprises a ferroelectric material, a semiconductor material, and a conductive material; and a via electrically connected to the first metallization layer, the via being adjacent to the ferroelectric material and the semiconductor material.

[0122] Example 16. The semiconductor device according to Example 15 further includes a second metallization layer on the memory cell.

[0123] Example 17. The semiconductor device according to Example 16, wherein the second metallization layer electrically connects the via to a memory cell in the ferroelectric random access memory array.

[0124] Example 18. The semiconductor device according to Example 15, wherein the via is positioned along the edge of the ferroelectric random access memory array.

[0125] Example 19. The semiconductor device according to Example 15, wherein the via is located at the center of the ferroelectric random access memory array.

[0126] Example 20. A semiconductor device according to Example 15, wherein the bit line driver is located directly below the via.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A source line driver is formed on a semiconductor substrate; A first metallization layer is formed on the source line driver; Multiple layers are directly deposited on top of the first metallization layer; Ferroelectric random access memory cells are formed within the multilayer stack; and A via is formed simultaneously with the ferroelectric random access memory cell to lead to the first metallization layer.

2. The method according to claim 1, further comprising: A second metallization layer is formed on the ferroelectric random access memory cell, and the second metallization layer electrically connects the source line driver to the ferroelectric random access memory cell through the via.

3. The method according to claim 1, further comprising: A bit line driver is formed on the semiconductor substrate prior to the formation of the first metallization layer.

4. The method according to claim 1, further comprising: A second via is formed leading to the first metallization layer, and the second via is formed simultaneously with the ferroelectric random access memory cell.

5. The method according to claim 1, wherein, After the via is formed, the via is adjacent to the semiconductor layer.

6. The method according to claim 5, wherein, After the via is formed, the semiconductor layer is adjacent to the ferroelectric layer.

7. The method according to claim 1, further comprising: A dielectric layer is formed on top of the first metallization layer; and A via is formed through the dielectric layer, wherein the dielectric layer isolates the ferroelectric random access memory cell from the first metallization layer, and the via is electrically connected to the first metallization layer through the via.

8. A method for manufacturing a semiconductor device, the method comprising: A multilayer stack is deposited on a semiconductor substrate, wherein an active device array is formed directly beneath the multilayer stack; The multilayer stack is patterned to form a first opening and a second opening, the first opening exposing a dielectric material and the second opening exposing a conductive portion of a metallization layer connected to the active device array. Replace some layers of the multi-layer stack to form word lines; Ferroelectric layers are deposited along the sidewalls of the first and second openings; A semiconductor layer is deposited in the first opening and the second opening so that it is adjacent to the ferroelectric layer; Deposit a second dielectric material to fill the remaining portions of the first opening and the second opening; The second dielectric material is planarized until the multilayer stack is reached; and A conductive material is formed that extends through the second dielectric material, and the conductive material is in physical contact with the conductive portion of the metallization layer.

9. The method according to claim 8, further comprising: A second metallization layer is formed on the conductive material to electrically connect a first portion of the conductive material within one of the first openings to a second portion of the conductive material within one of the second openings.

10. The method according to claim 8, wherein, The first plurality of active device arrays in the active device array are part of a bit line driver.

11. The method according to claim 10, wherein, The second plurality of active device arrays in the active device array is part of the source line driver.

12. The method according to claim 8, wherein, The second opening is positioned along the edge of the memory array.

13. The method according to claim 8, wherein, The second opening is located within the memory array.

14. The method according to claim 8, wherein, The ferroelectric layer is part of a ferroelectric random access memory cell.

15. A semiconductor device, comprising: Bit line drivers are located on a semiconductor substrate; A first metallization layer above the bit line driver, the first metallization layer comprising a dielectric material; A ferroelectric random access memory array above the first metallization layer, wherein each memory cell within the ferroelectric random access memory array comprises a ferroelectric material, a semiconductor material, and a conductive material; and A via, electrically connected to the first metallization layer, is adjacent to both the ferroelectric material and the semiconductor material. The bit line driver is located directly below the via.

16. The semiconductor device of claim 15, further comprising a second metallization layer on the memory cell.

17. The semiconductor device according to claim 16, wherein, The second metallization layer electrically connects the via to the memory cells in the ferroelectric random access memory array.

18. The semiconductor device according to claim 15, wherein, The via is positioned along the edge of the ferroelectric random access memory array.

19. The semiconductor device according to claim 15, wherein, The via is located at the center of the ferroelectric random access memory array.

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