Image sensor and method of forming the same

Abstract

A metal grid within a trench isolation structure on a backside of an image sensor is coupled to a contact pad such that a voltage on the metal grid continuously varies with a voltage on the contact pad. One or more conductive structures directly couple the metal grid to the contact pad. The conductive structures can bypass a frontside of the image sensor. A bias voltage on the metal grid can be changed through the contact pad, whereby a tradeoff between reducing cross talk and increasing quantum efficiency can be dynamically adjusted according to an application of the image sensor, its usage environment, or its mode of operation. Embodiments of the present application also relate to image sensors and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to image sensors and methods of forming the same. Background Technology

[0002] Integrated circuits (ICs), including image sensors, are widely used in modern electronic devices such as cameras and mobile phones. Complementary metal-oxide-semiconductor (CMOS) devices have become popular IC image sensors. Compared to charge-coupled devices (CCDs), CMOS image sensors (CIS) are increasingly favored due to their low power consumption, small size, fast data processing speed, direct data output, and low manufacturing cost. As IC dimensions shrink, small pixel sizes in CMOS devices are desirable. For smaller pixel sizes, crosstalk between pixels can be a problem, where unique solutions can improve the performance of CIS with small pixel sizes. Summary of the Invention

[0003] Some embodiments of this application provide an image sensor, including: a semiconductor substrate including a front side, a back side, a pixel region, and a peripheral region; photodetector pixels located in an array within the pixel region; a back-side isolation structure extending into the back side between the photodetector pixels, the back-side isolation structure including a metal grid in the substrate and a dielectric pad separating the metal grid in the substrate from the semiconductor substrate; contact pads located in the peripheral region; and one or more conductive structures directly coupling the metal grid in the substrate to the contact pads.

[0004] Other embodiments of this application provide an image sensor, including: a semiconductor substrate including a front side, a back side, a pixel region, and a peripheral region; photodetector pixels located in an array within the pixel region; a back-side isolation structure extending to the back side and located between adjacent pairs of the photodetector pixels; and contact pads; wherein the back-side isolation structure includes a metal grid in the substrate and a dielectric pad separating the metal grid in the substrate from the semiconductor substrate; and the metal grid in the substrate is coupled to the contact pads such that the voltage on the metal grid in the substrate changes continuously with the voltage on the contact pads.

[0005] Further embodiments of this application provide a method for forming an image sensor, comprising: providing a semiconductor substrate including a front side, a back side, a pixel region, a peripheral region, and photodetector pixels in an array within the pixel region; forming a back-side isolation structure including a metal grid having segments extending into the semiconductor substrate between the photodetector pixels; and forming contact pads on the back side; wherein the metal grid is coupled to the contact pads. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A A cross-sectional side view of an IC device is shown in accordance with some aspects of this teaching.

[0008] Figure 1B It shows the use of Figure 1A The layout of IC devices.

[0009] Figure 1C It shows Figure 1A The structure of the IC device, in which the metal grid in the substrate is coupled to the contact pads.

[0010] Figure 1D The diagram illustrates a metal grid in a substrate and the coupling of the metal grid in the substrate to... Figure 1A The layout of the contact pad structure in IC devices.

[0011] Figure 2A A cross-sectional side view of an IC device is shown in accordance with some aspects of this teaching.

[0012] Figure 2B A cross-sectional side view of an IC device is shown in accordance with some aspects of this teaching.

[0013] Figure 3A A cross-sectional side view of an IC device is shown in accordance with some aspects of this teaching.

[0014] Figure 3B It shows the use of Figure 3A Possible layouts of IC devices.

[0015] Figure 3C It shows Figure 3A The structure of the IC device, in which the metal grid in the substrate is coupled to the contact pads.

[0016] Figure 3D The diagram illustrates a metal grid in a substrate and the coupling of the metal grid in the substrate to... Figure 3A The layout of the contact pad structure in IC devices.

[0017] Figure 4 A cross-sectional side view of an IC device is shown in accordance with some aspects of this teaching.

[0018] Figure 5 A cross-sectional side view of an IC device is shown in accordance with some aspects of this teaching.

[0019] Figure 6AA cross-sectional side view of an IC device is shown in accordance with some aspects of this teaching.

[0020] Figure 6B It shows the use of Figure 6A Possible layouts of IC devices.

[0021] Figure 6C It shows Figure 6A The structure of the IC device, in which the metal grid in the substrate is coupled to the contact pads.

[0022] Figure 6D The diagram illustrates a metal grid in a substrate and the coupling of the metal grid in the substrate to... Figure 6A The layout of the contact pad structure in IC devices.

[0023] Figure 7A , Figure 7B and Figures 8 to 33 These are a series of cross-sectional views illustrating methods for forming IC devices.

[0024] Figures 34 to 40 This is an example. Figure 7A , Figure 7B and Figures 8 to 33 A series of cross-sectional diagrams showing the changes in the method.

[0025] Figures 41 to 46 This is an example. Figure 7A , Figure 7B and Figures 8 to 33 A series of cross-sectional diagrams showing the changes in the method.

[0026] Figures 47 to 48 This is an example. Figures 41 to 46 A series of cross-sectional diagrams showing the changes in the method.

[0027] Figures 49 to 52 This is an example. Figures 41 to 46 A series of cross-sectional diagrams showing the changes in the method.

[0028] Figures 53 to 56 This is an example. Figures 41 to 46 A series of cross-sectional diagrams showing the changes in the method.

[0029] Figures 57 to 58 This is an example. Figures 53 to 56 A series of cross-sectional diagrams showing the changes in the method.

[0030] Figures 59 to 64 This is an example. Figure 7A , Figure 7B and Figures 8 to 33 A series of cross-sectional diagrams showing the changes in the method.

[0031] Figures 65 to 67 This is a flowchart of the manufacturing process based on various aspects of this teaching.

[0032] Figures 68 to 71 This is a flowchart of the operating methods for each aspect of this teaching. Detailed Implementation

[0033] This invention provides numerous different embodiments or instances for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0034] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0035] Some image sensors designed for back-illuminated (BSI) systems are integrated circuit devices (ICs) that include an array of photodetector pixels arranged within a semiconductor substrate and a back-side isolation structure. The back-side isolation structure includes a grid of straight or curved segments extending into the back side of the semiconductor substrate and located between adjacent photodetector pixels. The grid may include square or ring-shaped elements surrounding individual photodetector pixels. The back-side isolation structure reduces crosstalk between photodetector pixels. However, crosstalk can remain significant and increases as the spacing between the photodetector pixel arrays decreases.

[0036] Crosstalk can be further reduced by incorporating a metal grid into a back-side isolation structure and applying a suitable bias voltage to the metal grid. The metal grid in the substrate is separated from the semiconductor substrate by one or more dielectric layers. The metal grid may be referred to herein as a "metal grid in the substrate" to emphasize that the metal grid extends into the semiconductor substrate between adjacent photodetector pixels, and to distinguish it from a type of back-side metal grid that is entirely outside the semiconductor substrate. A suitable bias voltage is negative for p-type semiconductor substrates and zero or positive for n-type semiconductor substrates. The bias voltage reduces crosstalk; however, it also reduces the quantum efficiency for image sensors. Therefore, a trade-off must be struck between reducing crosstalk and increasing quantum efficiency when selecting the bias voltage.

[0037] The bias voltage can be provided by appropriate circuitry within the IC device. However, according to this teaching, the IC device is configured for external analog control of the bias voltage on a metal grid in the substrate. In some embodiments, the metal grid in the substrate is coupled to contact pads such that the voltage on the metal grid in the substrate varies continuously with the voltage on the contact pads. In some embodiments, one or more conductive structures directly couple the metal grid in the substrate to the contact pads. In some embodiments, one or more conductive structures are metal. These structures enable external control of the bias voltage on the metal grid in the substrate, thereby dynamically adjusting the tradeoff between reducing crosstalk and increasing quantum efficiency according to the application of the IC device, its operating environment, or its operating mode.

[0038] In some embodiments, a metal grid in the substrate is coupled to a back-side contact pad via a connection that bypasses the front side of the substrate. This configuration helps maintain the voltage on the metal grid in the substrate close to the voltage on the contact pads. In some embodiments, the back-side contact pads are formed simultaneously with a type of back-side metal grid that is entirely outside the semiconductor substrate and comprise the same metal as the type of back-side metal grid outside the semiconductor substrate. This configuration simplifies manufacturing. In some embodiments, the back-side contact pads are formed opposite unused contact pads near the front side of the substrate. This allows the contact pads used for the metal grid in the substrate to use a structure substantially the same as the contact pads formed with the front-side connection.

[0039] In some embodiments, a metal grid in the substrate is coupled to a back-side contact pad via a metal interconnect on the front side of the substrate. Specifically, the connection may include metal pads within the metal interconnect that are electrically isolated from other circuitry. In some embodiments, the contact metal pads are located within the M1 metallization layer of the metal interconnect structure. The connection from the metal grid in the substrate to the metal interconnect may include a back-side substrate via (TSV). This structure allows the use of a class of standard contact pads that form connections with the metal interconnect.

[0040] In some embodiments, a metal grid in the substrate is coupled to a back-side TSV via conductive bridges formed on the back side. In these embodiments, the conductive bridges and the back-side TSV can be formed simultaneously. Therefore, in some embodiments, the conductive bridges and the back-side TSV are an integral structure of a single material. This allows for a simplified manufacturing process.

[0041] In some embodiments, the metal grid in the substrate includes an extension intersecting with a back-side TSV within the semiconductor substrate. In these embodiments, the metal grid in the substrate and the back-side TSV can be formed simultaneously. Therefore, in some embodiments, the metal grid in the substrate and the back-side TSV are a monolithic structure of a single material. This allows for a simplified manufacturing process and allows the connection between the metal grid in the substrate and the back-side TSV to have a relatively large thickness.

[0042] In some embodiments, the back-side TSV extends into the front side. In some embodiments, the back-side TSV encounters metal pads or similar structures in a metal interconnect. In some other embodiments, the back-side TSV extends only partially through the substrate and the connection to the front side is accomplished by another structure. In some embodiments, this other structure is or includes the front-side TSV. In some embodiments, this other structure includes a heavily doped region of the semiconductor substrate. These structures allow the back-side TSV to have a lower aspect ratio, thereby simplifying its formation. In some embodiments, the back-side TSV has a hollow core. The hollow core allows the back-side TSV to form with less metal deposition.

[0043] In some embodiments, the bias voltage on the metal grid in the substrate is selected based on the application for the photodetector. Contact pads may be coupled to an external source that provides a predetermined bias voltage based on the application selection. In some embodiments, the bias voltage on the metal grid in the substrate is selected based on the operating mode of the photodetector. The operating mode may be user-selectable, and the bias voltage varies accordingly. In some embodiments, the bias voltage is selected based on the usage environment. For example, the bias voltage may be selected based on sensed temperature or ambient light levels. In some embodiments, the bias voltage is dynamically selected in a feedback control loop. The control loop may adjust the bias voltage according to a criterion that balances crosstalk and quantum efficiency.

[0044] Figure 1A A cross-section of an image sensing IC device 100A according to some aspects of this teaching is shown. The IC device 100A includes a first semiconductor substrate 107 having a pixel region 114 and a peripheral region 112. The peripheral region 112 may include an inner peripheral region 112A, a middle peripheral region 112B, and an outer peripheral region 112C. Figure 1BA top view of IC device 100A is provided, showing a possible layout of these areas on IC device 100A. Photodetector pixel 126 may be disposed in pixel area 114 and contact pad 103A may be disposed in outer peripheral area 112C.

[0045] The photodetector pixel 126 may include a photodiode or the like formed within the first semiconductor substrate 107. A floating diffusion region 123 may be coupled to the photodetector pixel 126 via a transfer gate 122. A front isolation structure 125 may be configured adjacent to the floating diffusion region 123. Although only one transfer gate 122 is shown for each photodetector pixel 126, multiple gates may be associated with each photodetector pixel 126.

[0046] The back-side isolation structure 134A includes a segment 135 extending from the back side 101 into the first semiconductor substrate 107 and located between adjacent photodetector pixels 126. The back-side isolation structure 134A and its segment 135 include a substrate metal grid 133A separated from the first semiconductor substrate 107 by a dielectric pad structure 131 that may include a high-k pad 128 and a second dielectric pad 129. Applying a negative bias voltage to the substrate metal grid 133A creates an aperture 132 in the first semiconductor substrate 107, which increases the electrical isolation between adjacent photodetector pixels 126 if the first semiconductor substrate 107 is p-type.

[0047] The metal grid 133A in the substrate includes a segment 153A that extends from the pixel region 114 and into the inner peripheral region 112A. The segment 153A has the same structure as the segment 135. Figure 1A The cross section along Figure 1D The line A-A' shown in the diagram. Line A-A' is... Figure 1D The curve bends at point B-B', and point B-B' is Figure 1A The line B-B'. Due to this bend, Figure 1A The cross-sectional view shows most of the length of segment 135, but extends along the length of segment 153A.

[0048] The back-side TSV 157A extends from the back side 101 through the first semiconductor substrate 107 to the front side 108. The back-side TSV 157A is a back-side TSV because it is formed on the back side 101, and as can be clearly seen from the back side, the TSV 157A becomes narrower as it extends from the back side 101 to the front side 108. The back-side TSV 157A is separated from the first semiconductor substrate 107 by a dielectric pad 159 and coupled to a metal grid 133A in the substrate via a conductive bridge 155A on the back side 101.

[0049] A conductive bridge 155A is situated above a first semiconductor substrate 107. In some embodiments, the conductive bridge 155A is situated above a back-side TSV 157A and a metal grid 133A in the substrate. In some embodiments, the conductive bridge 155A and the back-side TSV 157A comprise an integral structure of one component. In some embodiments, the conductive bridge 155A is separated from the first semiconductor substrate 107 at least by a dielectric layer of the dielectric pad structure 131. The conductive bridge 155A may be further separated from the first semiconductor substrate 107 by one or more of a high-k capping layer 137, a second capping layer 138, or thicker versions of these layers, to the extent that they are part of the dielectric pad structure 131. In some embodiments, the conductive bridge 155A is embedded within a thick oxide layer 139. In some embodiments, the conductive bridge 155A and the thick oxide layer 139 have the same thickness.

[0050] The back-side TSV 157A is coupled to the contact pad 103A via a first metal interconnect 109 disposed on the front side 108. In some embodiments, the connection is made via a metal pad 163 within the first metal interconnect 109. Figure 1C As shown, metal pad 163, backside TSV 157A, and conductive bridge 155A together directly couple contact pad 103A to metal grid 133A in the substrate, thereby causing the voltage on metal grid 133A in the substrate to continuously change with the voltage 171 applied to contact pad 103A. The negative bias voltage applied to contact pad 103A will result in a negative voltage on metal grid 133A in the substrate exhibiting a voltage-to-voltage analog relationship.

[0051] The metal grid 133A in the substrate can have any suitable composition. In some embodiments, the metal grid 133A in the substrate includes aluminum (Al), tungsten (W), etc. Aluminum and tungsten have the advantage of being easily deposited in high aspect ratio openings. Aluminum (Al) is particularly suitable for the metal grid 133A in the substrate due to its high conductivity.

[0052] The conductive bridge 155A can have any suitable composition. In some embodiments, the conductive bridge 155A includes copper (Cu), aluminum (Al), etc. Copper (Cu) and aluminum (Al) have high conductivity that allows the conductive bridge 155A to be relatively thin. Copper (Cu) is particularly suitable due to its high conductivity.

[0053] Return to Figure 1AContact pad 103A may be disposed in the first semiconductor substrate 107 near the front side 108 and spaced apart from the back side 101 by pad dielectric 102. Pad dielectric 102 may be covered by a sealing layer 145. Access from the back side 101 to contact pad 103A may be provided by an opening 165A extending through the sealing layer 145 and the pad dielectric 102. Sealing layer 145 may have a concave surface 167A that facilitates bonding to contact pad 103A through opening 165A. Contact pad 103A may be considered a back-side contact pad because it is open to the back side 101 and adapted for bonding on the back side 101; however, contact pad 103A is close to the front side 108 and may extend into the first interlayer dielectric 120 on the front side 108.

[0054] Color filter 146 and microlens 147 can be positioned directly above photodetector pixel 126. Composite grid 149 can be positioned directly above back-side isolation structure 134A and between color filter 146. Composite grid 149 may include back-side metal grid 141, dielectric grid 142, and hard mask grid 143. Sealing layer 145 may extend above composite grid 149. Back-side metal grid 141 reflects photons and improves optical separation between photodetector pixels 126.

[0055] like Figure 1A and Figure 1B As shown, a portion 141A of the back metal grid 141 extends laterally from the pixel region 114 to the inner peripheral region 112A. Within the inner peripheral region 112A, the back metal grid 141 has a grounding bar 141B extending into the first semiconductor substrate 107 to ground the back metal grid 141. Like the back metal grid 141, the in-substrate metal grid 133A extends across the pixel region 114 and into the inner peripheral region 112A, but the back metal grid 141 and the in-substrate metal grid 133A never contact each other. The grounding bar 141B is located in the inner peripheral region 112A at a position different from that of the segment 153A of the back metal grid 141 and different from that of the conductive bridge 155A. The back TSV 157A may be located in the middle peripheral region 112B, and the contact pad 103A may be located in the outer peripheral region 112C.

[0056] In addition to the first semiconductor substrate 107 and the first metal interconnect 109, the IC device 100A may include a second semiconductor substrate 111 and a second metal interconnect 110. A plurality of logic gates 113 may be disposed on the second semiconductor substrate 111. The second semiconductor substrate 111, the second metal interconnect 110, and related devices may be manufactured separately from the first semiconductor substrate 107 and may provide image signal processing (ISP) circuitry, read and / or write circuitry, or other suitable circuitry for the operation of the photodetector pixel 126.

[0057] The first metal interconnect 109 includes a first wiring 121 and a first via 119 in a first interlayer dielectric 120. These can be arranged as multiple metallization layers, which can be referred to as M1 metallization layer, M2 metallization layer, etc., in order of their distance from the first semiconductor substrate 107. Any first wiring 121 at the height of the transfer gate 122 can be referred to as the M0 metallization layer. The second metal interconnect 110 includes a second wiring 115 and a second via 118 in a second interlayer dielectric 117. The connection between the back-side TSV 157A and the contact pad 103A is shown as being formed in the M1 metallization layer; however, this connection can be formed anywhere in the first metal interconnect 109 or the second metal interconnect 110, or can be formed using both the first metal interconnect 109 and the second metal interconnect 110. The connection between the back-side TSV 157A and the contact pad 103A is isolated from other circuitry formed in the first metal interconnect 109 or the second metal interconnect 110.

[0058] Figure 2A Image sensing IC device 100B according to some other aspects of this teaching is shown. IC device 100B differs from IC device 100A in that IC device 100B has a front-side TSV 160 opposite to the back-side TSV 157B. (The image of the back-side TSV 157B is shown.) Figure 1A Similar to the back-side TSV 157A, except that the back-side TSV 157B extends only halfway through the first semiconductor substrate 107. The conductive bridge 155A and the back-side TSV 157B can be formed simultaneously and can be a monolithic structure of one material. The front-side TSV 160 completes the connection between the back-side TSV 157B and the metal pads 163 or similar structures in the first metal interconnect 109 or the second metal interconnect 110. The front-side TSV 160 allows the first semiconductor substrate 107 to be thicker relative to the width of the back-side TSV 157B without making the back-side TSV 157B difficult to fill due to its aspect ratio. In IC device 100B, conductive bridge 155A, back-side TSV 157B, front-side TSV 160, and metal pad 163 together provide direct coupling between contact pad 103A and metal grid 133A in the substrate, thereby applying a negative bias voltage to contact pad 103A to result in a negative voltage on metal grid 133A in the substrate having an analog relationship between voltages.

[0059] Various structures can be used to replace the front TSV 160 to create a connection between the rear TSV 157B and the metal pad 163. Figure 2BIC device 110B is shown, illustrating one such variation. In IC device 110B, connections are formed using heavily doped regions 164 of a first semiconductor substrate 107 and a plurality of vias 166. The heavily doped regions 164 may have the same doping type as the first semiconductor substrate 107.

[0060] Figures 3A to 3D An image sensing IC device 100C is illustrated according to some other aspects of this teaching. IC device 100C differs from IC device 100A in that it lacks a conductive bridge 155A. Instead, IC device 100C has an isolation structure 134C including a metal grid 133C in a substrate, the metal grid 133C having a segment 153C extending across an inner peripheral region 112A to an intermediate peripheral region 112B, wherein the segment 153C intersects with a back-side TSV 157C within a first semiconductor substrate 107. In some embodiments, the back-side TSV 157C and the segment 153C are integral, whereby the back-side TSV 157C has the same composition as the metal grid 133C in the substrate. Figure 3C As shown, in IC device 100C, metal pad 163 and back-side TSV 157C together provide direct coupling between contact pad 103A and metal grid 133C in the substrate, whereby the voltage on metal grid 133C in the substrate varies continuously with the voltage on contact pad 103A. A negative bias voltage applied to contact pad 103A will result in a negative voltage on metal grid 133C in the substrate having an analog relationship between voltages.

[0061] Figure 4 Image sensing IC device 100D is illustrated according to some other aspects of this teaching. IC device 100D is similar to IC device 100C, but differs in that IC device 100D has a back-side TSV 157D instead of a back-side TSV 157C. The back-side TSV 157D has a filler 156 in a centrally located region within the back-side TSV 157D. In some embodiments, the filler 156 is a dielectric. In some embodiments, the filler 156 extends from the back side 101 but terminates before the front side 108. In some embodiments, the back-side TSV 157D and segment 153C are integral, whereby the back-side TSV 157D has the same composition as the metal grid 133C in the substrate. IC device 100D can function like IC device 100C, but the metal of the back-side TSV 157D is not as... Figure 3A The metal on the back side of the TSV 157C is applied as thickly as possible. Figures 1A to 1D The back side TSV 157A can also be formed using a thinner metal deposition and has a central region occupied by filler 156.

[0062] Figure 5An image sensing IC device 100E according to some other aspects of this teaching is illustrated. IC device 100E differs from IC device 100C in that IC device 100E has a front-side TSV 160 opposite to the back-side TSV 157E. The front-side TSV 160 completes a direct connection between the back-side TSV 157E and the metal pads 163 or similar structures in the first metal interconnect 109 or the second metal interconnect 110. Other suitable structures can be used instead of the front-side TSV 160. In IC device 100E, the back-side TSV 157E, the front-side TSV 160, and the metal pads 163 together provide a direct coupling between the contact pads 103A and the metal grid 133C in the substrate, whereby the voltage on the metal grid 133C in the substrate varies continuously with the voltage on the contact pads 103A.

[0063] Figures 6A to 6D An IC device 100F is illustrated according to some other aspects of this teaching. IC device 100F differs from IC device 100A in that it uses contact pads 103F disposed on the back side 101 and forms a direct connection between the metal grid 133A in the substrate and the contact pads 103F bypassing the front side 108. This connection can be provided by a conductive bridge 155F extending laterally from the contact pads 103F on the back side 101. Forming a direct connection between the metal grid 133A in the substrate and the contact pads 103F on the back side 101 provides a low-resistance path through which the voltage on the metal grid 133A in the substrate can be tightly controlled. Avoiding the connection through the front side 108 also eliminates process steps.

[0064] In some embodiments, the conductive bridge 155F and the contact pad 103F are integral, thus having the same composition. In some embodiments, this composition is also a component of the back metal grid 141. In these embodiments, the back metal grid 141, the conductive bridge 155F, and the contact pad 103F can be formed simultaneously. In some embodiments, the contact pad 103A is formed opposite to the contact pad 103F and close to the front side 108. The contact pad 103A opposite to the contact pad 103F can be a dummy contact pad. The pad dielectric 102 can completely seal the dummy contact pad from the back side 101. The dummy contact pad can be formed simultaneously with other operable contact pads. The dummy contact pad structure can help provide the contact pad 103F with a desired geometry, such as a concave surface 167F.

[0065] Figure 7A , Figure 7B and Figures 8 to 33 This is a cross-sectional view illustrating an example of a method for forming an IC device 100A according to this teaching. While various embodiments of the reference method are described... Figure 7A , Figure 7B and Figures 8 to 33 However, it should be understood that Figure 7A , Figure 7B and Figures 8 to 33 The structure shown is not limited to this method, but can exist independently of the method. Although Figure 7A , Figure 7B and Figures 8 to 33 The description is a series of steps, but it should be understood that the order of the steps may be changed in other embodiments. Although Figure 7A , Figure 7B and Figures 8 to 33 Specific sets of steps are shown and described, but some steps shown and / or described may be omitted in other embodiments. Furthermore, steps not shown and / or described may be included in other embodiments. Although described according to forming IC device 100A Figure 7A , Figure 7B and Figures 8 to 33 This method, however, can be used to form other IC devices according to this teaching.

[0066] like Figure 7A As shown in cross-sectional view 700, the method can begin by bonding partially fabricated IC device 701 and second IC device 703 together. Each of IC device 701 and second IC device 703 may have undergone front-end online (FEOL) and back-end online (BEOL) processes. In IC device 701, the FEOL process provides front-side isolation structures 125, 161, and 105, photodetector pixel 126, floating diffusion region 123, and transfer gate 122. The BEOL process provides a first metal interconnect 109. In second IC device 703, the FEOL process provides a logic gate 113 and similar structures, and the BEOL process provides a second metal interconnect 110. Bonding occurs between the first metal interconnect 109 and the second metal interconnect 110. The bonding process can be fusion bonding, hybrid bonding, or some other suitable bonding process. After bonding, the first semiconductor substrate 107 can be thinned from the back side 101 to provide, for example, Figure 7B The structure shown in cross-sectional diagram 710.

[0067] Each of the first semiconductor substrate 107 and the second semiconductor substrate 111 may be or include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate. In some embodiments, an etch stop layer 124 is disposed directly on the front side 108. The etch stop layer 124 is a dielectric and may be an oxide, carbide, nitride, etc. Each of the first interlayer dielectric 120 and the second interlayer dielectric 117 may be or include silicon oxide, a low-k dielectric, an ultra-low-k dielectric, etc. The first wiring 121, the first via 119, the second wiring 115, the second via 118, and the metal pad 163 may be copper (Cu), aluminum (Al), etc., or some other suitable metal. In some embodiments, the metal pad 163 is copper (Cu), etc. The front isolation structures 125, 161, and 105 may be shallow trench isolation structures, field oxides, or any other suitable type of isolation structure. The photodetector pixel 126, the floating diffusion region 123, and the transmission gate 122 can constitute an active pixel sensor with a fixed photodiode, but the photodetector pixel 126 can be any type of photodetector including a photodiode.

[0068] Figures 8 to 19 The cross-sectional views 800-1900 all correspond to Figure 7B The cross-sectional view of region C in section 710. (As shown in the image) Figure 8 As shown in the cross-sectional view 800, the process can continue with photolithography to form a mask 803 on the back side 101 and use the mask 803 to etch a trench 801 of width W1 in the first semiconductor substrate 107. It should be understood that the trench 801A extending into the inner peripheral region 112A also has a width W1. Due to... Figure 1D The cross-section shown by line A-A' extends along the length of groove 801A, where groove 801A is located... Figure 8 It occupies a wider spacing in the cross-sectional view 800. After etching the trench 801, the mask 803 can be peeled off.

[0069] like Figure 9As shown in cross-sectional view 900, a high-k liner 128 and a high-k capping layer 137 can be deposited in and between trenches 801. In some embodiments, the high-k liner 128 is deposited using a conformal deposition process. The conformal deposition process can be low-speed chemical vapor deposition (CVD), atomic layer deposition (ALD), or some other suitable process. In some embodiments, the high-k capping layer 137 is deposited using a non-conformal deposition process. Non-conformal deposition can be a process with poor gap-filling capability, resulting in very little high-k capping layer 137 deposited within trenches 801. Non-conformal deposition processes can be physical vapor deposition (PVD), high-speed CVD, plasma-enhanced CVD (PECVD), or some other suitable process. The high-k liner 128 and the high-k capping layer 137 may each be hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), strontium oxide (SrO), barium oxide (BaO), barium titanate (BaTiO3), tantalum oxide (Ta2O3), lanthanum oxide (La2O3), yttrium oxide (Y2O3), or some other suitable high-k dielectric, or mixtures thereof. The high-k liner 128 and the high-k capping layer 137 may have the same composition or different compositions. In some embodiments, the total thickness of the high-k dielectric within the trench 801 is from about 50 angstroms to about 250 angstroms. In some embodiments, the total thickness of the high-k liner 128, the high-k capping layer 137, and any other high-k dielectric within the trench 801 is from about 100 angstroms to about 180 angstroms. In some embodiments, the thickness of the high-k capping layer 137 outside the trench 801 is from about 300 angstroms to about 700 angstroms.

[0070] like Figure 10 As shown in cross-sectional view 1000, a second dielectric pad 129 may be deposited in and between trenches 801. In some embodiments, the second dielectric pad 129 is deposited by a conformal deposition process such as ALD. In some embodiments, the second dielectric pad 129 is an oxide or the like. In some embodiments, the second dielectric pad 129 has a thickness of about 50 angstroms to about 300 angstroms. In some embodiments, the second dielectric pad 129 has a thickness of about 150 angstroms to about 250 angstroms. It should be understood that the number, thickness, and order of the layers constituting the dielectric pad structure 131 within the trench 801 can vary widely.

[0071] like Figure 11As shown in cross-sectional view 1100, a second capping layer 138 can be formed. The second capping layer 138 can be deposited using a non-conformal deposition process such as PECVD, resulting in minimal deposition of the second capping layer 138 within the trench 801 to be added to the dielectric pad structure 131. In some embodiments, the second capping layer 138 is an oxide or the like. In some embodiments, the second capping layer 138 has a thickness of approximately 200 angstroms to approximately 1500 angstroms outside the trench 801. In some embodiments, the second capping layer 138 has a thickness of approximately 300 angstroms to approximately 700 angstroms. The second capping layer 138 may have overhangs relative to the trench 801, but any such overhangs do not affect the filling of the trench 801 and are not shown in the description.

[0072] like Figure 12 As shown in cross-sectional view 1200, a conductive layer 1201 is deposited to fill trench 801. The conductive layer 1201 can be a metal suitable for processes with good gap filling. In some embodiments, the conductive material is tungsten (W), aluminum (Al), etc. The conductive material can be deposited by CVD, PVD, electroplating, electroless plating, etc. In some embodiments, a conductive pad is deposited before the conductive material. The conductive pad can be, for example, titanium nitride, tantalum, nitride, etc. The conductive pad can be deposited to a thickness of about 20 angstroms to about 100 angstroms, for example, 50 angstroms. The conductive material can be deposited to a thickness of about 1000 angstroms to about 3000 angstroms.

[0073] like Figure 13 As shown in cross-sectional view 1300, the conductive layer 1201 can be planarized. Planarization removes material outside the trench 801. The planarization process can be chemical mechanical polishing (CMP) or some other suitable planarization process. The remaining conductive material forms a metal grid 133A in the substrate. The metal grid 133A in the substrate, together with the high-k pad and the second dielectric pad 129, provides a back-side isolation structure 134A, which includes a segment 135 extending between the photodetector pixels 126 and a segment 153A extending into the inner peripheral region 112A. In some embodiments, CMP reduces the second capping layer 138 to a thickness in the range of about 500 angstroms to about 800 angstroms. In some embodiments, CMP reduces the second capping layer 138 to a thickness in the range of about 200 angstroms to about 500 angstroms, for example, about 400 angstroms.

[0074] like Figure 14As shown in cross-sectional view 1400, a mask 1401 for etching a TSV opening 1403 in a first semiconductor substrate 107 within the intermediate peripheral region 112B can be formed by photolithography. Etching can be stopped on the front-side isolation structure 161. In some embodiments, the TSV opening 1403 has a width ranging from about 1 μm to about 5 μm. In some embodiments, the TSV opening 1403 has a width ranging from about 2 μm to about 3 μm, for example, about 2.4 μm. After etching, the mask 1401 can be stripped off.

[0075] like Figure 15 As shown in the cross-sectional diagram 1500, it can be seen that... Figure 14 A dielectric layer 1501 is deposited over the structure shown in the cross-sectional view 1400, such that the dielectric layer 1501 liner the TSV opening 1403. The dielectric layer 1501 can be deposited relatively thickly using a partially non-conformal deposition process, such that the dielectric layer 1501 forms overhangs 1503 at the edges of the TSV opening 1403. The deposition process can be PECVD or any other suitable process. The dielectric layer 1501 can be one or more layers of silicon oxide, silicon nitride, or any other suitable dielectric. In some embodiments, the dielectric layer 1501 is deposited to a thickness ranging from about 1 μm to about 5 μm. In some embodiments, the dielectric layer 1501 is deposited to a thickness ranging from about 2 μm to about 4 μm, for example, about 3 μm.

[0076] like Figure 16 As shown in the cross-sectional view 1600, a mask 1601 for masking the pixel region 114 while etching in the peripheral region 112 can be formed by photolithography. At least a portion of segment 153A of the metal grid 133A in the substrate is etched to expose the metal grid 133A in the substrate and form an opening 1605 through which the metal pads 163 are exposed within the TSV opening 1403. A portion of the dielectric layer 1501 protected by the mask 1601 is retained to provide a thick oxide layer 139 in the pixel region 114 and the outer peripheral region 112C (see...). Figure 1A It extends upward and has an opening 1603 that extends from the inner peripheral region 112A to the middle peripheral region 112B.

[0077] In some embodiments, the etching is anisotropic plasma etching, whereby a portion of the dielectric layer 1501 is retained to form a dielectric pad 159 within the TSV opening 1403. Specifically, the overhang 1503 (see...) Figure 15This prevents this portion of dielectric layer 1501 from being etched away. Dielectric layer 1501 is thinner at the substrate of TSV opening 1403, so that the etching time for exposed metal pad 163 is nearly the same as the etching time for exposed section 153A. In some embodiments, the etching times are within about 25% of each other. In some embodiments, the etching times are within about 10% of each other. The thickness of dielectric layer 1501 or the degree of uniformity of dielectric layer 1501 deposition can be adjusted to affect this balance. After etching, mask 1601 can be stripped.

[0078] like Figure 17 As shown in cross-sectional view 1700, a conductive layer 1701 can be deposited to fill openings 1605, TSV openings 1403, and opening 1603. The conductive layer 1701 can be selected to have high conductivity and is selected to be suitable for filling TSV openings 1403, which can have a high aspect ratio. In some embodiments, the conductive material is tungsten (W), aluminum (Al), etc. The conductive material can be deposited by CVD, PVD, electroplating, electroless plating, etc.

[0079] like Figure 18 As shown in cross-sectional view 1800, the conductive layer 1701 can be planarized using CMP or similar methods to form the conductive bridge 155A and the back-side TSV 157A. CMP thins the thick oxide layer 139 and makes the thick oxide layer 139 coplanar with the conductive bridge 155A. In some embodiments, the thickness of the thick oxide layer 139 is reduced to a thickness in the range of about 500 angstroms to about 2000 angstroms. In some embodiments, the thickness of the thick oxide layer 139 is reduced to a thickness in the range of about 900 angstroms to about 1500 angstroms.

[0080] like Figure 19 As shown in the cross-sectional diagram 1900, it can be seen that... Figure 18 An etch stop layer 140 is formed over the structure shown in the cross-sectional view 1800. The etch stop layer 140 may be silicon nitride or some other suitable dielectric. The etch stop layer 140 may be formed by PVD, CVD, ALD, or any other suitable process. In some embodiments, the etch stop layer 140 has a thickness of about 400 angstroms to about 1200 angstroms. In some embodiments, the etch stop layer 140 has a thickness of about 600 angstroms to about 1000 angstroms, for example, about 880 angstroms. Figure 20 The cross-sectional view 2000 corresponds to Figure 19 A wider view of the cross-section of 1900.

[0081] like Figure 21As shown in cross-sectional view 2100, a mask 2103 for etching pad openings 2101 in the first semiconductor substrate 107 within the outer peripheral region 112C can be formed by photolithography. Etching can be stopped on the isolation structure 105 formed on the front side 108. After etching, the mask 2103 can be peeled off.

[0082] like Figure 22 As shown in the cross-sectional diagram 2200, it can be seen that... Figure 21 The structure shown in cross-sectional view 2100 has a deposited pad dielectric liner 104. The pad dielectric liner 104 can be an oxide or some other suitable dielectric. In some embodiments, the pad dielectric liner 104 is about 2000 angstroms to about 5000 angstroms thick. The pad dielectric liner can be deposited by PVD, CVD, or any other suitable process.

[0083] like Figure 23 As shown in cross-sectional view 2300, a mask 2303 for etching opening 2301 within pad opening 2101 can be formed by photolithography. Metal pad 163 is exposed through opening 2301. After etching, mask 2303 can be removed.

[0084] like Figure 24 As shown in the cross-sectional view 2400, it can be seen that... Figure 23 Pad metal 2401 is deposited over the structure shown in cross-sectional view 2300 (including opening 2301). Instead of completely filling the opening 2301, the pad metal 2401 may line the opening 2301, leaving a gap 2403 within the pad metal 2401. The pad metal 2401 may be aluminum (Al), copper (Cu), or any other suitable pad metal. In some embodiments, the metal is aluminum copper (AlCu). In some embodiments, the pad metal 2401 is deposited to a thickness of about 0.8 μm to about 1.6 μm, for example, about 1.3 μm. The pad metal 2401 may be deposited by CVD, PVD, electroplating, electroless plating, etc.

[0085] like Figure 25 As shown in cross-sectional view 2500, a mask 2501 for defining contact pads 103A from pad metal 2401 can be formed by photolithography. After etching, the mask 2501 can be removed.

[0086] like Figure 26 As shown in the cross-sectional diagram 2600, it can be seen that... Figure 25A pad dielectric 2601 of sufficient thickness to fill the pad opening 2101 is deposited above the structure shown in the cross-sectional view 2500. The pad dielectric 2601 may fill the gap 2403. The pad dielectric 2601 may be an oxide or other suitable dielectric. The pad dielectric 2601 may be deposited by PVD, CVD, or any other suitable process or combination of processes.

[0087] like Figure 27 As shown in the cross-sectional view 2700, a mask 2701 for thinning the pad dielectric 2601 in an area away from the contact pad 103A can be formed by photolithography. Figure 28 As shown in cross-sectional view 2800, the mask 2701 is stripped and planarization and additional etching are performed to form the pad dielectric 102 from the pad dielectric 2601. This process helps to provide the pad dielectric 102 with a concave surface 167A. Etching may also remove portions of the pad dielectric 102 and the pad dielectric pad 104 located outside the pad opening 2101.

[0088] like Figure 29 As shown in cross-sectional view 2900, a mask 2901 for etching the grounding rod opening 2903 in the first semiconductor substrate 107 within the inner peripheral region 112A can be formed by photolithography. The etching process can be plasma etching. After etching, the mask 2901 can be removed.

[0089] like Figure 30 As shown in the cross-sectional diagram 3000, it can be seen that... Figure 29 A composite grid stack 3009 is deposited over the structure shown in cross-sectional view 2900. The composite grid stack 3009 may include a metal layer 3001, a dielectric layer 3003, and a hard mask layer 3005. The metal layer 3001 forms a grounding rod 141B within the grounding rod opening 2903 and a portion 141A of the back metal grid 141 that connects the grounding rod 141B to the remainder of the back metal grid 141. The metal layer 3001 may include any suitable metal or combination of metals. In some embodiments, the metal layer 3001 includes tungsten (W), etc. In some embodiments, the metal layer 3001 includes a pad layer of titanium nitride (TiN), tantalum nitride (TaN), etc. The dielectric layer 3003 may be silicon oxide, etc., or any suitable dielectric. The hard mask layer 3005 may be a nitride, carbide, etc., a combination thereof, or any other suitable hard mask material. These layers can be deposited by CVD, PVD, electroplating, electroless plating, or any other suitable combination of processes.

[0090] like Figure 31As shown in cross-sectional view 3100, a mask 3101 for etching the composite grid 149 from the composite grid stack 3009 can be formed by photolithography. The etching removes the composite grid from above the photodetector pixel 126 and the pad dielectric 102. The etching forms a back-side metal grid 141 from the metal layer 3001, a dielectric grid 142 from the dielectric layer 3003, and a hard mask grid 143 from the hard mask layer 3005. After etching, the mask 3101 can be stripped.

[0091] like Figure 32 As shown in the cross-sectional view 3200, it can be seen that... Figure 31 A sealing layer 145 is formed above the structure shown in the cross-sectional view 3100. The sealing layer 145 reflects the surface of the pad dielectric 102 and presents a concave surface 167A. The sealing layer 145 can be an oxide or some other suitable dielectric. Figure 33 As shown in cross-sectional view 3300, a color filter 146 can be formed above the photodetector pixel 126 within the composite grid 149. A microlens 147 can be formed above the color filter 146. An opening 165A can be etched through the sealing layer 145 and the pad dielectric 102 to expose the contact pad 103A and create... Figure 1A The structure.

[0092] Figures 34 to 40 The cross-sectional view 3400-4000 shows Figure 7A , Figure 7B and Figures 8 to 33 The process variation is shown in cross-sectional diagrams 700-3300. This variation can be used to form... Figure 2A IC device 100B. For example... Figure 34 As shown in the cross-sectional diagram 3400, it can be compared with... Figure 7A Compared to the cross-sectional view 700, the change begins with IC device 3401 replacing IC device 701. IC device 3401 is similar to IC device 701, but includes a front-side TSV 160. The front-side TSV 160 can be insulated from the first semiconductor substrate 107 via TSV pad 162. TSV pad 162 can be an oxide, nitride, or some other suitable dielectric.

[0093] Processing such as Figures 7B to 13 The cross-sectional view shown in 710-1300 can be continued. As... Figure 35 As shown in cross-sectional view 3500, the etching forming the TSV opening 3501 can stop on the front TSV 160 or TSV pad 162. Figure 36 As shown in cross-sectional view 3600, dielectric layer 1501 can be deposited on top of the resulting structure. As... Figure 37As shown in cross-sectional view 3700, an opening 3701 can be formed through the dielectric layer 1501 and the TSV pad 162 by etching using mask 1601, thereby exposing the front TSV 160 within the TSV opening 3501. Figure 38 As shown in the cross-sectional view 3800, the deposited conductive layer 1701 fills the TSV openings 3501 and 3701. (As...) Figure 39 As shown in cross-sectional view 3900, planarization defines conductive bridge 155A and back-side TSV 157B from conductive layer 1701. This can be achieved as follows: Figure 40 The resulting structure, as shown in cross-sectional view 4000, has an etch stop layer 140 deposited on top, and is then processed as follows: Figures 20 to 30 The cross-sectional diagrams 2000-3000 continue to provide IC devices, such as Figure 2A IC device 100B.

[0094] Figures 41 to 46 Cross-sectional views 4100-4600 show Figure 7A , Figure 7B and Figures 8 to 33 The process variation is shown in cross-sectional diagrams 700-3300. This variation can be used to form... Figures 3A to 3D IC device 100C. For example... Figure 41 As shown in the cross-sectional diagram 4100, it can be compared with... Figure 8 Compared to the cross-sectional view 800, the change begins with etching using mask 4101 instead of mask 803. Etching with mask 4101 creates a trench 801C extending from pixel region 114 to intermediate peripheral region 112B. In intermediate peripheral region 112B, trench 801C engages with TSV opening 4103. The layout of trenches 801 and 801C, and TSV opening 4103, corresponds to the layout of metal grid 133C, segment 153C, and back-side TSV 135C in the substrate, as shown below. Figure 3D As shown in the image.

[0095] The depth D2 of the TSV opening 4103 can be greater than the depth D1 of the trench 801. The etching process can provide a greater depth in the TSV opening 4103 than in the trench 801 because the TSV opening 4103 has a width W2 greater than the width W1 of the trench 801. In some embodiments, the width W2 is 1.1 to 10 times the width W1. In some embodiments, the width W2 is 1.3 to 5 times the width W1.

[0096] The depth D2 of the TSV opening 4103 can be close to the thickness T1 of the first semiconductor substrate 107. In some embodiments, the thickness T1 is from 1 μm to about 5 μm. In some embodiments, the thickness T1 is from 2 μm to about 4 μm, for example, about 3.5 μm. In some embodiments, the depth D1 is from about 0.5 μm to about 3 μm. In some embodiments, the depth D1 is from about 1 μm to about 2 μm or about 1.5 μm. In some embodiments, the width W1 is from about 0.03 μm to about 0.5 μm. In some embodiments, the width W1 is from about 0.08 μm to about 0.16 μm or about 0.12 μm.

[0097] like Figure 42 As shown in cross-sectional view 4200, the stripping mask 4101 and the deposition of high-k pad 128, high-k capping layer 137, and second dielectric pad 129 result in the TSV opening 4103 being lined with the same dielectric pad structure 131 as the trench 801. Figure 43 As shown in the cross-sectional diagram 4300, this process can be performed... Figure 42 A non-conformal deposition of a thick dielectric layer 4301 is performed on top of the structure shown in cross-sectional view 4200. The thick dielectric layer 4301 can be an oxide or some other suitable dielectric. The thick dielectric layer 4301 can be deposited by PECVD or some other suitable process. The non-conformal deposition process can result in the thick dielectric layer 4301 being mainly formed outside the trench 801 and TSV opening 4103, thus the thick dielectric layer 4301 is only added in small amounts to the dielectric pad structure 131.

[0098] The thick dielectric layer 4301 can be deposited such that it is closed above the trench 801 but has an opening 4307 through which the TSV opening 4103 is exposed. It should be understood that the trench 801C has the same width as the trench 801, and structure 4305 corresponds to the portion 4303 of the thick dielectric layer 4301 located in the middle above the trench 801. The elongated appearance of structure 4305 corresponds to... Figure 3D The result of the cross-sectional profile of line A-A'.

[0099] like Figure 44 As shown in cross-sectional view 4400, etching can be performed, in which the thick dielectric layer 4301 serves as a mask. The etching process forms an opening 4401 through which the metal pads 163 are exposed. The etching can be timed to provide a second overlay 138 for the remaining portion of the thick dielectric layer 4301. The etching process exposes trench 801 but stops before removing the dielectric pad structure 131 from trench 801 or from the sidewalls of TSV opening 4103.

[0100] like Figure 45 As shown in the cross-sectional view 4500, it can be seen that... Figure 44A conductive material 4501 is deposited over the structure shown in the cross-sectional view 4400. The conductive material 4501 is a material that provides sufficient gap filling in the trench 801. In some embodiments, the conductive material is tungsten (W), aluminum (Al), etc. The conductive material can be deposited by CVD, PVD, electroplating, electroless plating, or any other suitable process.

[0101] like Figure 46 As shown in cross-sectional view 4600, the conductive material 4501 can be planarized using CMP or similar methods, and an etch stop layer 140 can be deposited on the planarized surface. Planarization defines the back-side TSV 157C, segment 153C, and metal grid 133C in the substrate from the conductive material 4501. The process can be as follows... Figures 20 to 30 The cross-sectional diagrams 2000-3000 continue to provide IC devices, such as Figures 3A to 3D IC device 100C.

[0102] Figure 47 and Figure 48 Cross-sectional views 4700 and 4800 show Figure 43 and Figure 44 The process variations are shown in cross-sectional views 4300 and 4400. (As...) Figure 47 As shown in cross-sectional view 4700, in this variation, the thick dielectric layer 4301 can be deposited to a smaller thickness and the closed trench 801 is not required. Figure 48 As shown in the cross-sectional view 4800, the opening 4401 is etched using a mask 4801 formed by photolithography. The mask 4801 can then be peeled off, and the processing can proceed as follows: Figure 45 The cross-sectional view 4500 and subsequent figures continue.

[0103] Figures 49 to 52 Cross-sectional views 4900-5200 show Figure 45 and Figure 46 The process variations are shown in cross-sectional views 4500 and 4600. These variations can be used to produce… Figure 4 IC device 100D. For example... Figure 49 As shown in cross-sectional view 4900, in this variation, the conductive material 4501 is deposited thinner, thereby retaining the gap 4903 within the TSV opening 4103. As... Figure 50 As shown in cross-sectional view 5000, deposited filler material 5001 fills gaps 4903. Filler material 5001 can be a dielectric, such as an oxide, but can be any suitable filler material. Filler material 5001 can be deposited by CVD, PVD, electroplating, electroless plating, or any other suitable process.

[0104] like Figure 51As shown in cross-sectional view 5100, the conductive material 4501 and the filler material 5001 can be planarized together to define the back-side TSV 157D, filler 156, segment 153C, and metal grid 133C in the substrate. Figure 52 As shown in cross-sectional view 5200, an etch stop layer 140 can be deposited, and the process can be as follows: Figures 20 to 30 The cross-sectional diagrams 2000-3000 continue to provide IC devices, such as Figure 4 IC device 100D.

[0105] Figures 53 to 56 Cross-sectional views 5300-5600 show the process, which combines Figure 7A , Figure 7B and Figures 8 to 33 The cross-sectional diagrams 700-3300 show two variations of the process to produce Figure 5 The IC device 100E. One of the changes is the use of Figure 34 IC device 3401, which includes replacing Figure 7A The front side of the IC device 701 is TSV 160. Another change is the use of... Figure 41 and Figure 44 The cross-sectional views 4100 and 4400 show the processing to produce a metal grid 133C in the substrate that intersects with the back-side TSV 157E.

[0106] like Figure 53 As shown in the cross-sectional diagram 5300, it can be compared with... Figure 41 Compared to cross-sectional view 4100, if the starting IC device includes the front TSV 160, then the TSV opening 5301 does not need to be as deep as the TSV opening 4103. The depth D3 of the TSV opening 4103 reduces the depth D4 of the front TSV 160, thus allowing the depth D3 to be within the range of... Figure 41 Anywhere between the depth D2 of the TSV opening 4103 and the depth D1 of the trench 801.

[0107] like Figure 54 and Figure 55 As shown in cross-sectional views 5400 and 5500, the high-k pad 128, the high-k cover layer 137, the second dielectric pad 129, and the thick dielectric layer 4301 can be formed on... Figure 53 Above the structure shown in cross-sectional view 5300. As... Figure 56 As shown in the cross-sectional view 5600, etching using a thick dielectric layer 4301 as a mask creates an opening 5601 through which the front-side TSV 160 is exposed. The opening 5601 can be more transparent than... Figure 44The corresponding process, as shown in the cross-sectional view 4400, produces a much shallower opening 4401. Therefore, the front-side TSV 160 reduces the need for an etching process using a thick dielectric layer 4301 as a mask. The process can be as follows... Figure 45 and Figure 46 Cross-sectional views 4500 and 4600 and Figures 20 to 30 The cross-sectional diagrams 2000-3000 continue to provide IC devices, such as Figure 5 IC device 100E.

[0108] Figure 57 and Figure 58 Cross-sectional views 5700 and 5800 show Figures 55 to 56 The cross-sectional views 5500 and 5600 show variations in the processing. In this variation, the thick dielectric layer 4301 can be deposited to a smaller thickness and the closed trench 801 is not required. Figure 58 As shown in the cross-sectional view 5800, an opening 5601 is etched using a mask 5801 formed and patterned by photolithography. This process uses an additional mask, but ensures that the opening 5601 can be formed within the trench 801 or on the sidewall of the TSV opening 5301 without etching.

[0109] Figures 59 to 64 Cross-sectional views 5900-6400 show Figure 7A , Figure 7B and Figures 8 to 33 The cross-sectional diagram 700-3300 shows a process variation that can be used to form IC devices, such as... Figures 6A to 6D IC device 100F. For example... Figure 59 As shown in cross-sectional diagram 5900, it can be compared with... Figure 20 Compared to the cross-sectional view of 2000, in this change, the process of forming the conductive bridge 155A and the back-side TSV 157A is omitted.

[0110] like Figure 60 As shown in the cross-sectional view 6000, a mask 6001 for etching the grounding rod opening 2903 can be formed by photolithography. This is consistent with... Figure 29 The process is the same as shown in cross-sectional view 2900. In addition to the example shown here, the process can also be used to etch opening 6013 through which segments 153A of the metal grid 133A in the substrate are exposed. After etching, mask 6001 can be stripped.

[0111] like Figure 61 As shown in the cross-sectional view 6100, the composite grid stack 3009 can be deposited on Figure 60Above the structure shown in cross-sectional view 6000. In addition to forming a grounding rod 141B within the grounding rod opening 2903, the metal layer 3001 of the composite grid stack 3009 forms a through-hole 152 in the opening 6013. As... Figure 62 As shown in the cross-sectional view 6200, the mask 6201 can be formed by photolithography and is used to etch the composite grid 149 from the composite grid stack 3009, as... Figure 31 As in the process, the composite grid stack 3009 is etched to form the composite grid 149, separating the back-side metal grid 141 from the other portions of the metal layer 3001 that provide the conductive bridge 155F and contact pads 103F. The mask 6201 can then be stripped.

[0112] like Figure 63 As shown in cross-sectional view 6300, a mask 6301 for removing the dielectric layer 3003 and the hard mask layer 3005 from the conductive bridge 155F and the contact pad 103F can be formed by photolithography. Figure 64 As shown in the cross-sectional view 6400, the sealing layer 145 can be formed in Figure 63 The structure shown in cross-sectional view 6300 is above the structure. Color filters 146 and microlenses 147 can be formed above the composite grid 149, and openings 165F are etched through the sealing layer 145 above the contact pads 103F to create a connection with... Figures 6A to 6D It has the same structure as the IC device 100F.

[0113] Figure 65 A flowchart for process 6500 according to the present invention is presented, which can be used to form Figures 1A to 1D IC device 100A, Figure 2A IC device 100B, Figure 2B IC device 110B or another IC device. Although Figure 65 The process 6500 is shown and described herein as a series of steps or events; however, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, it may not be necessary to implement all the steps shown herein to achieve one or more aspects or embodiments described herein, and one or more steps described herein may be performed in one or more separate steps and / or stages.

[0114] Process 6500 begins with steps 6501 and 6503, where the FEOL process includes processes for forming photodetector pixels and BEOL processes for forming metal interconnects. In various embodiments, the resulting structure is Figure 7A IC device 701, Figure 34The IC device 3401 or some other IC device including photodetector pixels.

[0115] The process continues to step 6505, thinning the substrate from the back side. Figure 7B Examples are provided. For example... Figure 7A As shown, the IC device can be attached to the second IC device via metal interconnects before thinning. The second IC device can then be made structurally intact through the thinning process.

[0116] The process continues to step 6507, etching trenches for the backside isolation structure. Figure 8 Cross-sectional view 800 provides an example. The trench includes a trench extending into the semiconductor substrate and located between the photodetector pixel and at least one trench extending outside the pixel region.

[0117] The process continues to step 6509, depositing one or more dielectric layers to line the trench. Figures 9 to 11 Cross-sectional views 900-1100 provide examples. The dielectric layer may include one or more high-k dielectric layers.

[0118] The process continues to step 6511, filling the trench with a conductive material. This may include depositing the conductive material and planarization. Figure 12 and Figure 13 Cross-sectional views 1200 and 1300 provide examples. The conductive material is formed in a substrate comprising a metal grid extending from the pixel region.

[0119] The process continues to step 6513, forming a back-side TSV opening and an insert on the back side. The insert may be formed within a dielectric on the back side of the semiconductor substrate and extend from a segment of the metal grid in the substrate to the TSV opening. The TSV opening extends into the semiconductor substrate but does not need to extend through the semiconductor substrate. Figure 14 and Figure 15 The cross-sectional views 1400 and 1500 provide an example. Figure 35 and Figure 36 The cross-sectional views 3500 and 3600 provide another example.

[0120] The process continues to step 6515, extending the back TSV opening to connect with the front conductive structure. Figure 16 Cross-sectional view 1600 provides an example, in which the front conductive structure is metal pad 163. Figure 37 Cross-sectional view 3700 provides another example, where the front conductive structure is a front TSV 160 coupled to a metal pad 163. The front conductive structure can also be... Figure 2B The heavily doped region 164, via 166, and metal pad 163 are shown.

[0121] The process continues to step 6517, where the insert and back-side TSV openings are filled with a conductive material to form a conductive bridge and a back-side TSV. The back-side TSV is coupled to the front-side conductive structure. The conductive bridge couples the back-side TSV to a metal grid in the substrate. The process may include depositing conductive material and planarization. Figure 17 and Figure 18 The cross-sectional views 1700 and 1800 provide an example. Figure 38 and Figure 39 Cross-sectional views 3800 and 3900 provide another example.

[0122] The process continues to step 6519, forming contact pads coupled to the front conductive structure. Figures 21 to 31 Cross-sectional diagrams 2100-3100 provide examples. The contact pads can be back-side contact pads and are directly coupled to the metal grid in the substrate via front-side conductive structures, back-side TSVs, and conductive bridges.

[0123] Figure 66 A flowchart of process 6600 according to the present invention is presented, which can be used to form Figures 3A to 3D IC device 100C, Figure 4 IC device 100D, Figure 5 The IC device 100E or another IC device. Although Figure 66 The process 6600 is shown and described herein as a series of steps or events; however, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, it may not be necessary to implement all the steps shown herein to achieve one or more aspects or embodiments described herein, and one or more steps described herein may be performed in one or more separate steps and / or stages.

[0124] Process 6600 begins with steps 6501, 6503, and 6505, which can be identical to process 6500. Process 6600 continues with step 6601, etching trenches for the back-side isolation structure and the back-side TSV opening. In process 6600, trenches for both the back-side isolation structure and the TSV opening can be etched simultaneously, and the trenches for the back-side isolation structure extend to intersect with the TSV opening. The layout of the trenches for the back-side isolation structure and the TSV opening can be similar to... Figure 3D The layout of the metal grid 133C and the back TSV 135C in the substrate shown corresponds. Figure 41 Cross-sectional view 4100 provides an example where the TSV opening is deeper than the trench, which can be facilitated by a wider TSV opening than the trench. Figure 53Cross-sectional view 5300 provides another example where depth differences can be reduced or eliminated by using a front TSV or other structures that allow for a shorter rear TSV.

[0125] The process continues to step 6603, depositing one or more dielectric layers for the inner liner trench and the back-side TSV opening. The dielectric layers may include one or more high-k dielectric layers. Figure 42 The cross-sectional view 4200 provides an example. Figure 54 The cross-sectional view 5400 provides another example.

[0126] The process continues to step 6605, extending the back TSV opening to connect with the front conductive structure. Figure 43 and Figure 44 Cross-sectional views 4300 and 4400 provide examples where a non-conformally deposited thick dielectric layer provides a mask for the etching, and the etching allows the TSV opening to be directly connected to the metal pads on the front side. Figure 47 and Figure 48 Cross-sectional views 4700 and 4800 provide examples where photolithography provides a mask for the etching and the etching allows the TSV opening to be directly connected to the front metal pad. Figure 55 and Figure 56 An example is provided in which a non-conformally deposited thick dielectric layer provides a mask for the etching, and the etching connects the TSV opening to a similar structure coupled to the front TSV or itself to the front metal pad. Figure 57 and Figure 58 Cross-sectional diagrams 5700 and 5800 provide examples in which photolithography provides a mask for the etching, and the etching enables the TSV opening to communicate with a similar structure that is coupled to the front TSV or itself to the front metal pad.

[0127] The process continues to step 6607, depositing metal in the trenches and back-side TSV openings to form a back-side TSV and a metal grid in the substrate having segments intersecting with the back-side TSV. This may include depositing conductive material and planarization. Figure 43 and Figure 55 Cross-sectional views 4300 and 5500 provide examples of fully metal-filled trenches and backside TSV openings. Figure 49 Cross-sectional view 4900 provides an example where metal forms the back-side TSV but does not completely fill the back-side TSV opening. The voids in the filling metal, such as... Figure 50 and Figure 51 Cross-sectional views 5000 and 5100 are shown. In all these cases, the metal grid in the substrate is coupled to the front conductive structure via a back-side TSV.

[0128] The process continues to step 6519, forming contact pads coupled to the front conductive structure. This can be the same as in process 6500.

[0129] Figure 67 A flowchart of process 6700 according to the present invention is presented, which can be used to form Figures 6A to 6D The IC device 100F or a similar IC device according to this teaching may be used. Although process 6700 is shown and described herein as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, it may not be necessary to implement all the steps shown herein to implement one or more aspects or embodiments described herein, and one or more steps described herein may be performed in one or more separate steps and / or stages.

[0130] Process 6700 begins at step 6701, where the FEOL process includes forming photodetector pixels, forming metal interconnects, and substrate thinning. These can be the same steps 6501, 6503, and 6505 as in process 6500. Process 6700 continues at step 6703, forming a back-side isolation structure including a metal grid in the substrate, and at step 6703, forming a contact pad substrate with a concave surface. Figure 59 Cross-sectional view 5900 provides an example of the resulting structure. The back-side isolation structure can be formed in the same manner as in process 6500 or process 6600, except for those aspects of those processes that form the back-side TSV.

[0131] Step 6705 involves forming a contact pad substrate with a concave surface. The contact pad substrate can be as follows: Figures 21 to 31 The cross-sectional views 2100-3100 show the formation. The contact pad substrate with concave surface can be formed using fewer process steps, but the process steps mentioned can also help form contact pads independent of the metal grid in the bias substrate.

[0132] Process 6700 continues to step 6707, etching trenches for grounding the back-side metal grid and openings for segments of the metal grid exposed in the substrate. Etching can occur in the peripheral region away from the photodetector pixels. These openings can be etched simultaneously. Figure 60 The cross-sectional view 6000 provides an example.

[0133] Process 6700 continues to step 6709, depositing a composite grid stack. The base layer of the composite grid stack is metal. A portion of the metal is deposited in a trench to form a ground structure. Another portion is deposited in the openings of the metal grid in the exposed substrate to form vias. Additional portions of the metal layer form contact pads on the concave surface and laterally extend from the contact pads on the back side, coupling the contact pads to the vias and conductive bridges from the vias to the metal grid in the substrate. Figure 61The cross-sectional view 6100 provides an example.

[0134] Step 6711 involves patterning the composite grid from the composite grid stack. Patterning also separates the composite grid from the structure including vias, contact pads, and conductive bridges. Figure 62 The cross-sectional diagram 6200 provides an example.

[0135] Step 6713 is an optional step to remove the composite grid dielectric and etch stop layer from the contact pads. Figure 63 An example is provided in cross-sectional view 6300. This step is optional because the contact pads can be subsequently exposed without this separate step.

[0136] Step 6715 is to form a sealing layer over the composite grid and contact pads. Figure 64 A cross-sectional view 6400 provides an example. Step 6717 is etching to expose the contact pads. Figures 6A to 6D An example of the resulting structure is provided.

[0137] Figure 68 A flowchart of process 6800, which can be applied using the image sensing IC device according to the present invention, is provided. The process begins at step 6801, determining the application for which a light sensor will be used. Step 6803 selects a bias voltage for a metal grid in the substrate based on the application. This selection can be based on a trade-off between quantum efficiency and crosstalk suitable for the application. This selection provides a predetermined bias voltage. Step 6805 applies the predetermined bias voltage to the metal grid in the substrate via contact pads directly coupled to the metal grid in the substrate. In some embodiments, the contact pads are coupled to hardware providing the predetermined bias voltage.

[0138] Figure 69 A flowchart of process 6900, which can be applied using an image sensing IC device according to the present invention, is provided. The process begins at step 6901, determining an operating mode for the light sensor. In some embodiments, the operating mode is dynamically selected. In some embodiments, the operating mode is selected by a user. Step 6903 selects a bias voltage for a metal grid in the substrate based on the operating mode. Step 6905 applies the selected bias voltage to the metal grid in the substrate via contact pads directly coupled to the metal grid in the substrate. In some embodiments, the contact pads are coupled to hardware configured to provide multiple discrete voltages.

[0139] Figure 70A flowchart of process 7000, which can be applied using the image sensing IC device according to the present invention, is provided. The process begins at step 7001, determining the operating environment for the light sensor. In some embodiments, the operating environment is determined by the sensor. In some embodiments, the sensor is a temperature sensor. Step 7003 selects a bias voltage for a metal grid in the substrate based on the operating environment. Step 7005 applies the selected bias voltage to the metal grid in the substrate via contact pads directly coupled to the metal grid in the substrate.

[0140] Figure 71 A flowchart of process 7100, which can be applied using an image sensing IC device according to the present invention, is provided. Process 7100 uses feedback control to adjust a bias voltage on a metal grid in a substrate. The process begins at step 7101, selecting and initializing a bias voltage. The process continues to step 7103, applying the bias voltage to the metal grid in the substrate. Step 7105 is to evaluate the performance of the optical sensor. In some embodiments, this includes obtaining measurements related to quantum efficiency and obtaining measurements related to crosstalk. Step 7109 is to adjust the bias voltage selection based on the evaluation. The process then repeats step 7103, applying the adjusted bias voltage.

[0141] Some aspects of this teaching relate to image sensors. An image sensor includes a semiconductor substrate having a front side, a back side, pixel regions, and peripheral regions. Photodetector pixels are arranged in an array within the pixel regions. A back-side isolation structure extends into the back side and is located between the photodetector pixels. The back-side isolation structure includes a metal grid in the substrate and dielectric pads separating the metal grid in the substrate from the semiconductor substrate. Contact pads are present in the peripheral regions. One or more conductive structures directly couple the metal grid in the substrate to the contact pads.

[0142] Some aspects of this teaching relate to image sensors. An image sensor includes a semiconductor substrate having a front side, a back side, pixel regions, and peripheral regions. Photodetector pixels are arranged in an array within the pixel regions. A back-side isolation structure extends into the back side and is located between the photodetector pixels. The back-side isolation structure includes a metal grid in the substrate and dielectric pads separating the metal grid in the substrate from the semiconductor substrate. Contact pads are present in the peripheral regions. The metal grid in the substrate is coupled to the contact pads such that the voltage on the metal grid in the substrate varies continuously with the voltage on the contact pads.

[0143] Some aspects of this teaching relate to a method comprising providing a semiconductor substrate including a front side, a back side, a pixel region, a peripheral region, and an array of photodetector pixels within the pixel region. A back-side isolation structure including a metal grid is formed on the back side, the metal grid extending into the semiconductor substrate between the photodetector pixels in the array. Contact pads coupled to the metal grid are formed on the back side.

[0144] Some embodiments of this application provide an image sensor, including: a semiconductor substrate including a front side, a back side, a pixel region, and a peripheral region; photodetector pixels located in an array within the pixel region; a back-side isolation structure extending into the back side between the photodetector pixels, the back-side isolation structure including a metal grid in the substrate and a dielectric pad separating the metal grid in the substrate from the semiconductor substrate; contact pads located in the peripheral region; and one or more conductive structures directly coupling the metal grid in the substrate to the contact pads.

[0145] In some embodiments, the one or more conductive structures include a front conductive member disposed on the front side and a back substrate via (TSV) extending into the peripheral region on the back side; and a connection between the metal grid in the substrate and the front conductive member is formed through the back substrate via. In some embodiments, the one or more conductive structures further include a conductive bridge on the back side connecting the metal grid in the substrate to the back substrate via. In some embodiments, the conductive bridge and the back substrate via are integral structures. In some embodiments, the metal grid in the substrate extends into the peripheral region and intersects with the back substrate via. In some embodiments, the metal grid in the substrate and the back substrate via are integral structures. In some embodiments, the front conductive member extends from the back substrate via to directly below the contact pad. In some embodiments, the image sensor further includes: a dielectric layer located centrally within the back substrate via and extending from the back side to the front side. In some embodiments, the image sensor further includes: a back metal grid located in the pixel region; wherein the back metal grid is located outside the semiconductor substrate. In some embodiments, the one or more conductive structures that directly couple a metal grid in the substrate to the contact pads include conductive bridges extending laterally from the contact pads on the back side. In some embodiments, the conductive bridges and the contact pads are integral structures. In some embodiments, the image sensor further includes: a pad structure extending into a dielectric layer on the front side; wherein the contact pads are directly below the pad structure but electrically isolated from it. In some embodiments, the one or more conductive structures include front-side substrate vias in the peripheral region.

[0146] Other embodiments of this application provide an image sensor, including: a semiconductor substrate including a front side, a back side, a pixel region, and a peripheral region; photodetector pixels located in an array within the pixel region; a back-side isolation structure extending to the back side and located between adjacent pairs of the photodetector pixels; and contact pads; wherein the back-side isolation structure includes a metal grid in the substrate and a dielectric pad separating the metal grid in the substrate from the semiconductor substrate; and the metal grid in the substrate is coupled to the contact pads such that the voltage on the metal grid in the substrate changes continuously with the voltage on the contact pads.

[0147] In some embodiments, the coupling between the metal grid in the substrate and the contact pads bypasses the front side.

[0148] Further embodiments of this application provide a method for forming an image sensor, comprising: providing a semiconductor substrate including a front side, a back side, a pixel region, a peripheral region, and photodetector pixels in an array within the pixel region; forming a back-side isolation structure including a metal grid having segments extending into the semiconductor substrate between the photodetector pixels; and forming contact pads on the back side; wherein the metal grid is coupled to the contact pads.

[0149] In some embodiments, the method further includes forming a conductive bridge extending from the metal grid to the contact pads. In some embodiments, the conductive bridge and the contact pads are formed simultaneously. In some embodiments, the method further includes depositing a composite grid stack comprising a metal layer on the back side; wherein the metal layer provides the conductive bridge and the contact pads. In some embodiments, the method further includes forming an opening in a dielectric layer that exposes the metal grid before depositing the metal layer; wherein the metal layer forms vias intersecting the metal grid.

[0150] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An image sensor, comprising: Semiconductor substrate, including front side, back side, pixel area and peripheral area; The photodetector pixels are located in an array within the pixel region; A back-side isolation structure extends from the back side into the semiconductor substrate between the photodetector pixels, the back-side isolation structure including a metal grid in the substrate and a dielectric pad separating the metal grid in the substrate from the semiconductor substrate; Contact pads are located in the peripheral area; as well as One or more conductive structures directly couple a metal grid in the substrate to the contact pads, wherein a portion of the one or more conductive structures is a front-side conductive structure located in the peripheral region.

2. The image sensor according to claim 1, wherein: The front conductive structure is a metal pad disposed on the front side. The one or more conductive structures include the metal pads and back-side substrate vias (TSVs) extending from the back side of the peripheral region into the semiconductor substrate; and The connection between the metal grid and the metal pad in the substrate is made through the through-hole of the back substrate.

3. The image sensor according to claim 2, wherein, The one or more conductive structures further include conductive bridges on the back side that connect the metal grid in the substrate to the vias in the back side substrate.

4. The image sensor according to claim 3, wherein, The conductive bridge and the back-side substrate via are an integral structure.

5. The image sensor according to claim 2, wherein, The metal grid in the substrate extends into the peripheral region and intersects with the via in the back substrate.

6. The image sensor according to claim 5, wherein, The metal grid in the substrate and the via in the back substrate are an integral structure.

7. The image sensor according to claim 2, wherein, The metal pads extend from the back substrate via to directly below the contact pads.

8. The image sensor according to claim 2, further comprising: A dielectric layer is located centered within the via of the back substrate and extends from the middle of the back side to the front side.

9. The image sensor according to claim 1, further comprising: A back-side metal grid is located in the pixel region; The back-side metal grid is located outside the semiconductor substrate.

10. The image sensor according to claim 3, wherein, The conductive bridge is located above the back-side substrate via and the metal grid in the substrate.

11. The image sensor according to claim 10, wherein, The conductive bridge and the back-side substrate via are made of the same material.

12. The image sensor according to claim 1, wherein, The contact pads are open to the back side and are adapted to be bonded on the back side.

13. The image sensor according to claim 1, wherein, The one or more conductive structures include a front-side substrate via in the peripheral region.

14. An image sensor, comprising: Semiconductor substrate, including front side, back side, pixel area and peripheral area; The photodetector pixels are located in an array within the pixel region; A back-side isolation structure extends from the back side to the semiconductor substrate and is located between adjacent pairs of the photodetector pixels; as well as Contact pads; The back-side isolation structure includes a metal grid in the substrate and a dielectric pad that separates the metal grid in the substrate from the semiconductor substrate. as well as The metal grid in the substrate is coupled to the contact pad, such that the voltage on the metal grid in the substrate changes continuously with the voltage on the contact pad, wherein a portion of the coupling path between the metal grid in the substrate and the contact pad is a front-side conductive structure.

15. The image sensor according to claim 14, wherein, The coupling between the metal grid in the substrate and the contact pads passes through the front side.

16. A method for forming an image sensor, comprising: A semiconductor substrate including a front side, a back side, a pixel region, and a peripheral region is provided; a photodetector pixel in an array within the pixel region; and a front conductive structure located on the front side within the peripheral region. A back-side isolation structure is formed, comprising a metal grid having segments extending into the semiconductor substrate between the photodetector pixels; Forming a back-side substrate via extending from the back side of the peripheral region into the semiconductor substrate; as well as Form contact pads open on the back side; The metal grid is coupled to the contact pad at least through the back substrate via and the front conductive structure, such that the voltage on the metal grid changes continuously with the voltage on the contact pad.

17. The method of claim 16, further comprising: A conductive bridge is formed extending from the metal grid to the via in the back substrate.

18. The method according to claim 17, wherein, The conductive bridge and the back-side substrate via are formed simultaneously.

19. The method of claim 16, wherein, The front conductive structure includes metal pads.

20. The method of claim 16, wherein, The front conductive structure includes a front substrate via and a metal pad.

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