Field effect transistor with negative capacitance gate structure

Abstract

A field effect transistor having a negative capacitance gate structure. The field effect transistor includes a channel and a gate dielectric disposed above the channel. The negative capacitance gate structure includes a bottom electrode structure including a bottom electrode, a multi-domain structure, and a top electrode structure. The multi-domain structure includes a multi-domain element disposed above the bottom electrode, the multi-domain element including a plurality of topological domains and at least one topological domain wall. The top electrode structure includes a top electrode disposed above the multi-domain element. At least a portion of the bottom electrode structure of the negative capacitance gate structure is disposed above the gate dielectric and is adapted to be coupled to the channel through the gate dielectric.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a field effect transistor, in particular to a gate structure of a field effect transistor, more particularly to a gate structure with negative capacitance. BACKGROUND

[0002] The microelectronics industry is experiencing rapid growth with the trend towards miniaturization, while the complexity of electronic circuits is also increasing. The functionality density, i.e. the number of interconnected devices per chip area, is increasing, while the geometrical size, i.e. the smallest circuit feature, that can be produced using the most advanced manufacturing processes is decreasing. The increasing power density of integrated circuits can generate waste heat at high density, thereby limiting the continued growth of integrated circuits according to Moore’s law.

[0003] Transistors, more particularly field effect transistors, are the basic circuit components in microelectronics technology. The continued miniaturization of semiconductor circuits is challenged by the power dissipation and the resulting heat of field effect transistors. For many years, efforts have been made to overcome the heating caused by power dissipation in order to try to prevent implementations of sub-threshold slopes exceeding 60-mV / decade at room temperature.

[0004] Existing alternatives to standard metal-oxide-semiconductor field effect transistors have been proposed and investigated, specifically including tunnel field effect transistors, nano-electro-mechanical systems and feedback field effect transistors. Recently, the idea that a ferroelectric material can provide a negative capacitance has been proposed. In particular, a negative capacitor can solve the problem of overcoming a 60-mV / decade sub-threshold slope. A negative capacitance transistor can be created by incorporating a ferroelectric material into the gate. However, to date, no single material combination or single geometry has been successfully demonstrated to realize a capacitor with stable, reversible and hysteresis-free negative capacitance.

[0005] General design principles for negative capacitance transistors are desirable for realizing stable performance and flexible integration in semiconductor devices. SUMMARY

[0006] In view of the above technical problems, there is a need for an improved field effect transistor with a negative capacitance gate structure having an adjusted negative capacitance, in particular for a negative capacitance gate structure that guarantees a stable static negative capacitance.

[0007] This object is achieved by the field effect transistor provided by the present disclosure. The present disclosure also provides a method for operating a field effect transistor with a negative capacitance gate structure. Preferred embodiments of the aforementioned field effect transistor and the method of operating the same are provided by the present disclosure.

[0008] In a first aspect, a field effect transistor has a negative capacitance gate structure. The field effect transistor includes a channel and a gate dielectric arranged above the channel. The negative capacitance gate structure includes a bottom electrode structure including a bottom electrode, a multiferroic structure, and a top electrode structure. The multiferroic structure includes a multiferroic element arranged above the bottom electrode, the multiferroic element including a plurality of topological domains and at least one topological domain wall. The top electrode structure includes a top electrode arranged above the multiferroic element. At least a portion of the bottom electrode structure of the negative capacitance gate structure is arranged above the gate dielectric and is adapted to be coupled to the channel through the gate dielectric.

[0009] A field effect transistor having a negative capacitance gate structure can provide enhanced switching speed. A field effect transistor having a negative capacitance gate structure can also provide improved energy efficiency. Thus, a field effect transistor having a negative capacitance gate structure can operate with reduced energy dissipation and produce less waste heat, which can further improve the performance of the field effect transistor. A field effect transistor having a plurality of topological domains can provide a stable and reversible negative capacitance. A field effect transistor having a plurality of topological domains can have reduced or even negligible hysteresis of voltage at the channel with respect to voltage applied to the top electrode when operating.

[0010] A topological domain can be a ferroelectric polarization domain, and a topological domain wall can be a ferroelectric domain wall.

[0011] According to a corresponding embodiment, a field effect transistor has a negative capacitance gate structure. The field effect transistor includes a channel and a gate dielectric arranged above the channel. The negative capacitance gate structure includes a bottom electrode structure including a bottom electrode, a ferroelectric structure, and a top electrode structure. The ferroelectric structure includes a ferroelectric element arranged above the bottom electrode, the ferroelectric element including a plurality of ferroelectric polarization domains and at least one ferroelectric domain wall. The top electrode structure includes a top electrode arranged above the ferroelectric element. At least a portion of the bottom electrode structure of the negative capacitance gate structure is arranged above the gate dielectric and is adapted to be coupled to the channel through the gate dielectric.

[0012] Alternatively, a topological domain can be represented by a topological excitation, in particular a topological soliton. A topological domain wall can be a topological excitation domain wall, in particular a topological soliton domain wall.

[0013] In particular, a topological domain can be a polaron and a topological domain wall can be a polaron domain wall; or a topological domain can be a skyrmion and a topological domain wall can be a skyrmion domain wall; or a topological domain can be a hopfion and a topological domain wall can be a hopfion domain wall.

[0014] According to embodiments, the total capacitance of the channel, the gate dielectric, and the negative capacitance gate structure is negative.

[0015] The top surface of the bottom electrode can be conformal with the bottom surface of the multi-domain element.

[0016] The top surface of the multi-domain element can be conformal with the bottom surface of the top electrode.

[0017] The bottom surface of the multi-domain element can be in direct contact with the top surface of the bottom electrode.

[0018] The top surface of the multi-domain element can be in direct contact with the bottom surface of the top electrode.

[0019] According to some embodiments, the field effect transistor further comprises a substrate, and the channel is arranged above the substrate.

[0020] According to some embodiments, the field effect transistor further comprises a first source / drain region and a second source / drain region, and the channel extends from the first source / drain region to the second source / drain region.

[0021] The first source / drain region and the second source / drain region can be arranged above the substrate.

[0022] The field effect can further comprise a fin structure, and the channel can be arranged on the fin structure.

[0023] The transistor can comprise or can be a planar transistor, a metal-insulator-semiconductor transistor, a metal-oxide-semiconductor transistor, in particular a dual-gate metal-oxide-semiconductor transistor or a tri-gate metal-oxide-semiconductor transistor, an insulated-gate bipolar transistor, a tunnel field effect transistor, a metal-semiconductor field effect transistor, a quantum field effect transistor, a Schottky barrier field effect transistor, and / or a fin field effect transistor.

[0024] According to some embodiments, the negative capacitance gate structure has a stable static negative capacitance.

[0025] The multi-domain element can comprise a cross-sectional area having an orientation corresponding to an orientation of the top surface of the bottom electrode, and the cross-sectional area can define a shortest separation line to divide the cross-sectional area into a plurality of regions of equal or substantially equal area.

[0026] In the context of the present disclosure, the shortest separation line can denote the shortest cross-sectional line dividing the cross-sectional area into a plurality of regions of (substantially) equal area, in particular into two regions of (substantially) equal area. The separation line can be the shortest, i.e. there is no cross-sectional line or segment line dividing the cross-sectional area into a plurality of regions of (substantially) equal area and having a shorter intersection length with the cross-sectional area than the shortest separation line.

[0027] However, in some embodiments, e.g. when the cross-sectional area is circular, there can be several equilong shortest separation lines.

[0028] In the context of the present disclosure, the shortest separation line can correspond to or represent a topological domain wall separating adjacent topological domains, and / or the plurality of areas can correspond to or represent a plurality of topological domains.

[0029] The shortest separation line dividing the cross-sectional area into a plurality of areas of substantially equal area can correspond to an equilibrium position of a topological domain wall at zero gate voltage. Thus, in the context of the present disclosure, the shortest separation line can be referred to as an equilibrium separation line.

[0030] The reference line can be shifted with respect to the shortest separation line, and in particular can be parallel to the shortest separation line and extend at least partially in the surface defined by the cross-sectional area. The length of the reference line within the cross-sectional area can be shorter than the length of the shortest separation line within the cross-sectional area, and the length of the reference line within the cross-sectional area can differ from the length of the shortest separation line within the cross-sectional area by a difference that increases with increasing distance between the reference line and the shortest separation line in the vicinity of the shortest separation line. The shortest separation line can provide an image of at least one topological domain wall. The difference between the length of the shortest separation line and the reference line can represent an enhanced reliability and robustness of the negative capacitance.

[0031] Upon application of a gate voltage, the shortest / equilibrium separation line can be shifted from its equilibrium position at zero voltage, and the reference line can correspond to or represent the shifted separation line. The length of the separation line can decrease upon shifting from its equilibrium position at zero voltage, and can bow or curve to remain orthogonal to the edges of the cross-sectional area at the boundaries of the cross-sectional area.

[0032] In some embodiments, the reference line is a straight line segment. In other embodiments, the reference line can comprise a bowing portion and a curving portion.

[0033] The plurality of areas of substantially equal area can consist exactly of two areas of equal area.

[0034] This ensures control over the dynamics of the at least one topological domain wall and the dynamics of embodiments with two topologically polarized domains.

[0035] The top surface of the bottom electrode can be planar, and the cross-sectional area can be parallel to the top surface of the bottom electrode.

[0036] The top surface of the bottom electrode can comprise several planar surfaces, in particular planar surfaces of a reflective bottom layer fin structure, and the cross-sectional area can be arranged in several planes, wherein each plane can be parallel to a planar surface of the bottom electrode.

[0037] The top surface of the bottom electrode can be cylindrical or spherical, and the cross-sectional area can be coaxial or concentric to the top surface of the bottom electrode.

[0038] The vicinity of the shortest separation line can comprise a region within the cross-sectional area closest to the shortest separation line, in particular a region within the cross-sectional area having an area of at least 5% of the area of the cross-sectional area, in particular an area of at least 10% of the area of the cross-sectional area, or an area of at least 20% of the area of the cross-sectional area.

[0039] The field effect transistor can further comprise an additional dielectric element disposed between the bottom electrode structure and the top electrode structure, for example an additional dielectric element constituting a shell coating of the multiferroic element, in particular a shell coating of the ferroelectric element.

[0040] The material of the additional dielectric element can be different from the material of the multiferroic element.

[0041] At least a portion of the material, in particular at least a substantial portion of the material, of the additional dielectric element can not be ferroelectric.

[0042] The first region between the first portion of the bottom electrode structure and the first portion of the top electrode structure can comprise the material of the multiferroic element but not the material of the additional dielectric element, and / or the second region between the second portion of the bottom electrode structure and the second portion of the top electrode structure can comprise the material of the additional dielectric element but not the material of the multiferroic element.

[0043] The first capacitor region can comprise or consist of the first portion of the bottom electrode structure, the first region, and the first portion of the top electrode structure, wherein the first capacitor region can have a negative capacitance.

[0044] According to some embodiments, the second capacitor region comprises or consists of the second portion of the bottom electrode structure, the second region, and the second portion of the top electrode structure, wherein the second capacitor region has a positive capacitance.

[0045] The space between the bottom electrode structure and the top electrode structure can comprise a gas or a vacuum.

[0046] The space between the bottom electrode structure and the top electrode structure can be partially or completely filled by the multiferroic structure and the additional dielectric element.

[0047] The multiferroic element can have a thickness along a first direction pointing from the bottom electrode to the top electrode, wherein the width of the multiferroic element at the position of the shortest separation line exceeds the thickness.

[0048] According to some embodiments, the width of the multiferroic element at the position of the shortest separation line does not exceed 1,000 nm, in particular does not exceed 100 nm, or does not exceed 50 nm, or does not exceed 20 nm, or does not exceed 15 nm.

[0049] The corresponding width of the multi-domain element advantageously facilitates formation of a topological domain wall, in particular controlled formation of a topological domain wall at a location proximate to the shortest separation line.

[0050] According to some embodiments, the width of the multi-domain element at the location of the shortest separation line is at least 2 nm, in particular at least 5 nm, or at least 8 nm.

[0051] The plurality of topological domains can comprise exactly two topological domains.

[0052] Embodiments with exactly two topological domains can give a high level of control over formation of a topological domain wall, in particular controlled formation of a topological domain wall at a location proximate to the shortest separation line.

[0053] The at least one topological domain wall can comprise the shortest separation line when a difference between a surface potential of the bottom electrode and a surface potential of the top electrode is zero.

[0054] The difference between the surface potential of the bottom electrode and the surface potential of the top electrode can be a difference between a voltage of the bottom electrode and a voltage of the top electrode corrected for a work function difference between a work function of the bottom electrode and a work function of the top electrode.

[0055] In embodiments where the work function of the bottom electrode and the work function of the top electrode are the same, the difference between the surface potential of the bottom electrode and the surface potential of the top electrode can be a difference between the voltage of the bottom electrode and the voltage of the top electrode.

[0056] The field effect transistor can further comprise a second multi-domain element, wherein an additional dielectric element separates the multi-domain element and the second multi-domain element.

[0057] The second multi-domain element can have some or all of the features described above in the context of the multi-domain element.

[0058] Both the multi-domain element and the second multi-domain element can be arranged on top of the bottom electrode.

[0059] Both the multi-domain element and the second multi-domain element can be arranged below the top electrode.

[0060] In embodiments, the multi-domain structure can comprise at least three multi-domain elements, and an additional dielectric structure can separate each of the at least three multi-domain elements from any other element of the at least three multi-domain elements.

[0061] Each of the at least three multi-domain elements can be arranged between the bottom electrode and the top electrode.

[0062] In embodiments, the additional dielectric element can completely or partially enclose the cross-sectional area.

[0063] The additional dielectric element can completely or partially surround each multi-domain element comprised in the multi-domain structure.

[0064] The second multi-domain element can be disposed above the second gate dielectric.

[0065] In embodiments, the channel of the field effect transistor can have a fin structure, and the gate dielectric and the second gate dielectric can be arranged on different sides of the fin structure.

[0066] The gate dielectric and the second gate dielectric can form a continuous layer.

[0067] The field effect transistor can further comprise a second bottom electrode, the second bottom electrode can be disposed above the second gate dielectric, and the second multi-domain element can be disposed above the second bottom electrode.

[0068] The bottom electrode and the second bottom electrode can be electrically connected to have a common electrical potential.

[0069] The field effect transistor can comprise a second top electrode, and the second top electrode can be disposed above the second multi-domain element.

[0070] The top electrode and the second top electrode can be electrically connected to have a common electrical potential.

[0071] The additional dielectric element can be arranged above the second bottom electrode, and the second bottom electrode can be different from the bottom electrode.

[0072] In particular, the part of the bottom electrode structure of the negative-capacitance gate structure that is adapted to be coupled to the channel by the gate dielectric can comprise the bottom electrode or the second bottom electrode.

[0073] In corresponding embodiments, the first structure formed by the bottom electrode, the multi-domain element, and the top electrode can provide a negative capacitance, in particular a greater negative capacitance than a (positive) capacitance of the second structure formed by the second bottom electrode, the additional dielectric element, and the second top electrode.

[0074] The first structure can be formed on a part of the semiconductor substrate, and the second structure can be formed on a different part of the semiconductor substrate.

[0075] Separating the first structure and the second structure can improve flexibility of a layout design and make manufacturing of a device comprising the field effect transistor more efficient, e.g. more cost-effective, and / or easier, and / or more reliable.

[0076] The part of the bottom electrode structure that is adapted to be coupled to the channel by the gate dielectric can comprise the bottom electrode, and the second bottom electrode can be arranged remote from the channel.

[0077] The part of the bottom electrode structure that is adapted to be coupled to the channel through the gate dielectric can comprise a second bottom electrode, and the bottom electrode can be arranged away from the channel.

[0078] All bottom electrodes comprised in the bottom electrode structure can be electrically connected to each other, and / or all top electrodes comprised in the top electrode structure can be electrically connected to each other.

[0079] The charge of the bottom electrode can be floating.

[0080] In particular, the bottom electrode can be partially or completely surrounded by an insulating material.

[0081] In an embodiment, the field effect transistor can further comprise a charge control circuit electrically coupled to the bottom electrode, and the charge control circuit can be adapted to maintain a fixed charge of the bottom electrode.

[0082] In a second aspect, the disclosure relates to a method for operating a field effect transistor having a negative capacitance gate structure, wherein the field effect transistor comprises a channel and a gate dielectric arranged above the channel. The negative capacitance gate structure comprises a bottom electrode structure comprising a bottom electrode. A part of the bottom electrode structure is arranged above the gate dielectric. The negative capacitance gate structure further comprises a multiferroic structure and a top electrode structure. The multiferroic structure comprises a multiferroic element arranged above the bottom electrode, the multiferroic element comprising a plurality of topological domains and at least one topological domain wall. The top electrode structure comprises a top electrode arranged above the multiferroic element. The method comprises increasing a voltage of the top electrode in its modulus to reach a gate voltage, thereby changing a shape of the topological domain wall and amplifying a voltage of the bottom electrode in its modulus by a modulus that is larger than the modulus of the gate voltage.

[0083] According to an embodiment, the disclosure relates to a method for operating a field effect transistor having a negative capacitance gate structure, wherein the field effect transistor comprises a channel and a gate dielectric arranged above the channel. The negative capacitance gate structure comprises a bottom electrode structure comprising a bottom electrode. At least a part of the bottom electrode structure is arranged above the gate dielectric. The negative capacitance gate structure further comprises a ferroelectric structure and a top electrode structure. The ferroelectric structure comprises a ferroelectric element arranged above the bottom electrode, the ferroelectric element comprising a plurality of ferroelectric polarization domains and at least one ferroelectric domain wall. The top electrode structure comprises a top electrode arranged above the ferroelectric element. The method comprises increasing a voltage of the top electrode in its modulus to reach a gate voltage, thereby changing a shape of the ferroelectric domain wall and amplifying a voltage of the bottom electrode in its modulus by a modulus that is larger than the modulus of the gate voltage.

[0084] Alternatively, the topological domain can be represented by a topological excitation, in particular a topological soliton. The topological domain wall can be a topological excitation domain wall, in particular a topological soliton domain wall.

[0085] In particular, the topological domain can be a polariton and the topological domain wall can be a polariton domain wall; or the topological domain can be a skyrmion and the topological domain wall can be a skyrmion domain wall; or the topological domain can be a hopfion and the topological domain wall can be a hopfion domain wall.

[0086] The method can further comprise keeping the charge on the bottom electrode constant while increasing the voltage of the top electrode in its modulus.

[0087] Changing the shape of the topological domain wall can comprise increasing the curvature of the topological domain wall.

[0088] Each bottom electrode comprised in the bottom electrode structure can have the same bottom electrode voltage, and / or each top electrode comprised in the top electrode structure can have the same top electrode voltage.

[0089] Increasing the voltage of the top electrode in its modulus can be such that for each voltage applied to the top electrode a corresponding voltage of the bottom electrode is generated.

[0090] The method can further comprise decreasing the voltage of the top electrode in its modulus after the gate voltage has been reached, such that in particular for each voltage applied to the top electrode during increasing the voltage of the top electrode the same corresponding voltage of the bottom electrode is generated.

[0091] For each voltage applied to the top electrode, the corresponding voltage of the bottom electrode can correspond to a net polarization of the multiferroic element.

[0092] In embodiments, increasing the voltage of the top electrode to a reference value below the gate voltage can yield the same net polarization of the multiferroic element as decreasing the voltage of the top electrode to the reference value.

[0093] The method can be characterized by features corresponding to some or all of the features described above in the context of a field effect transistor.

[0094] In particular with respect to amplifying the voltage of the bottom electrode, the amplification effect can be significantly enhanced by an additional dielectric element, like a housing coating, which can adjust the total gate capacity to be negative but small by its modulus. BRIEF DESCRIPTION OF DRAWINGS

[0095] Figure 1a is a voltage-charge diagram illustrating a negative capacitance of the reversible static type,

[0096] Figure 1b is a voltage-charge diagram illustrating a negative capacitance of the reversible differential type,

[0097] Figure 1c is a voltage-charge diagram illustrating a negative capacitance of the irreversible transient type,

[0098] Figure 2a shows a perspective view of an exemplary field effect transistor having a negative capacitance gate structure,

[0099] Figure 2b shows an equivalent circuit of the field effect transistor having a negative capacitance gate structure of Figure 2a

[0100] Figure 3a schematically illustrates a cross-sectional area of a multi-domain element according to an embodiment,

[0101] Figure 3b schematically illustrates a cross-sectional area of a multi-domain element according to another embodiment,

[0102] Figure 3c schematically illustrates a cross-sectional area of a multi-domain element according to another embodiment,

[0103] Figure 4a schematically illustrates a vertical cross-section of a field effect transistor having a negative capacitance gate structure according to an embodiment, with a zero voltage applied,

[0104] Figure 4b schematically illustrates a vertical cross-section of a field effect transistor having a negative capacitance gate structure according to an embodiment of Figure 4a , but with a non-zero voltage applied,

[0105] Figure 4c schematically illustrates a horizontal cross-section of the field effect transistor of Figure 4a

[0106] Figure 4d schematically illustrates a horizontal cross-section of the field effect transistor of Figure 4b

[0107] Figure 5a schematically illustrates a perspective view of a field effect transistor having a negative capacitance gate structure according to another embodiment,

[0108] Figure 5b shows an equivalent circuit of the field effect transistor having a negative capacitance gate structure of Figure 5a

[0109] Figure 6a ​​​​schematically illustrates a horizontal cross-section of a multi-domain structure and additional dielectric elements of a field effect transistor having a negative capacitance gate structure according to another embodiment, and

[0110] Figure 6b schematically illustrates a horizontal cross-section of a multi-domain structure and additional dielectric elements of a field effect transistor having a negative capacitance gate structure according to another embodiment, and DETAILED DESCRIPTION

[0111] The following disclosure provides a number of different embodiments or examples for implementing circuits of field effect transistors having negative capacitance gate structures to produce improved versatility. Thus, the present disclosure can expand the capacitance matching window of field effect transistors. In particular, the present disclosure can implement negative capacitance gate structures that guarantee reversible, stable static negative capacitance, as opposed to non-linear differential capacitance or transient negative capacitance under transient dynamic mechanisms.

[0112] The following description of the specific examples of components and arrangements is not intended to limit the present disclosure. Indeed, the specific examples are merely examples of embodiments of the disclosure. For example, the formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed in direct contact, and embodiments in which additional features can be formed between the first and second features such that the first and second features do not directly contact. In addition, the present disclosure can repeat reference numerals and / or letters in each example. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the examples discussed.

[0113] In addition, the present disclosure can repeat reference numerals and letters in each example. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the examples discussed.

[0114] Further, for the sake of brevity, the disclosure can use only a few of the possible arrangements, configurations, elements, or options for the elements, and will not repeat similar descriptions at different locations of the present disclosure. In addition, the present disclosure can list a number of possible structural, functional, or positional relationships but not every possible relationship can be included. Moreover, the present disclosure can use the terms “first,” “second,” “third,” etc. to refer to different elements, but these elements should not be limited by these terms. The terms are used only to distinguish different elements. For example, a first element could be termed a second or third element, and, similarly, a second element could be termed a first or third element.

[0115] Likewise, a number or range of numbers described as “about,” “approximately,” or the like, encompasses numbers within a reasonable range given the nature of the described number, such as within + / - 10% of the described number or within + / - 5% or other values understood by one of skill in the art. For example, the term “about 5 nm” encompasses a range of sizes from 4.5 nm to 5.5 nm.

[0116] Various aspects of the present disclosure are now discussed in more detail below with reference to the accompanying drawings.

[0117] Figure 1a , Figure 1b and Figure 1c depicts the voltage-charge characteristic of different types of negative capacitance. In these figures, the horizontal axis corresponds to the charge Q on the capacitor and the vertical axis corresponds to the voltage U applied to the capacitor during a charging process. The charging process can include, starting from a negative voltage with a given modulus (absolute value), changing the voltage to a positive voltage of the same modulus and returning to the initial negative voltage. The arrow on the voltage-current curve indicates the direction of the charging process.

[0118] In Figure 1a , the dashed line 102a depicts a direct proportionality between the voltage U and the charge Q with a negative slope. The direct proportionality is a characteristic of a capacitor with a stable negative capacitance, and the negative slope defines the value of the stable static negative capacitance. Figure 1a The thick solid curve 104a in represents the voltage-current characteristic of a capacitor that exhibits a stable negative capacitance at least for sufficiently small applied voltages U and has a stable negative capacitance that is approximately independent of the voltage.

[0119] Figure 1b In , the thick solid line 104b depicts a non-linear, non-monotonic dependence of the voltage U on the applied charge Q. The falling part of the curve, where increasing charge leads to a decrease of the capacitor voltage, defines a differential negative capacitance. The dashed line 102b is tangent to the voltage-current characteristic in the corresponding voltage U / charge Q range, the slope depicts the value of the differential negative capacitance.

[0120] Figure 1c In , the thick solid curve 104c shows an example of a dynamic hysteresis behavior of the voltage U to the change of the charge Q of the capacitor, exhibiting a dynamic transient negative capacitance. Such a dynamic transient negative capacitance can be realized during transient, irreversible switching between equilibrium states. For example, the equilibrium states can correspond to two different states of a topological domain. The characteristic of the dynamic transient negative capacitance is that the tangents 102c and 102cc to the voltage-charge characteristic recorded upon increasing charge (right arrow 106) and decreasing charge (left arrow 108) are different, i.e., the device with the voltage-charge characteristic 104c has a hysteresis.

[0121] In the prior art, the term “negative capacitance” generally refers to the negative capacitance of a device with a single ferroelectric domain, see e.g. KR 2014 / 0004855 A. It can be expected that such a device has a hysteresis voltage-charge characteristic similar to the curve 104c in Figure 1c , and has a dynamic transient negative capacitance. In contrast, the present disclosure provides a field effect transistor with a negative capacitance gate structure featuring a stable static negative capacitance, as in Figure 1aThe solid line 104a in FIG. 1 schematically indicates that the hysteresis is weak or even negligible. In some embodiments, the technology of the present disclosure allows to achieve full reversibility and full absence of hysteresis. The field effect transistor according to the present description can thus reduce the heat generated in the operation of the field effect transistor. The field effect transistor according to the present description can thus have improved energy efficiency. Moreover, in conventional field effect transistors, the dissipation of such heat poses a severe limitation to the miniaturization of the technological circuits. The field effect transistor according to the present description can thus improve the miniaturization of the semiconductor integrated circuits comprising the field effect transistor. In addition, the reduction of the overall capacitance of the field effect transistor associated with the negative capacitance gate structure according to the present description can speed up the switching of the channel of the field effect transistor, thus speeding up the switching speed of the field effect transistor. The stable static negative capacitance can also provide a stable linear amplification of the gate voltage, which can be advantageous to overcome the 60-mV / decade subthreshold slope limit of the subthreshold slope.

[0122] Figure 2a A perspective view of an exemplary field effect transistor 200 having a negative capacitance gate structure 202 is shown. The negative capacitance gate structure 202 comprises a multi-domain element 204 having a plurality of topological domains, which in the context of some embodiments is also referred to as a domain structure or a multi-domain polarization structure. Topological domain walls 210 separate the topological domains 206, 208 of the domain structure. For example, the topological domains can correspond to ferroelectric polarization domains, polarons, skyrmions or hopfions; they can be separated by respective ferroelectric domain walls 210, polaron domain walls 210, skyrmion domain walls 210 or hopfion domain walls 210.

[0123] In the following, the field effect transistor 200 having a negative capacitance gate structure 202 is mainly exemplified with a multi-domain polarization texture (domain structure) comprising a first ferroelectric polarization domain 206 and a second ferroelectric polarization domain 208 separated by a ferroelectric domain wall 210. The first ferroelectric polarization domain 206 has a first polarization orientation thereof, and the second ferroelectric polarization domain 208 has a second polarization orientation thereof different from the first orientation. The ferroelectric domain wall 210 separates the first ferroelectric polarization domain 206 from the second ferroelectric polarization domain 208.

[0124] The ferroelectric element 204 is sandwiched between a bottom electrode 212 and a top electrode 214. The bottom electrode 212 is field coupled or electromagnetically coupled to the channel 216 via a gate dielectric 218. One of the electrodes 212, 214, preferably the bottom electrode 212, comprises a material that facilitates the formation of the domain structure of the ferroelectric element 204 during the fabrication thereof and / or stabilizes the domain structure of the ferroelectric element 204 during the operation of the field effect transistor 200. Alternatively, an additional material, such as a semiconducting or dielectric material, can be provided on the bottom electrode 212 to facilitate the formation of the domain structure during the fabrication, or to stabilize the domain structure.

[0125] In Figure 2a example embodiments, the bottom electrode 212 and the top electrode 214 are conformal to the ferroelectric element 204 at their interfaces with the ferroelectric element 204. In this example, the cross-sectional area of the ferroelectric element 204, the bottom electrode 212, and the top electrode 214 does not change in the direction from the bottom electrode 212 to the top electrode 214. In the context of the present disclosure, more complex shapes, e.g., changing the diameter or shape of the elements 204, 212, 214 included in the negative capacitance gate structure 202 in the direction z, are possible, as long as the size and shape of the ferroelectric element 204 is chosen to form a multi-domain polarization structure, e.g., a two-domain polarization structure.

[0126] The ferroelectric element 204 can comprise or be made of a variety of ferroelectric materials, including Pb(Zr,Ti)03, PbTi03, Hf02, in particular doped Hf02, including e.g., zirconium, BaTi03, Ba(Sr,Ti)03, P(VDF-TrFE). The ferroelectric element 204 can have a diameter (more generally, a width at the position of the shortest domain wall, which can correspond to the equilibrium domain wall when applying zero voltage at the top electrode, see the description of reference Figures 3a to 3c ) in the range of 2 nm to 1,000 nm, with an exemplary diameter (width at the position of the shortest domain wall) of about 10 nm. The thickness d f of the ferroelectric element can also fall in the range from 2 nm to 1,000 nm. The characteristic dimensions of the ferroelectric element 204 providing a static stable negative capacitance can vary for different materials and span a similar length interval. The shape of the negative capacitance gate structure 202 is chosen to be a disc or a cylinder. The cylindrical shape can have an advantage for achieving the desired stable reversible static negative capacitance value.

[0127] The top electrode 214 is connected to an external voltage source via a contact line 222 to provide an input voltage V g , which can be designated for applying a voltage adjustment. The bottom electrode 212 can not only improve the formation and / or stability of the domain structure described above, but can also provide a uniform electric potential at its bottom surface. The uniform electric potential at the bottom surface of the bottom electrode 212 can in turn improve the potential uniformity at the gate dielectric 218 and eventually at the channel at 216, thereby improving the performance of the field effect transistor. When changing the input voltage V gThe bottom electrode 212 can remain at a constant charge, e.g., zero charge, when changing the state of the field effect transistor 200, e.g., changing the resistance of the channel 216 between the first source / drain region 224 and the second source / drain region 226. An optional contact line 228 can be used to connect the bottom electrode 212 to an external source and can be used to adjust the charge at the electrode, e.g., change the charge if needed to move the operating point of the FET, or keep the charge constant, e.g., equal to zero.

[0128] Uncontrolled charge leakage between the bottom electrode 212 and the channel 216 can be prevented by the gate dielectric 218. For example, the gate dielectric 218 can include a high-k dielectric, including SiO2, Al2O3, Li2O, HfSiO4, Sc2O3, SrO, ZrO2, Y2O3, BaO, Ta2O5, BaO, WO3, MoO3, TiO2, SrTiO3, DyScO3. The gate dielectric 218 can also include a low-k dielectric such as SiO2or an organic dielectric.

[0129] The channel 216, the gate dielectric 218, the first source / drain region 224, and the second source / drain region 226 can all be formed on or in the substrate 220. For example, the substrate can be composed of a semiconductor such as crystalline silicon. The first source / drain region 224 and the second source / drain region 226 can be highly doped. According to Figure 2a example embodiments, the channel 216 has the same doping type (n-type or p-type) and / or conductivity (primarily electrons or holes) as the source / drain regions 224, 226, respectively, which is different from the doping type of the substrate 220. The source / drain regions 224, 226 can be connected to other electrical components, particularly other components of a semiconductor integrated circuit, using contact lines 230, 232. A back electrode 234, also referred to as a body electrode 234, can be present in some embodiments and is used to apply a body voltage. In embodiments with the body electrode 234, the body voltage can be used, e.g., as a reference for other potentials or voltages of the bottom electrode 212 and the top electrode 214, respectively. According to Figure 2a example embodiments, the body electrode 234 is grounded, but in alternative embodiments, a different voltage can be applied to improve the performance of the field effect transistor.

[0130] To fabricate the field effect transistor 200 with the negative capacitance gate structure 202, well-established nanofabrication procedures can be applied, in particular nanofabrication procedures developed in the context of the semiconductor industry. These procedures allow for the fabrication of complex designs in a precise and reliable manner. For example, advances in fabrication enable the creation of three-dimensional designs of the field effect transistor 200. Exemplary single-crystalline semiconductor substrates 220 with a selected type of doping or conductivity, e.g., n-conductivity, are commercially available from various sources. The source and drain features 224, 226 can be formed by appropriately doping regions of the substrate 220 or thereon, e.g., by ion implantation or depositing highly doped semiconductor material. The appropriate geometrical design is achieved by appropriate lithography and etching techniques, e.g., e-beam lithography and ion etching. The gate dielectric layer 218 can be grown, e.g., using ALD techniques. The bottom electrode 212 and the top electrode 214 can be created by sophisticated CVD and PVD methods and / or other suitable processes. For example, a ferroelectric layer can be disposed over, e.g., the bottom electrode 212 by, e.g., ALD methods and / or other suitable processes. An optional coating dielectric layer can be grown over the bottom electrode 212 by, e.g., ALD techniques. The elements 212, 204, 214 of the negative capacitance gate structure 202 can be constructed individually or together after their deposition, e.g., in a single construction step. In the former case, the geometrical configuration of each stage is designed using appropriate lithography techniques, e.g., extreme ultraviolet light or e-beam lithography. The top conductive layer can be formed on or in the substrate to form the gate, source and drain wire connections 222, 230, 232, e.g., by CVD and PVD methods. The patterning and architecture of the device will be implemented by, e.g., the Cadence Allegro software package and / or other suitable software packages.

[0131] Figure 2b An effective circuit diagram 240 of an embodiment of a field effect transistor 200 with a negative capacitance gate structure 202 similar to that of the embodiment of Figure 2a is presented. The field effect transistor 200 with the negative capacitance gate structure 202 similar to that of the embodiment of Figure 2b has a ferroelectric capacitor C f The ferroelectric capacitor 242 can correspond to a structure similar to that including the bottom electrode 212, the ferroelectric element 204, the negative capacitance gate structure 202 at the top electrode 214 in the embodiment of Figure 2a The gate voltage V g can correspond to a gate voltage V g applied to the top electrode 214 similar to the top electrode of the embodiment of d The dielectric capacitor 244 with the negative capacitance C s can correspond to a structure similar to that including the bottom electrode 212, the gate dielectric 218 and the channel 216 of the embodiment of s The internal operating voltage V q can correspond toFigure 2a The voltage at channel 216. To the reference potential 250 with capacitance C. s Capacitor 246 can be having a relationship with Figure 2a This is a capacitor with a structure similar to that of the channel 216 and the body electrode 234. The reference potential 250 can correspond to... Figure 2a The reference potential 250 is the potential of the substrate 220, or, in embodiments including the body electrode 234, the potential corresponding to the body electrode 234. Alternatively or additionally, the reference potential 250 may correspond to the potential of an internal depletion layer formed in a semiconductor substrate similar to the semiconductor substrate 220. Figure 2b In the example embodiment, the reference potential is grounded, but in alternative embodiments, a different reference potential may be applied. Current I q It can correspond to the flow and Figure 2a The current is similar to that of contact wire 228.

[0132] The negative capacitance of the gate structure 202 with ferroelectric element 204 is determined by the negative ferroelectric capacitance C of ferroelectric capacitor 242. f The ferroelectric capacitor 242 and the capacitor with positive capacitance C are generated. d (Right now, C d Dielectric capacitors 244 (>0) are connected in series. The total capacitance C of substructure 248, which consists of ferroelectric capacitor 242 and dielectric capacitor 244, is... g for C g = 1 / ( C d -1 + C f -1 ).

[0133] Optional intermediate contact 228' (which can be similar to) Figure 2a Contact wire 228) with current I Q The form in external source and located C d and C f Charge is transferred between reference points 250. Reference point 212' can correspond to... Figure 2a The point on the bottom electrode 212. Current. I Q Used to maintain a constant charge on one of the electrodes of the ferroelectric capacitor 242, and / or to maintain a constant charge on one of the electrodes of the dielectric capacitor 244. For example, the charge on the corresponding electrodes of capacitors 242 and 244 can be kept zero.

[0134] The quantity typically used to characterize the efficiency of devices, including field-effect transistors, is the volume factor. In a conventional field-effect transistor, V s V g and the body factor is greater than one. In the embodiment of the field-effect transistor 200 with the negative-capacitance gate structure 202 corresponding to the circuit diagram 240, the internal operating voltage Figure 2b s (which can correspond to the voltage at the channel 216) is related to the gate voltage V g (which can correspond to the voltage applied to the top electrode 214) as V .

[0135] C f The negative sign of the negative-capacitance gate structure 202 leads to a body factor

[0136]

[0137] that can be reduced to a value less than one, provided that (i.e., C g <0).

[0138] By integrating the negative-capacitance gate structure 202 with the ferroelectric element 204 into the gate stack, the field-effect transistor 200 of the present description can thus have a significantly reduced gate voltage V g while maintaining the same internal operating voltage V s in the region of the channel 216. This leads to a reduction of V s > V g and the body factor m to less than one, respectively. This can improve the switching speed of the field-effect transistor 200. This can also improve the energy efficiency of the field-effect transistor 200, thereby reducing energy dissipation and heat generation. Thus, the field-effect transistor 200 according to the present description can make an important step towards a subthreshold slope of more than 60-mV / decade at room temperature, which is considered a limiting slope in conventional field-effect transistors.

[0139] Figures 3a to 3c Some examples of cross-sectional areas 300a, 300b, 300c of the ferroelectric element 204 that can be applied in the negative-capacitance gate structure 202 are shown. The negative capacitance of the negative-capacitance gate structure 202 is closely related to the shape of the cross-sectional area of the ferroelectric element 204. According to Figure 2a ​​In one embodiment, the field-effect transistor 200 has a flat gate 216 and a cylindrical ferroelectric element 204. According to this embodiment, the cross-sectional region of the ferroelectric element 204 is as follows: Figure 3a The depicted circle 300a can be defined by the intersection of a horizontal (perpendicular to direction z) plane (i.e., a plane parallel to the bottom electrode 212) with the ferroelectric element 204 located in the region between the bottom electrode 212 and the top electrode 214. However, more complex shapes of the negative capacitance gate structure 202 are also possible, for example, if the channel 216 is not flat and / or arranged on an uneven portion of the semiconductor substrate. For example, in embodiments where the channel 216, gate dielectric 218, and / or negative capacitance gate structure 202 are bent, the cross-section of the ferroelectric element 204 can refer to the intersection of the bent surface with the ferroelectric element 204, for example, a bent surface coaxial or concentric with the arc of the bottom electrode 212, the channel 216, and / or the gate dielectric 218.

[0140] It is also possible for the channel 216 to be disposed on or at least partially disposed on two or three or more sides of the semiconductor fin structure, particularly a fin-type field-effect transistor. In such embodiments, the cross-sectional region of the ferroelectric element 204 may be defined by the intersection of the ferroelectric element 204 with a surface comprising two or three or more planes, each plane being parallel to one side of the fin structure on or within which the channel 216 is disposed. The cross-sectional region defined in this way may be curved or may comprise multiple flat regions. A flat cross-sectional region may be defined by appropriately projecting a cross-sectional region with curvature having several flat regions onto a single plane, for example by “tiling” several flat regions onto a single plane while maintaining at least some of their boundary lines.

[0141] For any cross-sectional region of any ferroelectric element 204, at least one shortest dividing line can be defined as the cross-sectional line with the minimum width, that is, the cross-sectional line that divides the cross-sectional region of the ferroelectric element 204 into two sub-regions of equal area and has the shortest intersection length with the cross-sectional region among all such cross-sectional lines.

[0142] Figures 3a to 3c The illustration depicts an exemplary method for defining minimum width section lines 302a, 302b, 302c for several exemplary cross-sectional regions 300a, 300b, 300c. According to this embodiment, for any one of the cross-sectional regions 300a, 300b, 300c, the shortest dividing line is determined that divides the cross-sectional region 300a, 300b, 300c into two regions of equal area. The selection of the shortest dividing line does not need to be unique, and for example, in… Figure 3aIn particular, any line including the center of the circular cross-sectional area 300a can be considered the shortest separation line in the context of the present disclosure. The minimum width is given by the cross-sectional length 302a, 302b, 302c of the shortest separation line 304a, 304b, 304c within the cross-sectional area 300a, 300b, 300c.

[0143] The method can be particularly useful for embodiments of the plurality of ferroelectric polarization domains comprising exactly two ferroelectric polarization domains 206, 208. In embodiments of the plurality of ferroelectric polarization domains comprising 3 (or 4 or any larger number) of ferroelectric polarization domains, a set of 2 (or 3 or any larger number) shortest separation lines dividing the cross-sectional area into 3 (or 4 or more) areas of equal area can be determined. The minimum width can then correspond to the length of the shortest separation line of the set of separation lines.

[0144] Figures 3a to 3c The cross-sectional areas 300a, 300b, 300c of FIGS. 3A, 3B, 3C have in common that their width changes in the vicinity (neighborhood) of the shortest separation line 304a, 304b, 304c. Such a shape can support the formation of a negative capacitance gate structure 202, which will be explained in more detail in the context of FIGS. 4A, 4B, 4C. Figure 4a , Figure 4b , Figure 4c and Figure 4d will be explained in more detail. The width change can be characterized using a reference line 306 depicted in FIG. 3B. The reference line 306 is parallel to the shortest separation line 304b and also lies within the cross-sectional area 300b. For the sake of clarity, the reference line is only shown in the embodiment of FIG. 3B, but can similarly and in a straightforward manner be defined for the embodiments of FIGS. 3A, 3C or any other cross-sectional area and shortest separation line of any other ferroelectric element 202. Figure 3b The difference between the length 308 of the reference line 306 and the length 302b of the shortest separation line 304b increases with increasing distance 310 between the reference line 308 and the shortest separation line 302b. Such a shape can be considered a property of the cross-sectional area of the ferroelectric element 204. It can also be sufficient if the difference between the length of the shortest separation line and the length of the reference line increases with the distance of the reference line from the shortest separation line in the vicinity of the shortest separation line, but not so for another reference line outside the vicinity of the shortest separation line. Figure 3b Figure 3a , Figure 3c

[0145] ​​The vicinity of the shortest separation lines 304a, 304b, 304c provides a preferential formation site for domain walls 210 which are advantageously used in the field effect transistor 200 according to the present disclosure with a negative capacitance gate structure 202. This can distinguish the field effect transistor 200 from conventional negative capacitance transistors which are based on a single domain structure without domain walls using a different working principle, for example as described in KR 2014 / 0004855 A. With both the ferroelectric polarization of the domain walls 210 and the ferroelectric polarization domains 206, 208, the field effect transistor 200 according to the present disclosure can advantageously have a voltage-charge characteristic without hysteresis, similar to Figure 1a The multi-domain structure 206, 208 of the field effect transistor 200 according to the present description can be particularly efficiently formed for a minimum 302a, 302b, 302c width of the cross-sectional area 300a, 300b, 300c of the ferroelectric element 204 of a few nanometers to a few tens of nanometers, for example for a minimum width 302a, 302b, 302c in the range from 2 to 20 nm. This makes the field effect transistor 200 with a negative capacitance gate structure 202 particularly attractive for integration in semiconductor devices and circuits.

[0146] Figures 4a to 4d The working mechanism of an exemplary field effect transistor 200 generating a negative capacitance of the negative capacitance gate structure 202 is illustrated. Figure 4a and Figure 4b A vertical cross-section of the field effect transistor 200 is shown. Figure 4c and Figure 4d A horizontal cross-section of the field effect transistor 200 is shown.

[0147] Figure 4a and Figure 4c The field effect transistor 200 with equal surface potentials of the bottom electrode 212 and the top electrode 214 is shown. The surface potential of the top electrode 214 can refer to the voltage of the top electrode 214 at its surface, which can correspond to the input voltage V gThe surface potential of the bottom electrode 212 can be defined analogously. In the depicted embodiment, the work function of the top electrode 214 and the bottom electrode 212 are considered to be identical for the sake of clarity. The bottom electrode 212 has been grounded (a voltage U = 0 is applied to the top electrode 214) and then isolated to have a floating potential. Thus, when a voltage of U = 0 is applied to the top electrode 214, there is no surface potential difference between the top electrode 214 and the bottom electrode 212. In this case, the domain wall 210 essentially comprises the shortest separation line. In the depicted embodiment of the cylindrical ferroelectric element 204 with two polarized domains 206, 208 and a circular cross-sectional area 300a, the domain wall 210 thus coincides with a plane along the z-direction comprising the center of the ferroelectric element 204. While the electrodes 212, 214 are each neutral in the whole, the charge along the respective electrode is distributed according to the polarization direction of the ferroelectric domains 206, 208, which compensates for the polarization of the polarized domains 206, 208, thereby reducing the electrostatic energy of the system. The minimum of the electrostatic energy of the system corresponds to the vanishing electric field inside the ferroelectric element 204.

[0148] Figure 4b and Figure 4d The field effect transistor 200 of Figure 4a , Figure 4c is shown, with the difference that a voltage U 0 is applied to the top electrode 214. The domain wall 210 is displaced relative to the position depicted in Figure 4a , Figure 4c to reduce the electrostatic energy of the system. The shape and position of the domain wall 210 are most clear in Figure 4d . The domain wall is displaced from its original zero-field (U = 0) splitting position to compensate for the electric field caused by the additional charge on the top electrode 214. Importantly, the domain wall 210 can tend to minimize its surface energy. Thus, the displacement to the edge of the ferroelectric element 204 can exceed the displacement required for the vanishing electric field within the ferroelectric domains 206, 208. The domain wall 210 can bow near the edge of the ferroelectric element 204 and with Figure 4a , Figure 4cThe curvature of the domain wall 210 may be increased compared to the curvature of the first domain wall 210. This bend and increased curvature of the domain wall 210 may generate a reverse electric field within the ferroelectric element 204 (compared to the electric field direction between the top electrode 214 and the bottom electrode 212 caused by applying a voltage U = U0 when the ferroelectric element 204 is replaced by a conventional dielectric). In other words, in the region of the ferroelectric element 204, the electric field has a component pointing from the negatively charged electrode (e.g., the bottom electrode 212 in the case of positive U0) to the positively charged electrode (e.g., the top electrode 214 in the case of positive U0). Furthermore, in the region of the ferroelectric element 204 with a reverse electric field direction, the bend and increased curvature of the ferroelectric domain wall 210 may cause more net polarization than is required to compensate for the electric field caused by the electrode charge. The physical principles underlying the generation of negative capacitance in ferroelectrics with double-domain textures are described in more detail in the following literature: "Harnessing ferroelectric domains for negative capacitance" by Luk'yanchuk, I., Tikhonov, Y., Sené, A., and VM Vinokur. Commun. Phys. 2, 22 (2019).

[0149] Figure 5a A field-effect transistor 200' with a negative capacitance gate structure 202' according to another embodiment is shown. Figure 5b The corresponding circuit diagram 240' is given.

[0150] Figure 5a Example 200' is similar to Figure 2a Embodiment 200, but further includes an additional dielectric element 400 located between the bottom electrode 212 and the top electrode 214. The portions of the bottom electrode 212 and the top electrode 214 having the additional dielectric element 400 sandwiched between them form an additional capacitor 252, which can contribute a positive capacitance C0 in parallel with the ferroelectric capacitor 242 including the bottom electrode 212, the top electrode 214, and the ferroelectric element 204. The total (negative) capacitance C of the negative capacitance gate structure 202... f Therefore, based on capacitances C0 and C f The sum is given, and therefore can be adjusted by filling the space between the top electrode 214 and the bottom electrode 212 with appropriate volumes of ferroelectric element 204 or dielectric element 400, respectively, to adjust C0 and C. f This allows for flexible adjustment of the capacitance C of the 248' substructure. g This adapts the operating mechanism of the field-effect transistor 200' with the negative capacitance gate structure 202' to the requirements of a given application. Specifically, according to...Figure 2a The negative capacitance of the field-effect transistor 200 in the embodiment may be too large (by its modulus) for a particular application, and the introduction of the additional dielectric element 400 can improve the reduction of the volume factor of the device including the field-effect transistor 200'.

[0151] refer to Figure 5b The circuit diagram 240' has a negative capacitor. C f Ferroelectric capacitor 242, positive capacitance C Additional capacitor 252 with 0>0 and positive capacitor C d The total capacitance of substructure 240' of dielectric capacitor 244 with a capacitance greater than 0 is: C g = 1 / ( C d -1 + ( C f + C 0) -1 Appropriate selection of the size of the additional dielectric element 400 can adjust... C 0 and therefore can realize capacitance. C g The expected value is negative.

[0152] and Figure 5a The voltage at channel 216 of the field-effect transistor 200' corresponds to the internal operating voltage. V s 'With the input voltage applied to the top electrode 214 V g The relationship is V s '= V g / (1 + C s / C g ) = V g / (1 + C s / C d + C s / ( C f + C 0)). C f The negative sign may cause the production of body factors.

[0153]

[0154] Reduced to a value less than one, provided that... (Right now, Therefore, this disclosure provides the opportunity to reduce the volume factor to a value significantly less than one, which can enhance the performance of devices including field-effect transistors 200' with negative capacitance gate structures 202'.

[0155] according to Figure 5a In embodiment 200', the ferroelectric element 204 is surrounded by an additional dielectric element 400, and the field-effect transistor 200' can be referred to as a field-effect transistor 200' with a coated capacitor. However, alternative designs of the negative capacitance gate structure 202' are possible, wherein the additional dielectric element 400 can be located, for example, adjacent to but specifically separated from the ferroelectric element 204, or even positioned away from the ferroelectric element 204, to improve the layout flexibility of the negative capacitance field-effect transistor 200'. In particular, in these designs, the shape and / or position of the additional dielectric element 400 can be selected independently of the cross-sectional area of ​​the ferroelectric element 204 and / or the shape and / or position of the ferroelectric element 204.

[0156] Figure 6a and Figure 6b Some other examples of negative capacitance gate structures 200”, 200'” with a feasible arrangement of ferroelectric elements 204a, 204b, 204c, 204d… and at least one additional dielectric element 400a, 400a', 400b, 400c are shown. Figure 6a and Figure 6b In an embodiment, ferroelectric element 400a connects ferroelectric elements 204a, 204b (and Figure 6b Separated from 204c). This allows for the provision of laterally extending negative capacitance gate structures 202”, 202'”. Each of the negative capacitance gate structures 202”, 202'” and structure 402 may include a single bottom electrode and a single top electrode, or alternatively, multiple bottom electrodes and / or top electrodes. The negative capacitance gate structure may include a first negative capacitance gate structure 202” and a second negative capacitance gate structure 202'”, and / or include a first negative capacitance gate structure 202” and a structure 402 with positive capacitance. Preferably, all top electrodes will be held at the same first potential, and all bottom electrodes will similarly be held at the same second potential. For example, the top and bottom electrodes may be formed having a shape defined by the outermost contour of each of the additional dielectric elements 400a, 400a', 400b, 400c above and below the additional dielectric elements 400a, 400a', 400b, 400c, and the ferroelectric elements 204a, 204b, 204c, 204d… Figure 6aIn embodiments, this results in a first negative capacitance gate structure 202” with ferroelectric elements 204a, 204b and an additional dielectric element 400a sandwiched between a first bottom electrode and a second top electrode, and a second negative capacitance gate structure 202’” with ferroelectric elements 204c, 204d and an additional dielectric structure 400b sandwiched between a second bottom electrode and a second top electrode. For example, the first negative capacitance gate structure 202” can be disposed on a first side of a fin structure of a field effect transistor, and the second negative capacitance gate structure 202’” can be disposed on a second side of the fin structure of the same field effect transistor.

[0157] Figure 6b An alternative embodiment is shown with an expanded additional dielectric structure 400a’ with multiple ferroelectric elements 204a, 204b, 204c... embedded therein. They are sandwiched between a first bottom electrode and a first top electrode forming a first negative capacitance gate structure 202”. Sandwiching an additional dielectric structure 400c between a second bottom electrode and a second top electrode results in forming a second layered structure 402. The first negative capacitance gate structure 202” can be used as a reservoir for negative capacitance, and the second layered structure 402 can be disposed above the channel and gate dielectric of a field effect transistor for gating the field effect transistor with the negative capacitance gate structure. Forming the first negative capacitance gate structure 202” away from the second layered structure 402 and disposing only the second bottom electrode on the gate dielectric and channel can improve layout flexibility of a semiconductor integrated circuit including a field effect transistor with a negative capacitance gate structure.

[0158] The description and drawings are illustrative only and are not intended to be limiting in any respect. The scope of the disclosure will be determined by the appended claims.

Claims

1. A field effect transistor (200, 200') having a negative capacitance gate structure (202, 202'), the field effect transistor (200, 200') comprising a channel (216) and a gate dielectric (218) arranged above the channel (216), the negative capacitance gate structure (202, 202') comprising: a bottom electrode structure comprising a bottom electrode (212), a multiferroic structure comprising a multiferroic element (204) arranged above the bottom electrode (212), the multiferroic element (204) comprising a plurality of topological domains (206, 208) and at least one topological domain wall (210), and a top electrode structure comprising a top electrode (214) arranged above the multiferroic element (204); wherein, at least a portion of the bottom electrode structure of the negative capacitance gate structure (202, 202') is arranged above the gate dielectric (218) and is adapted to be coupled to the channel (216) through the gate dielectric (218), wherein the multiferroic element (204) comprises: a cross-sectional area (300a, 300b, 300c) having an orientation corresponding to an orientation of a top surface of the bottom electrode (212), the cross-sectional area (300a, 300b, 300c) defining a shortest separation line (304a, 304b, 304c) to divide the cross-sectional area (300a, 300b, 300c) into a plurality of areas of substantially equal area, and a reference line (306) shifted with respect to the shortest separation line (304a, 304b, 304c) and lying in a surface defined by the cross-sectional area (300a, 300b, 300c), wherein a length (308) of the reference line (306) within the cross-sectional area (300a, 300b, 300c) is shorter than a length (302a, 302b, 302c) of the shortest separation line (304a, 304b, 304c) within the cross-sectional area (300a, 300b, 300c), the difference increasing near the shortest separation line (304a, 304b, 304c) with increasing distance (310) between the reference line (306) and the shortest separation line (304a, 304b, 304c).

2. The field effect transistor (200, 200') according to claim 1, wherein the topological domains (206, 208) are ferroelectric domains, and wherein the topological domain wall (210) is a ferroelectric domain wall.

3. The field effect transistor (200') according to claim 1 or 2, further comprising an additional dielectric element (400, 400a, 400a', 400b, 400c) arranged between the bottom electrode structure and the top electrode structure.

4. The field effect transistor (200, 200') according to claim 1 or 2, wherein The multi-domain element (204) has a thickness (d f ) along a first direction (z) pointing from the bottom electrode (212) to the top electrode (214), and wherein the width (302a, 302b, 302c) of the multi-domain element (204) at the shortest separation line (304a, 304b, 304c) position exceeds the thickness (d f ).

5. The field effect transistor (200, 200') according to claim 1 or 2, wherein a width (302a, 302b, 302c) of the multiferroic element (204) at the location of the shortest separation line (304a, 304b, 304c) does not exceed 50 nm.

6. The field effect transistor (200, 200') according to claim 1 or 2, wherein The plurality of topological domains (206, 208) comprises exactly two topological domains (206, 208).

7. The field effect transistor (200') according to claim 3, further comprising a second multi-domain element (204b), wherein, The additional dielectric element (400, 400a, 400a') separates the multi-domain element (204a) from the second multi-domain element (204b).

8. The field effect transistor (200') according to claim 3, wherein The additional dielectric element (400c) is arranged above a second bottom electrode, wherein the second bottom electrode is different from the bottom electrode (212), in particular wherein the part of the bottom electrode structure of the negative capacitance gate structure (202') adapted to be coupled to the channel (216) by the gate dielectric (218) comprises the bottom electrode (212) or the second bottom electrode.

9. The field effect transistor (200, 200') according to claim 1 or 2, wherein The charge of the bottom electrode (212) is floating.

10. A method for operating a field effect transistor (200, 200') having a negative capacitance gate structure (202, 202'), wherein, The field effect transistor (200, 200') comprises a channel (216) and a gate dielectric (218) arranged above the channel (216), wherein the negative capacitance gate structure (202, 202') comprises: a bottom electrode structure comprising a bottom electrode (212), wherein at least a part of the bottom electrode structure is arranged above the gate dielectric (218), a multi-domain structure comprising a multi-domain element (204) arranged above the bottom electrode (212), the multi-domain element (204) comprising a plurality of topological domains (206, 208) and at least one topological domain wall (210), and a top electrode structure comprising a top electrode (214) arranged above the multi-domain element (204); wherein the multi-domain element (204) comprises: a cross-sectional area (300a, 300b, 300c) having an orientation corresponding to an orientation of a top surface of the bottom electrode (212), the cross-sectional area (300a, 300b, 300c) defining a shortest separation line (304a, 304b, 304c) to divide the cross-sectional area (300a, 300b, 300c) into a plurality of areas of substantially equal area, and a reference line (306) shifted with respect to the shortest separation line (304a, 304b, 304c) and lying in a surface defined by the cross-sectional area (300a, 300b, 300c), wherein a length (308) of the reference line (306) within the cross-sectional area (300a, 300b, 300c) is shorter than a length (302a, 302b, 302c) of the shortest separation line (304a, 304b, 304c) within the cross-sectional area (300a, 300b, 300c), the difference increasing near the shortest separation line (304a, 304b, 304c) with increasing distance (310) between the reference line (306) and the shortest separation line (304a, 304b, 304c); The method comprises: a voltage of the top electrode (214) is increased in its modulus to reach a gate voltage, thereby changing a shape of the topological domain wall (210) and amplifying a voltage of the bottom electrode (212) in its modulus by a modulus larger than the modulus of the gate voltage.

11. The method according to claim 10, the method further comprising keeping a charge on the bottom electrode (212) constant while increasing a voltage of the top electrode (214) in its modulus.

12. The method of claim 10 or 11, wherein, changing the shape of the topological domain wall (210) comprises increasing a curvature of the topological domain wall (210).

13. The method of claim 10 or 11, wherein, each bottom electrode (212) comprised in the bottom electrode structure has the same bottom electrode voltage, and / or wherein each top electrode (214) comprised in the top electrode structure has the same top electrode voltage.

14. The method of claim 10 or 11, wherein, increasing the voltage of the top electrode (214) in its modulus is such that for each voltage applied to the top electrode (214) a corresponding voltage of the bottom electrode (212) is generated, and the method further comprises decreasing the voltage of the top electrode (214) in its modulus after the gate voltage has been reached, such that in particular for each voltage applied to the top electrode (214) during increasing the voltage of the top electrode (214) the same corresponding voltage of the bottom electrode (212) is generated.

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