Circuit for improving the linearity of a PAM4 analog receiving front-end and channel compensation

Abstract

The present application discloses a circuit for improving the linearity and channel compensation of a PAM4 analog receiving front-end, which includes a first stage and a second stage. The first stage includes: a first to twentieth transistor, a first resistor, a pair of second resistors, a pair of first capacitors, and a pair of second capacitors. In the first-stage circuit, the ninth and tenth transistors are directly connected to the ground terminal, and the electrical connection with the bias current source is cancelled. The input terminals of the ninth and tenth transistors are connected to the output signals of the nineteenth and twentieth transistors in the previous stage, so that the ninth and tenth transistors are both input pair transistors and current-source transistors. The overall current is restricted by the thirteenth and fourteenth transistors, so that the power supply voltage of the first stage where the ninth to fourteenth transistors are located can be relatively low.

Description

Technical Field

[0001] The present invention generally relates to the field of integrated circuit technology, and particularly relates to a circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end. Background Art

[0002] The PAM4 signal is a popular signal transmission technology for high-speed signal interconnection in the next-generation data center, and can be widely applied to the electrical or optical signal transmission of 200G / 400G interfaces.

[0003] As the data transmission speed gradually increases, the data transmission channel shows a large attenuation. Different application scenarios result in different signal amplitudes of the transmitted signal reaching the PAM4 analog receiving front end. Since PAM4 is a signal composed of four different levels, requirements are imposed on the amplitudes of the four different level signals. The difference in the amplitudes of the four different level signals is also called the linearity of the PAM4 analog receiving front end. After the PAM4 analog receiving front end compensates for the attenuation of the channel, it poses a great challenge to the linearity, that is, the magnitudes of the four output level amplitudes. On the other hand, the PAM4 analog receiving front end needs to have zeros at different frequencies to compensate for the attenuation of the channel at different frequencies and increase the bandwidth of the PAM4 analog front end.

[0004] As the process node advances, the power supply voltage that the transistor can withstand gradually decreases, which brings great difficulties to the design of the analog front end of high-speed PAM4 circuits. Summary of the Invention

[0005] The purpose of the present invention is to provide a circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end, enabling the circuit to operate at a low voltage and expanding the bandwidth of the circuit.

[0006] The present application discloses a circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end, including a first stage, which includes: a first to twentieth transistor, a first resistor, a pair of second resistors, a pair of first capacitors, and a pair of second capacitors; wherein,

[0007] The drain and gate of the first transistor, the gate of the second transistor, one end of each of the pair of second resistors, the gate of the seventeenth transistor, and the gate of the eighteenth transistor are connected and coupled to a bias current;

[0008] The drain of the second transistor, the drain of the third transistor, the gates of the fourth to sixth transistors, and the gates of the thirteenth to sixteenth transistors are connected;

[0009] The gate of the third transistor is coupled to a common-mode voltage;

[0010] The sources of the fourth to sixth transistors, the sources of the thirteenth to sixteenth transistors are connected to one end of each of the pair of first capacitors and are coupled to a voltage source;

[0011] The drains of the fifth and fifteenth transistors, the source of the nineteenth transistor, one end of one of the pair of first capacitors are connected to one end of the first resistor, the drains of the sixth and sixteenth transistors, the source of the twentieth transistor, the other end of the other of the pair of first capacitors are connected to the other end of the first resistor;

[0012] The drain of the nineteenth transistor, the gates of the ninth and eleventh transistors are connected to the drains of the seventh and seventeenth transistors, the drain of the twentieth transistor, the gates of the tenth and twelfth transistors are connected to the drains of the eighth and eighteenth transistors;

[0013] The gate of the seventh transistor is coupled to the other end of one of the pair of second resistors and one end of one of the pair of second capacitors, the gate of the eighth transistor is coupled to the other end of the other of the pair of second resistors and one end of the other of the pair of second capacitors;

[0014] The gate of the nineteenth transistor and the other end of one of the pair of second capacitors are coupled to a non-inverting input signal, the gate of the twentieth transistor and the other end of the other of the pair of second capacitors are coupled to an inverting input signal;

[0015] The sources of the eleventh and twelfth transistors are connected to the drains of the thirteenth and fourteenth transistors, the drain of the eleventh transistor is connected to the drain of the ninth transistor and outputs a first-stage non-inverting output signal, the drain of the twelfth transistor is connected to the drain of the tenth transistor and outputs a first-stage inverting output signal;

[0016] The sources of the first, second, seventh to tenth, seventeenth and eighteenth transistors are coupled to the ground terminal.

[0017] In a preferred example, the pair of first capacitors are variable capacitors, and the first resistor is a variable resistor.

[0018] In a preferred example, the pair of second capacitors are variable capacitors, and the pair of second resistors are variable resistors.

[0019] In a preferred example, the first stage further includes: a pair of third resistors, one of the pair of third resistors is connected in series between the drain and the gate of the eleventh transistor, and the other of the pair of third resistors is connected in series between the drain and the gate of the twelfth transistor.

[0020] In a preferred example, the first stage further includes: a pair of first inductors, one of the pair of first inductors being connected in series between the drain and the gate of the eleventh transistor, and the other of the pair of first inductors being connected in series between the drain and the gate of the twelfth transistor.

[0021] In a preferred example, the circuit further includes a second stage, which includes: the twenty-first to fortieth transistors, a fourth resistor, a pair of fifth resistors, a pair of fourth capacitors, and a pair of fifth capacitors; wherein,

[0022] The drain and the gate of the twenty-first transistor, the gate of the twenty-second transistor, one end of each of the pair of fifth resistors, and the gates of the thirty-fifth to thirty-eighth transistors are connected and coupled to a bias current;

[0023] The drain of the twenty-second transistor, the drain of the twenty-third transistor are connected to the gates of the twenty-fourth to twenty-sixth transistors;

[0024] The gate of the twenty-third transistor is coupled to a common-mode voltage;

[0025] The sources of the twenty-fourth to twenty-sixth transistors, the sources of the thirty-third to thirty-fourth transistors are connected to one end of each of the pair of fourth capacitors and coupled to a voltage source;

[0026] The drain of the twenty-fifth transistor, the source of the thirty-ninth transistor, and the other end of one of the pair of fourth capacitors are connected to one end of the fourth resistor, and the drain of the twenty-sixth transistor, the source of the fortieth transistor, and the other end of the other of the pair of fourth capacitors are connected to the other end of the fourth resistor;

[0027] The drain of the thirty-ninth transistor, the gates of the twenty-ninth and thirty-first transistors are connected to the drains of the twenty-seventh and thirty-seventh transistors, and the drain of the fortieth transistor, the gates of the thirtieth and thirty-second transistors are connected to the drains of the twenty-eighth and thirty-eighth transistors;

[0028] The gate of the twenty-seventh transistor is coupled to the other end of one of the pair of fifth resistors and one end of one of the pair of fifth capacitors, and the gate of the twenty-eighth transistor is coupled to the other end of the other of the pair of fifth resistors and one end of the other of the pair of fifth capacitors;

[0029] The gate of the thirty-ninth transistor and the other end of one of the pair of fifth capacitors are coupled to the in-phase output signal of the first stage, and the gate of the fortieth transistor and the other end of the other of the pair of fifth capacitors are coupled to the anti-phase output signal of the first stage;

[0030] The sources of the thirty - first and thirty - second transistors are connected to the drains of the thirty - third and thirty - fourth transistors. The drain of the thirty - first transistor is connected to the drain of the twenty - ninth transistor and outputs a second - stage in - phase output signal. The drain of the thirty - second transistor is connected to the drain of the thirtieth transistor and outputs a second - stage anti - phase output signal;

[0031] The sources of the twenty - first, twenty - second, twenty - seventh, twenty - eighth, thirty - fifth to thirty - eighth transistors are coupled to the ground terminal.

[0032] In a preferred example, the second stage further includes: a pair of sixth resistors, one of the pair of sixth resistors is connected in series between the drain and the gate of the thirty - first transistor, and the other of the pair of sixth resistors is connected in series between the drain and the gate of the thirty - second transistor.

[0033] In a preferred example, the second stage further includes: a pair of second inductors, one of the pair of second inductors is connected in series between the drain and the gate of the thirty - first transistor, and the other of the pair of second inductors is connected in series between the drain and the gate of the thirty - second transistor. In a preferred example, the second stage further includes: a pair of sixth capacitors, one of the pair of sixth capacitors is connected between the gate of the thirty - first transistor and the drain of the thirty - second transistor, and the other of the pair of sixth capacitors is connected between the drain of the thirty - first transistor and the gate of the thirty - second transistor.

[0034] In a preferred example, the second stage further includes: a comparator, whose output terminal is coupled to the gates of the thirty - third and thirty - fourth transistors, whose first input terminal is coupled to a reference voltage, and whose second input terminal is coupled to the second - stage in - phase output signal or the second - stage anti - phase output signal.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1) In order to enable the circuit to operate at a low voltage, in the first - stage circuit, M9 / M10 cancels the current source at the sources of M29 / M30 in the second stage and directly connects the M9 / M10 transistors to the ground. The input terminals of the M9 / M10 transistors are connected to the output signals of the previous - stage M19 / M10, making the M9 / M10 transistors both input pair transistors and current - source transistors. The overall current is limited by M13 / M14, so that the power supply voltage of the stage where M9 / M10 / M11 / M12 / M13 / M14 are located can be relatively low.

[0037] 2) In the first-stage circuit, the current sources at the sources of M7 / M8 are removed, and M7 / M8 are directly connected to ground, enabling the circuit to operate at a low supply voltage. The input terminals of M7 / M8 in the first-stage circuit are connected to the bias voltage through R2 / R2', and to the input signal through C2 / C2'. Thus, M7 / M8 serve both as bias current transistors and input differential pairs. This circuit structure provides an additional zero. In the structure of the first-stage circuit composed of the bias voltage, R2 / R2', C2 / C2', and M7 / M8, adjusting the values of R2 / R2' and C2 / C2' can provide zeros at different frequencies. Similarly, in the structure of the second-stage circuit composed of the bias voltage, R5 / R5', C5 / C5', and M27 / M28, adjusting the values of R5 / R5' and C5 / C5' can provide zeros at different frequencies.

[0038] 3) In the first-stage circuit, by adopting the previous-stage low-voltage structure and varying the bias current of M15 / M16 / M17 / M18, the gain at low frequencies in this stage of the circuit can be changed.

[0039] 4) In the first-stage structure, M7 / M8 form the input stage of the NMOS. The DC operating point of M7 / M8 is the bias voltage. Due to the presence of C2 / C2', there is a zero at the input of M7 / M8. High-frequency signals can be amplified by M7 / M8, while low-frequency signals cannot pass through C2 / C2'. Low-frequency signals can only be amplified by the upper input differential pair M19 / M20, resulting in poor linearity of the signal after amplifying the input signal. Similarly, in the second-stage circuit, by changing the size or type of M37 / M38 transistors, the linearity of the signal output can be optimized.

[0040] 5) Since the output load capacitance is large, to increase the bandwidth, in the second-stage structure, a new zero (in addition to the zero provided by the inductor) is formed by the differential transistors M31 / M32 and M29 / M30, R6 / R6', L2 / L2', and the variable capacitor C6 / C6'. The frequency of this zero can be changed by varying the value of C6 / C6'. When the bandwidth requirement is met, the inductor L2 / L2' can be removed from the circuit, and a new zero is formed solely by the differential transistors M31 / M32 and M29 / M30, R6 / R6', and the variable capacitor C6 / C6', thereby expanding the output bandwidth of the circuit.

[0041] 6) In the PVT condition, to stabilize the output common-mode level, the output stage consists of M33 / M34, the comparator outputs the common-mode level, and the input reference voltage forms a feedback circuit.

[0042] A large number of technical features are described in this specification and are distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of this application were to be listed, the specification would become overly lengthy. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of this specification, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (all of these technical solutions should be regarded as having been described in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A+B+C are disclosed, and in another example, features A+B+D+E are disclosed, and features C and D are equivalent technical means that perform the same function and only one of them can be used technically and it is impossible to use both simultaneously. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been described because it is technically infeasible, while the solution of A+B+C+E should be regarded as having been described. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 FIG. shows a schematic diagram of the first stage of a circuit for improving the linearity and channel compensation of a PAM4 analog receiving front-end in an embodiment of the present invention.

[0044] Figure 2 FIG. shows a schematic diagram of the second stage of a circuit for improving the linearity and channel compensation of a PAM4 analog receiving front-end in an embodiment of the present invention.

[0045] Figure 3 FIG. shows a schematic diagram of a simulation result in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] Aspects and examples of the present application will now be described. The following description provides specific details for a thorough understanding and implementation of these examples. However, those skilled in the art will understand that the present application can be practiced without many of these details.

[0047] In addition, some well-known structures or functions may not be shown or described in detail in order to be concise and avoid unnecessarily obscuring the relevant description.

[0048] The terms used in the following description are intended to be interpreted in the broadest reasonable manner, even when used in conjunction with the detailed description of certain specific examples of the present application. Some terms may be emphasized below, however, any term intended to be interpreted in any restricted manner will be clearly and specifically defined in this detailed description section.

[0049] The present application discloses a circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end. The circuit for linearity and channel compensation includes a first stage and a second stage. Figure 1 FIG. 2 shows a schematic diagram of the first stage 100 of the circuit for improving the linearity and channel compensation of the PAM4 analog receiving front end in an embodiment of the present application. Figure 2 FIG. 3 shows a schematic diagram of the first stage 200 of the circuit for improving the linearity and channel compensation of the PAM4 analog receiving front end in an embodiment of the present invention.

[0050] The first stage 100 includes: first to twentieth transistors M1 - M20, a first resistor R1, a pair of second resistors R2, R2', a pair of first capacitors C1, C1', and a pair of second capacitors C2, C2'.

[0051] The drain and gate of the first transistor M1, the gate of the second transistor M2, one end of each of the pair of second resistors R2, and the gates of the seventeenth transistor M17 and the eighteenth transistor M18 are connected and coupled to the bias current IB.

[0052] The drain of the second transistor M2, the drain of the third transistor M3, and the gates of the fourth to sixth transistors M4 - M6 are connected to the gates of the thirteenth to sixteenth transistors M13 - M16. The gate of the third transistor M3 is coupled to the common - mode voltage VCM - IN. In the first - stage circuit 100, by adopting the low - voltage structure of the pre - stage M7 / M8 plus the variation of the bias current of the M15 / M16 / M17 / M18 transistors, the gain at low frequencies in this stage of the circuit can be changed.

[0053] The sources of the fourth to sixth transistors M4 - M6, the sources of the thirteenth to sixteenth transistors M13 - M16 are connected to one end of a pair of first capacitors C1, C1' and coupled to the voltage source VDDH.

[0054] The drains of the fifth transistor M5 and the fifteenth transistor M15, the source of the nineteenth transistor M19, and the other end of the first capacitor C1 are connected to one end of the first resistor R1. The drains of the sixth transistor M6 and the sixteenth transistor M16, the source of the twentieth transistor M20, and the other end of the first capacitor C1' are connected to the other end of the first resistor R1.

[0055] The drain of the nineteenth transistor M19, and the gates of the ninth transistor M9 and the eleventh transistor M11 are connected to the drains of the seventh transistor M7 and the seventeenth transistor M17. The drain of the twentieth transistor M20, and the gates of the tenth transistor M10 and the twelfth transistor M12 are connected to the drains of the eighth transistor M8 and the eighteenth transistor M18;

[0056] The gate of the seventh transistor M7 is coupled to the other end of the second resistor R2 and one end of the second capacitor C2, and the gate of the eighth transistor M8 is coupled to the other end of the second resistor R2' and one end of the second capacitor C2'.

[0057] The gate of the nineteenth transistor M19 and the other end of the second capacitor C2 are coupled to the in-phase input signal INP, and the gate of the twentieth transistor M20 and the other end of the second capacitor C2' are coupled to the anti-phase input signal INN.

[0058] The sources of the eleventh transistor M11 and the twelfth transistor M12 are connected to the drains of the thirteenth transistor M13 and the fourteenth transistor M14. The drain of the eleventh transistor M11 is connected to the drain of the ninth transistor M9 and outputs the first-stage in-phase output signal OUTP1, and the drain of the twelfth transistor M12 is connected to the drain of the tenth transistor M10 and outputs the first-stage anti-phase output signal OUTN1.

[0059] The sources of the first transistor M1, the second transistor M2, the seventh to tenth transistors M7 - M10, the seventeenth transistor M17, and the eighteenth transistor M18 are coupled to the ground terminal VSSA.

[0060] In the first-stage circuit 100, the M9 / M10 transistors are directly connected to the ground terminal, canceling the electrical connection with the current source IB. The input terminals of the M9 / M10 transistors are connected to the output signals of the previous-stage M19 / M20 transistors, making the M9 / M10 transistors both input pair transistors and current source transistors. The overall current is limited by the M13 / M14 transistors, so that the power supply voltage of the first stage where the M9 / M10 / M11 / M12 / M13 / M14 transistors are located can be relatively low.

[0061] In the first-stage circuit 100, the sources of the M7 / M8 transistors are directly connected to the ground terminal, canceling the electrical connection with the current source IB, enabling the circuit to operate at a low power supply voltage. The input terminals of the M7 / M8 transistors in the first-stage circuit are connected to the bias current IB through R2 / R2' and to the input signal INP through C2 / C2'. Thus, the M7 / M8 transistors are both bias current transistors and input pair transistors. This circuit structure provides an additional zero point. In the structure of the first-stage circuit 100 composed of the bias voltage, the second resistors R2 / R2', the second capacitors C2 / C2', and the M7 / M8 transistors, by adjusting the magnitudes of R2 / R2' and C2 / C2', zero points at different frequencies can be provided.

[0062] In the first - stage structure, M7 / M8 form the input stage of the NMOS. The DC operating point of M7 / M8 is the bias voltage. Due to the existence of C2 / C2’, there is a zero - point in the input of M7 / M8. High - frequency signals can be amplified by M7 / M8, while low - frequency signals cannot pass through C2 / C2’. Low - frequency signals can only be amplified by the upper input differential pair transistors M19 / M20, resulting in poor linearity of the signal after amplifying the input signal.

[0063] In one embodiment, a pair of first capacitors C1, C1’ are variable capacitors, and the first resistor R1 is a variable resistor. In one embodiment, a pair of second capacitors C2, C2’ are variable capacitors, and a pair of second resistors R2 are variable resistors.

[0064] In one embodiment, the first - stage 100 further includes: a pair of third resistors R3, R3’. The third resistor R3 is connected in series between the drain and the gate of the eleventh transistor M11, and the third resistor R3’ is connected in series between the drain and the gate of the twelfth transistor M12.

[0065] In one embodiment, the first - stage 100 further includes: a pair of first inductors L1, L1’. The first inductor L1 is connected in series between the drain and the gate of the eleventh transistor M11, and the first inductor L1’ is connected in series between the drain and the gate of the twelfth transistor M12.

[0066] In one embodiment, the second - stage 200 includes: the twenty - first transistor to the fortieth transistor M21 - M40, the fourth resistor R4, a pair of fifth resistors R5, R5’, a pair of fourth capacitors C4, C4’, and a pair of fifth capacitors C5, C5’.

[0067] The drain and the gate of the twenty - first transistor M21, the gate of the twenty - second transistor M22, one end of the fifth resistors R5, R5’, and the gates of the thirty - fifth to thirty - eighth transistors M35 - M38 are connected and coupled to the bias current IB.

[0068] The drain of the twenty - second transistor M22, the drain of the twenty - third transistor M23 are connected to the gates of the twenty - fourth to twenty - sixth transistors M24 - M26. The gate of the twenty - third transistor M23 is coupled to the common - mode voltage VCM - IN.

[0069] The sources of the twenty - fourth to twenty - sixth transistors M24 - M26, the sources of the thirty - third to thirty - fourth transistors M33 - M34 are connected to one end of the fourth capacitors C4, C4’ and coupled to the voltage source VDDH.

[0070] The drain of the twenty-fifth transistor M25, the source of the thirty-ninth transistor M39, the other end of the fourth capacitor C4 are connected to one end of the fourth resistor R4, and the drain of the twenty-sixth transistor M26, the source of the fortieth transistor M40, the other end of the fourth capacitor C4' are connected to the other end of the fourth resistor R4.

[0071] The drain of the thirty-ninth transistor M39, the gates of the twenty-ninth M29 and thirty-first M31 transistors are connected to the drains of the twenty-seventh M27 and thirty-seventh transistors M37. The drain of the fortieth transistor M40, the gates of the thirtieth M30 and thirty-second transistors M32 are connected to the drains of the twenty-eighth M28 and thirty-eighth transistors M38. In the second-stage circuit 200, the sources of the M27 / M28 transistors are directly connected to the ground terminal, canceling the electrical connection to the current source IB, enabling the circuit to operate at a low supply voltage. The input terminals of the M27 / M28 transistors are connected to the bias current IB through R5 / R5', and to the input signal OUTP1 through C5 / C5'. Thus, the M27 / M28 transistors are both bias current transistors and input pair transistors. This circuit structure provides an additional zero point. In the structure composed of the bias voltage, the fifth resistors R5 / R5', the fifth capacitors C5 / C5' and the M27 / M28 transistors, adjusting the sizes of R5 / R5' and C5 / C5' can provide zero points at different frequencies.

[0072] In the second-stage circuit 200, the added M37 / M38 transistors and M27 / M28 form the NMOS input stage. The DC operating point of M27 / M28 is the bias voltage. Due to the existence of C5 / C5', there is a zero point in the input of M27 / M28. High-frequency signals can be amplified by M27 / M28, while low-frequency signals cannot pass through C5 / C5'. Low-frequency signals can only be amplified by the upper input differential pair transistors M39 / M40, resulting in poor linearity of the signal after amplifying the input signal. The input terminals of the M37 / M38 transistors are directly connected to the signal, and the DC operating point works at the output of the previous stage, amplifying the low-frequency and high-frequency signals of the previous stage output. By changing the size or type of the M37 / M38 transistors, the linearity of the signal output can be optimized.

[0073] The gate of the twenty-seventh transistor M27 is coupled to the other end of the fifth resistor R5 and one end of the fifth capacitor C5, and the gate of the twenty-eighth transistor M28 is coupled to the other end of the fifth resistor R5' and one end of the fifth capacitor C5'.

[0074] The gate of the thirty-ninth transistor M39 and the other end of the fifth capacitor C5 are coupled to the in-phase output signal OUTP1 of the first stage, and the gate of the fortieth transistor M40 and the other end of the fifth capacitor C5' are coupled to the anti-phase output signal OUTN1 of the first stage.

[0075] The sources of the thirty-first transistor M31 and the thirty-second transistor M32 are connected to the drains of the thirty-third transistor M33 and the thirty-fourth transistor M34. The drain of the thirty-first transistor M31 is connected to the drain of the twenty-ninth transistor M29 and outputs a second-stage in-phase output signal OUTP2. The drain of the thirty-second transistor M32 is connected to the drain of the thirtieth transistor M30 and outputs a second-stage anti-phase output signal OUTN2.

[0076] The sources of the twenty-first transistor M21, the twenty-second transistor M22, the twenty-seventh transistor M27, the twenty-eighth transistor M28, and the thirty-fifth to thirty-eighth transistors M35 - M38 are coupled to the ground terminal VSSA.

[0077] In one embodiment, the second stage 200 further includes a pair of sixth resistors R6, R6'. The sixth resistor R6 is connected in series between the drain and the gate of the thirty-first transistor M31, and the sixth resistor R6' is connected in series between the drain and the gate of the thirty-second transistor M32.

[0078] In one embodiment, the second stage 200 further includes a pair of second inductors L2, L2'. The second inductor L2 is connected in series between the drain and the gate of the thirty-first transistor M31, and the second inductor L2' is connected in series between the drain and the gate of the thirty-second transistor M32.

[0079] In one embodiment, the second stage 200 further includes a pair of sixth capacitors C6, C6'. The sixth capacitor C6 is connected between the gate of the thirty-first transistor M31 and the drain of the thirty-second transistor M32, and the sixth capacitor C6' is connected between the drain of the thirty-first transistor M31 and the gate of the thirty-second transistor M32. Due to the relatively large output load capacitance, to increase the bandwidth, the structure in the second stage 200 is adopted. The differential transistors M31 / M32 and M29 / M30, the sixth resistors R6, R6', the second inductors L2, L2', and the sixth capacitors C6, C6' variable capacitors form another zero point in addition to the zero point provided by the inductor. The zero point frequency can be changed with the change of the size of the sixth capacitor C6. When the bandwidth requirement is met, the second inductors L2, L2' can be removed from the circuit, and a new zero point is formed by the differential transistors M31 / M32 and M29 / M30, the sixth resistors R6, R6', and the sixth capacitors C6, C6' variable capacitors alone. Thereby, the output bandwidth of the circuit is expanded.

[0080] In one embodiment, the second stage 200 further includes: a comparator OPAMP, whose output terminal is coupled to the gates of the thirty-third transistor M33 and the thirty-fourth transistor M34, whose first input terminal is coupled to the reference voltage VREF, and whose second input terminal is coupled to the second-stage in-phase output signal OUTP2 or the second-stage anti-phase output signal OUTN2. In the case of PVT, to stabilize the common-mode level of the output, the output stage consists of M33 / M34, the comparator output common-mode level, and the input reference voltage to form a feedback circuit.

[0081] In addition, the second-stage circuit 200 can also set the M15 / M16 transistors in the first-stage circuit, which can change the gain at low frequencies in this stage of the circuit.

[0082] Figure 3 A schematic diagram of the simulation results of this application is shown. The zero point generated by the added R2 / C2 in the first stage is located at low frequencies. From the simulation results, at a frequency of 500 MHz, the gain of the signal is significantly larger than that at lower frequencies. In the second stage, it can be clearly seen from the simulation results that the peak point frequency of curve 2 is higher than that of curve 1 for R6 / L2 and the added C6. From the simulation results, the peak is pushed up by nearly 1.5 dB.

[0083] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one" does not exclude the existence of additional identical elements in the process, method, article or device including the said element. In the application documents of this patent, if it is mentioned that an act is performed according to a certain element, it means at least performing the act according to that element, including two cases: performing the act only according to that element, and performing the act according to that element and other elements. Expressions such as multiple, multiple times, multiple types, etc. include 2, 2 times, 2 types, and more than 2, more than 2 times, more than 2 types.

[0084] The term "coupled to" and its derivatives can be used herein. "Coupling" can mean that two or more elements are in direct physical or electrical contact. However, "coupling" can also mean that two or more elements are in contact with each other indirectly, but still cooperate or interact with each other, and can mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0085] This specification includes combinations of various embodiments described herein. Separate references to embodiments (e.g., "an embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated to be mutually exclusive or clearly understood to be mutually exclusive by those skilled in the art, these embodiments are not mutually exclusive. It should be noted that the word "or" is used in a non-exclusive sense in this specification unless the context clearly indicates otherwise or requires otherwise.

[0086] All documents mentioned in this specification are considered to be incorporated herein by reference in their entirety so that they can be used as a basis for modification if necessary. In addition, it should be understood that the above are only preferred embodiments of this specification and are not used to limit the scope of protection of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of one or more embodiments of this specification shall be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A circuit for improving the linearity and channel compensation of a PAM4 analog receiving front-end, characterized in that, it includes a first stage, which includes: a first to twentieth transistor, a first resistor, a pair of second resistors, a pair of first capacitors, and a pair of second capacitors; wherein, the drain and gate of the first transistor, the gate of the second transistor, one end of each of the pair of second resistors, the gate of the seventeenth transistor and the gate of the eighteenth transistor are connected and coupled to a bias current; the drain of the second transistor, the drain of the third transistor, the gates of the fourth to sixth transistors and the gates of the thirteenth to sixteenth transistors are connected; the gate of the third transistor is coupled to a common-mode voltage; the sources of the fourth to sixth transistors, the sources of the thirteenth to sixteenth transistors are connected to one end of each of the pair of first capacitors and coupled to a voltage source; the drains of the fifth and fifteenth transistors, the source of the nineteenth transistor, the other end of one of the pair of first capacitors are connected to one end of the first resistor, the drains of the sixth and sixteenth transistors, the source of the twentieth transistor, the other end of the other of the pair of first capacitors are connected to the other end of the first resistor; the drain of the nineteenth transistor, the gates of the ninth and eleventh transistors are connected to the drains of the seventh and seventeenth transistors, the drain of the twentieth transistor, the gates of the tenth and twelfth transistors are connected to the drains of the eighth and eighteenth transistors; the gate of the seventh transistor is coupled to the other end of one of the pair of second resistors and one end of one of the pair of second capacitors, the gate of the eighth transistor is coupled to the other end of the other of the pair of second resistors and one end of the other of the pair of second capacitors; the gate of the nineteenth transistor and the other end of one of the pair of second capacitors are coupled to a in-phase input signal, the gate of the twentieth transistor and the other end of the other of the pair of second capacitors are coupled to an anti-phase input signal; the sources of the eleventh and twelfth transistors are connected to the drains of the thirteenth and fourteenth transistors, the drain of the eleventh transistor is connected to the drain of the ninth transistor and outputs a first-stage in-phase output signal, the drain of the twelfth transistor is connected to the drain of the tenth transistor and outputs a first-stage anti-phase output signal; the sources of the first, second, seventh to tenth, seventeenth and eighteenth transistors are coupled to a ground terminal.

2. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front-end according to claim 1, characterized in that, the pair of first capacitors are variable capacitors, and the first resistor is a variable resistor.

3. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front-end according to claim 1, characterized in that, the pair of second capacitors are variable capacitors, and the pair of second resistors are variable resistors.

4. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front-end according to claim 1, characterized in that, The first stage further includes: a pair of third resistors, one of the pair of third resistors being connected in series between the drain and the gate of the eleventh transistor, and the other of the pair of third resistors being connected in series between the drain and the gate of the twelfth transistor.

5. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end according to claim 1, wherein, the first stage further includes: a pair of first inductors, one of the pair of first inductors being connected in series between the drain and the gate of the eleventh transistor, and the other of the pair of first inductors being connected in series between the drain and the gate of the twelfth transistor.

6. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end according to claim 1, wherein, the circuit further includes a second stage, which includes: transistors Q21 to Q40, a fourth resistor, a pair of fifth resistors, a pair of fourth capacitors, and a pair of fifth capacitors; wherein, the drain and the gate of the twenty-first transistor, the gate of the twenty-second transistor, one end of each of the pair of fifth resistors, and the gates of the thirty-fifth and thirty-sixth transistors are connected and coupled to a bias current, the gate of the thirty-seventh transistor is coupled to a common-phase input signal, and the gate of the thirty-eighth transistor is coupled to an anti-phase input signal; the drain of the twenty-second transistor, the drain of the twenty-third transistor are connected to the gates of the twenty-fourth to twenty-sixth transistors; the gate of the twenty-third transistor is coupled to a common-mode voltage; the sources of the twenty-fourth to twenty-sixth transistors, the sources of the thirty-third to thirty-fourth transistors are connected to one end of each of the pair of fourth capacitors and coupled to a voltage source; the drain of the twenty-fifth transistor, the source of the thirty-ninth transistor, and the other end of one of the pair of fourth capacitors are connected to one end of the fourth resistor, the drain of the twenty-sixth transistor, the source of the fortieth transistor, and the other end of the other of the pair of fourth capacitors are connected to the other end of the fourth resistor; the drain of the thirty-ninth transistor, the gates of the twenty-ninth and thirty-first transistors are connected to the drains of the twenty-seventh and thirty-seventh transistors, the drain of the fortieth transistor, the gates of the thirtieth and thirty-second transistors are connected to the drains of the twenty-eighth and thirty-eighth transistors; the gate of the twenty-seventh transistor is coupled to the other end of one of the pair of fifth resistors and one end of one of the pair of fifth capacitors, the gate of the twenty-eighth transistor is coupled to the other end of the other of the pair of fifth resistors and one end of the other of the pair of fifth capacitors; the gate of the thirty-ninth transistor and the other end of one of the pair of fifth capacitors are coupled to the common-phase output signal of the first stage, the gate of the fortieth transistor and the other end of the other of the pair of fifth capacitors are coupled to the anti-phase output signal of the first stage; The sources of the thirty-first and thirty-second transistors are connected to the drains of the thirty-third and thirty-fourth transistors. The drain of the thirty-first transistor is connected to the drain of the twenty-ninth transistor and outputs a second-stage in-phase output signal. The drain of the thirty-second transistor is connected to the drain of the thirtieth transistor and outputs a second-stage anti-phase output signal. The sources of the twenty-first, twenty-second, twenty-seventh, twenty-eighth, thirty-fifth to thirty-eighth transistors are coupled to the ground terminal.

7. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end according to claim 6, wherein, The second stage further includes: a pair of sixth resistors, one of the pair of sixth resistors is connected in series between the drain and the gate of the thirty-first transistor, and the other of the pair of sixth resistors is connected in series between the drain and the gate of the thirty-second transistor.

8. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end according to claim 6, wherein, The second stage further includes: a pair of second inductors, one of the pair of second inductors is connected in series between the drain and the gate of the thirty-first transistor, and the other of the pair of second inductors is connected in series between the drain and the gate of the thirty-second transistor.

9. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end according to claim 6, wherein, The second stage further includes: a pair of sixth capacitors, one of the pair of sixth capacitors is connected between the gate of the thirty-first transistor and the drain of the thirty-second transistor, and the other of the pair of sixth capacitors is connected between the drain of the thirty-first transistor and the gate of the thirty-second transistor.

10. The circuit for improving the linearity and channel compensation of a PAM4 analog receiving front end according to claim 6, wherein, The second stage further includes: a comparator, whose output terminal is coupled to the gates of the thirty-third and thirty-fourth transistors, whose first input terminal is coupled to a reference voltage, and whose second input terminal is coupled to the second-stage in-phase output signal or the second-stage anti-phase output signal.

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