Digital temperature sensor

Abstract

The embodiment of the present application provides a kind of digital temperature sensor, comprising: temperature sensing circuit, temperature determination circuit and voltage processing circuit consisting of voltage-driven analog device.Electric voltage processing circuit is electrically connected to the power supply end of digital temperature sensor, can utilize the volt-ampere characteristic of analog device to stabilize power supply voltage, and provide stable voltage processing after power supply voltage for temperature sensing circuit and temperature sensing circuit;Temperature sensing circuit can generate the temperature of the device to be measured corresponding to the signal to be measured;Temperature determination circuit can determine the temperature of the device to be measured according to the signal to be measured, realize the measurement of the temperature of the device to be measured.The embodiment of the present application designs suitable digital voltage domain voltage processing circuit using analog circuit, which can reduce the power supply voltage fluctuation of digital temperature sensor, help to reduce the influence of power supply voltage fluctuation on the temperature measurement accuracy of digital temperature sensor, and further help to improve the temperature measurement accuracy of digital temperature sensor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a digital temperature sensor. BACKGROUND

[0002] With the rapid development of integrated circuit technology, temperature sensors are widely used in medical treatment, environmental monitoring, machines and even temperature monitoring of chips. Although the analog temperature sensor has high temperature measurement accuracy, the circuit structure of the analog temperature sensor is complex and the power consumption is large. The digital temperature sensor is widely used in temperature measurement of chips due to the simple circuit structure and low power consumption.

[0003] Among them, the temperature measurement accuracy is an important indicator for measuring the performance of the temperature sensor, and how to improve the temperature measurement accuracy of the digital temperature sensor becomes a problem that the technical personnel in the field continuously researches. SUMMARY

[0004] The present application provides a digital temperature sensor to improve the temperature measurement accuracy of the digital temperature sensor.

[0005] The present application provides a digital temperature sensor, which comprises a temperature sensing circuit, a temperature determining circuit and a voltage processing circuit composed of a voltage driven analog device.

[0006] The voltage processing circuit is electrically connected to a power supply end for supplying power to the digital temperature sensor and the temperature sensing circuit, and is used for stabilizing the power supply voltage and providing the temperature sensing circuit with a stabilized voltage processing power supply voltage.

[0007] The temperature sensing circuit and the temperature determining circuit are electrically connected, and are used for sensing the temperature of a measured device, generating a to-be-measured signal carrying the temperature information of the measured device, and outputting the to-be-measured signal to the temperature determining circuit.

[0008] The temperature determining circuit is used for determining the temperature of the measured device according to the corresponding relationship between the to-be-measured signal and the pre-calibrated detection signal and temperature.

[0009] The digital temperature sensor provided by the embodiment of the present application comprises a temperature sensing circuit, a temperature determining circuit and a voltage processing circuit composed of analog devices driven by voltage. The voltage processing circuit is electrically connected between a power supply end for supplying power to the digital temperature sensor and the temperature sensing circuit, and can stabilize the power supply voltage by using the volt-ampere characteristic of the analog devices and provide the temperature sensing circuit and the temperature determining circuit with the stabilized power supply voltage. The temperature sensing circuit can sense the temperature of a measured device and generate a to-be-measured signal carrying the temperature information of the measured device. The temperature determining circuit can determine the temperature of the measured device according to the correspondence between the to-be-measured signal and the pre-labeled detection signal and temperature, and realize the measurement of the temperature of the measured device. The embodiment of the present application designs the voltage processing circuit suitable for the digital voltage domain by using the analog circuit, can stabilize the power supply voltage by using the volt-ampere characteristic of the analog devices, reduces the power supply voltage fluctuation of the digital temperature sensor, helps to reduce the influence of the power supply voltage fluctuation on the temperature measurement accuracy of the digital temperature sensor, and further helps to improve the temperature measurement accuracy of the digital temperature sensor. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the present application, constitute a part of the present application and illustrate the exemplary embodiments of the present application and their descriptions serve to explain the present application and do not constitute improper limitations on the present application. In the drawings:

[0011] Figure 1a And Figure 1b The working scene schematic diagram of the digital temperature sensor provided by the embodiment of the present application;

[0012] Figure 1c And Figure 2 The structure schematic diagram of the voltage processing circuit provided by the embodiment of the present application;

[0013] Figures 3-5 The circuit principle schematic diagram of the voltage processing circuit provided by the embodiment of the present application;

[0014] Figures 6-8 The circuit principle schematic diagram of another voltage processing circuit provided by the embodiment of the present application;

[0015] Figure 9 And Figure 10 The structure schematic diagram of the digital temperature sensor provided by the embodiment of the present application;

[0016] Figure 11 The structure schematic diagram of the temperature correction circuit and the temperature determining circuit provided by the embodiment of the present application;

[0017] Figure 12 The structure schematic diagram of the temperature sensing circuit provided by the embodiment of the present application;

[0018] Figure 13This is a schematic diagram of the structure of a ring oscillator provided in an embodiment of this application;

[0019] Figure 14 for Figure 13 The provided diagram shows the operating waveforms of the ring oscillator. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] While analog temperature sensors offer high accuracy, their complex circuitry and high power consumption significantly increase their effectiveness. Applying analog temperature sensors to chip temperature measurement would undoubtedly increase the chip's size and power consumption. Digital temperature sensors, on the other hand, are widely used in chip temperature measurement due to their simpler circuitry and lower power consumption.

[0022] For temperature sensors, temperature measurement accuracy is an important indicator of their performance. How to improve the temperature measurement accuracy of digital temperature sensors has become a problem that those skilled in the art have been continuously researching.

[0023] To improve the temperature measurement accuracy of a temperature sensor, this application proposes a novel temperature sensor. The temperature sensor includes a temperature sensing circuit, a temperature determination circuit, and a voltage processing circuit composed of voltage-driven analog devices. The voltage processing circuit is electrically connected to the power supply terminal that powers the digital temperature sensor, the temperature sensing circuit, and the temperature determination circuit. It utilizes the volt-ampere characteristics of the analog devices to stabilize the power supply voltage and provides a regulated voltage to the temperature sensing and temperature determination circuits. The temperature sensing circuit generates a test signal corresponding to the temperature of the device under test. The temperature determination circuit determines the temperature of the device under test based on the test signal, thus achieving temperature measurement. The temperature sensor provided in this application uses an analog circuit design suitable for the digital voltage domain voltage processing circuit. It utilizes the volt-ampere characteristics of the analog devices to stabilize the power supply voltage, reducing power supply voltage fluctuations and thus mitigating their impact on the temperature measurement accuracy of the digital temperature sensor, thereby improving the temperature measurement accuracy.

[0024] On the other hand, the voltage processing circuit is composed of voltage-driven analog devices, and the requirements of wide power voltage working range and low power voltage of the digital voltage domain can be met by using analog devices with different threshold voltages, so as to realize an analog voltage processing circuit that meets the voltage domain requirements of the digital temperature sensor.

[0025] The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0026] It should be noted that the same reference numerals represent the same objects in the following drawings and embodiments, and therefore, once an object is defined in one drawing or embodiment, it does not need to be further discussed in subsequent drawings and embodiments.

[0027] Figure 1a And Figure 1b The structural schematic diagram of the working scene of the digital temperature sensor provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the digital temperature sensor TS can measure the temperature of the measured device S1. Figure 1a As shown in FIG. 2, the digital temperature sensor TS can be coupled to the measured device S1 and integrated in the same chip as the measured device S1; as shown in FIG. 3, the digital temperature sensor TS and the measured device S1 are different chips. Among them, the chip can be a chip that can realize any function, for example, the chip can be a processor chip, a memory chip, etc. The processor chip can be a processor chip of any electronic device. For example, it can be a processor chip of an Internet of Things (IOT) device, a processor chip of a server, or a data center processor chip, etc. Figure 1a Figure 1b For the embodiment in which the digital temperature sensor TS and the measured device S1 are different chips, the distance between the digital temperature sensor TS and the measured device S1 is not limited when the digital temperature sensor TS measures the temperature of the measured device S1. Among them, the distance between the digital temperature sensor TS and the measured device S1 can be flexibly set according to the sensitivity of the digital temperature sensor TS to temperature and the requirement of the actual application scene to the temperature measurement accuracy, and is also limited by the processing technology to a certain extent.

[0028] For the processor S11 in the chip, the digital temperature sensor TS can be electrically connected to the processor S11, the digital temperature sensor TS can measure the temperature of the measured device S1 and provide the temperature of the measured device S1 to the processor S11; the processor S11 can perform a set operation according to the temperature of the measured device S1. For example, the processor can adjust the working mode of the measured device according to the temperature of the measured device; for another example, the processor can monitor whether the temperature of the measured device exceeds a set temperature threshold; if it is monitored that the temperature of the measured device exceeds the set temperature threshold, the measured device is limited to work in a high-frequency mode, etc.

[0029] For the processor S11 in the chip, the digital temperature sensor TS can be electrically connected to the processor S11, the digital temperature sensor TS can measure the temperature of the measured device S1 and provide the temperature of the measured device S1 to the processor S11; the processor S11 can perform a set operation according to the temperature of the measured device S1. For example, the processor can adjust the working mode of the measured device according to the temperature of the measured device; for another example, the processor can monitor whether the temperature of the measured device exceeds a set temperature threshold; if it is monitored that the temperature of the measured device exceeds the set temperature threshold, the measured device is limited to work in a high-frequency mode, etc. ​

[0030] like Figure 1a and Figure 1b As shown, the voltage processing circuit 10 can be electrically connected between the power supply terminal Vin that supplies power to the powered device and the powered device. Figure 1a and Figure 1b The illustration only takes the temperature sensing module S2 in the digital temperature sensor TS as an example of the powered device, but does not limit the implementation form and function of the powered device.

[0031] The voltage processing circuit 10 provided in this embodiment is composed of voltage-driven analog devices. It uses the volt-ampere characteristics of the analog devices to regulate the power supply voltage output from the power supply terminal Vin to obtain the power supply voltage Vout. The power supply voltage Vout is then output to the powered device. This provides the powered device with a regulated power supply voltage, which helps to improve the stability of the power supply voltage and thus reduce the impact of power supply voltage fluctuations on the powered device.

[0032] In this embodiment, the powered device can be any device that requires power, and the voltage processing circuit 10 is used to provide a stable power supply voltage to the powered device. For example, the powered device can be a powered device whose power supply voltage operates in the digital voltage domain, such as... Figure 1a and Figure 1b The temperature sensing module S2 in the digital temperature sensor TS shown. Figure 1a and Figure 1b In the middle, the voltage processing circuit 10 is used to provide a stable power supply voltage to the temperature sensing module S2, which can measure the temperature of the device under test S1.

[0033] The voltage processing circuit provided in this application embodiment consists of voltage-driven analog devices. By selecting analog devices with different voltage thresholds, it can adapt to different digital domain voltage operating ranges, thus realizing an analog voltage processing circuit that meets the requirements of a wide operating range of power supply voltages and lower required voltages in the digital voltage domain. For example, in a compact 12-nanometer field-effect transistor scheme, the digital domain voltage range can be from 500mV to 1050mV. By selecting analog devices with different voltage thresholds, the output voltage Vout of the voltage processing circuit 10 can be adjusted to meet the requirement of a wide range of digital domain voltages.

[0034] Alternatively, the lower voltage requirements in the digital domain can be met by selecting analog devices with ultra-low voltage thresholds (ULVT). ULVT devices can be MOSFETs, allowing the voltage processing circuit to output a supply voltage as low as 450mV, enabling the circuit to operate in the digital voltage domain and meeting the lower power supply voltage requirements of this domain. For example, in a compact 12nm MOSFET design, the supply voltage can be as low as 500mV. This is something that traditional analog voltage conversion circuits using PNP and NPN devices cannot achieve. On the one hand, transistors operate on a low-current-driven, high-current model; when a transistor is turned on, the generated current is large, resulting in a large load voltage, which cannot meet the low voltage requirements of the digital domain. On the other hand, voltage conversion circuits composed of transistors have a limited power supply voltage adjustment range, which cannot meet the wide voltage range requirements of the digital domain.

[0035] The implementation structure and working principle of the voltage processing circuit provided in the embodiments of this application will be described below. Figure 1c This is a schematic diagram of the voltage processing circuit provided in an embodiment of this application. Figure 1c As shown, the voltage processing circuit 10 includes: a current generation circuit 101, a current comparator 102, a current sampling circuit 103, and a voltage output circuit 104. The current generation circuit 101, the current comparator 102, the current sampling circuit 103, and the voltage output circuit 104 can be composed of voltage-driven analog devices.

[0036] In this embodiment, the current generating circuit 101, the current comparator 102, and the voltage output circuit 104 are electrically connected to the power supply terminal Vin that supplies power to the powered device. Specifically, the analog devices in the current generating circuit 101, the current comparator 102, and the voltage output circuit 104 are electrically connected to the power supply terminal Vin that supplies power to the powered device. The analog device in the current comparator 102 can be electrically connected to the analog device in the current generating circuit 101 to form a mirror circuit, and the analog device in the current comparator 102 is also electrically connected to the analog device in the current sampling circuit 103 to form a mirror circuit.

[0037] In this embodiment, the analog device in the current generating circuit 101 can generate a reference current I1 when driven. Since the analog device in the current comparator 102 forms a mirror circuit with the current generating circuit 101, it can generate a mirror current I2 of the reference current I1. The mirror current of the reference current refers to a current that is equal in magnitude and in the same direction as the reference current.

[0038] The analog device in the current comparator 102 is also electrically connected with the analog device in the voltage output circuit 104. The current comparator 102 generates a mirror current I2 of the reference current, which can trigger the analog device in the voltage output circuit 104 to output the supply voltage Vout, i.e., the voltage output circuit 104 generates the supply voltage Vout. The analog device in the current sampling circuit 103 is electrically connected with the voltage output circuit 104, which can sample the output voltage of the analog device in the voltage output circuit 104 to obtain a sampling current I3. Correspondingly, the supply voltage Vout output by the voltage output circuit 104 is sampled by the current sampling circuit 103 to obtain the sampling current I3. Since the analog device in the current comparator 102 is also electrically connected with the current sampling circuit 103 to form a mirror circuit, the analog device in the current comparator 102 can also generate a mirror current I4 of the sampling current I3.

[0039] In this embodiment, the current comparator 102 can adjust the supply voltage Vout output by the analog device of the voltage output circuit 104 according to the size relationship between the mirror current I3 of the reference current and the mirror current I4 of the sampling current. Specifically, the current comparator 102 can adjust the size of the conduction signal of the analog device of the voltage output circuit 104 according to the size relationship between the mirror current I3 of the reference current and the mirror current I4 of the sampling current, and then adjust the conduction capability of the voltage output circuit 104. By adjusting the conduction capability of the voltage output circuit 104, the supply voltage Vout output by the voltage output circuit 104 is adjusted.

[0040] The supply voltage Vout output by the voltage output circuit 104 changes, causing the sampling current I3 collected by the current sampling circuit 103 to change, and thus causing the mirror current I4 of the sampling current I3 to change. This process is repeated until the mirror current I4 of the sampling current is equal to the mirror current I3 of the reference current. When the mirror current I4 of the sampling current is equal to the mirror current I3 of the reference current, the conduction capability of the analog device in the voltage output circuit 104 reaches a balance, and the voltage output circuit 104 outputs a stable supply voltage Vout. By utilizing the IV characteristic of the analog device in the voltage output circuit 104, the voltage at the power supply end is stabilized, which helps to improve the stability of the power supply voltage.

[0041] The voltage output circuit 104 can be electrically connected with the powered device, and can output the supply voltage Vout to the powered device to provide the powered device with the stabilized supply voltage Vout, which can reduce the impact of power supply voltage fluctuations on the powered device.

[0042] In this embodiment, the current generation circuit 101, current comparator 102, current sampling circuit 103, and voltage output circuit 104 may be composed of voltage-driven analog devices, but their specific implementation is not limited. In some embodiments, the current generation circuit 101, current comparator 102, current sampling circuit 103, and voltage output circuit 104 may be constructed using voltage-driven analog devices. By using analog devices with different threshold voltages, the requirements for a wide operating range and low power supply voltage in the digital voltage domain can be met, thus realizing an analog voltage processing circuit that meets the requirements of the digital voltage domain.

[0043] The implementation of the current generation circuit 101, current comparator 102, current sampling circuit 103, and voltage output circuit 104 provided in the embodiments of this application will be described by way of example below.

[0044] In some embodiments, such as Figure 2 As shown, the current generating circuit includes a differential voltage circuit 1011 and a first mirror circuit 1012 connected in series. The differential voltage circuit 1011 and the first mirror circuit 1012 each include a voltage-driven analog device. The analog device in the differential voltage circuit 1011 is electrically connected to the power supply terminal Vin. The analog device in the current comparator 102 is electrically connected to the series path between the differential voltage circuit 1011 and the first mirror circuit 1012, forming a mirror circuit with the first mirror circuit 1012.

[0045] The differential voltage circuit 1011 can generate a voltage difference when its analog devices are driven, and can generate a reference current I0 based on the generated voltage difference. The differential voltage circuit 1011 can output the reference current I0 to the first mirror circuit 1012. Accordingly, the analog devices in the first mirror circuit 1012 can mirror the reference current I0 to generate a mirror current of the reference current I0, which serves as a reference current I1.

[0046] In this application embodiment, the specific implementation of the differential pressure circuit 1011 is not limited. In some embodiments, combined with Figures 3-8 As shown in the circuit diagram, the analog components of the differential voltage circuit 1011 may include: a first PMOS circuit 1011a and a second PMOS circuit 1011b with different threshold voltages. The threshold voltage of the first PMOS circuit is greater than or less than that of the second PMOS circuit. The differential voltage circuit 1011 may also include: a resistor R1.

[0047] In the embodiment, in order to realize the different threshold voltages of the first PMOS circuit 1011a and the second PMOS circuit 1011b, the first PMOS circuit 1011a and the second PMOS circuit 1011b can adopt PMOS tubes of different specifications. Alternatively, the first PMOS circuit 1011a and the second PMOS circuit 1011b can also adopt PMOS tubes of the same specification but different numbers. The specification of the PMOS tube refers to the type and size of the PMOS tube. The PMOS tubes of the same specification refer to the same type and size of the PMOS tube. The PMOS tubes of different specifications can be different in type and / or size.

[0048] For the embodiment of the first PMOS circuit 1011a and the second PMOS circuit 1011b using PMOS tubes of the same specification but different numbers, the number of PMOS tubes in the first PMOS circuit 1011a is greater than or less than the number of PMOS tubes in the second PMOS circuit 1011b. For the circuit including a plurality of PMOS tubes, the plurality of PMOS tubes are connected in parallel. The plurality refers to 2 or more. The more the number of PMOS tubes connected in parallel, the greater the threshold voltage of the PMOS circuit. For the case that the threshold voltage of the first PMOS circuit is greater than that of the second PMOS circuit, the number of PMOS tubes included in the first PMOS circuit is greater than the number of PMOS tubes included in the second PMOS circuit.

[0049] For example, the first PMOS circuit 1011a includes a plurality of PMOS tubes MP1 connected in parallel; the second PMOS circuit 1011b includes at least one PMOS tube MP2 of the same specification as the PMOS tube MP1; and the number of PMOS tubes MP1 is greater than the number of PMOS tubes MP2. In the case that the second PMOS circuit 1011b includes a plurality of PMOS tubes MP2, the plurality of PMOS tubes MP2 are connected in parallel.

[0050] In the embodiment, for the PMOS circuit including a plurality of PMOS tubes connected in parallel, the plurality of PMOS tubes share the source and drain; and the gate of each PMOS tube is electrically connected to the driving circuit (not shown in the figure). Accordingly, for the PMOS circuit including a plurality of PMOS tubes connected in parallel, the gate refers to the gate of each PMOS tube, and the source and drain refer to the common source and drain of the plurality of PMOS tubes.

[0051] In combination with the above description, the first PMOS circuit 1011a and the second PMOS circuit 1011b can be used as the first PMOS circuit 1011a and the second PMOS circuit 1011b of the first embodiment of the application. Figures 3-8The sources of the first PMOS circuit 1011a and the second PMOS circuit 1011b are electrically connected to the power supply terminal Vin. The gates of the first PMOS circuit 1011a and the second PMOS circuit 1011b are electrically connected across the resistor R1. The first PMOS circuit 1011a and the second PMOS circuit 1011b can be driven by a circuit ( Figures 3-8 (Not shown in the diagram) Startup. Since the threshold voltages of the first PMOS circuit 1011a and the second PMOS circuit 1011b are different, both circuits start up. The voltages across resistor R1 are the gate voltages of the first PMOS circuit 1011a and the second PMOS circuit 1011b, respectively. Because the voltages across resistor R1 are different, a voltage difference is generated across resistor R1. Furthermore, resistor R1 generates a reference current I0 due to this voltage difference; and I0 is output to the first branch 1012a of the first mirror circuit 1012.

[0052] The second branch 1012b of the first mirror circuit 1012 is electrically connected to the first PMOS circuit 1011a. When the first PMOS circuit 1011a starts, it triggers the second branch 1012b of the first mirror circuit to generate a mirror current of the reference current I0, i.e., a reference current I1. Specifically, when the first PMOS circuit 1011a starts, it triggers the second branch 1012b of the first mirror circuit to conduct, and the second branch 1012b generates current. Since the second branch 1012b and the first branch 1012a form a mirror circuit, the current generated by the second branch 1012b is equal to the current flowing in the first branch 1012a, i.e., the reference current I0. The second branch 1012b generates a mirror current of the reference current I0, i.e., the reference current I1.

[0053] Optionally, such as Figures 3-8 As shown, for the first mirror circuit 1012, the analog device of its first branch 1012a may include: NMOS transistor MN2; the analog device of the second branch 1012b of the first mirror circuit includes: NMOS transistor MN1 with the same specifications as NMOS transistor MN2. The drain of NMOS transistor MN2 is electrically connected to resistor R1; the gate of NMOS transistor MN2 is electrically connected to the gate of NMOS transistor MN1; the drain of NMOS transistor MN1 is electrically connected to the drain of the first PMOS circuit 1011a, and the drain and gate of NMOS transistor MN1 are shorted; the sources of NMOS transistors MN1 and MN2 are grounded.

[0054] Based on the connection relationship, the first PMOS circuit 1011a and the second PMOS circuit 1011b are started, the PMOS tube MP1 in the first PMOS circuit 1011a and the PMOS tube MP2 in the second PMOS circuit 1011b are turned on, the gate voltage of the NMOS tubes MN1 and MN2 is pulled up to be greater than the threshold voltage of the NMOS tubes MN1 and MN2, and the NMOS tubes MN1 and MN2 are triggered to be turned on. The NMOS tube MN2 is turned on, and a path 1 from the power supply end Vin to the ground through the second PMOS circuit 1011b, the resistor R1 and the NMOS tube MN2 is formed with the second PMOS circuit 1011b and the resistor R1. Figure 5 The voltage at both ends of the resistor R1 in the path 1 is equal to the gate voltage of the first PMOS circuit 1011a and the second PMOS circuit 1011b respectively, and the gate voltage of the first PMOS circuit 1011a and the second PMOS circuit 1011b is different, resulting in a voltage difference at both ends of the resistor R1, and then the resistor R1 generates a reference current I0 and outputs to the NMOS tube MN2. Correspondingly, the drain current of the NMOS tube MN2 is I0.

[0055] As shown in the dashed line in the middle, Figure 5 The NMOS tube MN1 is turned on, and a path 2 from the power supply end Vin to the ground through the first PMOS circuit 1011a and the NMOS tube MN1 is formed with the first PMOS circuit 1011a, because the NMOS tube MN1 and the NMOS tube MN2 form a mirror circuit, the drain current I1 of the NMOS tube MN1 is equal to the drain current I0 of the NMOS tube MN2, and the drain current of the NMOS tube MN2 can be understood as the mirror image of the drain current of the NMOS tube MN1, that is, the NMOS tube MN1 generates a reference current I1 which is the mirror image of the reference current I0.

[0056] In combination with Figures 3-8 , the current comparator 102 is electrically connected to the series connection path of the drain of the first PMOS circuit 1011a and the drain of the NMOS tube MN1, and forms a mirror circuit with the NMOS tube MN1. Therefore, the current comparator 102 generates a mirror current I2 of the reference current I1 during the starting of the first PMOS circuit 1011a. Specifically, the first PMOS circuit 1011a is started, the current comparator 102 is triggered to be turned on, a path is formed, and the current comparator 102 generates a current. Because the current comparator 102 forms a mirror circuit with the NMOS tube MN1, the current in the current comparator 102 is equal to the reference current I1, that is, the current comparator 102 generates a mirror current I2 of the reference current I1.

[0057] For the current comparator 102, as shown in the dashed line in the middle, Figure 2As shown, the current comparator 102 can include a first circuit unit 1021 and a second circuit unit 1022 connected in series. The first circuit unit 1021 and the second circuit unit 1022 include voltage-driven analog devices. The voltage output circuit 104 is electrically connected to a series connection path A of the first circuit unit 1021 and the second circuit unit 1022. The analog device in the first circuit unit 1021 is electrically connected to a series connection path of the differential voltage circuit 1011 and the first mirror circuit 1012, and forms a mirror circuit with the first mirror circuit 1012. The differential voltage circuit 1011 triggers the analog device in the first circuit unit 1021 to conduct when there is a voltage difference, and generates a current on the series connection path A of the first circuit unit 1021 and the second circuit unit 1022. Since the first circuit unit 1021 forms a mirror circuit with the first mirror circuit 1012, the first circuit unit 1021 conducts, and the current generated on the series connection path A is equal to the reference current I1 generated by the current generating circuit, i.e., the mirror current I2 of the reference current I1 generated on the series connection path A.

[0058] In combination Figures 3-8 In combination with the specific circuit structure of the differential voltage circuit 1011 and the first mirror circuit 1012, the first circuit unit 1021 is electrically connected to a series connection path of the drain of the first PMOS circuit 1011a and the drain of the NMOS tube MN1. Therefore, when the first PMOS circuit 1011a is started, the voltage of the connection end of the series connection path of the first circuit unit 1021, the drain of the first PMOS circuit 1011a and the drain of the NMOS tube MN1 can be pulled up, triggering the first circuit unit 1021 to conduct, and generating the mirror current I2 of the reference current I1 on the series connection path A of the first circuit unit 1021 and the second circuit unit 1022.

[0059] Next, referring to Figure 2 The second circuit unit 1022 is electrically connected to the analog device in the current sampling circuit 103, and forms a mirror circuit with the current sampling circuit 103. The current sampling circuit 103 can sample the supply voltage Vout output by the analog device in the voltage output circuit 104 to obtain a sampling current I3. The analog device in the second circuit unit 1022 forms a mirror circuit with the circuit sampling circuit 103, and thus can generate a mirror current I4 of the sampling current I3 on the series connection path A of the second circuit unit 1022 and the first circuit unit 1021.

[0060] Accordingly, the current comparator 102 adjusts the size of the conduction signal of the analog device in the voltage output circuit 104 according to the size relationship between the mirror current I2 of the reference current and the mirror current I4 of the sampling current on the series connection path A of the first circuit unit 1021 and the second circuit unit 1022, so as to adjust the output voltage of the voltage output circuit 104. Specifically, since the voltage output circuit 104 is electrically connected to the series connection path A of the first circuit unit 1021 and the second circuit unit 1022, the mirror current I2 of the reference current and the mirror current I4 of the sampling current exist on the series connection path A, and in the case that the mirror current I2 of the reference current and the mirror current I4 of the sampling current are not equal, the conduction signal of the analog device in the voltage output circuit 104 is pulled up or pulled down according to the size relationship between the mirror current I2 of the reference current and the mirror current I4 of the sampling current on the series connection path A, so as to adjust the conduction capability of the voltage output circuit 104, thereby realizing the adjustment of the supply voltage Vout output by the voltage output circuit 104. Wherein, the size relationship between the mirror current I2 of the reference current and the mirror current I4 of the sampling current on the series connection path A and whether the conduction signal of the voltage output circuit 104 is pulled up or pulled down are determined by the specific implementation structure of the voltage output circuit 104 and the current comparator 102.

[0061] The working principle of the current comparator 102 and the voltage output circuit 104 will be exemplarily described below in combination with specific circuit structures. In the embodiment of the present application, as shown in Figures 3-8 the analog device of the voltage output circuit 104 can include a MOS tube. The gate of the MOS tube is electrically connected to the series connection path A of the first circuit unit 1021 and the second circuit unit 1022, the source thereof is electrically connected to the power supply end Vin, and the drain thereof serves as the voltage output end and is electrically connected to the current sampling circuit 103. Wherein, the current difference between the mirror current I2 of the reference current and the mirror current I4 of the sampling current can adjust the size of the conduction signal of the voltage output circuit 104, so as to adjust the output voltage of the voltage output circuit 104.

[0062] The MOS tube in the voltage output circuit 104 can be a PMOS tube or an NMOS tube. Wherein, the implementation form of the MOS tube in the voltage output circuit 104 can affect the circuit structure of the current comparator. The MOS tube in the voltage output circuit 104 will be exemplarily described below by taking the MOS tube as a PMOS tube or an NMOS tube as an example.

[0063] As shown in Figures 3-5As shown, for the analog device of the voltage output circuit 104, the first circuit unit 1021 includes NMOS MN3 for the embodiment of PMOS MP5. The source of NMOS MN3 is connected to ground. The drain of NMOS MN3 is electrically connected to the second circuit unit 1022, forming the above-mentioned series path A. The gate of NMOS MN3 is electrically connected to the series path of the differential voltage circuit 1011 and the first mirror circuit 1012. The differential voltage circuit 1011 can trigger NMOS MN3 to conduct when there is a voltage difference, generating a mirror current I2 of the reference current I1 on the series path A.

[0064] In combination Figures 3-5 As shown, the specific circuit structure of the differential voltage circuit 1011 and the first mirror circuit 1012 receives the current in the above-mentioned path 1 equal to the reference current I0, i.e. the current in the path 1 is the mirror current of the reference current I0. As the NMOS MN3 is electrically connected to the series path of the drain of the first PMOS circuit 1011a and the drain of NMOS MN1, the analysis of the reference current I1 is as follows. Therefore, when the first PMOS circuit 1011a is started, the first PMOS circuit 1011a conducts, the gate voltage of NMOS MN3 is pulled up, NMOS MN3 conducts, and the drain current is generated. Since NMOS MN3 and NMOS MN1 form a mirror circuit, the drain current of NMOS MN3 is equal to the reference current I1, which is equivalent to the drain of NMOS MN3 generating the mirror current I2 of the reference current I1. Since NMOS MN3 is connected in series with the second circuit unit 1022 to form the series path A, the mirror current I2 of the reference current I1 is generated on the series path A of the drain of NMOS MN3 and the second circuit unit 1022.

[0065] Correspondingly, as Figures 3-5 As shown, the analog device of the second circuit unit 1022 includes NMOS MN4 and the second mirror circuit 1022a including voltage-driven analog devices. The analog device of the second mirror circuit 1022a is connected in series with the drain of NMOS MN3 to form the series path A. The drain of NMOS MN4 is also connected in series with the second mirror circuit 1022a to form the series path B.

[0066] The gate of NMOS MN4 is electrically connected to the analog device in the current sampling circuit 103, and forms a mirror circuit with the analog device in the current sampling circuit 103. The current sampling circuit 103 triggers NMOS MN4 to conduct when the sampling current I3 exists, generating a mirror current I4 of the sampling current I3 on the series path B.

[0067] The analog device in the second mirror circuit 1022a mirrors the mirror current I4 of the sampling current I3 on the series path B, and generates a current equal to the mirror current I4 on the series path A with the NMOS tube MN3. The current can also be referred to as the mirror current I4 of the sampling current.

[0068] Optionally, as shown in Figures 3-5 The analog device of the second mirror circuit 1022a can include a PMOS tube MP3 and a PMOS tube MP4. The source of the PMOS tube MP3 and the source of the PMOS tube MP4 are electrically connected to the power supply end Vin. The gate of the PMOS tube MP3 is electrically connected to the gate of the PMOS tube MP4. The drain of the PMOS tube MP3 is electrically connected to the drain of the NMOS tube MN3, forming the series path A. The gate of the PMOS tube MP4 is short-circuited to the drain of the PMOS tube MP4. The drain of the PMOS tube MP4 is electrically connected to the drain of the NMOS tube MN4.

[0069] In combination with the circuit structure shown in Figures 3-5 When the current sampling circuit 103 has the sampling current I3, the gate voltage of the NMOS tube MN4 is pulled up due to the conduction of the current sampling circuit 103, the NMOS tube MN4 is turned on, and the drain current is generated. Since the NMOS tube MN4 forms a mirror circuit with the current sampling circuit 103, the drain current of the NMOS tube MN4 is equal to the sampling current I3, that is, the NMOS tube MN4 generates the mirror current I4 of the sampling current I3.

[0070] The drain voltage of the PMOS tube MP4 is pulled down due to the conduction of the NMOS tube MN4. Since the drain of the PMOS tube MP4 is short-circuited to the gate, and the gates of the PMOS tubes MP3 and MP4 are short-circuited, the gate voltages of the PMOS tubes MP3 and MP4 are also pulled down, and the PMOS tubes MP3 and MP4 are turned on, forming Figure 5 The drain of the PMOS tube MP4 is short-circuited to the drain of the NMOS tube MN4, forming the series path B. Therefore, the drain current of the PMOS tube MP4 is equal to the mirror current I4 of the sampling current I3, and the PMOS tube MP3 and the PMOS tube MP4 form the second mirror circuit 1012a. Therefore, the drain current of the PMOS tube MP3 is equal to the mirror current I4 of the sampling current I3, that is, the PMOS tube MP3 generates the mirror current I4 of the sampling current I3 on the series path A with the NMOS tube MN3.

[0071] For the PMOS transistor MP3 in the series connection path A with the NMOS transistor MN3, there are the mirror current I2 of the reference current and the mirror current I4 of the sampling current I3. In the starting stage of the voltage processing circuit, the mirror current I2 of the reference current and the mirror current I4 of the sampling current I3 are not equal, which leads to the mirror current I2 of the reference current and the mirror current I4 of the sampling current in the current comparator 102, the gate voltage of the PMOS transistor MP5 in the voltage output circuit 104 is adjusted, the conduction capability of the PMOS transistor MP5 is adjusted, and then the supply voltage of the drain output of the PMOS transistor MP5 can be adjusted. The change of the supply voltage of the drain output of the PMOS transistor MP5 leads to the change of the size of the sampling current I3 collected by the current sampling circuit 103, and then the mirror current I4 of the sampling current I3 in the current comparator 102 changes, and the process is repeated in sequence, until the mirror current I4 of the sampling current is equal to the mirror current I2 of the reference current in the current comparator 102, the gate voltage of the PMOS transistor MP5 no longer changes, and the stable supply voltage is output.

[0072] Specifically, it is assumed that in the starting stage of the voltage processing circuit, the mirror current I4 of the sampling current I3 is greater than the mirror current I2 of the reference current. Since the mirror current I4 of the sampling current I3 is greater than the mirror current I2 of the reference current, the gate voltage of the PMOS transistor MP5 connected in the series connection path A can be pulled up, the conduction capability of the PMOS transistor MP5 is reduced, and the supply voltage Vout of the drain output of the PMOS transistor MP5 is reduced. Further, since the supply voltage Vout of the drain output of the PMOS transistor MP5 is reduced, the sampling current I3 collected by the current sampling circuit 103 is reduced, and then the mirror current I4 of the sampling current I3 in the current comparator 102 is reduced, and the process is repeated in sequence, until the mirror current I4 of the sampling current I3 is equal to the mirror current I2 of the reference current in the current comparator 102. When the mirror current I4 of the sampling current I3 is equal to the mirror current I2 of the reference current, the gate voltage of the PMOS transistor MP5 no longer changes, the conduction capability of the PMOS transistor MP5 reaches stability, and then the supply voltage Vout of the drain output of the PMOS transistor MP5 reaches stability, that is, the IV characteristic of the PMOS transistor MP5 is used to realize voltage stabilization.

[0073] As shown in FIG. 1, Figures 6-8 In some other embodiments, the MOS transistor included in the voltage output circuit 104 is an NMOS transistor MN7. The source of the MOS transistor MN7 is electrically connected to the power supply end Vin, and the gate of the NMOS transistor MN7 is electrically connected to the series connection path A of the first circuit unit 1021 and the second circuit unit 1022. The current comparator 102 adjusts the size of the gate conduction signal of the NMOS transistor MN7 according to the size relationship between the mirror current of the reference current and the output current on the series connection path A, so as to adjust the supply voltage Vout of the drain output of the NMOS transistor MN7.

[0074] Correspondingly, for the embodiment that the MOS tube included in the voltage output circuit 104 is the NMOS tube MN7, in combination with Figures 6-8 , the analog device of the first circuit unit 1021 includes: the NMOS tube MN3 and the third mirror circuit 1021a including the voltage-driven analog device. The source of the NMOS tube MN3 is grounded; the drain of the NMOS tube MN3 is electrically connected with the third mirror circuit 1021a, forming the series connection path B. The analog device of the third mirror circuit 1021a is electrically connected with the second circuit unit 1022, forming the series connection path A.

[0075] As shown in Figures 6-8 , the gate of the NMOS tube MN3 is electrically connected on the series connection path of the differential voltage circuit 1011 and the first mirror circuit 1012, forming a mirror circuit with the first mirror circuit 1012; the differential voltage circuit triggers the NMOS tube MN3 to conduct in the presence of a voltage difference, generating the mirror current I2 of the reference current I1 on the series connection path B. Wherein, for the description of the NMOS tube MN3 generating the mirror current I2 of the reference current I1 on the series connection path B, please refer to the above Figures 3-5 related embodiments of the NMOS tube MN3 generating the mirror current I2 of the reference current I1 on the series connection path A.

[0076] Correspondingly, the analog device of the third mirror circuit 1021a can mirror the current on the series connection path B, generating the current equal to the current on the series connection path B, i.e. the mirror current I2 of the reference current I1, on the series connection path A.

[0077] Optionally, in combination with Figures 6-8 , the analog device of the third mirror circuit 1021a includes: the PMOS tube MP3 and the PMOS tube MP4. Wherein, the source of the PMOS tube MP3 and the source of the PMOS tube MP4 are electrically connected with the power supply end; the gate of the PMOS tube MP3 is electrically connected with the gate of the PMOS tube MP4; the drain of the PMOS tube MP3 is electrically connected with the drain of the NMOS tube MN3, forming the series connection path B. The gate of the PMOS tube MP4 is short-circuited with the drain of the PMOS tube MP4, and the drain of the PMOS tube MP4 is in series connection with the second circuit unit 1022, forming the series connection path A.

[0078] In this embodiment, the NMOS tube MN3 is turned on, triggering the PMOS tube MP3 and the PMOS tube MP4 to conduct, generating the mirror current I2 of the reference current I1 on the series connection path B of the PMOS tube MP3 and the NMOS tube MN3; the PMOS tube MP4 is turned on, generating the current equal to the current on the series connection path B, i.e. the mirror current I2 of the reference current, on the series connection path A.

[0079] Specifically, in combination with the above description of Figures 3-5The analysis of the conduction of NMOS MN3, in combination with Figures 6-8 As shown in the specific circuit structure, the conduction of NMOS MN3, the drain voltage of PMOS MP3 connected in series with NMOS MN3 is pulled low, because the drain and gate of PMOS MP3 are shorted, and the gates of PMOS MP3 and MP4 are shorted, thus the gates of PMOS MP3 and MP4 are pulled low, PMOS MP3 and MP4 are turned on, forming a current path as shown in the dotted line in Figure 8 from the power supply terminal Vin through PMOS MP3 and NMOS MN3 to ground, and a current path 6 from the power supply terminal Vin through PMOS MP4 and the second circuit unit 1022 to ground. Among them, the series path B is located on the current path 5, and the series path A is located on the current path 6. Because NMOS MN3 and NMOS MN1 form a mirror circuit, the drain current of NMOS MN3 is equal to the reference current, that is, the drain current of NMOS MN3 is equal to the mirror current I2 of the reference current I1. Correspondingly, the current on the series path B is also equal to the mirror current I2 of the reference current I1.

[0080] Further, because the drain of PMOS MP3 is connected in series with the drain of NMOS MN3, the drain current of PMOS MP3 is also equal to the mirror current I2 of the reference current I1. On the other hand, because PMOS MP4 and PMOS MP3 form a mirror circuit, the drain current of PMOS MP4 is equal to the drain current of PMOS MP3, that is, equal to the mirror current I2 of the reference current I1. Correspondingly, the current on the series path A is also equal to the mirror current I2 of the reference current I1, that is, the mirror current I2 of the reference current I1 is generated on the series path A of PMOS MP4 and the second circuit unit 1022.

[0081] Correspondingly, the analog device of the second circuit unit includes: NMOS MN4; the drain of NMOS MN4 is connected in series with the drain of PMOS MP4, forming a series path A.

[0082] The gate of the NMOS tube MN4 is electrically connected with the analog device of the current sampling circuit 103, and forms a mirror circuit with the analog device of the current sampling circuit 103. When the sampling current exists, the current sampling circuit 103 can trigger the NMOS tube MN4 to conduct, and generate a mirror current of the sampling current on the series connection path A. Specifically, when the sampling current exists, the current sampling circuit 103 can trigger the NMOS tube MN4 to conduct, and the NMOS tube MN4 generates a drain current. Since the NMOS tube MN4 forms a mirror circuit with the current sampling circuit 103, the drain current of the NMOS tube MN4 is equal to the mirror current I4 of the sampling current I3. Since the drain of the NMOS tube MN4 is connected with the PMOS tube MP4 in the first circuit unit 1021 in series, a current equal to the drain current of the NMOS tube MN4 is generated on the series connection path A, that is, the mirror current I4 of the sampling current I3 is generated on the series connection path A.

[0083] For the PMOS tube MP4 in the series connection path A with the NMOS tube MN4, there are the mirror current I2 of the reference current and the mirror current I4 of the sampling current I3. In the starting stage of the voltage processing circuit, the mirror current I2 of the reference current and the mirror current I4 of the sampling current I3 are not equal, which causes the mirror current I2 of the reference current and the mirror current I4 of the sampling current in the current comparator 102 to adjust the gate voltage of the NMOS tube MN7 in the voltage output circuit 104, to adjust the conduction capability of the NMOS tube MN7, and further to adjust the supply voltage outputted by the drain of the NMOS tube MN7. The change of the supply voltage outputted by the drain of the NMOS tube MN7 causes the change of the size of the sampling current I3 collected by the current sampling circuit 103, and further causes the change of the mirror current I4 of the sampling current I3 in the current comparator 102, and then the changes are repeated in sequence, until the mirror current I4 of the sampling current in the current comparator 102 is equal to the mirror current I2 of the reference current, and the gate voltage of the NMOS tube MN7 no longer changes, and a stable supply voltage is outputted.

[0084] Specifically, assuming that in the voltage processing circuit starting stage, the mirror current I4 of the sampling current I3 is greater than the mirror current I2 of the reference current, since the mirror current I4 of the sampling current I3 is greater than the mirror current I2 of the reference current, the gate voltage of the NMOS transistor MN7 connected on the series connection path A can be pulled down, the conduction ability of the PMOS transistor MP5 is reduced, and the supply voltage Vout outputted by the drain of the NMOS transistor MN7 is reduced. Further, since the supply voltage Vout outputted by the drain of the NMOS transistor MN7 is reduced, the sampling current I3 collected by the current sampling circuit 103 is reduced, and then the mirror current I4 of the sampling current I3 in the current comparator 102 is reduced, and the process is repeated, until the mirror current I4 of the sampling current I3 in the current comparator 102 is equal to the mirror current I2 of the reference current. When the mirror current I4 of the sampling current I3 is equal to the mirror current I2 of the reference current, the gate voltage of the NMOS transistor MN7 no longer changes, the conduction ability of the NMOS transistor MN7 reaches stability, and then the supply voltage Vout outputted by the drain of the NMOS transistor MN7 reaches stability.

[0085] In the embodiment of the present application, no matter which MOS transistor is used by the voltage output circuit 104, as shown in the following table, the current sampling circuit 103 can include a switch circuit 1031 including a voltage-driven analog device and an NMOS transistor MN5. Figures 3-8

[0086] In the embodiment of the present application, no matter which MOS transistor is used by the voltage output circuit 104, as shown in the following table, the current sampling circuit 103 can include a switch circuit 1031 including a voltage-driven analog device and an NMOS transistor MN5.

[0087] The gate of the NMOS transistor MN5 is electrically connected to the gate of the NMOS transistor MN4; the gate of the NMOS transistor MN5 is shorted to the drain; and the source of the NMOS transistor MN5 is grounded. In this way, the NMOS transistor MN5 and the NMOS transistor MN4 form a mirror circuit.

[0088] In the embodiment of the present application, no matter which MOS transistor is used by the voltage output circuit 104, as shown in the following table, the current sampling circuit 103 can include a switch circuit 1031 including a voltage-driven analog device and an NMOS transistor MN5.

[0089] Optionally, as shown in FIG. 2, the switch circuit 1031 can include a switch 1031a and a resistor R1. Figures 3-5 ​As shown, the analog device of the switch circuit 1031 can include an NMOS transistor MN6. The drain of the NMOS transistor MN6 is electrically connected to the voltage output circuit 104; the gate of the NMOS transistor MN6 is shorted to the drain; and the source of the NMOS transistor MN6 is electrically connected to the drain of the NMOS transistor MN5. Figures 3-5 As shown, the current sampling circuit, the source of the NMOS transistor MN6 is electrically connected to the voltage output terminal of the voltage output circuit 104, and the drain of the NMOS transistor MN6 is shorted to the gate. Therefore, the supply voltage output by the voltage output circuit 104 can pull up the gate voltage of the NMOS transistor MN6, and the NMOS transistor MN6 is turned on.

[0090] The turn-on of the NMOS transistor MN6 can pull up the drain voltage of the NMOS transistor MN5. Since the drain of the NMOS transistor MN5 is shorted to the gate, the turn-on of the NMOS transistor MN6 can pull up the gate voltage of the NMOS transistor MN5, triggering the NMOS transistor MN5 to be turned on. A path is formed from the supply voltage Vout output by the voltage output circuit 104 to ground through the NMOS transistors MN6 and MN5, which can generate a current, i.e., the sampling current I3, thereby achieving the current sampling of the supply voltage Vout by the current sampling circuit 103.

[0091] In other embodiments, as shown in FIG. 10, the analog device of the switch circuit 1031 can also include a PMOS transistor MP6. The source of the PMOS transistor MP6 is electrically connected to the voltage output circuit; the gate of the PMOS transistor MP6 is shorted to the drain; and the drain of the PMOS transistor MP6 is electrically connected to the drain of the NMOS transistor MN5. Figures 6-8

[0092] For the current sampling circuit shown in FIG. 10, the source of the PMOS transistor MP6 is electrically connected to the voltage output terminal of the voltage output circuit 104. Therefore, the supply voltage output by the voltage output circuit 104 can pull up the source voltage of the PMOS transistor MP6, so that the voltage difference between the source voltage and the gate voltage of the PMOS transistor MP6 is greater than the threshold voltage for the PMOS transistor MP6 to be turned on, and the PMOS transistor MP6 is turned on. Figure 4 The turn-on of the PMOS transistor MP6 can pull up the drain voltage of the NMOS transistor MN5. Since the drain of the NMOS transistor MN5 is shorted to the gate, the turn-on of the PMOS transistor MP6 can pull up the gate voltage of the NMOS transistor MN5, triggering the NMOS transistor MN5 to be turned on. A path is formed from the supply voltage Vout output by the voltage output circuit 104 to ground through the PMOS transistor MP6 and the NMOS transistor MN5, which can generate a current, i.e., the sampling current I3, thereby achieving the current sampling of the supply voltage Vout by the current sampling circuit 103.

[0093] The above-mentioned

[0094] Figures 3-8 ​​The current sampling circuit in the voltage processing circuit provided in the present application uses a MOS transistor as a sampling device, and the I-V characteristic of the MOS transistor can reduce the influence of the reference voltage I1 variation on the output supply voltage of the voltage sampling circuit, and reduce the variation of the supply voltage Vout caused by the reference current I1 variation.

[0095] It is worth mentioning that the above Figures 3-8 The circuit structure shown in the present application is only exemplary. In some embodiments, Figures 3-5 The current sampling circuit 103 shown in the present application can be combined with Figures 6-8 The current generation circuit 101, the current comparator 102, and the voltage output circuit 104 shown in the present application to form another voltage processing circuit. In other embodiments, Figures 6-8 The current sampling circuit 103 shown in the present application can be combined with Figures 3-5 The current generation circuit 101, the current comparator 102, and the voltage output circuit 104 shown in the present application to form another voltage processing circuit; and the like.

[0096] It is also worth mentioning that the voltage processing circuit provided in the present application can not only improve the stability of the output voltage, but also Figures 3-8 The voltage processing circuit provided in the present application can use MOS transistors with different voltage thresholds to stabilize the power supply end Vin for the powered device, obtain different supply voltages, and meet the different voltage requirements of the powered device, thereby meeting the wide range of requirements of the digital voltage domain for the power supply voltage. On the other hand, the MOS transistor can use an ultra-low voltage threshold (ulvt) MOS transistor, and the supply voltage output by the voltage processing circuit can be as low as 450 mV, which can meet the very low requirement of the digital voltage domain for the power supply voltage, for example, the digital voltage domain voltage can be as low as 500 mV. This cannot be achieved by the PNP and NPN devices in the traditional analog voltage conversion circuit.

[0097] Figures 3-8 The current comparator in the voltage processing circuit provided in the present application adopts a loop structure composed of MOS transistors, and the MOS transistor has a relatively high cutoff frequency, so the current comparator has a fast response speed and can be applied to high-frequency digital circuits.

[0098] The voltage processing circuit provided in the present application can be applied to any powered device to provide a stable supply voltage to the powered device. For example, the voltage processing circuit provided in the present application can be used as a power supply module of a digital temperature sensor to provide a stable voltage to the digital temperature sensor, which can reduce the influence of the power supply voltage fluctuation on the temperature measurement accuracy of the digital temperature sensor and help to improve the temperature measurement accuracy of the digital temperature sensor.

[0099] The digital temperature sensor provided in the embodiments of this application will be described exemplarily below.

[0100] Figure 9 This is a schematic diagram of the structure of a digital temperature sensor provided in an embodiment of this application. Figure 9 As shown, the digital temperature sensor (TS) includes a voltage processing circuit 10 composed of voltage-driven analog devices and a temperature sensing module S2. The temperature sensing module S2 includes a temperature sensing circuit 20 and a temperature determination circuit 30. The voltage processing circuit 10 is electrically connected to the temperature sensing circuit 20.

[0101] In this embodiment, the input terminal of the voltage processing circuit 10 is electrically connected to the power supply terminal Vin of the digital temperature sensor TS; its output terminal is electrically connected to the temperature sensing circuit 20 and the temperature determination circuit 30. The voltage processing circuit 10 can utilize the IV characteristic of its analog device to stabilize the power supply voltage and provide the temperature sensing circuit 20 and the temperature determination circuit 30 with a regulated power supply voltage Vout. For the specific implementation and working principle of the voltage processing circuit 10, please refer to the above. Figure 1b , Figure 1c and the above Figures 2-8 The relevant details will not be repeated here.

[0102] Temperature sensing circuit 20 is electrically connected to temperature determining circuit 30. For example, Figure 1a As shown, the temperature sensing circuit 20 can generate a test signal corresponding to the temperature of the device under test. This test signal can reflect the temperature information of the device under test to a certain extent. The temperature sensing circuit 20 outputs the generated test signal to the temperature determination circuit 30.

[0103] Accordingly, the temperature determination circuit 30 can determine the temperature of the device under test based on the signal under test, thereby realizing the temperature measurement of the device under test.

[0104] Optionally, the temperature determination circuit 30 can determine the temperature of the device under test based on the signal to be measured and the correspondence between the pre-calibrated detection signal and the temperature.

[0105] In this embodiment, the detection signal in the correspondence between the detection signal and temperature refers to the signal carrying temperature information generated by the temperature sensing circuit 20. The specific implementation of the correspondence between the detection signal and temperature is not limited in this embodiment. In some embodiments, the correspondence between the detection signal and temperature can be implemented as a mathematical model with the detection signal as the independent variable and temperature as the dependent variable. Accordingly, the temperature determination circuit 30 can input the signal to be measured as the independent variable value into the mathematical model for solution, obtaining the value of the dependent variable of the mathematical model, which is the temperature corresponding to the signal to be measured.

[0106] The correspondence between the detection signal and the temperature can be obtained by calibrating the temperature sensor before each measurement, or can be obtained by calibrating the temperature sensor before the temperature sensor is shipped. Accordingly, as shown in FIG. 4, the digital temperature sensor TS can further include a temperature correction circuit 40. The temperature correction circuit 40 is electrically connected between the temperature sensing circuit 20 and the temperature determination circuit 30, and is configured to calibrate the correspondence between the detection signal and the temperature, and provide the correspondence between the detection signal and the temperature to the temperature determination circuit 30. Figure 10

[0107] In some embodiments, when calibrating the temperature of the digital temperature sensor, the digital temperature sensor can be placed in a constant temperature device, and the temperature control accuracy of the constant temperature device is higher than the temperature measurement accuracy requirement of the temperature sensor. For example, the temperature measurement accuracy requirement of the temperature sensor is ≤±0.05℃, and the temperature control accuracy of the constant temperature device is higher than ±0.05℃, such as ±0.01℃, ±0.001℃, etc.

[0108] Accordingly, the temperature of the constant temperature device set when calibrating the temperature of the digital temperature sensor TS can be defined as a calibration temperature. In this embodiment, when calibrating the temperature of the digital temperature sensor TS, the digital temperature sensor TS can be tested multiple times at different calibration temperatures. Each test can set the temperature of the constant temperature device to a calibration temperature, so that the temperature sensing circuit 20 can sense the calibration temperature and output a test signal corresponding to the calibration temperature to the temperature correction circuit 40. In this embodiment, in order to improve the accuracy of temperature calibration, the temperature sensor TS can be tested multiple times at the same calibration temperature. The temperature sensing circuit 20 can sense the calibration temperature and output multiple test signals to the temperature correction circuit 40. Thus, the temperature correction circuit 40 can obtain multiple sets of test signals sensed by the temperature sensing circuit 20 at multiple calibration temperatures. Each calibration temperature corresponds to a set of test signals, and the set of test signals can include multiple test signals generated by the temperature sensing circuit 20 at the corresponding calibration temperature. Multiple means 2 or more than 2. Multiple means 2 or more than 2.

[0109] Further, the temperature correction circuit 40 can calibrate the correspondence between the detection signal output by the temperature sensing circuit and the temperature according to the multiple sets of test signals and the calibration temperatures in the process of obtaining the multiple sets of test signals.

[0110] ​In some embodiments, the temperature correction circuit 40 can calculate the average value of the test signal at each calibration temperature to obtain the test mean signal corresponding to multiple calibration temperatures respectively; and use the multiple calibration temperatures and the test mean signals corresponding to the multiple calibration temperatures to calculate the coefficients of the mathematical model reflecting the correspondence between the detection signal and the temperature; then, substitute the coefficients of the mathematical model into the mathematical model to obtain a mathematical model with the detection signal as the independent variable and the temperature as the dependent variable.

[0111] It should be noted that the above description only uses the calibration logic of the temperature correction circuit 40 as an example and does not limit the specific structure of the temperature correction circuit 40. In some embodiments, such as Figure 11 As shown, the temperature correction circuit 40 may include an averaging module 401 and a parameter calculation module 402. The averaging module 401 averages the test signals at each calibration temperature to obtain the average test signal at that calibration temperature. The parameter calculation module 402 uses multiple calibration temperatures and the corresponding average test signals to calculate the coefficients of a mathematical model reflecting the relationship between the detection signal and the temperature.

[0112] In this application embodiment, the specific implementation of the cumulative averaging module 401 and the parameter calculation module 402 is not limited. In some embodiments, such as Figure 11 As shown, the accumulator averaging module 401 may include an accumulator and a divider. Optionally, the accumulator may be composed of multiple cascaded adders. The number of adders is equal to (n-1), where n represents the number of test signals at each calibration temperature. n ≥ 2 and is an integer.

[0113] The accumulator sums the test signals at each calibration temperature and then inputs the summed signals into a divider for averaging to obtain the average test signal at that calibration temperature. Figure 11 As shown, the accumulator sums the test signals x11, x12, ..., x1n at the calibration temperature y1, and then inputs the summed signals into the divider for averaging to obtain the average test signal x1 at the calibration temperature y1; similarly, the average test signal x2 at the calibration temperature y2 can be obtained.

[0114] The specific circuit structure of the parameter calculation module 402 can be determined by the implementation form of the mathematical model, and the implementation form of the temperature sensing circuit 20 determines the relationship between the detection signal carrying temperature information output by the temperature sensing circuit 20 and the temperature. The specific implementation circuit of the temperature sensing circuit provided in this application embodiment will be described below by way of example.

[0115] like Figure 12As shown, the temperature sensing circuit 20 comprises: a plurality of ring oscillators (Ring OSCillatior, ROSC) 201 with different temperature sensing coefficients and a calculation circuit 202 electrically connected with the plurality of ring oscillators 201. The plurality refers to 2 or more than 2. Figure 12 Only 2 ring oscillators 201 are illustrated, but not limited thereto.

[0116] The plurality of ring oscillators 201 are electrically connected with the voltage processing circuit 10. The voltage processing circuit 10 outputs a supply voltage Vout to supply power for the plurality of ring oscillators 201. For the ring oscillators 201, the performance of the temperature sensing material in the ring oscillators 201 changes with the change of temperature, resulting in the change of the oscillation period of the ring oscillators 201 with the change of temperature, such as the oscillation period of the ring oscillators 201 can increase with the rise of temperature. Based on this, in the embodiment, the ring oscillators 201 can be used to sense the temperature. The ring oscillators 201 sense the temperature of the measured device and generate a clock signal corresponding to the temperature of the measured device; further, the ring oscillators 201 can also output the clock signal to the connected calculation circuit 202.

[0117] Although the oscillation period of a single ring oscillator changes with the change of temperature, the change relationship between the oscillation period and the temperature has a certain uncertainty. Considering that the change trend of the oscillation period of different ring oscillators 201 affected by temperature is the same, the ratio of the vibration periods of the plurality of ring oscillators 201 and the change of temperature has a certain linear relationship. Based on this, the temperature sensing circuit 20 provided in the embodiment sets the plurality of ring oscillators 201 with different temperature sensing coefficients. The ring oscillators 201 have different temperature sensing coefficients, so that different ring oscillators 201 can output clock signals with different oscillation periods at the same temperature.

[0118] In the embodiment, the number and specific implementation form of the ring oscillators 201 are not limited. Alternatively, the ring oscillators 201 can comprise: M cascaded inverters. Wherein, M is an odd number greater than 1. For two adjacent inverters, the output terminal of the former inverter is electrically connected with the input terminal of the latter inverter. The temperature sensing coefficients of the inverters in different ring oscillators 201 are different. The number of the inverters in different ring oscillators 201 can be the same or different.

[0119] Alternatively, as shown in FIG. 2, the temperature sensing circuit 20 comprises: a plurality of ring oscillators 201 with different temperature sensing coefficients and a calculation circuit 202 electrically connected with the plurality of ring oscillators 201. The plurality refers to 2 or more than 2. Figure 13As shown, the inverter in the ring oscillator 201 can be a CMOS inverter. The CMOS inverters in different ring oscillators 201 contain MOSFETs of different specifications. This is mainly because the gate oxide thickness and doping concentration of the MOSFET cause drift in the MOSFET's process parameters. Changes in the MOSFET's process parameters directly lead to changes in the MOSFET's threshold voltage and carrier mobility. Furthermore, the MOSFET's carrier mobility and threshold voltage change with temperature. Therefore, different specifications of MOSFETs have different temperature sensing coefficients, resulting in different temperature sensing coefficients for ring oscillators composed of different specifications of MOSFETs. Consequently, at the same temperature, ring oscillators composed of different specifications of MOSFETs output clock signals with different frequencies.

[0120] For CMOS inverters, such as Figure 13 As shown, a CMOS inverter can include a PMOS transistor and an NMOS transistor. The specifications of the PMOS and NMOS transistors differ in different ring oscillators. The source of the PMOS transistor is electrically connected to the voltage processing circuit 10 to receive the supply voltage Vout. The gate of the PMOS transistor is electrically connected to the gate of the NMOS transistor; the drain of the PMOS transistor is electrically connected to the drain of the NMOS transistor; the source of the NMOS transistor is grounded. For a CMOS inverter, the input terminal can be led out from the connection path between the gates of the PMOS and NMOS transistors, and the output terminal can be led out from the connection path between the drains of the PMOS and NMOS transistors. The input terminal of the CMOS inverter is electrically connected to the output terminal of the cascaded previous CMOS inverter; the output terminal of the CMOS inverter is electrically connected to the input terminal of the cascaded next CMOS inverter. Figure 13 The dashed line connecting CMOS inverter numbered 2 and CMOS inverter numbered M (M being an odd number greater than 1) indicates that the two inverters are indirectly connected through other CMOS inverters. In this embodiment, the ring oscillator contains an odd number of CMOS inverters greater than 1, but the number of CMOS inverters contained in the ring oscillator 201 is not limited.

[0121] The following is about Figure 13 The working principle of the ring oscillator constructed from the CMOS inverter shown is illustrated by way of example. Figure 13 As shown, for ease of description, Figure 13 The CMOS inverter numbered k is simply referred to as CMOS inverter k. Here, k = 1, 2, ..., M. M is the total number of CMOS inverters contained in the ring oscillator, and is an odd number greater than 1.

[0122] like Figure 13As shown, the voltage processing circuit 10 is electrically connected to the source of the PMOS transistor in the CMOS inverter. When the voltage processing circuit 10 supplies power to the CMOS inverter, the output voltage Vout of the voltage processing circuit 10 pulls up the source voltage of the PMOS transistor, turning it on. The PMOS transistor in CMOS inverter 1 turns on, outputting a high-level signal, which pulls up the gate voltages of the PMOS and NMOS transistors in CMOS inverter 2, causing the PMOS transistor in CMOS inverter 2 to turn off and the NMOS transistor to turn on, outputting a low-level signal. The NMOS transistor in CMOS inverter 2 turns on, pulling down the gate voltages of the PMOS and NMOS transistors in the next CMOS inverter connected to CMOS inverter 2, turning on the PMOS transistor in the next CMOS inverter connected to CMOS inverter 2, and so on, until the PMOS transistor in CMOS inverter M turns on, outputting a high-level signal. When the PMOS transistor in CMOS inverter M is turned on, it pulls up the gate voltage of the PMOS and NMOS transistors in CMOS inverter 1. When the PMOS transistor in CMOS inverter 1 is turned off, the NMOS transistor is turned on, outputting a low-level signal, and pulling down the gate voltage of the PMOS and NMOS transistors in CMOS inverter 2. This process repeats, with the PMOS transistor in CMOS inverter M turning off and the NMOS transistor turning on, outputting a low-level signal. Following the same principle, the ring oscillator 201 generates self-oscillation and produces a clock signal. Figure 14 for Figure 13 The diagram shows the operating waveform of the ring oscillator. The oscillation period of the clock signal is T = 2Mt0, where t0 represents the delay time of one CMOS inverter, and M represents the number of CMOS inverters included in the ring oscillator.

[0123] Since different ring oscillators 201 have different temperature sensing coefficients, they can output clock signals with different oscillation periods at the same temperature. Based on this, in this embodiment, the computing circuit 202 can calculate the ratio of the frequencies of the clock signals output by multiple ring oscillators as the test signal carrying temperature information generated by the temperature sensing circuit 20.

[0124] In this application embodiment, the specific implementation of the computing circuit 202 is not limited. In some embodiments, optionally, such as Figure 12 As shown, the calculation circuit 202 may include: multiple counters 202a connected to multiple ring oscillators 201 respectively, and a division unit 202b connected to the multiple counters 202a. Each ring oscillator 201 is connected to one counter 202a. The counters 202a can count pulses of the clock signal output from the ring oscillator 201 to which they are connected, and provide the counted number of pulses to the division unit 202b.

[0125] The division unit 202b can calculate the ratio of the number of pulses contained in the clock signals output by the plurality of ring oscillators 201 as the ratio of the frequencies of the clock signals output by the plurality of ring oscillators 201.

[0126] In the embodiments of the present application, each ring oscillator is connected with a counter. The working principle and implementation structure of the calculation circuit 202 are exemplarily described below by taking the number of ring oscillators as 2. In the embodiments of the present application, in order to facilitate description and distinction, the two ring oscillators 201 are defined as a first ring oscillator 201a and a second ring oscillator 201b, and the counters 202a connected with the first ring oscillator 201a are defined as a first counter Acc1 and a second counter Acc2. Correspondingly, the division unit 202b includes a flip-flop 202a electrically connected with the first counter Acc1 and the second counter Acc2, and a divider 202b electrically connected with the flip-flop 202a. The first counter Acc1 can be electrically connected with the signal input end of the flip-flop 202a, and the second counter Acc2 is electrically connected with the enable end of the flip-flop 202a.

[0127] The first counter Acc1 can count the pulses of the clock signal output by the first ring oscillator 201a and provide the number of pulses of the clock signal output by the connected ring oscillator to the flip-flop 202a. When the enable end of the flip-flop 202a is in an inactive state, the flip-flop 202a can register the number of pulses output by the first counter Acc1; when the enable end of the flip-flop 202a is activated, the flip-flop 202a can output the number of pulses output by the first counter Acc1. For example, for the D flip-flop shown in the figure, the signal input end D of the D flip-flop is electrically connected with the first counter 201a, and the enable end (CLK port) is electrically connected with the second counter 201b. When the enable end of the D flip-flop is in an inactive state, the D flip-flop can register the number of pulses output by the first counter ACC1; when the enable end of the D flip-flop is activated, the D flip-flop can output the number of pulses output by the first counter Acc1. Figure 12

[0128] The second counter Acc2 can count the pulses of the clock signal output by the second ring oscillator 201b and trigger the flip-flop 202a to output the number of pulses counted by the first counter Acc1 to the divider 202b when the second counter Acc2 counts to the full. Specifically, the second counter 201b can count the pulses of the clock signal output by the connected second ring oscillator and output an activation signal to the enable port (CLK port) of the flip-flop 202a when the pulse count is full, which can trigger the flip-flop 202a to output the number of pulses counted by the first counter 201a. For example, for the D flip-flop shown in the figure, the signal input end D of the D flip-flop is electrically connected with the first counter 201a, and the enable end (CLK port) is electrically connected with the second counter 201b. When the enable end of the D flip-flop is in an inactive state, the D flip-flop can register the number of pulses output by the first counter ACC1; when the enable end of the D flip-flop is activated, the D flip-flop can output the number of pulses output by the first counter Acc1. Figure 12 ​The D flip-flop is electrically connected with the first counter Acc1 at the signal input end D, and is electrically connected with the second counter ACC2 at the enable end (CLK port). When the second counter Acc2 is full, the second counter Acc2 outputs a high level signal to the enable end (CLK port) of the D flip-flop, so that when the enable end of the D flip-flop is activated, the D flip-flop can output the pulse number counted by the first counter Acc1 at the signal input end D.

[0129] In the embodiment of the present application, in order to facilitate calculation, the pulse number counted by the second counter 201b when full can be stored in the divisor end of the divider 202b, and in the case that the divider 202b receives the pulse number counted by the first counter ACC1 output by the flip-flop 202a at the dividend end, the ratio of the pulse number counted by the first counter Acc1 to the pulse number counted by the second counter Acc2 when full can be calculated as the ratio of the frequency of the clock signal output by the first ring oscillator 201a connected with the first counter Acc1 to the frequency of the clock signal output by the second ring oscillator 201b connected with the second counter Acc2, and as the detection signal (or to-be-detected signal) output by the temperature sensing circuit 20.

[0130] Compared with the uncertainty of the change relationship between the oscillation period of a single ring oscillator and temperature, the temperature sensing circuit provided in the embodiment uses the ratio of the frequencies of the clock information generated by multiple ring oscillators as the to-be-detected signal, and can obtain a certain linear relationship between the ratio of the frequencies of the clock information generated by multiple ring oscillators and temperature. Therefore, the digital temperature sensor provided in the embodiment uses the certain linear relationship between the ratio of the frequencies of the clock information generated by multiple ring oscillators and temperature to calculate temperature, and can further improve the temperature measurement accuracy of the digital temperature sensor.

[0131] Since there is a certain linear relationship between the ratio of the frequencies of the clock signals output by the multiple clock oscillators 201 and temperature, the mathematical model reflecting the corresponding relationship between the detection signal and temperature can be implemented as a polynomial function. The independent variable of the polynomial function is the detection signal, the dependent variable is the temperature, and the coefficients of the polynomial function are obtained by calibration of the temperature correction circuit 40.

[0132] For the mathematical model of the polynomial function, the parameter calculation module 402 can include an adder, a divider and a multiplier. The adder, the divider and the multiplier can cooperate with each other to calculate the coefficients of the mathematical model reflecting the corresponding relationship between the detection signal and temperature by using multiple calibration temperatures and multiple test average signals corresponding to the multiple calibration temperatures. The connection structure of the adder, the divider and the multiplier in the temperature correction circuit 40 can be implemented as a circuit structure for solving the coefficients of the polynomial function.

[0133] For example, suppose the polynomial function reflecting the correspondence between the detection signal and temperature is a linear function in one variable: y = ax + b; where x represents the detection signal, y represents the temperature corresponding to the detection signal, and a and b are coefficients to be calibrated. Correspondingly, such as Figure 11 As shown, the temperature correction circuit 40 may include a multiplier, an adder, and a divider. The adder, multiplier, and divider constitute... Figure 11 The connection structure shown can calculate the coefficient a = (y1-y2) / (x1-x2) of y = ax + b, and output the calculated coefficient a to the temperature determination circuit 30; Figure 11 In addition, the coefficient b = y1 - a*x1 can be calculated for y = ax + b, and the calculated coefficient b is output to the temperature determination circuit 30.

[0134] Furthermore, the temperature correction circuit 40 can output the coefficients of the calculated mathematical model to the temperature determination circuit 30. The temperature determination circuit 30 can store the coefficients of the mathematical model, and during actual temperature testing, it inputs the temperature signal corresponding to the temperature of the device under test generated by the temperature sensing circuit 20 into the mathematical model for calculation to determine the temperature of the device under test.

[0135] The circuit structure of the temperature determination circuit 30 is determined by the implementation of a mathematical model reflecting the correspondence between the detection signal and temperature. Specifically, the input terminal of the temperature determination circuit 30 is electrically connected to the temperature sensing circuit 20 to receive the temperature-to-be-measured signal generated by the temperature sensing circuit 20. The output terminal of the temperature determination circuit 30 outputs the temperature corresponding to the temperature-to-be-measured signal. The circuit structure of the temperature determination circuit 30 is constructed according to the aforementioned mathematical model.

[0136] In some embodiments, the mathematical model reflecting the correspondence between the detection signal and temperature can be implemented as a polynomial function, where the independent variable of the polynomial function is the detection signal, and the coefficients of the polynomial function are calibrated by the temperature correction circuit 40 described above. Correspondingly, the circuit structure of the temperature determination circuit 30 is constructed as a polynomial function. For example, assume the polynomial function is a linear function in one variable: y = ax + b; where x represents the detection signal, y represents the temperature corresponding to the detection signal, and a and b are the coefficients calibrated by the temperature calibration circuit 40. Accordingly, as... Figure 11 As shown, the temperature determination circuit 30 may include a multiplier and an adder. The input terminal A of the multiplier is electrically connected to the temperature sensing circuit 20 to receive the signal to be measured output by the temperature sensing circuit 20. The other input terminal B of the multiplier is electrically connected to the temperature calibration circuit 40 to receive the coefficient 'a' calibrated by the temperature calibration circuit 40. The input terminal of the adder is electrically connected to both the output terminal of the multiplier and the temperature calibration circuit 40 to receive the (a*x) output by the multiplier and the coefficient 'b' output by the temperature calibration circuit 40. The output of the adder is the y-value, which is the temperature corresponding to the signal to be measured, x.

[0137] It is worth mentioning that, Figure 11 The temperature determination circuit 30 and the temperature correction circuit 40 shown are only exemplary and do not constitute a limitation.

[0138] The digital temperature sensor provided by the embodiment adopts an analog circuit to design a digital voltage domain voltage processing circuit, can stabilize the power supply voltage, can reduce the power supply voltage fluctuation of the digital temperature sensor, helps to reduce the influence of voltage fluctuation on the temperature measurement accuracy of the temperature sensor, and further helps to improve the temperature measurement accuracy of the digital temperature sensor.

[0139] On the other hand, by selecting analog devices with different voltage thresholds, different digital domain voltage working ranges can be adapted, and an analog voltage processing circuit meeting the digital voltage domain is realized, meeting the requirements of a wide power supply voltage working range of the digital voltage domain and a low required voltage.

[0140] It should be noted that the "first", "second", and the like in the present text are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do "first" and "second" represent different types.

[0141] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0142] The present application is described with reference to flowcharts and / or block diagrams according to the method, device (system), and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of the flows and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flows in the flowchart and / or one or more blocks in the block diagram.

[0143] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart or flowsheets and / or block or blocks of the block diagrams.

[0144] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart or flowsheets and / or block or blocks of the block diagrams.

[0145] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0146] The memory can include non-persistent memory and / or volatile memory, such as random access memory (RAM) and / or cache memory, non-volatile memory, such as read-only memory (ROM), EPROM, and / or flash memory, etc. The memory is an example of computer-readable media.

[0147] Computer-readable media includes permanent and non-permanent, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to computing devices. According to the definition herein, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

[0148] It should also be noted that the terms "comprising," "including," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0149] The above description is merely illustrative of the application, and not restrictive. Various modifications and changes can become apparent to those skilled in the art. Incorporating any modification, equivalent substitution, improvement, etc. within the spirit and principle of the application, shall be included in the scope of the claims of the application.

Claims

1. A digital temperature sensor, characterized by The application relates to a digital temperature sensor, which comprises a temperature sensing circuit, a temperature determining circuit and a voltage processing circuit composed of voltage-driven analog devices. The input end of the voltage processing circuit is electrically connected with a power supply end for supplying power to the digital temperature sensor, and the output end is electrically connected with the temperature sensing circuit and the temperature determining circuit, so as to stabilize the power supply voltage by using the volt-ampere characteristic of the analog devices and provide the temperature sensing circuit and the temperature determining circuit with the voltage-processed power supply voltage. The temperature sensing circuit and the temperature determining circuit are electrically connected, and are used for generating a to-be-tested signal corresponding to the temperature of a measured device and outputting the signal to the temperature determining circuit. The temperature determining circuit is used for determining the temperature of the measured device according to the to-be-tested signal. The voltage processing circuit comprises a current generating circuit composed of voltage-driven analog devices, a current comparator, a current sampling circuit and a voltage output circuit. The current generating circuit is used for generating a reference current when the analog device is driven. The analog device of the current comparator is electrically connected with the analog device of the current generating circuit to form a mirror circuit, and is used for generating a mirror current of the reference current. The analog device of the voltage output circuit is electrically connected with the current comparator and the current sampling circuit, and is used for generating a power supply voltage. The analog device of the current comparator is also electrically connected with the analog device of the current sampling circuit to form a mirror circuit, and is used for generating a mirror current of the sampling current. The current comparator is also used for adjusting the power supply voltage output by the analog device of the voltage output circuit according to the size relationship between the mirror current of the reference current and the mirror current of the sampling current.

2. The sensor of claim 1, wherein, The current generating circuit comprises a differential voltage circuit and a first mirror circuit connected in series. The analog device of the differential voltage circuit is electrically connected with the power supply end. The analog device of the current comparator is electrically connected on the series connection path of the differential voltage circuit and the first mirror circuit, and forms a mirror circuit with the analog device of the first mirror circuit.

3. The sensor of claim 2, wherein, The differential voltage circuit generates a voltage difference when the analog device is driven, generates a reference current based on the generated voltage difference, and outputs the reference current to the first mirror circuit. The first mirror circuit generates a mirror current of the reference current by using the analog device, as the reference current. The analog device of the differential voltage circuit comprises a first PMOS circuit and a second PMOS circuit. The source of the first PMOS circuit and the second PMOS circuit is electrically connected with the power supply end. The threshold voltage of the first PMOS circuit is greater than that of the second PMOS circuit. The gate of the first PMOS circuit and the second PMOS circuit is electrically connected at both ends of the resistor R1. In the starting process of the first PMOS circuit and the second PMOS circuit, a voltage difference is generated across the resistor (R1), and the reference current is generated due to the voltage difference and output to the first branch of the first mirror circuit; The second branch of the first mirror circuit is electrically connected with the drain of the first PMOS circuit; the first PMOS circuit is started to trigger the second branch of the first mirror circuit to generate the reference current.

4. The sensor of claim 2, wherein, The current comparator comprises a first circuit unit and a second circuit unit connected in series; the first circuit unit and the second circuit unit comprise voltage-driven analog devices; The analog device of the first circuit unit is connected on the series connection path of the differential voltage circuit and the first mirror circuit, and forms a mirror circuit with the first mirror circuit; the differential voltage circuit triggers the analog device of the first circuit unit to conduct in the presence of a voltage difference, and generates a mirror current of the reference current on the series connection path A of the first circuit unit and the second circuit unit; The analog device of the second circuit unit is electrically connected with the current sampling circuit to form a mirror circuit, for generating a mirror current of the sampling current on the series connection path A; The analog device of the voltage output circuit is electrically connected on the series connection path A; the current comparator adjusts the size of the conduction signal of the analog device of the voltage output circuit according to the size relationship between the mirror current of the reference current and the mirror current of the sampling current on the series connection path A, to adjust the output voltage of the voltage output circuit.

5. The sensor of claim 4, wherein, The analog device of the first circuit unit comprises an NMOS tube MN3; the source of the NMOS tube MN3 is grounded; The drain of the NMOS tube MN3 is electrically connected with the second circuit unit to form the series connection path A; The gate of the NMOS tube MN3 is electrically connected on the series connection path of the differential voltage circuit and the first mirror circuit; the differential voltage circuit triggers the NMOS tube MN3 to conduct in the presence of a voltage difference, to generate a mirror current of the reference current on the series connection path A.

6. The sensor of claim 5, wherein, The analog device of the second circuit unit comprises an NMOS tube MN4 and a second mirror circuit comprising voltage-driven analog devices; the analog device of the second mirror circuit is connected in series with the drain of the NMOS tube MN3 to form the series connection path A; the NMOS tube MN4 and the analog device of the second mirror circuit are connected in series to form a series connection path B; The gate of the NMOS tube MN4 is electrically connected with the analog device of the current sampling circuit, and forms a mirror circuit with the analog device of the current sampling circuit; the current sampling circuit triggers the NMOS tube MN4 to conduct in the presence of the sampling current, to generate a mirror current of the sampling current on the series connection path B; The analog device of the second mirror circuit generates a mirror current of the sampling current on the series connection path A.

7. The sensor of claim 6, wherein, The analog device of the second mirror circuit comprises a PMOS tube MP3 and a PMOS tube MP4; The source of the PMOS tube MP3 and the source of the PMOS tube MP4 are electrically connected to a power supply terminal; the gate of the PMOS tube MP3 is electrically connected to the gate of the PMOS tube MP4; The drain of the PMOS tube MP3 is electrically connected to the drain of the NMOS tube MN3, forming the serial connection path A; The gate of the PMOS tube MP4 is short-circuited to the drain of the PMOS tube MP4; the drain of the PMOS tube MP4 is electrically connected to the drain of the NMOS tube MN4; The NMOS tube MN4 is turned on, triggering the PMOS tubes MP4 and MP3 to be turned on, and the sampling on the serial connection path B is generated; the PMOS tube MP3 is turned on, and the mirror current of the sampling current on the serial connection path A is generated.

8. The sensor of claim 7, wherein, The analog device of the voltage output circuit comprises a PMOS tube MP5; the source of the PMOS tube MP5 is electrically connected to a power supply terminal; The gate of the PMOS tube MP5 is electrically connected to the serial connection path A; The current comparator adjusts the gate voltage of the PMOS tube MP5 according to the size relationship between the mirror current of the reference current on the serial connection path A and the mirror current of the output current, so as to adjust the power supply voltage output by the drain of the PMOS tube MP5.

9. The sensor of claim 6, wherein, The analog device in the current sampling circuit comprises an NMOS tube MN5 and a switch circuit comprising an analog device driven by voltage; The analog device in the switch circuit is electrically connected between the voltage output circuit and the drain of the NMOS tube MN5; The gate of the NMOS tube MN5 is electrically connected to the gate of the NMOS tube MN4; the gate of the NMOS tube MN5 is short-circuited to the drain of the NMOS tube MN5; the source of the NMOS tube MN5 is grounded; the NMOS tube MN5 and the NMOS tube MN4 form a mirror circuit; The analog device in the switch circuit is turned on when the voltage output circuit outputs the power supply voltage, and triggers the NMOS tube MN5 to be turned on, generating the sampling current.

10. The sensor according to any one of claims 1 to 9, characterized in that The temperature sensing circuit comprises a plurality of ring oscillators with different temperature coefficients and a calculation circuit connected to the plurality of ring oscillators; the plurality of ring oscillators are electrically connected to the output terminal of the voltage processing circuit, for generating a clock signal corresponding to the temperature of the device under test; and outputting the clock signal to the connected calculation circuit; The calculation circuit is configured to calculate the frequency ratio of the clock signals output by the plurality of ring oscillators as the signal to be measured.

11. The sensor of claim 10, wherein, Further comprising: A temperature correction circuit electrically connected between the temperature sensing circuit and the temperature determination circuit, for calibrating the corresponding relationship between the detection signal output by the temperature sensing circuit and the temperature; And providing the corresponding relationship to the temperature determination circuit; The temperature determination circuit is configured to determine the temperature of the device under test according to the signal to be measured and the corresponding relationship.

Images